| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327237000 |
Variable or adjustable
| 73 |
| 327233000 |
Correction to specific phase shift
| 19 |
| 327254000 |
Quadrature related (i.e., 90 degrees)
| 19 |
| 327258000 |
Multiple outputs
| 11 |
| 327256000 |
Phase inversion (i.e., 180 degrees between input and output) | 5 |
| 20080265964 | SINGLE SIGNAL-TO-DIFFERENTIAL SIGNAL CONVERTER AND CONVERTING METHOD - In an example embodiments, a single signal-to-differential signal converter includes a first inverter for receiving and inverting a single input signal and outputting an inverted single input signal to a first node, and a first differential signal generating portion for generating a first signal and an inverted first signal which have the opposite phases to each other to second and third nodes in response to the single input signal. The single signal-to-differential signal converter further includes a second differential signal generating portion for generating a second signal and an inverted second signal which have the opposite phases to each other to the second and third nodes in response to the inverted single input signal, wherein the single signal-to-differential signal converter outputs differential signals such that the first and second signals applied to the second node are merged by a phase interpolation and the inverted first and second signals applied to the third node are merged by a phase interpolation. | 10-30-2008 |
| 20090045862 | CLOCK GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A clock generating circuit of a semiconductor memory apparatus includes a phase splitter that delays a clock to generate a delayed clock and inverts the clock to generate an inverted clock, and a clock buffer that buffers the delayed clock and the inverted clock and outputs a rising clock and a falling clock. | 02-19-2009 |
| 20100109734 | CURRENT-MODE PHASE ROTATOR WITH PARTIAL PHASE SWITCHING - In one illustrative embodiment, an apparatus for a current-mode phase rotator with partial input phase switching comprises a mixer, wherein the mixer is a four quadrant current-mode mixer comprised of four interpolation buffers, wherein each interpolation buffer receives as input a clock phase from a set of four equidistant clock phases, and a set of two-output current-steering digital to analog converters that supply tail currents to the mixer wherein a first digital to analog converter has additional switches to connect each of two outputs to one of two polarities of a given clock while each remaining digital to analog converter has no additional switches and has two outputs supplying current only to two different polarities of a same clock phase wherein steering the current during incremental rotation about a phase circle defines an octagonal shaped phase envelope. | 05-06-2010 |
| 20100327933 | ELECTRONIC DEVICE FOR MICROWAVE APPARATUSES ONBOARD A SATELLITE - The present invention includes a solution to the adherence to and improvement of the specifications regarding the conducted susceptibility of a microwave chain. It has an advantage of enabling significant attenuation of parasitic modulated signals carried in microwave chains of microwave devices such as those that are integrated into satellites by adding one or more 180° phase shifters between the units which do not exhibit a sufficient conducted susceptibility performance. The invention consequently makes it possible to do away with certain elements charged with the attenuation of the parasitic signals generally integrated into the power supplies and other DC/DC converters present in all contemporary microwave equipment. | 12-30-2010 |
| 20130169335 | DELAY LINES, METHODS FOR DELAYING A SIGNAL, AND DELAY LOCK LOOPS - Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals. | 07-04-2013 |
| 327232000 |
Dependent on frequency | 3 |
| 20090021291 | Adaptive EMI reduction technique for wireline PHYS in multi-port applications - An adaptive electromagnetic interference (EMI) detection and reduction device for multi-port applications is provided. The invention includes at least two physical devices (PHY), where the PHYs transmit data along wire pairs to a register jack (RJ). The transmissions create EMI along the wire pairs, where the transmissions have constructively interfering resonant frequencies having phases and amplitudes. An antenna is disposed proximal to each RJ, where the antennae detect each frequency. A resonating network determines a peak amplitude of each frequency, an envelope detector amplifies each peak amplitude from the resonating network. A discretization circuit converts the amplified peak to discrete amplitude values, where the discretization circuit transmits the discrete amplitude values to a controller. The controller receives the discrete amplitude values from the discretization circuit, and communicates with each PHY, where a phase or frequency of the PHY signal is modified to minimize the constructive interference between the resonant frequencies. | 01-22-2009 |
| 20090289683 | Combination of analog and digital feedback for adaptive slew rate control - An apparatus for scaling a load device with frequency in a phase interpolator can include an analog loop and a digital loop. The load device of the phase interpolator can include a transistor and a plurality of resistors selectively configured in parallel with the transistor. The analog loop controls a resistance of the transistor based on a voltage applied to a control terminal of the transistor. For instance, the analog loop can tune the resistance of a PMOS device by adjusting a voltage applied to the PMOS device's gate terminal. In addition, the analog loop can include a comparator to compare a voltage across the transistor to a reference voltage such that an optimal voltage is maintained for an output swing of the phase interpolator. The analog loop can also include a low pass filter coupled to an output of the comparator to define frequency stability and loop bandwidth of the analog loop. The digital loop operates in conjunction with the analog loop and controls the plurality of resistors by incrementing or decrementing a number of resistors that are configured in parallel with the transistor in the load device. In combining the analog and digital loops to control the load device of the phase interpolator, this configuration takes advantage of the wide tuning range of the digital control and the smooth, continuous output of the analog control. Further, in operating the analog and digital loops in conjunction with each other, the present invention avoids a long observation time in locking the system, as seen in conventional designs, while guaranteeing frequency stability in the operation of both the analog and digital loops. | 11-26-2009 |
| 20160013772 | DIGITAL INTERPOLATOR AND METHOD OF INTERPOLATING | 01-14-2016 |
| Entries |
| Document | Title | Date |
|---|
| 20090015306 | SIGNAL GENERATING APPARTUS, FILTER APPARATUS, SIGNAL GENERATING METHOD AND FILTERING METHOD - There is provided a signal generating apparatus including: a multiphase oscillating portion for generating a number of base signals having the same frequency and a predetermined phase difference of which the signal level transitions between a first level and a second level, and where periods during which the signal level of any given base signal is at the first level and the signal level of the next base signal having the predetermined phase delay relative to the given base signal is at the first level overlap; and a transition time point changing portion for generating a pulse signal by changing the time point when each base signal transitions from the first level to the second level to a time point before the next base signal transitions from the second level to the first level. | 01-15-2009 |
| 20090160518 | METHOD IMPLEMENTING PERIODIC BEHAVIORS USING A SINGLE REFERENCE - A method for processing information is described. The method includes providing a phase reference, Φ | 06-25-2009 |
| 20090237138 | PATTERN-DEPENDENT PHASE DETECTOR FOR CLOCK RECOVERY - A phase detector apparatus and method used for clock recovery from a data signal is provided. The phase detector provides phase correction signals to a clock signal generator, where the phase correction signals are only generated if a predetermined data sample pattern is observed. In particular, the predetermined data sample pattern is preferably a transition from one to zero. Thus, transitions from zero to one will not provide a valid phase update output signal, even though a transition has occurred. In other embodiments the predetermined data sample pattern is preferably a one to zero transition preceded by an additional logic one sample. | 09-24-2009 |
| 20090243688 | SYSTEM AND METHOD OF CHANGING A PWM POWER SPECTRUM - In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively apply a phase shift operation to the at least one PWM signal at integer submultiples of a frame repetition rate to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit. | 10-01-2009 |
| 20090302917 | DELAY CIRCUIT AND TEST METHOD FOR DELAY CIRCUIT - A delay circuit includes: a delay unit configured to delay an input signal and output the delayed signal; a selecting unit configured to select a first signal at the time of a normal operation or a second signal at the time of a test operation, and provide the selected signal to the delay unit; an inverting unit configured to invert an output signal of the delay unit, and output the inverted signal as the second signal; and a counting unit configured to count an output waveform of the delay unit. | 12-10-2009 |
| 20100001775 | Phase shifting circuit which produces phase shift signal regardless of frequency of input signal - A waveform generating circuit includes a constant current circuit that supplies a constant current through a power source; a current mirror circuit that flows an output current that is n times an input current; and a switching circuit that switches a flowing direction of the current in the constant current circuit between the current mirror circuit and the output terminal according to the logical level of the rectangle input signal. The waveform generating circuit generates a triangle wave having a falling slope waveform that is n times the rising slope. On the other hand, the waveform generating circuit that receives an inverted signal of the signal generates a triangle wave and its voltage is compared with another in the comparator to generate an output signal. | 01-07-2010 |
| 20100237922 | CLOCK GENERATING CIRCUIT AND CLOCK GENERATING METHOD THEREOF - A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs. | 09-23-2010 |
| 20100253408 | TIMING GENERATING CIRCUIT AND PHASE SHIFT CIRCUIT - There are provided a timing generating circuit which can generate the rising edge or the falling edge of pulses with a resolution higher than the frequency of a repeat signal generating circuit, and a phase shift circuit which can be applied to the timing generating circuit. The phase shift circuit receiving a repeat signal generates a signal of which a phase is shifted by a predetermined quantity on the basis of the repeat signal, the phase shift controller controls what phase of signal the phase shift circuit output among first to M-th signals, and the counter circuit counts the number of output signals of the phase shift circuit and generates a count end signal when the count value reaches a set value, and thereby the counter circuit outputs a synthesized timing signal of the timing of the repeat signal and the timing shifted by the phase shift circuit. | 10-07-2010 |
| 20110050311 | FLAG SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A flag signal generation circuit includes a first periodic signal detection unit, a second periodic signal detection unit, and a flag signal output unit. The first periodic signal detection unit is configured to detect a change in a level of a first periodic signal and generate a first detection signal. The second periodic signal detection unit is configured to detect a change in a level of a second periodic signal and generate a second detection signal. The flag signal output unit is configured to generate a pre-flag signal from the first and second detection signals, buffer the pre-flag signal in response to a mode register read signal, and output the buffered pre-flag signal as a flag signal. | 03-03-2011 |
| 20110057701 | SIGNAL CONTROL DEVICE - A signal control device controls the period of a three-phase signal used to control a three-phase high-voltage converter. An arithmetic unit of the signal control device determines a timing for changing the period for each phase so that the period of the signal for a V phase or a W phase is changed at the point when the phase difference between a U phase and the V or W phase reaches a prescribed phase difference after the period of the signal for the U phase has been changed. A control unit performs control such that the signal period for each phase is changed at the timing determined by the arithmetic unit. | 03-10-2011 |
| 20110156788 | HIGH SPEED, WIDE FREQUENCY-RANGE, DIGITAL PHASE MIXER AND METHODS OF OPERATION - The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals. Because of the rules governing abstract, this abstract should not be used to construe the claims. | 06-30-2011 |
| 20110210777 | DISPERSION COMPENSATION CIRCUITRY AND SYSTEM FOR ANALOG VIDEO TRANSMISSION WITH DIRECT MODULATED LASER - An improved precompensation circuit includes a greatly improved differentiator in the dispersion precompensation path, a preprocessor in the dispersion precompensation path for reducing f2−f1 type Composite Second Order (CSO) distortion, and a broadband phase shifter for compensating undesired vector interaction between the laser predistortion and dispersion compensation. | 09-01-2011 |
| 20120146698 | RADIO FREQUENCY SWITCH FOR SUPPRESSING INTERMODULATION - A radio frequency (RF) switch adapted to reduce third order intermodulation (IM3) products generated as RF signals propagate through the RF switch is disclosed. The RF switch includes N semiconductor switch segments, and N−1 phase shift networks, individual ones of the N−1 phase shift networks being coupled between adjacent ones of the N semiconductor switch segments where N is a natural number greater than 1. In operation, when the RF switch is on, IM3 products generated by the RF switch propagating through the N−1 phase shift networks are phase shifted such that the IM3 products are at least partially canceled. | 06-14-2012 |
| 20120146699 | RF SYSTEM HAVING INTERMODULATION SUPPRESSION BRANCHES - An RF system for suppressing third-order intermodulation (IM3) products is disclosed. The RF system is made up of a plurality of branches coupled in parallel. Each of the plurality of branches includes a positive phase shift network, a negative phase shift network, and nonlinear components, wherein the nonlinear components are coupled between the positive phase shift network and the negative phase shift network. The RF system also includes a null offset branch with nonlinear components that are coupled in parallel with the plurality of branches. In one embodiment, the nonlinear components are series stacked field effect transistors (FETs) that comprise an RF switch having a switch segment for the null offset branch and a switch segment for each of the plurality of branches. The RF switch further includes a control terminal for turning the FETs on and off. | 06-14-2012 |
| 20120146700 | MULTIPLE DATA RATE INTERFACE ARCHITECTURE - Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation. | 06-14-2012 |
| 20120286838 | DELAY LINE CIRCUIT AND PHASE INTERPOLATION MODULE THEREOF - A phase interpolation module comprising a first, second, and third phase interpolation units is proposed. Each of the first, second, and third phase interpolation units comprises a first through third inverters, a first and second resistors, wherein the first resistor is coupled between an output end of the first inverter and an input end of the third inverter, and the second resistor is coupled between an output end of the second inverter and the input end of the third inverter. The first and second inverters of the first phase interpolation unit receive a first signal, the first and second inverters of the third phase interpolation unit receive a second signal, and the first and second inverters of the second phase interpolation unit respectively receive the first and second signals. | 11-15-2012 |
| 20130002329 | DELAY CONTROL DEVICE - A delay control device that controls a relative delay time between two signals and is easy to be miniaturized is provided. Signal routes | 01-03-2013 |
| 20130088274 | PHASE INTERPOLATOR, MULTI-PHASE INTERPOLATION DEVICE, INTERPOLATED CLOCK GENERATING METHOD AND MULTI-PHASE CLOCK GENERATING METHOD - A phase interpolator, multi-phase interpolation device, interpolated clock generating method and multi-phase clock generating method is related to a phase interpolator with a differential to single-ended converter, a load circuit, two differential pairs, a current source and at least a switch pair. By using the switch pair to control the current providing for the two differential pairs from the current source, and through regulating the load of the load circuit and/or the reference current of the current source, the intersection of a first signal and a second signal is in the overlap duration between a first input clock and a second input clock, so that uniform multi-phase output clock signal can be interpolated. | 04-11-2013 |
| 20130147535 | TUNABLE ACTIVE DIRECTIONAL COUPLERS - Active directional couplers are provided. In accordance with certain embodiments of the invention, the subject active directional couplers are tunable. The tuning is accomplished via varactors connected to the lines of the active directional couplers. Active directional elements are provided between different lines of the subject active directional couplers to control a signal path between ports of the different lines. The active directional elements are selected from diodes, transistors, inverting amplifiers, non-inverting amplifiers, differential amplifiers, and active baluns. The lines include a phase shift element between the two ports of each line. The phase shift element is selected from a transmission line, a delay line, and a phase shifter. Advantageously, the subject lines do not have to be designed for ideal phase shifting and can be designed at near 90° or near λ/4 values. | 06-13-2013 |
| 20130194017 | DELAY LINE PHASE SHIFTER WITH SELECTABLE PHASE SHIFT - A phase shifter with selectable phase shift and comprises a switchable phase shifting element that includes a first and second signal path coupled between an input and an output and providing a, respective, first and second phase shift for a signal coupled through the respective signal paths; a switch circuit for selecting between the first and second signal paths where the first and second signal paths and the switch circuit are configured to equalize the insertion loss for the first and second signal path, the phase shifter further including control circuit for controlling the switch circuit. | 08-01-2013 |
| 20130207706 | PHASE INTERPOLATOR AND METHOD OF PHASE INTERPOLATION WITH REDUCED PHASE ERROR - An exemplary phase interpolator includes a first to a fourth differential pair. Each of the differential pairs includes a first and a second transistor and a stabilizing capacitor connected between a source coupled node and a reference voltage. The phase interpolator also includes a plurality of current sources and a group of switches to switch connections between the source coupled nodes of the differential pairs and the current sources so that (i) a first operating current is supplied to a first selected one of the first and second differential pairs and (ii) a second operating current is supplied to a second selected one of the third and fourth differential pairs. Drains of the first transistors in the differential pairs are commonly connected and drains of the second transistors in the differential pairs are commonly connected to form a first and a second output node so that a differential output signal is output. | 08-15-2013 |
| 20130307602 | DYNAMIC CLOCK PHASE CONTROL ARCHITECTURE FOR FREQUENCY SYNTHESIS - Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal. | 11-21-2013 |
| 20140002163 | SIGNAL TRANSMISSION CIRCUITS | 01-02-2014 |
| 20140021996 | PHASE INTERPOLATING APPARATUS AND METHOD - The present invention discloses a phase interpolating apparatus comprising: a first signal generation circuit, configured for generating a first signal having a first phase; an optional second signal generation circuit, configured for generating a second signal having the first phase; a third signal generation circuit, configured for generating a third signal having a second phase; a fourth/fifth signal generation circuit, configured for generating a fourth signal having a third phase when operating in a first mode and for generating a fifth signal having the second phase instead of the fourth signal when operating in a second mode; and a phase interpolator, configured for generating an interpolated signal without utilizing the fourth signal when operating in the first mode and for generating the interpolated signal according to the first signal, the third signal, and the fifth signal when operating in the second mode. | 01-23-2014 |
| 20140375368 | SIGNAL PROCESSING APPARATUS AND SIGNAL PROCESSING METHOD - Digital signals with higher resolution are generated from dual-phase encode signals indicating phase changes of a position or an angle of a target. A signal processing apparatus for processing dual-phase encode signals indicating changes in position of a target, comprises: a first noise reduction unit configured to remove high frequency noise from each of the dual-phase encode signals before interpolation processing; an interpolating unit configured to apply interpolation processing to the dual-phase encode signals output from the first noise reduction unit to generate dual-phase encode signals with higher resolution; and a second noise reduction unit configured to remove noise from the dual-phase encode signals output from the interpolating unit. | 12-25-2014 |
| 20150022253 | PHASE COMPENSATION CIRCUIT AND PHASE COMPENSATING METHOD - A phase compensation circuit includes: a first circuit that increases phase characteristic of a specific frequency of an electrical signal; a second circuit that decreases the phase characteristic of the specific frequency of the electrical signal; and a limiting amplifier that amplifies an electrical signal that is processed by at least one of the first circuit and the second circuit. | 01-22-2015 |
| 20150028928 | PHASE INTERPOLATORS AND PUSH-PULL BUFFERS - Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the dock signals output from the push-pull buffers. | 01-29-2015 |
| 20150349763 | METHOD FOR PERFORMING PHASE SHIFT CONTROL IN AN ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS - A method for performing phase shift control in an electronic device and an associated apparatus are provided, where the method includes: obtaining a set of clock signals corresponding to a set of phases, wherein any two phases of the set of phases are different from each other; and controlling a phase shift of an output signal of an oscillator by selectively mixing the set of clock signals into the oscillator according to a set of digital weighting control signals, wherein the phase shift corresponds to the set of digital weighting control signals, and the set of digital weighting control signals carries a set of digital weightings for selectively mixing the set of clock signals. More particularly, the method may include: selectively mixing the set of clock signals into a specific stage of a plurality of stages of the oscillator according to the set of digital weighting control signals. | 12-03-2015 |
| 20150358008 | Linearity of Phase Interpolators using Capacitive Elements - A phase interpolator, including: a pair of load resistors coupled to a supply voltage; a plurality of branches coupled to the pair of load resistors, each branch including a differential pair of transistors connected at source terminal to form a source node; a plurality of tail current sources, each tail current source coupled to one of the source nodes; and a plurality of coupling capacitors, each coupling capacitor coupled between the source nodes in two adjacent branches of the plurality of branches. | 12-10-2015 |
| 20160099710 | METHOD FOR PERFORMING PHASE SHIFT CONTROL IN AN ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS - A method for performing phase shift control in an electronic device and an associated apparatus are provided, where the method includes: obtaining a set of clock signals corresponding to a set of phases; and controlling a phase shift of an output signal of an oscillator by selectively mixing the set of clock signals into the oscillator according to a set of digital control signals, wherein the phase shift corresponds to the set of digital control signals, and the set of digital control signals carries a set of digital weightings for selectively mixing the set of clock signals. More particularly, the method may include: selectively mixing the set of clock signals into a specific stage of a plurality of stages of the oscillator according to the set of digital control signals. | 04-07-2016 |
| 20160105177 | CLOCK BUFFERS WITH PULSE DRIVE CAPABILITY FOR POWER EFFICIENCY - A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output. The input is for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. The output is connected to the positive pulse driving branch and the negative pulse driving branch. The clock driver further includes a pulse generator having positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification. | 04-14-2016 |
| 20170237419 | DIFFERENTIAL PHASE ADJUSTMENT OF CLOCK INPUT SIGNALS | 08-17-2017 |
