| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327254000 | Quadrature related (i.e., 90 degrees) | 19 |
| 20080238515 | Signal generation apparatus for frequency conversion in communication system - A signal generation apparatus includes a signal generation portion and a phase compensator. The phase compensator generates a phase error control signal that maintains a phase difference between the in-phase and quadrature-phase signals generated by the signal generation portion. The phase compensator includes an offset compensator and a delay compensator. The offset compensator is set to compensate for an offset voltage through the phase compensator. The delay compensator is set to compensate for a difference of delays through paths for the in-phase and quadrature-phase signals within the phase compensator. | 10-02-2008 |
| 20090027098 | Phase shift circuit with lower intrinsic delay - A phase shift circuit that includes two, rather than four, delay chains and corresponding selectors is described. This provides a significant area savings and reduces the intrinsic delay of the phase shift circuit, which is particularly beneficial for embodiments in which there is no intrinsic delay matching. In one specific implementation, the phase shift circuit includes a first delay circuit and a matching delay circuit. The first delay circuit provides a first delay that includes a first intrinsic delay and a first intentional delay. The delay matching circuit provides a matching delay that matches the first intrinsic delay. In one specific implementation, the phase shift circuit also includes a second delay circuit to provide a second delay that includes a second intrinsic delay and second intentional delay, where the second intrinsic delay matches the first intrinsic delay and the second intentional delay is half as long as the first intentional delay. Matching the intrinsic delay of the first delay circuit allows for comparing its output against a delayed version of the input signal, rather than the input signal. As a result, Fmax, the maximum frequency of the input signal at which the phase shift circuit may operate, is not limited by the intrinsic delay or by Fmin, the minimum frequency of the input signal at which the phase shift circuit may operate. | 01-29-2009 |
| 20090140787 | Phase controller apparatus and pulse pattern generator and error detector using the phase controller apparatus - A quadrature modulator divides a first signal input as a local signal into an I channel signal and a Q channel signal orthogonal to each other and outputs a second signal having a desired phase delay corresponding to direct current voltages as for the first signal by giving the direct current voltages Vi and Vq to the I channel signal and the Q channel signal, respectively. A phase comparison unit detects a phase difference θ between the first signal and the second signal. A setting unit sets the desired phase delay. A controller section controls the direct current voltages supplied to the I channel signal and the Q channel signal respectively in the quadrature modulator so that an output value corresponding to the phase difference θ detected by the phase comparison unit is equal to a value corresponding to the desired phase delay set by the setting unit, and controls the direct current voltages to be the direct current voltages Vi and Vq satisfying the relation of Vi=cos θ and Vq=sin θ. | 06-04-2009 |
| 20090153212 | Clock generators for generation of in-phase and quadrature clock signals - Clock generator embodiments are provided to generate half-rate I and Q clock signals. The generators are configured to insure fan-out limitations, to insure correct phasing at startup, to reduce the number of signal inverters in a critical path, and to reduce the total number of inverter structures to thereby substantially extend generator operational frequency. An exemplary generator embodiment requires only two tri-state inverters and four inverters. These clock generators are particularly suited for variety of electronic systems such as high speed data serializers. | 06-18-2009 |
| 20090256610 | Quadrature phase correction circuit - A quadrature phase correction circuit includes an N-bit code counter configured to generate an N-bit code value according to a detected phase difference when a quadrature phase correction is carried out; a storage configured to store N-bit code values according to a plurality of detected phase differences; and a controller configured to share the N-bit code counter, control the generation of the N-bit code values according to the plurality of detected phase differences, and control the storing of the N-bit code values in an allocated space of the storage. | 10-15-2009 |
| 20100039153 | DIVIDE-BY-THREE QUADRATURE FREQUENCY DIVIDER - A local oscillator includes a programmable frequency divider coupled to the output of a VCO. The frequency divider can be set to frequency divide by three. Regardless of the divisor, the frequency divider outputs quadrature signals (I, Q) that differ from each other in phase by ninety degrees. To divide by three, the frequency divider includes a divide-by-three frequency divider. The divide-by-three frequency divider includes a divide-by-three circuit, a delay circuit, and a feedback circuit. The divide-by-three circuit frequency divides a signal from the VCO and generates therefrom three signals C, A′ and B that differ from each other in phase by one hundred twenty degrees. The delay circuit delays signal A′ to generate a delayed version A of the signal A′. The feedback circuit controls the delay circuit such that the delayed version A (I) is ninety degrees out of phase with respect to the signal C (Q). | 02-18-2010 |
| 20100090740 | AUTOMATIC RC/CR QUADRATURE NETWORK - A stabilized quadrature RC/CR phase shifting network for generating quadrature RF and microwave signals. The network uses offset biasing of postamplifiers following the phaseshifter to fine tune quadrature-phase, and further uses an output quadrature-phase detector to stabilize quadrature-phase with negative feedback by using the quadrature-phase error signal to drive the quadrature-phase fine tuning control. In an alternative embodiment, the stability of quadrature-phase can be enhanced without the output quadrature-phase detector by making the quadrature-phase fine tuning control dependent upon the amplitude-difference negative feedback error signal. | 04-15-2010 |
| 20100327932 | FEEDBACK SYSTEM WITH IMPROVED STABILITY - Techniques for improving stability of a feedback system are described. In an exemplary design, the feedback system includes a forward path and a feedback path. The forward path receives an input signal and a rotated feedback signal and provides an output signal having a phase shift. The feedback path receives the output signal, generates a feedback signal, and rotates the feedback signal to obtain the rotated feedback signal having at least part of the phase shift removed. In another exemplary design, the feedback system includes a forward path and a feedback loop. The forward path receives a combined signal and provides an output signal having a phase shift. The feedback loop generates an error signal based on an input signal and the output signal, generates the combined signal based on the error signal and the input signal, and performs phase rotation to remove at least part of the phase shift. | 12-30-2010 |
| 20110006826 | PHASE SIGNAL GENERATING APPARATUSES - In at least one example embodiment, a phase signal generating apparatus includes a phase signal generator and phase controller. The phase signal generator is configured to receive a plurality of first phase signals and a plurality of second phase signals, adjust a phase difference between the plurality of first phase signals and the plurality of second phase signals and generate a plurality of adjusted first phase signals and a plurality of adjusted second phase signals, based on a switch control signal and a phase control signal, a phase difference between the plurality of adjusted first phase signals and the plurality of adjusted second phase signals being the adjusted phase difference. The phase controller is configured to generate the switch control signal and the phase control signal based on phase information for the plurality of first phase signals and the plurality of second phase signals. | 01-13-2011 |
| 20130278316 | PHASED ARRAY ARCHITECTURE CONFIGURED FOR CURRENT REUSE - A phased array architecture configured for current reuse is disclosed. In an exemplary embodiment, an apparatus includes a current mode phase rotator (PR) module configured to generate phase shifted in-phase (I) and quadrature-phase (Q) current signals, and a current mode residual sideband (RSB) correction module configured to correct residual sideband error associated with the phase shifted I and Q current signals. The RSB correction module and the PR module form a phased array element configured to reuse a DC supply current. | 10-24-2013 |
| 20130285727 | OCTAL CLOCK PHASE INTERPOLATOR ARCHITECTURE - The present invention provides an apparatus and method of generating a set of 8 clock signals nominally spaced at equal 45° intervals by phase interpolation from a set of 4 quadrature reference clocks. The scheme is useful for clock generation for data capture in an oversampled clock/data recovery (CDR) system where the frequency of data sampling is twice that of the frequency of reference clock edges. | 10-31-2013 |
| 20140103984 | QUADRATURE SYMMETRIC CLOCK SIGNAL GENERATION - Exemplary embodiments are directed to systems, methods, and devices for generating quadrature clock signals. A device may include a plurality of dynamic logic cells and a plurality of inverters. Each inverter of the plurality of inverters may be coupled to at least two dynamic logic cells of the plurality of dynamic logic cells. Each inverter may be configured to output a twenty-five percent duty cycle clock signal. | 04-17-2014 |
| 20150070065 | SIGNAL-ALIGNMENT CIRCUITRY AND METHODS - Signal-alignment circuitry, comprising: phase-rotation circuitry connected to receive one or more input clock signals and operable to generate therefrom one or more output clock signals; and control circuitry operable to control the amount of phase rotation applied by the phase-rotation circuitry to carry out a plurality of alignment operations, the alignment operations comprising: one or more first operations each comprising rotating one or more of said output clock signals relative to one or more of the other said output clock signals, to bring a phase relationship between said output clock signals, or clock signals derived therefrom, towards or into a given phase relationship; and one or more second operations each comprising rotating all of said output clock signals together, to bring a phase relationship between said output or derived clock signals and said input clock signals or an external-reference signal towards or into a given phase relationship. | 03-12-2015 |
| 20150070066 | CIRCUITRY USEFUL FOR CLOCK GENERATION AND DISTRIBUTION - An integrated circuit comprising an inductor arrangement, the arrangement comprising: four inductors adjacently located in a group and arranged to define two rows and two columns, wherein: the integrated circuit is configured to cause two of those inductors diagonally opposite from one another in the arrangement to produce an electromagnetic field having a first phase, and to cause the other two of those inductors to produce an electromagnetic field having a second phase, the first and second phases being substantially in antiphase. | 03-12-2015 |
| 20160254800 | CIRCUITRY USEFUL FOR CLOCK GENERATION AND DISTRIBUTION | 09-01-2016 |
| 327255000 | 90 degrees between input and output | 4 |
| 20090009226 | System and method for implementing a swap function for an IQ generator - A system and method for implementing an IQ generator includes a master latch that generates an I signal in response to a clock input signal, and a slave latch that generates a Q signal in response to an inverted clock input signal. A master selector is configured to provide a communication path from the master latch to the slave latch, and a slave selector is configured to provide a feedback path from the slave latch to the master latch. The foregoing I and Q signals are output directly from the respective master and slave latches without any intervening electronic circuitry. | 01-08-2009 |
| 20090302919 | Phase Shifter - A phase shifter includes a phase shifting unit for operating at a timing at which a clock signal becomes equal to or greater than a threshold value and outputting periodic signals having phases shifted by 90 degrees from each other; a DC voltage setting unit for setting a voltage value of a DC component of the clock signal input into the phase shifting means; and a clock signal slope varying unit for varying a slope of a rising edge of the clock signal. | 12-10-2009 |
| 20100073060 | PHASE SHIFT CIRCUIT WITH LOWER INTRINSIC DELAY - A phase shift circuit that includes two, rather than four, delay chains and corresponding selectors is described. This provides a significant area savings and reduces the intrinsic delay of the phase shift circuit, which is particularly beneficial for embodiments in which there is no intrinsic delay matching. In one implementation, the phase shift circuit includes a first delay circuit and a matching delay circuit. The first delay circuit provides a first delay that includes a first intrinsic delay and a first intentional delay. The delay matching circuit provides a matching delay that matches the first intrinsic delay. In one implementation, the phase shift circuit also includes a second delay circuit to provide a second delay that includes a second intrinsic delay and second intentional delay, where the second intrinsic delay matches the first intrinsic delay and the second intentional delay is half as long as the first intentional delay. | 03-25-2010 |
| 20130200936 | PHASE INTERPOLATOR WITH INDEPENDENT QUADRANT ROTATION - The present invention provides an improvement of a 4-quadrant clock phase interpolator design to allow independent rotation of the output clocks in steps of 90°. This feature is useful in clock/data recovery where the 90° “jumps” can be used as a coarse control to re-align the data capture clock to achieve any desired data word alignment and/or receive bus clock alignment. The phase interpolator has a switching circuit comprising a single level of switches; a set of four transistor loads; and a set of four current sources operable to be switched by the switching circuit through to any of the set of four transistor loads. | 08-08-2013 |
