| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327200000 | Dynamic bistable | 10 |
| 20110001534 | Voltage Generator Capable of Preventing Latch-up and Method Thereof - A voltage generator capable of preventing latch-up is disclosed. The voltage generator includes a positive charge pump unit, a negative charge pump unit, a second stage charge pump unit, and a control unit. The positive charge pump unit is utilized for generating a positive charge pump voltage according to a first enable signal. The negative charge pump is utilized for generating a negative charge pump voltage according to a second enable signal. The second stage charge pump unit is utilized for generating a gate-on voltage and a gate-off voltage according to a third enable signal and a fourth enable signal. The control unit is utilized for generating the first enable signal, the second enable signal, the third enable signal, and the fourth enable signal and make the second stage charge pump unit generate the gate-on voltage (or the gate-off voltage) in a successively-increasing (or decreasing) manner. | 01-06-2011 |
| 20110063008 | SEMICONDUCTOR INTEGRATED CIRCUIT - In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S | 03-17-2011 |
| 20110210775 | DYNAMIC-TO-STATIC CONVERTER LATCH WITH GLITCH SUPPRESSION - A latch circuit. The latch circuit may include an input circuit, a precharge circuit, and a transfer circuit. The precharge circuit may precharge a first node during a first phase of a clock signal. Based on an input signal received at a first logic value, the input signal may drive the first node to a second logic value during the second clock phase. The transfer circuit may include a discharge circuit that is active during an evaluation phase beginning at a delay time subsequent to the clock signal entering the second phase and ending when the clock signal re-enters the first phase. The transfer circuit may also include pull-up and pull-down transistors, one of which may drive a logic value to a second node during the evaluation phase. | 09-01-2011 |
| 20130088273 | SEMI-DYNAMIC FLIP-FLOP WITH PARTIALLY FLOATING EVALUATION WINDOW - Implementations of the present disclosure involve a semi-dynamic flip-flop circuit incorporating a partially floating evaluation window that provides a faster data to output delay, a PMOS keeper device may be placed in series with an existing keeper circuit of the semi-dynamic flip-flop circuit. The gate of the PMOS series keeper device may be connected to a shut-off signal of the semi-dynamic flip-flop circuit that provides a three gate delay, self-timed positive pulse to control the keeper circuit. The PMOS series keeper device effectively turns off the keeper circuit when the clock signal rises but turns in back on after a three gate delay to sustain the precharge state of the dynamic node. The effective turning on and off of the keeper circuit portion may decrease the data to output delay of the flip-flop, resulting in higher performing microprocessors. | 04-11-2013 |
| 20130229217 | DYNAMIC LATCH AND DATA OUTPUT DEVICE COMPRISING SAME - A dynamic latch comprises a floating node, a storage node, a write transistor connected to the floating node and the storage node and configured to write data of the floating node to the storage node, and a read transistor connected to the floating node and configured to read the data of the storage node. | 09-05-2013 |
| 20140306743 | SEMI-DYNAMIC FLIP-FLOP - A semi-dynamic flip-flop is provided. A selecting circuit selects an input signal from a data signal and a test signal. A charging/discharging circuit charges/discharges an intermediate node according to the input signal, a clock signal and a modulation signal. A first storage circuit stores electric potential of the intermediate node. An adjusting circuit generates an adjustment signal according to the clock signal and the potential of the intermediate node. An output signal adjusts electric potential of an output node according to the clock signal and the potential of the intermediate node. A second storage circuit stores the potential of the output node. A reset circuit sets or resets the potential of the output node. A switch, connected between the adjusting circuit and the charging/discharging circuit, is turned on when the semi-dynamic flip-flop is in a normal operation mode. | 10-16-2014 |
| 20140320188 | SCANNABLE FAST DYNAMIC REGISTER - A scannable fast dynamic register including a data and scan enable circuit, a precharge circuit, a select circuit, a store circuit, and a scan input enable circuit. The data and scan enable circuit pulls a first precharge node to a discharge node in response to the clock upon evaluation in normal mode. The precharge circuit precharges first and second precharge nodes high, in which one of the precharged nodes discharges depending upon whether a data block evaluates. The store circuit and an output gate are responsive to the second precharge node to provide the output. The select circuit is interposed before the store circuit to allow injection of scan data in a scan mode. In scan mode, the scan input enable circuit provides scan data to the select and store circuits. The scan input enable circuit also includes a store circuit which operates with the first store circuit in a master-slave configuration. | 10-30-2014 |
| 20160006422 | LOW POWER FREQUENCY DIVIDER USING DYNAMIC MODULATED-LOAD LATCH - A dynamic latch is disclosed that may reduce power consumption in frequency dividers while widening their frequency operation ranges. The dynamic latch includes a sense component to detect an input voltage in response to a first state of a mode select signal, and to generate an output voltage based, at least in part, on the input voltage; a hold component to retain the output voltage in response to a second state of the mode select signal; and a first transistor, coupled between the sense component and ground potential, including a gate responsive to the mode select signal. | 01-07-2016 |
| 327201000 | Complementary clock inputs | 2 |
| 20080258788 | DYNAMIC DUAL OUTPUT LATCH - A dynamic latch includes a first stage for receiving an input data value and for providing true and complement logic values representing the input data value; a second stage for receiving the true and complement logic values into first and second dynamic node, when a control signal is active; and a holding that outputs the true and complement logic values while the control signal is active. The second stage may provide a feedback signal to the first stage to block propagation of changes in the input data value after the true and complement logic values have been received. The feedback signal may be derived, for example, from logic values on the dynamic nodes. A holding circuit may be provided. | 10-23-2008 |
| 20130113538 | DISCRETE SIGNAL CONSOLIDATION DEVICE AND METHOD AND AIRCRAFT WITH SAID DEVICE - A device and a method for eliminating transitions in discrete signals. The working of the device and method is based on allowing the charge of a capacitor with one state when the state opposite the state to which it has been assigned is produced and allowing their discharge through a corresponding capacitor when their state is active. The signal is advantageously consolidated without needing processors or programmes, is very simple, there is increased reliability, and the device can very easily be integrated in any sensor, such as those used in aircraft. | 05-09-2013 |
