Class / Patent application number | Description | Number of patent applications / Date published |
327153000 | With delay means | 38 |
20080224743 | SEQUENCE INDEPENDENT NON-OVERLAPPING DIGITAL SIGNAL GENERATOR WITH PROGRAMMABLE DELAY - A circuit for generating non-overlapping clock signals includes a programmable delayed reference clock signals circuit to produce a plurality of delayed reference clock signals and a plurality of delay clock signal generators, operatively connected to the programmable delayed reference clock signals circuit, to generate non-overlapping clock signals. Each delay clock signal generator includes a latch or flip-flop to control a delay in a rising edge of a clock signal and to output a first signal, another latch or flip-flop to control a delay in a falling edge of a delayed clock signal and to output a first signal, and a logic circuit to generate the clock signal from the first and second signals. The latches or flip-flops independently control a delay in the rising edge of the clock signal in response to one of the plurality of delayed reference clock signals. | 09-18-2008 |
20080303564 | ON CHIP TIMING ADJUSTMENT IN MULTI-CHANNEL FAST DATA TRANSFER - A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences. | 12-11-2008 |
20090051396 | Ring Oscillation Circuit, Delay Time Measuring Circuit, Testing Circuit, Clock Generating Circuit, Image Sensor, Pulse Generating Circuit, Semiconductor Integrated Circuit, and Testing Method Thereof - A ring oscillation circuit, which can operate the ring oscillation due to a positive feedback stably and continuously, is provided and it is applied to an accurate measurement of delay time and a measurement of timing accuracy in a jitter of a clock signal or the like with a high accuracy. A ring oscillation circuit comprises a delay circuit and a monostable multivibrator. An output of the delay circuit is connected to an input of the monostable multivibrator, an output of the monostable multivibrator is connected to an input of the delay circuit, and the delay circuit and the monostable multivibrator configure a positive feedback loop. An oscillation starting circuit for starting oscillation upon receipt of an input of a trigger pulse for triggering oscillation is provided on the positive feedback loop, or in the inside of the delay circuit or the monostable multivibrator. | 02-26-2009 |
20090102524 | TIMING CONTROL CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE - Disclosed is a timing control circuit that receives a first clock having a period T1, a group of second clocks of L different phases spaced apart from each other at substantially equal intervals and selection signals m, n supplied thereto and generates a fine timing signal delayed from the rising edge of the first clock signal by a delay td of approximately td=m·T1+n·(T2/L). The timing control circuit includes a coarse delay circuit and a fine delay circuit. The coarse delay circuit includes a counter for counting a rising edge of the first clock signal after an activate signal is activated and generates a coarse timing signal whose amount of delay from the first clock signal is approximately m·T1. The fine delay circuit comprises L-number of multiphase clock control delay circuits disposed in parallel, delays by n·T2/L the timing of sampling of the coarse timing signal by respective clocks of the group of L-phase second clocks, and takes the OR among the resulting delayed pulses to thereby produce the fine timing signal. | 04-23-2009 |
20090167380 | System and method for reducing EME emissions in digital desynchronized circuits - A system includes first and second synchronous circuits and an asynchronous circuit configured to receive input from the first synchronous circuit and to send output to the second synchronous circuit. First and second variable clock generators are configured to drive the first and second synchronous circuit. A delay circuit is configured in a pathway from the first variable clock generator to the second variable clock generator, the delay circuit being configured to add a delay to the pathway based upon a processing time or an expected processing time of the asynchronous circuit. The delay circuit is further configured to induce additional uneven delay into the pathway. The additional uneven delay disperses local current absorption, thereby decreasing overall electro magnetic emissions of the system. | 07-02-2009 |
20090174445 | Semiconductor devices, methods of operating semiconductor devices, and systems having the same - A semiconductor device includes a selection circuit and a phase detector. The selection circuit, in response to a first selection signal output from a controller, outputs as a timing signal a first clock signal output from the controller or an output signal of a PLL using the first clock signal as a first input. The phase detector generates a voltage signal indicating a phase difference between a second clock signal output from the controller and the timing signal output from the selection circuit. The semiconductor device further includes a data port, a memory core storing data, and a serializer, in response to the timing signal output from the selection circuit, serializing the data output from the memory core and outputting serialized data to the controller via the data port. The first selection signal is generated by the controller based on at least one of the voltage signal and the data output to the controller via the data port. | 07-09-2009 |
20090195274 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to the present invention comprises a clock tree circuit for delay-adjusting a clock signal using various delay amounts, and a clock synchronizing circuit to which the delay-adjusted clock signal is supplied. The clock tree circuit comprises a first clock tree cell provided in a poststage of a clock signal introducing terminal, a second clock tree cell provided in a prestage of the clock synchronizing circuit and a poststage of the first clock tree cell, and a clock ramification point provided in a prestage of the second clock tree cell. The clock synchronizing circuit comprises a first clock synchronizing circuit to which the clock signal delay-adjusted by the second clock tree cell and thereafter outputted from the clock tree circuit is supplied, and a second clock synchronizing circuit to which the clock signal outputted from the clock tree circuit at the clock ramification point is supplied. | 08-06-2009 |
20090251179 | CLOCK DISABLING CIRCUIT AND CLOCK SWITCHING DEVICE UTILIZING THE SAME - A clock disabling circuit includes a control unit, an OR gate, and a first AND gate. The control unit generates a first delay signal by delaying a selected enable signal when the selected enable signal is at a first level. The control unit generates a second delay signal by delaying the selected enable signal or by directly outputting the selected enable signal when the selected enable signal is at a second level. Delays of the first delay signal and the second delay signal are different. The OR gate generates an intermediate signal according to an output of the control unit and a processing signal. The first AND gate generates the processing signal according to the intermediate signal and a clock signal. A clock switching device and method and a clock disabling method are also disclosed. | 10-08-2009 |
20090278579 | Delay Line Calibration Mechanism and Related Multi-Clock Signal Generator - A delay line calibration mechanism includes a delay line, a phase detector, and a controller. The delay line receives an input pulse, a calibration pulse, a first delay selection signal, and a second delay selection signal, delays the input pulse for a delay period according to the first delay selection signal to output a delayed pulse, and delays the calibration pulse for a calibration delay period according to the second delay selection signal to output a delayed calibration pulse. The controller is for generating the input pulse, the calibration pulse, and a reference pulse. The controller also generates the first delay selection signal, and generates the second delay selection signal according to a phase difference signal. The phase detector is for generating the phase difference signal indicating the difference between the delayed calibration pulse and the reference pulse by comparing the delayed calibration pulse and the reference pulse. | 11-12-2009 |
20100007389 | MULTIPLE FREQUENCY SYNCHRONIZED PHASE CLOCK GENERATOR - Generation of multiple clocks having a synchronized phase relationship may reduce the size, complexity, power consumption, jitter and cost of circuitry while improving its functionality, performance, reliability and fault coverage. A multiple frequency clock generator may comprise an independent digital control oscillator (DCO) for generating a first clock and dependent DCOs for generating additional clocks that align at a common multiple frequency with the first clock with or without adjustment thereof. The independent and dependent DCOs may generate the first and additional clocks from a delay lock loop (DLL) by selecting a sequence of tap select signals. Tap select signals may be adjusted to maintain a desired phase and/or frequency of the first and additional clocks. Dependent DCOs may generate sequences of tap select signals based on the sequence of tap select signals generated by the independent DCO to incorporate adjustments, e.g., PLL error corrections. | 01-14-2010 |
20100026351 | System and Method to Improve the Efficiency of Synchronous Mirror Delays and Delay Locked Loops - A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore increase the efficiency, is disclosed. The invention includes taking a clock input signal and a clock delay or feedback signal, each having timing characteristics, and differentiating between four conditions based upon the timing characteristics of the signals. The phase detector and associated circuitry then determines, based upon the timing characteristics of the signals, which of a number of phase conditions the signals are in. Selectors select the signals to be introduced into the synchronous mirror delay or delay-locked loop by the timing characteristics of the phase conditions. The system is able to utilize the falling clock edge of the clock input signal, and the lock time is decreased under specific phase conditions. The invention increases the efficiency of the circuits by reducing the effective delay stages in the SMD or DLL while maintaining the operating range. | 02-04-2010 |
20100033216 | SYNCHRONIZATION CIRCUIT AND METHOD WITH TRANSPARENT LATCHES - A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock. | 02-11-2010 |
20100039149 | Programmable Delay Circuit Providing For A Wide Span Of Delays - According to an aspect of the present invention, one of multiple clock signals of different relative phases is selected based on a desired delay magnitude, and the digital values received on an input signal are then synchronized to an edge (“first edge”) of the selected clock signal to provide the digital values with the desired delay magnitude. In an embodiment, the selected clock signal can be delayed by a fine value (less than the minimum phase difference of the multiple clock signals) to provide a wide span of desired delays. An aspect of the invention provides for a synchronization circuit with reduced latency and which is substantially invariant to process, voltage and temperature (PVT) changes. | 02-18-2010 |
20100039150 | METHOD, CIRCUIT, AND DESIGN STRUCTURE FOR CAPTURING DATA ACROSS A PSEUDO-SYNCHRONOUS INTERFACE - A method for source synchronous communication. The method includes dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is synchronized with a local clock signal, and capturing data from a delayed data signal associated with the delay in a local domain. | 02-18-2010 |
20100127741 | Timing adjustment circuit, solid-state image pickup element, and camera system - A timing adjustment circuit includes at least one data line; a phase synchronization circuit that includes a plurality of oscillation delay elements which oscillate an oscillation signal, and that is configured to oscillate the oscillation signal by synchronizing a phase of a feedback clock with a phase of a reference clock; at least one delay circuit that includes a delay element which is disposed on the data line and which is equivalent to one of the plurality of oscillation delay elements, and that is configured to delay data which is to be transmitted on the data line; and a delay adjustment unit configured to adjust an amount of delay of the delay element of the delay circuit in accordance with a signal associated with oscillation of the phase synchronization circuit. | 05-27-2010 |
20100156480 | Control signal generation circuit - A control signal generation circuit includes a pulse signal generator configured to delay a column control signal by delay times different from each other and to generate first and second pulse signals, a reset signal generator configured to transfer alternatively the first and second pulse signals as a reset signal in response to a write/read flag signal, and a write-enable signal generator configured to generate a write-enable signal from the first pulse signal in response to the write/read flag signal. | 06-24-2010 |
20100164567 | INTERNAL SUPPLY VOLTAGE GENERATING CIRCUIT AND METHOD FOR GENERATING INTERNAL SUPPLY VOLTAGE - An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage. | 07-01-2010 |
20100164568 | LOW POWER VARIABLE DELAY CIRCUIT - A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units. | 07-01-2010 |
20100231274 | APPARATUS FOR OUTPUTTING DATA OF SEMICONDUCTOR INTEGRATED CIRCUIT - A data outputting apparatus of a semiconductor integrated circuit if presented for use in standardizing output timing brought about by different electrical output path lengths. The apparatus includes a data clock signal generating section and a data output section. The data clock signal generating section is configured to use an external clock signal in order to generate a plurality of data clock signals in which output timings of the data clock signals vary depending on a data output mode. The data output section is configured to be controlled by the plurality of data clock signals to output inputted data to the outside through a plurality of data input/output pads that have different path lengths. | 09-16-2010 |
20110018595 | METASTABILITY HARDENED SYNCHRONIZER CIRCUIT - A metastability hardened synchronizer circuit includes a plurality of transmission gates, each transmission gate responsive to an input signal and a clock signal to generate a driver signal. The synchronizer circuit also includes a plurality of latches. The plurality of latches includes a first one of the latches in electrical communication with any one of the plurality of transmission gates and responsive to a driver signal to resolve to a stable state and a second one of the latches in electrical communication with another transmission gate of the plurality of transmission gates and responsive to another driver signal to resolve to the stable state. | 01-27-2011 |
20110062999 | SOURCE-SYNCHRONOUS CLOCKING - Methods, circuits and systems for balanced distribution of source-synchronous clock signals are described. Multiple data sets together with one or more clock signals associated with the multiple data sets may be received at a number of interface devices. The multiple data sets may be captured in a number of data buffers. The clock signals may be programmably distributed to a group of the multiple data buffers that retain the one or more data sets, using a balanced clock network. Additional methods, circuits, and systems are disclosed. | 03-17-2011 |
20110163786 | MULTI-PHASE SIGNAL GENERATOR AND METHOD - A multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, a clock generator generates quadrature signals including those having 90, 180, 270 and 360 degrees phase difference with a first signal. The rising edge of an intermediate signal is compared with the rising edges of two of the other signals to generate an UP and DN pulse signal, respectively. The UP and DN signals are used to adjust the delay of a delay line producing the signals to synchronize the signals. In some embodiments, a reset signal generator is used to truncate the UP or DN signal pulse. | 07-07-2011 |
20110309865 | PARALLEL SYNCHRONIZING CELL WITH IMPROVED MEAN TIME BETWEEN FAILURES - In some embodiments, a synchronizing circuit includes at least one synchronization device that operates at a lower clock frequency than another synchronization device in the synchronization circuit. In at least one embodiment of the invention, a method includes sampling a first signal at a first frequency to thereby generate a plurality of sampled versions of the first signal. The first frequency is a frequency of a clock signal divided by N. N is a number greater than one. The method includes sampling a second signal at the frequency of the clock signal. The second signal is based on sequentially selected ones of the plurality of sampled versions of the first signal to thereby generate an output version of the first signal. | 12-22-2011 |
20120025878 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device includes a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals by mixing phases of first and second source clock signals having an identical frequency, a first clock transmission path configured to sequentially apply the first source clock signal to the plurality of synchronization clock generators by transferring the first source clock signal in a forward direction, a second clock transmission path configured to sequentially apply the second source clock signal to the plurality of synchronization clock generators by transferring the second source clock signal in a backward direction, and a plurality of data output units configured to synchronize a plurality of data with the plurality of synchronization clock signals and outputting the synchronized plurality of data. | 02-02-2012 |
20120038398 | METHODS AND APPARATUSES FOR CLOCK DOMAIN CROSSING - Clock-domain-crossing systems and methods include an integrator that accumulates input samples over multiple clock cycles in a first clock domain to generate an accumulation result. Clock-domain-crossing circuitry samples the accumulation result in the first clock domain after each of a repeating accumulation count to generate a first domain accumulation. The first domain accumulation is sampled in a second clock domain after a time delay to generate a second domain accumulation. The time delay ensures proper setup and hold time parameters for the second clock domain relative to the first clock domain. A differentiator generates output information in the second clock domain by delaying the second domain accumulation and subtracting the delayed second domain accumulation from the second domain accumulation. The systems and methods preserve temporal characteristics of the input information in the first clock domain when it is transferred to the second clock domain as the output information. | 02-16-2012 |
20120074994 | METHOD AND APPARATUS FOR ALIGNING PHASES OFA MASTER CLOCK AND A SLAVE CLOCK - The present invention discloses a method and apparatus for aligning the phases of a master clock and a slave clock; and the method comprises the following steps: A. locking a phase of a master clock; B. measuring phase difference between a slave clock and the master clock; and C. adjusting a phase output by the slave clock so as to align it with the phase of the master clock based on the phase difference measured in Step B. The present invention also discloses an apparatus for aligning the phases of a master clock and a slave clock. By measuring the phase difference between the master clock and the slave clock, and aligning the phases of the master clock and the slave clock according to the phase difference the present invention improves the precision of phase alignment without increasing costs. | 03-29-2012 |
20120212264 | COARSE LOCK DETECTOR - A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous. | 08-23-2012 |
20120242382 | PHASE ADJUSTER AND SEMICONDUCTOR APPARATUS - According to one embodiment, a phase adjuster operates according to a phase difference between a first clock signal and a second clock signal. The adjuster includes an adjustment driving element and a crosstalk driving element. The adjustment driving element drives an input signal and generates an adjusted signal. The crosstalk driving element generates an in-phase and/or a reverse-phase crosstalk signal in parallel to the adjusted signal when the phase difference occurs between the first clock signal and the second clock signal. | 09-27-2012 |
20120249194 | ROBUST GLITCH-FREE CLOCK SWITCH WITH AN UNATE CLOCK NETWORK - A system, method, and computer program product are provided for the switching of clock signals. A clock network switching system includes a first re-synchronization circuit coupled to a first input clock, and a second re-synchronization circuit coupled to a second input clock. There is also an input select decoder coupled to the first and second re-synchronization circuit that can dynamically select either the first or the second input clock to be active. When an input clock is selected to be active, the re-synchronization circuit associated with the selected input clock generates an output clock synchronized with the selected input clock where both a high pulse width and a low pulse width of the output clock are not less than those of the selected input clock. | 10-04-2012 |
20130057326 | SEMICONDUCTOR DEVICE USING MULTI-PHASE CLOCK SIGNAL AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1. | 03-07-2013 |
20140035636 | CLOCK SYNCHRONIZATION CIRCUIT - A method of synchronizing clock signals may include generating a replicated delay associated with a delay of a clock signal path. The clock signal path may be associated with communication of a slave clock signal by a master block of a circuit to a slave block of the circuit. The method may further include selecting the slave clock signal from one of multiple clock signals based on the replicated delay. Each of the multiple clock signals may have a same frequency and a different phase. | 02-06-2014 |
20140132317 | SEMICONDUCTOR DEVICE USING MULTI-PHASE CLOCK SIGNAL AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1. | 05-15-2014 |
20140139276 | MATRIX PHASE DETECTOR - A method and a system are provided for clock phase detection. A first set of delayed versions of a first clock signal is generated and a second set of delayed versions of a second clock signal is generated. The second set of delayed versions of the second clock signal is sampled using the first set of delayed versions of the first clock signal to produce an array of clock samples in a domain corresponding to the first clock signal. At least one edge indication is located within the array of clock samples. | 05-22-2014 |
20140184288 | SEMICONDUCTOR CIRCUIT AND METHOD FOR OPERATING THE SAME - Provided are a semiconductor circuit and method for operating the same. The semiconductor circuit includes a first flip-flop configured to, based on input data synchronized to a first clock, output first output data synchronized to a second clock different from the first clock, and a second flip-flop configured to, based on the first output data, output second output data synchronized to the second clock, wherein the first and the second flip-flops share an inverted second clock and a delayed second clock and output the first and the second output data based thereon, respectively. | 07-03-2014 |
20140312941 | COARSE LOCK DETECTOR - A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous. | 10-23-2014 |
20150042388 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes an enable signal generation unit configured to be inputted with a plurality of clocks which have different phases, and generate a plurality of enable signals; and a plurality of sampling units configured to output input data as sampling data in response to respective pairs of clocks of the plurality of clocks and respective ones of the plurality of enable signals. | 02-12-2015 |
20160043637 | CLOCKING CIRCUIT, CHARGE PUMPS, AND RELATED METHODS OF OPERATION - A charge pump includes a voltage multiplier core and a clocking circuit. The voltage multiplier core includes first and second cross-coupled CMOS devices, first and second output CMOS devices, a first capacitive node coupled between the first cross-coupled CMOS device and the first output CMOS device, and a second capacitive node coupled between the second cross-couple CMOS device and the second output CMOS device. The clocking circuit configured to control the first and second output CMOS devices to inhibit a drop in respective output voltages there from, while simultaneously controlling the first and second cross-coupled CMOS device and input voltages applied to the first and second capacitive nodes to minimize leakage from the first and second capacitive nodes. | 02-11-2016 |
20160191062 | Semiconductor Device and Method for Accurate Clock Domain Synchronization Over a Wide Frequency Range - A clock synchronization circuit has a clock sync detector. A first variable delay circuit is coupled to a first input of the clock sync detector. A controller is coupled to a digital output of the clock sync detector and a control input of the first variable delay circuit. A first clock signal is coupled to the first variable delay circuit. A second clock signal is coupled to a second input of the clock sync detector. The clock sync detector includes a first flip-flop and a first delay element coupled between the first variable delay circuit and a data input of the first flip-flop. A second variable delay circuit is coupled to a second input of the clock sync detector. A multiplexer is coupled between the first variable delay circuit and the first input of the clock sync detector. An offset compensation calibrates the clock sync detector. | 06-30-2016 |