| Entries |
| Document | Title | Date |
|---|
| 20080204090 | Glitch-free clock regeneration circuit - A clock regeneration circuit and method including an asynchronous clock signal input to a meta-stability filtering circuit, a synchronous clock signal input to the meta-stability filtering circuit with a frequency lower than the asynchronous clock signal, and being over-sampled and rate adapted to the asynchronous clock signal, an edge detector detecting an edge of the output of the meta-stability filtering circuit, a regenerated clock signal output therefrom, and a clock regeneration stage receiving an input that is the edge-detected output. | 08-28-2008 |
| 20080284473 | PHASE SYNCHRONOUS CIRCUIT - An external clock round-trips a round-trip delay block configured by a selector and a short delay array, and is made capable of corresponding to a wide frequency by generating a long delay time required for synchronization at the time of a low frequency operation. Further, when a plurality of phase comparators are disposed, in both cases where comparing phases all at once and comparing phases one after another, it is possible to complete the phase synchronization within a short time by making a delay amount variable. | 11-20-2008 |
| 20080290914 | Self-Clearing Asynchronous Interrupt Edge Detect Latching Register - A digital circuit may have at least two asynchronous clock domains with a controller responsive to a first domain clock signal and a target responsive to a second domain clock signal. A first domain control signal pulse is generated in response to the first domain clock signal for controlling the target. Each assertion the first domain control signal pulse is detected and used to form a second domain control signal pulse synchronized to the second domain clock signal. The target is controlled using the second domain control signal pulse. If the target is a clear-on-read register, contents of the clear-on-read register are latched in a feedback register in response to the first domain control signal pulse and provided to the controller. Each bit of the clear-on-read register is reset in response to the second domain control signal pulse only if the corresponding latched content of each bit in the feedback register is a logical one. | 11-27-2008 |
| 20100052744 | Multiphase Clock Generator with Enhanced Phase Control - A multi-phase clock generator circuit receives an input clock signal and produces multiple output clock signal, each from a respective delay stage of a multi-stage voltage-controlled delay line (VCDL). The rising edges of the multiple output clock signals produced by the circuit are substantially equidistant in time from one another and have substantially equal phase spacing. | 03-04-2010 |
| 20110221486 | DIGITALLY CALIBRATED HIGH SPEED CLOCK DISTRIBUTION - An electronic circuit for distributing a clock signal to a plurality of clock destinations includes phase adjustment circuits for adjusting phase shifts of the clock at the respective one of the clock destinations responsive to a respective DC voltage feedback signal receive from the respective one of the clock destinations; phase detectors for detecting a phase shift of the clock signal at the respective one of the clock destinations according to a nearest neighbor clock destination; and loop filters for generating and transmitting respective DC voltage feedback signals. | 09-15-2011 |
| 20120126865 | CLOCK REGENERATION CIRCUIT - A clock regeneration circuit according to an exemplary embodiment of the present invention is characterized in that a phase comparison result of serial data being inputted and a clock signal is shaped with use of the clock signal or another clock signal having a predetermined phase difference from the clock signal, and a phase of the clock signal is controlled with use of the shaped phase comparison result. | 05-24-2012 |
| 20130120033 | CHARGE-DOMAIN FILTER AND METHOD THEREOF - A charge domain filter (CDF) is provided. The CDF includes a switched-capacitor network (SCN) and a clock generator. An input of the SCN receives an input signal. The SCN samples the input signal according to clock signals with different phases. The clock generator is coupled to the SCN for providing the clock signals. The clock generator adjusts phase differences of the clock signals or pulse widths of the clock signals in accordance with a control signal. | 05-16-2013 |
| 20130229211 | TRANSMISSION/RECEPTION DEVICE AND INFORMATION PROCESSING DEVICE - A transmission/reception device includes a transmission circuit configured to apply a delay to at least one of a positive signal and a negative signal of differential signals to be sent to another device, detect a direction of a differential signal skew between the positive signal and the negative signal, to at least one of which the delay is applied, and control the delay in a manner as to reduce the differential signal skew; and a reception circuit configured to apply a delay to at least one of a positive signal and a negative signal of differential signals sent from another transmission/reception device, detect a direction of a differential signal skew between the positive signal and the negative signal, to at least one of which the delay is applied, and control the delay in a manner as to reduce the differential signal skew. | 09-05-2013 |
| 20140176203 | SYNCHRONIZATION OF NANOMECHANICAL OSCILLATORS - Synchronization of oscillators based on anharmonic nanoelectromechanical resonators. Experimental implimentation allows for unprecedented observation and control of parameters governing the dynamics of synchronization. Close quantitative agreement is found between experimental data and theory describing reactively coupled Duffing resonators with fully saturated feedback gain. In the synchonized state, a significant reduction in the phase noise of the oscillators is demonstrated, which is key for applications such as sensors and clocks. Oscillator networks constructed from nanomechanical resonators form an important laboratory to commercialize and study synchronization—given their high-quality factors, small footprint, and ease of co-integration with modern electronic signal processing technologies. Networks can be made including one-, two-, and three-dimensional networks. Triangular and square lattices can be made. | 06-26-2014 |
| 20140253192 | METHOD OF DISTRIBUTING A CLOCK SIGNAL, A CLOCK DISTRIBUTING SYSTEM AND AN ELECTRONIC SYSTEM COMPRISING A CLOCK DISTRIBUTING SYSTEM - A clock signal from a first electronic subsystem is distributed to a second electronic subsystem. The second electronic subsystem is remote from the first electronic subsystem and coupled to the first electronic subsystem by a bidirectional signal path. A first clock signal is generated on the first electronic subsystem and a training signal is generated on the first electronic subsystem clocked by the first clock signal. The training signal is sent on the bidirectional signal path on a round trip to the second electronic subsystem and back to the first electronic subsystem. A phase of the training signal is adjusted symmetrically on the way to the second electronic subsystem in a first phase adjuster and on the way back to the first electronic subsystem in a second phase adjuster until the measured time for the round trip is equal to an even number of clock cycles. | 09-11-2014 |
| 20150323960 | METHOD FOR ASYNCHRONOUS GATING OF SIGNALS BETWEEN CLOCK DOMAINS - An apparatus for synchronizing a signal from a first clock domain into a second clock domain is disclosed. The apparatus may include circuitry, a synchronization circuit, and a clock gate circuit. The circuitry may de-assert a first enable signal dependent upon a first clock signal. The synchronization circuit may generate a second enable signal synchronized to a second clock signal and may de-assert the second enable signal in response to de-asserting the first enable signal. The clock gate circuit may generate a third clock signal dependent upon the second clock signal, and may disable the third clock signal responsive to de-asserting the second enable signal. The circuitry may further disable the second clock signal in response to determining a predetermined period of time has elapsed since de-asserting the first enable signal. | 11-12-2015 |
