Entries |
Document | Title | Date |
20080238498 | CLOCK GENERATOR, METHOD FOR GENERATING CLOCK SIGNAL AND FRACTIONAL PHASE LOCK LOOP THEREOF - A clock generator includes a delta sigma modulator, a counter and a first phase lock loop. The delta sigma modulator sequentially generates a plurality of variable parameters according to a predetermined value and a first input clock signal. The counter, which is connected to the delta sigma modulator, is used to generate an output clock signal in accordance with a counting value and a second input clock signal. The counting value is relevant to the variable parameters. The first phase lock loop, which is connected to the output of the counter, is used to generate an objective clock signal in accordance with the output clock signal. | 10-02-2008 |
20080258780 | FREQUENCY DIVIDER - A frequency divider using a clock source with a plurality of phase signals of a multi-phase oscillator. In one version, the divider includes a plurality of spot-moving stages that are connected to form a ring. Spot-moving stages are stages that advance a one or a zero, while clearing the previous stage. Depending on the number of stages and the number of phases of the clock to advance a spot through all of the stages, a divider ratio is determined. In another embodiment, a plurality of latch elements is provided with a divided input and each is re-clocked with the phases of a multi-phase oscillator. The outputs of the latch elements are combined in a capacitor array to create the output waveform. An interpolator useful in conjunction with a frequency divider is also disclosed. When the interpolator is placed in the feedback path of a PLL, a fractional frequency multiplier/divider results. | 10-23-2008 |
20080258781 | Multi-Bit Programmable Frequency Divider - A multi-bit, programmable, modular digital frequency divider divides an input frequency by an m-bit integer divisor to produce an output frequency. The integer divisor re-initializes m-number of flip-flop stages with the divisor input at the end of every output clock. Each divisor bit is gated to a D-input through a respective data multiplexer controlled by a clock output. A run/initialize mode controller receives the input frequency and produces the divided output frequency and controls the timing of the re-initialization. | 10-23-2008 |
20080258782 | Oscillating divider topology - An oscillator includes a first circuit that asynchronously generates an oscillating signal in response to a second circuit of the oscillator acknowledging each cycle of the oscillating signal. | 10-23-2008 |
20090009220 | Signal generating apparatus, periodic-signal observing system, integrated circuit, periodic-signal observing method, and method of testing integrated circuit - A signal generating apparatus having an LSI circuit in which a plurality of cycle-observing signals are generated to be output via an I/O circuit to a device outside the LSI circuit in order to observe a prescribed periodic signal in the LSI circuit. The apparatus includes: a frequency-dividing circuit that frequency-divides the periodic signal at a preset frequency division ratio; and a delay circuit that imparts a prescribed phase difference to the signal to be frequency-divided by the frequency-dividing circuit, thereby obtaining a plurality of signals that differ in phase from one another. | 01-08-2009 |
20090085616 | SEMICONDUCTOR INTEGRATED CIRCUIT, COMMUNICATION APPARATUS, INFORMATION PLAYBACK APPARATUS, IMAGE DISPLAY APPARATUS, ELECTRONIC APPARATUS, ELECTRONIC CONTROL APPARATUS AND MOBILE APPARATUS - The semiconductor integrated circuit having a transmitter circuit for transmitting a supplied external data signal DIN. The transmitter circuit includes: a transmitter flip-flop circuit having a reference clock CK as an input for holding the external data signal DIN in synchronization with the reference clock CK; a frequency divider circuit for multiplying the frequency of the reference clock CK by n/m (m and n are integers equal to or more than 2 and m>n); a data signal buffer circuit for transmitting a data signal held by the transmitter flipflop circuit; and a clock buffer circuit for transmitting the output of the frequency divider circuit. | 04-02-2009 |
20090091361 | Frequency divider configuration - A frequency divider including at least one frequency divider cell having an adjustable circuit configuration which may be selected adaptively according to properties of an oscillator signal to be frequency-divided in the frequency divider. Accordingly, the circuit configuration of the frequency divider may be changed on the fly during the operation. | 04-09-2009 |
20090102521 | CIRCUIT AND OSCILLATING APPARATUS - A circuit includes a logic circuit containing a first transistor and a second transistor which are connected in series to each other between a high power supply and a low power supply in such a manner that an emitter of one of the first and second transistors is connected to a collector of the other of the first and second transistors. The first transistor is positioned closer to the high power supply, and the second transistor is positioned closer to the low power supply. The logic circuit operates in accordance with voltages input into bases of the first and second transistors. The circuit further includes a current amplifying circuit containing a third transistor whose collector is connected to one of the high and low power supplies, whose emitter is connected to the other of the high and low power supplies, and whose base is connected to an output from the logic circuit. The current amplifying circuit amplifies a current of a logic signal from the logic circuit and feeds, from the emitter of the third transistor, the current-amplified logic signal back to the base of the second transistor. | 04-23-2009 |
20090115466 | SEMICONDUCTOR APPARATUS AND RADIO CIRCUIT APPARATUS USING THE SAME - A semiconductor apparatus includes a signal source 7 that outputs a signal of predetermined frequency, a frequency divider 15 that receives the output signal of the signal source and is capable of switching the output signal to two or more frequency division ratios, a delta-sigma modulator 16 that controls the frequency division ratio of the frequency divider, and a bandpass filter 17 that receives an output of the frequency divider. The frequency of the input signal of the frequency divider is divided by the frequency division ratio controlled by the delta-sigma modulator, and quantization noise appearing in the output of the frequency divider generated by the delta-sigma modulator is attenuated with the bandpass filter. The semiconductor apparatus easily can convert a signal output by a single signal source to a signal of predetermined frequency and supply a plurality of signals of predetermined frequency using a simple configuration with reduced chip size. | 05-07-2009 |
20090115467 | Semiconductor device and operation method thereof - A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference. | 05-07-2009 |
20090160501 | CONTROL SIGNAL GENERATING CIRCUIT ENABLING VALUE OF PERIOD OF A GENERATED CLOCK SIGNAL TO BE SET AS THE PERIOD OF A REFERENCE SIGNAL MULTIPLIED OR DIVIDED BY AN ARBITRARY REAL NUMBER - A pulse signal circulates around a ring of delay elements with respective traversal signals being thereby successively outputted from the delay elements. The period of a reference signal is multiplied or divided by a real number to obtain control data specifying a required period of a clock signal as a value having an integer part and a fractional part. The control data are used to select the timings of specific traversal signal, and the clock signal is generated based these selected timings, with the timing selection being repetitively adjusted in accordance with the fractional part of the control data. | 06-25-2009 |
20090167375 | Signal Generation System - A signal generation system maintains a phase relationship between output signals of first and second signal generators even when the sampling clock frequency is changed. The signal generators are coupled via a communication means including a dedicated cable where the delay amount of the communication means is known and fixed. The first signal generator provides sampling clock, sequence clock and trigger/event signals to the second signal generator and CPUs of the generators share information via the cable. When the frequency of the sampling clock is changed, the CPU of the first or second signal generator calculates the clock number of the frequency changed sampling clock equivalent to the delay amount of the communication means. A delay circuit of the first signal generator | 07-02-2009 |
20090219063 | METHODS AND ARTICLES OF MANUFACTURE FOR OPERATING ELECTRONIC DEVICES ON A PLURALITY OF CLOCK SIGNALS - Embodiments of the invention relate to an integrated circuit comprising at least one functional unit configured to operate at a first clock frequency. The integrated circuit also comprises at least one first interconnect originating from a contact pad and leading to at least one frequency divider configured to receive a clock signal having a second frequency and generate one or more clock signals to operate the functional unit at the first frequency. The integrated circuit further comprises at least one second interconnect coupling an output of the frequency divider and an input of the functional unit, wherein a total length of the second wired interconnect is less than a total length of the first wired interconnects. | 09-03-2009 |
20090237128 | High frequency fractional-N divider - A divider can include a phase selection circuit that switches between a plurality of phase-separated clock signals in response to a fractional control signal to form a selected clock signal, the selected clock signal being utilized to generate a second clock signal; and a counter that receives the second clock signal and generates the fractional control signal and a transition control signal, the transition control signal indicating when the second clock signal should switch states in response to a transition of the selected clock signal, the counter generating a feed-back clock signal. | 09-24-2009 |
20090243668 | FREQUENCY DIVIDER SPEED BOOSTER - Embodiments of the present invention synthesize a core frequency divider by adding a switching feedback shell and using multiple clock edges to trigger the frequency divider. Feedback logic is used to determine which edge will be used. Embodiments allow multiple recursive use, which boosts the overall speed resulting frequency divider circuit 2 | 10-01-2009 |
20090295436 | ELECTRONIC CIRCUIT, FREQUENCY DIVIDER AND RADIO SET - A master stage | 12-03-2009 |
20090302900 | FREQUENCY DIVIDING DEVICE - In a frequency dividing device, a 1/P frequency divider subjects an input clock signal to 1/P frequency division. A phase shifter shifts the phase of the 1/P frequency signal and outputs multiple different Q-phase signals. A switch controls phase shifting in accordance with a division ratio control signal, to switch the Q-phase signals from one to another. A 1/R frequency divider subjects the output from the switch to 1/R frequency division and outputs an Rth frequency clock signal. A ½ frequency divider subjects the Rth frequency clock signal to ½ frequency division and outputs a frequency divided clock signal. A division ratio setter receives a division ratio set signal and generates the division ratio control signal. As a division ratio, P×R×2−2×P/Q, P×R×2−P/Q, P×R×2, P×R×2+P/Q, and P×R×2+2×P/Q can be set. | 12-10-2009 |
20090322386 | PROGRAMMABLE DIVIDER APPARATUS AND METHOD FOR THE SAME - A programmable divider apparatus comprises a first divider, a second divider, a feedback control unit, and a plurality of control signals. The first divider provides a frequency division operation of division by at least three integers, the second divider is cascaded to the first divider to provide a frequency division operation of division by two integers. The feedback control unit is coupled to between the first divider and the second divider to provide a feedback control signal to selectively supply an output of the second divider to an input of the first divider. The apparatus control signals and the feedback control signal are used to execute the first divider or the second divider. | 12-31-2009 |
20100052738 | FREQUENCY DIVIDER FOR WIRELESS COMMUNICATION SYSTEM AND DRIVING METHOD THEREOF - A frequency divider for a wireless communication system is provided. A frequency divider includes a body bias voltage generator and a divider. The body bias voltage generator generates a body bias voltage including a PMOS body bias voltage and an NMOS body bias voltage whose voltage levels are controlled according to an input signal. The divider includes a plurality of flip-flops whose operation points are determined according to the body bias voltage, and generates an output signal by dividing a frequency of the input signal by N. Each of the flip-flops may include a PMOS logic and an NMOS logic. The PMOS logic may include a plurality of PMOS transistors whose operation points are determined according to the PMOS body bias voltage. The NMOS logic may be connected electrically to the PMOS logic and include a plurality of NMOS transistors whose operation points are determined according to the NMOS body bias voltage. | 03-04-2010 |
20100052739 | Device and control method of device - A frequency divider section generates a frequency-divided clock RSELO by dividing the frequency of an internal clock LCLK, which lags behind an external clock in phase, and generates a delayed frequency-divided clock RSELI by delaying the frequency-divided clock RSELO. A signal input from the outside in synchronization with an internal clock PCLK which lags behind the external clock in phase is held in a latch circuit in synchronization with the delayed frequency-divided clock RSELI. Then, an output signal of the latch circuit is read into a latch circuit in synchronization with the frequency-divided clock RSELO and is output as a signal which is synchronized with the internal clock LCLK. In addition, a frequency divider section includes a variable divider which divides the frequency of the internal clock LCLK by a predetermined divide ratio which can be changed. | 03-04-2010 |
20100052740 | CLOCK SIGNAL FREQUENCY DIVIDING CIRCUIT AND CLOCK SIGNAL FREQUENCY DIVIDING METHOD - To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test costs are small. A clock signal frequency dividing circuit, the frequency division ratio of which is specified as N/M where are both N and Mare integers, includes an output clock selecting circuit ( | 03-04-2010 |
20100073040 | FREQUENCY DIVIDER USING LATCH STRUCTURE - There is provided a frequency divider using a latch structure including: a first latch sampling and latching an input signal in response to a first clock signal and a second clock signal having an inverse phase with respect to the first clock signal; a second latch toggled with the first latch, the second latch sampling and latching the input signal in response to the first and second clock signals; a bias adjustor generating a sampling bias current and a latching bias current to supply to the first and second latches, respectively and adjusting a relative ratio between the sampling bias current and the latching bias current to vary a minimum power point oscillating frequency of the first and second latches. | 03-25-2010 |
20100085085 | FREQUENCY SYNTHESIZER, FREQUENCY PRESCALER THEREOF, AND FREQUENCY SYNTHESIZING METHOD THEREOF - A frequency synthesizer is provided, including a voltage-controlled oscillator (VCO), a frequency prescaler, a divide-by-2.5 circuit, and a selector. The VCO determine the frequency of a first signal according to an input voltage. The frequency prescaler determines the frequency of a second signal to be the frequency of the first signal divided by 3, 3.5, or 4 according to a first selection signal, and the frequency prescaler also determines the frequency of a third signal to be the frequency of the first signal divided by 6, 7, or 8 according to the first selection signal. The divide-by-2.5 circuit generates a fourth signal, wherein the frequency of the fourth signal is the frequency of the first signal divided by 2.5. The selector selects one of the second signal, the third signal, and the fourth signal as a fifth signal according to a second selection signal. | 04-08-2010 |
20100085086 | Digital Frequency Detector - In one embodiment, a method is described that includes receiving a first clock signal and a second clock signal; dividing the first clock signal by a value of n to generate a divided first clock signal; sampling the frequency detector the divided first clock signal with the second clock signal to generate a plurality of samples; generating a first adjustment signal if more than a predetermined number of consecutive samples in a set of consecutive samples have identical logical values; and generating a second adjustment signal if less than the predetermined number of consecutive samples in the set of consecutive samples have identical logical values. | 04-08-2010 |
20100097106 | Novel double-feedback flexible non-integer frequency division circuit - An embodiment of this invention combines feed-forward and feedback frequency division circuits in a such a way, to provide greater flexibility in choosing the non-integer division ratios at the output, with little added complexity. Alternate embodiments include additional divider(s) in signal or feedback paths providing additional flexibility and design simplification. An embodiment uses in-phase/quadrature signals to select the desired modes at feedback-path and signal-path mixers. Various alternatives are also described. | 04-22-2010 |
20100141305 | Method For Carrying Out A Frequency Change - The invention relates to a method for carrying out a frequency change whilst retaining the phase relationship between several devices, in particular, network analyzers. Each device has at least one signal generator for stimulating an object for measurement and at least one local oscillator, connected to at least one mixer, for receiving a measuring signal obtained from the object for measurement by the superposition principle. On changing frequency, in a first step, only the frequency of the local oscillators of all devices is changed and the frequency of the signal generators of all devices remains unchanged. In a second step, only the frequency of at least one signal generator is changed and the frequency of the local oscillators of all devices remains unchanged. | 06-10-2010 |
20100141306 | PARALLEL-SERIAL CONVERSION CIRCUIT AND DATA RECEIVING SYSTEM - A parallel-serial conversion circuit includes: a plurality of data terminals each receiving a data signal; a selection circuit configured to select at least one of the data signals received through the plurality of data terminals; a first latch circuit configured to latch an output from the selection circuit based on a clock signal; a replica selection circuit configured to select one of a plurality of signals and output the selected signal; and a timing-signal generating circuit configured to generate a timing signal for controlling the selection circuit based on the output from the replica selection circuit, wherein the output from the replica selection circuit is latched based on the clock signal. | 06-10-2010 |
20100164561 | SYSTEM AND METHOD FOR WIDEBAND PHASE-ADJUSTABLE COMMON EXCITATION - A power generator system and apparatus that uses a frequency synthesizer in conjunction with an oscillator to lock both frequency of a drive signal with a reference signal. The oscillator center frequency is different from the nominal generator frequency, and as a consequence a variety of reference frequencies may be supported. By using a frequency synthesizer, the oscillator frequency can be locked onto a frequency that is a ratio of the reference frequency. Then, the frequency synthesizer may generate a drive signal that is closely matched to the reference frequency. | 07-01-2010 |
20100201409 | Frequency Divider Circuit - A frequency divider circuit includes: a shift register capable of storing at least n-bit data configured to shift an input signal sequentially in synchronization with a clock signal; a pulse generating circuit configured to change the input signal into a pulse form in response to a change in logic level of an output signal from a stage of the shift register among n-bit output signals from the shift register, the stage corresponding to a bit resulting from shifting of the input signal by n bits; and a frequency dividing signal generating circuit configured to generate a frequency dividing signal whose logic level is inverted in response to a change in logic level of an output signal from any one stage of the shift register or logic level of the input signal, in order to divide the clock signal in frequency by a dividing ratio corresponding to the n bits. | 08-12-2010 |
20100213991 | DELAY-LOCKED LOOP CIRCUIT AND METHOD FOR SYNCHRONIZATION BY DELAY-LOCKED LOOP - A delay-locked loop circuit has an adjustment period setting module configured to set a rough adjustment period and a fine adjustment period, a delay time adjustment module configured to increase or decrease a delay stage by a first unit or by a second unit based on a delay stages setting value to generate a second signal by delaying a first signal, a delay module configured to generate a third signal by delaying the second signal by a predetermined time, a phase comparator configured to detect a phase difference between the first signal and the third signal, and a delay controller configured to generate the delay stages setting value based on the phase difference in order to increase or decrease the number of delay stages by the first unit when the rough adjustment period is set and to increase or decrease the number of delay stages by the second unit when the fine adjustment period is set. | 08-26-2010 |
20100301907 | SYSTEM AND METHOD FOR SECURE REAL TIME CLOCKS - A secure real time clock (RTC) system is provided, comprising a secure RTC, a frequency signal generator, and a frequency adjuster connected between the secure RTC and the frequency signal generator to receive a signal having a first frequency from the frequency signal generator. On receipt of a first control signal the frequency adjuster outputs the signal having the first frequency to the secure RTC, and on receipt of a second control signal the frequency adjuster adjusts the signal having the first frequency to generate a signal having a second frequency, the second frequency being lower than the first frequency, and outputs the signal having the second frequency to the secure RTC. A clock line transmits the signal having the first frequency and the signal having the second frequency from the frequency adjuster to the secure RTC, and has a first power consumption when transmitting the signal having the first frequency and a second power consumption when transmitting the signal having the second frequency, the first power consumption being greater than the second power consumption. | 12-02-2010 |
20100315131 | Programmable Frequency Divider with Full Dividing Range - A programmable frequency divider with a full dividing range includes a plurality of cascaded 2/1 frequency dividers. Each of the 2/1 frequency dividers has a first input node, a first output node, a second input node, a second output node and a third input node. The first input node receives a first clock signal divided by the 2/1 frequency divider and outputted as a second clock signal through the first output node. A second logical signal is generated according to the second clock signal, the first clock signal and a first logical signal received from the second input node. The 2/1 frequency divider selectively switches to perform a divide-by-two or divide-by-one operation according to the second logical signal and a first divisor signal received from the third input nodes. The programmable frequency divider provides the full dividing range as the result of utilizing various divisor of the 2/1 frequency divider. | 12-16-2010 |
20100315132 | PEAK POWER REDUCTION METHODS IN DISTRIBUTED CHARGE PUMP SYSTEMS - A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage. | 12-16-2010 |
20110006816 | Method and Apparatus for Generating Frequency Divided Signals - In a method for dividing a frequency of a clock signal, a first frequency divided signal is generated based on a clock signal. Rising edges in the first frequency divided signal are detected. Alternatively, falling edges in the first frequency divided signal are detected. An edge detection signal that includes a pulse for each detected edge is generated. A second frequency divided signal is generated based on the edge detection signal. | 01-13-2011 |
20110012647 | FREQUENCY DIVIDER WITH A CONFIGURABLE DIVIDING RATIO - A method for dividing the frequency of a signal using a configurable dividing ratio is disclosed. An input signal with a first frequency is received at clocked switches in a frequency divider with a configurable dividing ratio. Non-clocked switches inside the frequency divider are operated to select one of multiple dividing ratios. An output signal is output with a second frequency that is the first frequency divided by the selected dividing ratio. | 01-20-2011 |
20110025382 | FREQUENCY DIVIDER - A frequency divider ( | 02-03-2011 |
20110084738 | LOW-POWER FREQUENCY DIVIDER AND LOW-POWER PHASE-LOCKED LOOP EQUIPPED THEREWITH - A low power frequency divider and a low power phase locked loop, which consume the least power. The low power frequency divider generates a frequency dividing signal by dividing a frequency of an input signal in a uniform ratio, and includes a phase to voltage converter, a comparator, a phase synchronization circuit, and a reset circuit. The phase to voltage converter generates a phase voltage signal corresponding to phase change of the input signal in response to a reset signal. The comparator generates a comparator signal by comparing the phase voltage signal and a reference phase voltage signal. The phase synchronization circuit generates the frequency dividing signal by matching phases of the input signal and the comparator signal. The reset circuit generates the reset signal in response to the comparator signal or the frequency dividing signal. | 04-14-2011 |
20110115531 | PLL CIRCUIT - A PLL comprises a current-controlled oscillator ( | 05-19-2011 |
20110121869 | FREQUENCY DIVIDER SYSTEMS AND METHODS THEREOF - At least one example embodiment provides for a frequency divider system including a delay unit configured to receive a first input clock signal having a first input clock frequency and a requirement and output a modified clock signal, and a frequency divider configured to receive the modified clock signal and output an output clock signal having an output clock frequency. The output clock frequency is an odd or even integer division of the first input clock frequency based on the requirement such as an input control word. | 05-26-2011 |
20110128052 | CLOCK HAND-OFF CIRCUIT - A second latch latches the output data of a first latch using a third clock having the same frequency as that of a first clock. A third latch latches the output data of the second latch using a second clock having a frequency N (N represents an integer) times that of the first clock and the third clock. The second clock and the third clock have a frequency division/multiplication relation therebetween. | 06-02-2011 |
20110163784 | FRACTIONAL FREQUENCY DIVIDER - A fractional-n frequency divider that overcomes the presence of so-called dead zones in known frequency divider circuits, n divider cells ( | 07-07-2011 |
20110187419 | SEMICONDUCTOR INTEGRATED CIRCUIT AND VOLTAGE CONTROLLER THEREWITH - A semiconductor integrated circuit is capable of accurately detecting the characteristics of a chip. The semiconductor integrated circuit includes a monitor circuit and a control circuit. The control circuit generates a clock pulse signal having M successive pulses (M is 2 or a greater integer), and outputs the clock pulse signal to the monitor circuit. The monitor circuit includes a frequency divider and a ring oscillator. The frequency divider frequency divides the clock pulse signal by M and generates the resulting signal as an enable signal. The ring oscillator generates an oscillation signal as a monitor output value during a period defined in accordance with the enable signal. | 08-04-2011 |
20110204931 | PEAK POWER REDUCTION METHODS IN DISTRIBUTED CHARGE PUMP SYSTEMS - A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage. | 08-25-2011 |
20110215843 | Frequency Generator - A frequency generator comprising an oscillator that generates I and Q signals and a prescaler with a clock phase generator that uses the I and Q signals as input and can generate a predetermined number of phases, a switch bank with a number of switches corresponding to the number of phases that can be generated by the clock phase generator, and a clock select logic component. The prescaler comprises a state machine that can assume a predetermined number of states as output. The output state is input to the clock select logic component and determines which switch to use as output from the switch bank and as “clock” input to the state machine, with one of the outputs of the state machine being a signal f | 09-08-2011 |
20110248752 | CLOCK SIGNAL GENERATORS HAVING A REDUCED POWER FEEDBACK CLOCK PATH AND METHODS FOR GENERATING CLOCKS - Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by a adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal. | 10-13-2011 |
20120038396 | INJECTION LOCKED FREQUENCY DIVIDER AND PLL CIRCUIT - An injection locked frequency divider and a PLL circuit, having a wide operating frequency bandwidth and capable of reducing the influence of any parasitic capacitance, are provided. Injection locked frequency divider ( | 02-16-2012 |
20120119798 | METHOD AND DEVICE FOR DIVIDING A FREQUENCY SIGNAL - A method for dividing a frequency includes the steps of receiving a first signal having a first frequency as a clock input to a first digital counter and outputting a second signal as a clock input to a second digital counter having a higher counting capacity than the first counter. The output occurs when the first counter reaches a first number of count cycles. The method also includes generating a third signal having a high cycle and a low cycle, which are determined at least as a function of the first number of count cycles. Depending on a desired division ratio, the high and low cycles may also be a function of a second number of count cycles associated with the second counter. The third signal has a frequency lower than the first frequency. | 05-17-2012 |
20120169383 | LEVEL CONVERSION CIRCUIT AND SEMICONDUCTOR DEVICE - A first conversion circuit converts a first clock signal based on a signal level of a first voltage into a second clock signal based on a signal level of a second voltage. A flip-flop circuit supplied with the first voltage as an operation voltage latches and outputs a signal, which is based on the signal level of the first voltage, in accordance with the first clock signal. A second conversion circuit supplied with the second voltage as an operation voltage converts a signal level of an input signal, which is based on an output signal of the flip-flop circuit, into the signal level of the second voltage in synchronization with the second clock signal. | 07-05-2012 |
20120169384 | FREQUENCY DIVIDER ARRANGEMENT AND METHOD FOR PROVIDING A QUADRATURE OUTPUT SIGNAL - A frequency divider arrangement for providing a quadrature output signal with a quadrature output signal frequency, includes a signal source for providing a base signal with a base signal frequency at the output side. Further, the frequency divider arrangement includes a first integer number quadrature divider with a first divider ratio for receiving the base signal on the input side and for providing a first quadrature signal with a first quadrature signal frequency according to the first divider ratio of the first integer number quadrature divider. | 07-05-2012 |
20120176165 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a mixer circuit unit having a first single gate mixer configured to receive a first input signal having a first frequency and a second input signal having a second frequency as inputs, a second single gate mixer configured to receive the first input signal and a third input signal of a phase inverted from a phase of the second input signal as inputs, a third single gate mixer configured to receive a fourth input signal of a phase inverted from the phase of the first input signal and the second input signal as inputs, and a fourth single gate mixer configured to receive the third and the fourth input signals as inputs; and a ½-frequency divider unit configured to receive output signals from the first to the fourth single gate mixers as inputs and output a desired signal. | 07-12-2012 |
20120194228 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus may include a transmission control signal generation unit, a fuse signal transmission unit, a reception control signal generation unit and a fuse signal reception unit. The transmission control signal generation unit receives a clock signal and generates a plurality of divided clock signals based on the clock signal to output transmission control signals from the plurality of divided clock signals. The fuse signal transmission unit transmits fuse information in synchronization with the transmission control signals. The reception control signal generation unit receives the clock signal and generates the plurality of divided clock signals, and generates reception control signals based on the plurality of divided clock signals. The fuse signal reception unit receives the fuse information in synchronization with the reception control signals. | 08-02-2012 |
20120242378 | FREQUENCY DIVIDER CIRCUIT - A frequency divider circuit is described. The frequency divider circuit includes a first cross-coupling. The first cross-coupling includes a first cross-coupled transistor with a first gate. The first gate is separately biased. The first cross-coupling also includes a second cross-coupled transistor with a second gate. The second gate is separately biased. The first gate is coupled to the second cross-coupled transistor and the second gate is coupled to the first cross-coupled transistor. | 09-27-2012 |
20120242379 | VARIABLE FREQUENCY CIRCUIT CONTROLLER - Apparatus and methods for distributing spurious tones through the frequency domain are disclosed. One such apparatus can include a dithering circuit configured to generate a sequence of numbers that exhibit statistical randomness and a variable frequency circuit configured to adjust a frequency of an output based on the sequence of numbers so as to spread energy of spurious tones in a frequency response of the output to lower a noise floor. In one example, spurious tones can be reduced in a negative voltage generator of a radio frequency (RF) attenuator. | 09-27-2012 |
20120268171 | CLOCK SIGNAL GENERATORS HAVING A REDUCED POWER FEEDBACK CLOCK PATH AND METHODS FOR GENERATING CLOCKS - Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by a adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal. | 10-25-2012 |
20120313673 | FREQUENCY DIVIDER WITH RETIMED CONTROL SIGNAL AND RELATED FREQUENCY DIVIDING METHOD - A frequency divider includes a phase selection circuit, control circuit and a retiming circuit. The phase selection circuit is arranged to receive a plurality of input signals with different phases, and generate an output signal by selectively outputting one of the input signals according to a plurality of retimed signals. The control circuit is arranged to receive the output signal to generate a plurality of control signals. The retiming circuit is arranged to retime the control signals to generate the retimed signals according to the input signals | 12-13-2012 |
20120313674 | High-Speed Non-Integer Frequency Divider Circuit - The invention relates to a high-speed non-integer frequency divider circuit for use in generating frequencies in a communication device, comprising: at least four bi-stable memory devices each having an input terminal, a clock terminal and an output terminal for outputting an output signal. The high-speed non-integer frequency divider circuit is characterized in that the at least four bi-stable memory devices are arranged in a cascaded chain such that each bi-stable memory device following the first bi-stable memory device receives the output signal of a previous bi-stable memory device in the cascaded chain at its input terminal and such that at least one of the output signals of the last bi-stable memory device is used to control the input terminal of the first bi-stable memory device, and in that the frequency divider circuit further comprises a clocking arrangement adapted to provide an in-phase clock signal, a quadrature clock signal, an inverse of the in-phase clock signal and an inverse of the quadrature clock signal to the clock terminals of each of the at least four bi-stable memory devices such that a combination of output signals from the at least bi-stable memory devices produces a frequency divided output signal of the frequency divider circuit having a frequency division ratio of fourths of the frequency of the in-phase clock signal. The invention also relates to a frequency synthesizer and a communication device. | 12-13-2012 |
20130015892 | DOUBLE-POINT MODULATOR WITH ACCURATE AND FAST GAIN CALIBRATIONAANM Badets; FranckAACI VoironAACO FRAAGP Badets; Franck Voiron FRAANM Ramet; SergeAACI JarrieAACO FRAAGP Ramet; Serge Jarrie FRAANM Ayraud; MichelAACI VoreppeAACO FRAAGP Ayraud; Michel Voreppe FR - A phase-locked loop double-point modulator may include a frequency divider having a ratio which can be changed by a first modulation signal, and an oscillator, a frequency of which can be changed by a second modulation signal correlated to the first modulation signal. A calibration circuit may be configured, in a calibration mode, to match the gains of the first and second modulation signals based on frequency measurements of the oscillator for two different calibration values of the second modulation signal. The phase-locked double-point modulator may also include an attenuator having a constant ratio greater than 1 and placed in the path of the second modulation signal, and a selector switch configured to be controlled by the calibration circuit to reduce the ratio of the attenuator in the calibration mode. | 01-17-2013 |
20130027093 | PLL - One embodiment provides a phase-locked loop (PLL), in which a sequencer controls a loop filter such that, when a signal indicating turning-off of a power supply of the PLL is input thereto, or when a signal indicating turning-on of the power supply of the PLL is input thereto, a resistance value of a first resistance change device in the loop filter is a first resistance value, and that, after the PLL is stabilized, the resistance value of the first resistance change device is a second resistance value which is higher than the first resistance value. | 01-31-2013 |
20130069696 | Fractional-N Phase Locked Loop - A frequency division circuit with a rational-valued division ratio includes a frequency divider with a selectable integer-valued division ratio supplied with an input signal of a first frequency. An output signal provides a second frequency. A first sigma-delta modulator provides a first modulated control signal representative of a first fractional number. A second sigma-delta modulator provides a second modulated control signal of a second fractional number. The integer-valued division ratio of the frequency divider is modified in accordance with the modulation of the first and the second modulated control signals. | 03-21-2013 |
20130076408 | High Performance Divider Using Feed Forward, Clock Amplification and Series Peaking Inductors - A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations. | 03-28-2013 |
20130088268 | Multi-Phase Clock Generation System and Clock Calibration Method Thereof - A multi-phase clock generation system and a clock calibration method thereof. The multi-phase clock generation system comprises an input module, a frequency division module and a control module. The input module inputs a reference clock signal with a clock period. The frequency division module according to the reference clock signal produces a phase clock signal with a frequency magnification relationship. The control module divides the phase clock signal into a plurality of clock intervals. There is a clock interval between two adjacent phase clock signals, and each of the plurality of clock intervals has a phase time delay. The control module controls a first phase clock signal of the plurality of phase clock signals to align with a last phase clock signal. The control module sequentially arranges each of the plurality of phase clock signals according to the phase time delay. | 04-11-2013 |
20130113528 | Digital Phase-Locked Loop with Wide Capture Range, Low Phase Noise, and Reduced Spurs - The present disclosure is directed to digital phase-locked loops (DPLLs) and hybrid phase-locked loops (HPLL) for establishing and maintaining a phase relationship between a generated output signal and a reference input signal. The DPLLs use a counter based loop to initially bring the DPLL into lock. Thereafter, the DPLLs disable the counter based loop and switch to a loop with a multi-modulus divider (MMD). The DPLLs can implement a cancelation technique to reduce phase noise introduced by the MMD. The HPLLs further include a loop with a MMD. The HPLLs can implement a similar cancelation technique to reduce phase noise introduced by the MMD. | 05-09-2013 |
20130154691 | MULTI-PHASE CLOCK GENERATION APPARATUS AND METHOD - A multi-phase clock generator may receive an input clock signal as an input. The clock generator may also receive an inverse of the input clock signal. The clock generator may produce a plurality of output clock signals having different phases. The phases of the output clock signals may be evenly spaced. The output clock signals may have a similar waveform to the input clock signal, with a frequency that is lower than the input clock signal by a division factor. | 06-20-2013 |
20130162308 | SEMICONDUCTOR DEVICE THAT CAN ADJUST PROPAGATION TIME OF INTERNAL CLOCK SIGNAL - Disclosed herein is a semiconductor device that includes: a measurement circuit which measures propagation time of an internal clock signal; a delay adjustment circuit which adjusts the propagation time of the internal clock signal on the basis of a result of measurement by the measurement circuit; and a data output circuit which outputs a data signal in synchronization with the internal clock signal. | 06-27-2013 |
20130187686 | FLIP-FLOP CIRCUIT, FREQUENCY DIVIDER AND FREQUENCY DIVIDING METHOD - In response to a first level of the clock signal, an inverting output of a flip-flop circuit is connected, via a non-inverting input thereof, to a first intermediate node of the flip-flop circuit and a non-inverting output of the flip-flop circuit is connected, via an inverting input thereof, to a second intermediate node of the flip-flop circuit. In response to a second level of the clock signal, the first intermediate node is connected, via a third intermediate node of the flip-flop circuit, to the non-inverting output and the second intermediate node is connected, via a fourth intermediate node of the flip-flop circuit, to the inverting output. A first cross-coupled gates arrangement of the flip-flop circuit is coupled between the first and second intermediate nodes. A second cross-coupled gates arrangement of the flip-flop circuit is coupled between the third and fourth intermediate nodes. | 07-25-2013 |
20130241607 | PHASE LOCKED LOOP AND PHASE COMPARISON METHOD - In a phase locked loop, a first frequency divider divides the frequency of an input signal. A low-pass filter receives a frequency-divided signal output from the first frequency divider and having an average phase difference calculated by a calculation unit, cuts off high-frequency components of the received signal, and outputs a resultant signal. A voltage controlled oscillator varies the frequency of a signal to be output based on the signal output from the low-pass filter. A second frequency divider divides the frequency of the signal output from the voltage controlled oscillator. The calculation unit calculates a phase difference between signals individually output from the first frequency divider and the second frequency divider for each phase in one cycle of the signal output from the first frequency divider, and calculates an average phase difference based on the calculated phase differences. | 09-19-2013 |
20130278303 | AUTO FREQUENCY CALIBRATION FOR A PHASE LOCKED LOOP AND METHOD OF USE - A phase locked loop includes a phase difference detector configured to receive a reference frequency and a divider frequency and output a phase difference signal. The phase locked loop includes a code generator configured to receive the reference frequency and the phase difference signal, and output a coarse tuning signal and a reset signal. The phase locked loop includes a digital loop filter configured to receive the phase difference signal and output a fine tuning signal. The phase locked loop includes a voltage control oscillator configured to receive the coarse and fine tuning signals, and output an output frequency. The phase locked loop includes a divider configured to receive the reset signal, a divider number control signal and the output frequency, and output the divider frequency. The phase locked loop includes a delta-sigma modulator configured to receive a divisor ratio and the reset signal, and output divider number control signal. | 10-24-2013 |
20130278304 | Apparatuses and Methods for Conversion of Radio Frequency (RF) Signals to Intermediate Frequency (IF) Signals - Various embodiments implement apparatuses and methods for conversion of radio frequency (RF) signals to intermediate frequency (IF) signals. More particularly, some embodiments are directed toward down conversion of RF signals to IF signals in a multi-band radio receiver, such as a satellite receiver, using a single oscillator for different frequency bands. For example, some of the apparatuses and methods presented are suitable for integration into monolithic RF integrated circuits in low-cost satellite receivers for home entertainment use. | 10-24-2013 |
20130335124 | DOWN CONVERTER AND CONTROL METHOD OF THE SAME - A down converter has two down converter circuits. The one down converter circuit has a first mixer, a first ½ frequency-divider, and a first PLL. The other down converter circuit has a second mixer, a second ½ frequency-divider, and a second PLL. A difference frequency between a frequency of a local oscillation frequency signal of the second PLL and a frequency of a frequency-divided signal of the first ½ frequency-divider is higher than an upper limit of a receive frequency band of a tuner. | 12-19-2013 |
20140015572 | ULTRA LOW PHASE NOISE SIGNAL SOURCE - An apparatus and method for providing an output signal. The apparatus comprises an input for receiving a reference signal, an oscillator for providing an output signal, and an offset signal generator for frequency multiplying the reference signal to generate an offset signal that has a plurality of frequency products in a plurality of frequency bands. The apparatus further includes a mixer for mixing the offset signal with the output signal to produce a combined signal, an offset frequency selector for controllably selecting a frequency band of the offset signal, and a difference detector for detecting a difference between the reference signal and the combined signal and for providing a control signal to the oscillator based on the detected difference. | 01-16-2014 |
20140035632 | PHASE-LOCKED LOOP - A phase-locked loop for generating an output signal including a signal generator arranged to generate an output, a comparison unit arranged to compare the output with a reference signal so as to provide a digital signal, and a loop filter arranged to generate a control signal for controlling the signal generator in dependence on the digital signal. The loop filter includes a proportional path having a digital filter arranged to generate a first component of the control signal for controlling the phase of the output generated by the signal generator, and an analogue integral path arranged to generate a second component of the control signal for controlling the frequency of the output generated by the signal generator. | 02-06-2014 |
20140111257 | FREQUENCY DIVIDER, CLOCK GENERATING APPARATUS, AND METHOD CAPABLE OF CALIBRATING FREQUENCY DRIFT OF OSCILLATOR - A clock generating apparatus includes an oscillator and a frequency synthesizer. The oscillator is utilized for generating a reference clock signal. The frequency synthesizer is coupled to the oscillator and utilized for synthesizing a target clock signal in accordance with the reference clock signal and a frequency division factor that has been adjusted or compensated, and outputting the target clock signal as an output of the clock generating apparatus. | 04-24-2014 |
20140139272 | FRACTIONAL FREQUENCY DIVIDER WITH PHASE PERMUTATION - Some embodiments of the present disclosure relate to a fractional divider for frequency generation. The fractional divider includes a permutation network including a plurality of phase input terminals and a plurality of permuted phase output terminals with a plurality of propagation paths extending therebetween. Multiple propagation paths extend between a phase input terminal and a permuted phase output terminal. A control unit switches an input signal on the phase input terminal through the multiple propagation paths in time to produce a permuted phase signal on the permuted phase output terminal. A phase selection element individually switches the permuted phase output terminals to an output terminal of the fractional divider in time to generate an output signal. The output signal has an output frequency that is a non-unity fraction of an input frequency of the input signal. | 05-22-2014 |
20140139273 | CURRENT REUSE FREQUENCY DIVIDER AND METHOD THEREOF AND VOLTAGE CONTROL OSCILLATOR MODULE AND PHASE-LOCKED LOOP USING THE SAME - A current reuse frequency divider including a first latch circuit and a second latch circuit is provided. The first latch circuit includes a first transistor pair and a second transistor pair. The first latch circuit receives a first differential oscillation signal through bodies of the first transistor pair and the second transistor pair and divides the frequency of the first differential oscillation signal to generate a second differential oscillation signal. The second latch circuit is coupled to the first latch circuit and includes a third transistor pair and a fourth transistor pair. The second latch circuit receives the first differential oscillation signal through bodies of the third transistor pair and the fourth transistor pair and divides the frequency of the first differential oscillation signal to generate a third differential oscillation signal. | 05-22-2014 |
20140152354 | GENERATING A TUNED FREQUENCY OUTPUT FROM A SIGNAL GENERATOR - A method of tuning the frequency of a generated signal to form an output signal including: forming the generated signal at a signal generator; comparing a feedback signal with a reference signal and generating a control signal in dependence on that comparison, wherein the feedback signal is generated using the output signal; and generating the output signal by performing a frequency-dividing operation in dependence on the generated signal and a dividing factor, wherein the dividing factor is determined in dependence on the control signal. | 06-05-2014 |
20140152355 | HIGH-PRECISION ELECTRONIC CLOCK MOVEMENT AND PROCESS FOR ADJUSTING A TIME BASE - Process for adjusting a time base by inhibiting clock pulses supplied by a clock circuit, this adjustment process comprising the following steps:
| 06-05-2014 |
20140159781 | LOCAL OSCILLATOR SIGNAL GENERATION - A local oscillator signal generation circuit is presented. The circuit comprises: a delay device adapted to delay a data signal according to a control signal; a data flip-flop having the delayed data signal provided to its data input terminal and a reference clocking signal provided to its clock input terminal; and a control circuit adapted to generate first and second partially overlapping pulse windows from the delayed data signal and to generate a control signal based on the first and second partially overlapping pulse windows and the reference clocking signal. The control signal is provided to the delay device to control the amount by which the data signal is delayed so as to align the rising edges of the data signal and the reference clock signal. A local oscillator signal is derived from the output of the data flip-flop. | 06-12-2014 |
20140327473 | METHOD AND APPARATUS FOR A PROGRAMMABLE FREQUENCY DIVIDER - A dual-edge triggered variable frequency divider for use in digital frequency synthesis is disclosed. The variable frequency divider utilizes a multiphase clock and a logic unit, including both positive and negative edge triggered unit delay elements connected in parallel. The variable frequency divider generates a clock pulse from a signal source that corresponds to an input value from a logic unit, generates a next input value by the logic unit based on the input value and a frequency control word, and transmits the next input value from the logic unit to the signal source in response to the clock pulse. The multiphase clock is configured to generate the clock signal in response to the falling edge of the first pulse of the clock signal. Iteratively selecting signals by this process results in an observed output frequency of f | 11-06-2014 |
20150070054 | SYNCHRONIZATION SYSTEM AND FREQUENCY DIVIDER CIRCUIT - In a synchronization system, a frequency divider circuit generates a divided clock by dividing a reference clock in a first division ratio. First and second devices operate in synchronization with the reference clock and the divided clock. A division ratio detection circuit, for each period of the divided clock, detects a division ratio of the divided clock based on a count value counted in synchronization with the reference clock and output the division ratio as a second division ratio. A decoder generates a strobe signal, which is for controlling a timing at which the first device transmits and receives a signal to and from the second device, based on the count value and the second division ratio. The first device communicates with the second device through a bus, which operates in synchronization with the divided clock, based on the strobe signal. | 03-12-2015 |
20150091620 | REDUCING CURRENT VARIATION WHEN SWITCHING CLOCKS - An apparatus includes a glitchless divider and a glitchless multiplexer. The glitchless divider may be configured to generate a first system clock in response to a divider value and a clock signal received from a first source. The divider value changes from a first value to a second value in a predetermined number of steps. The glitchless multiplexer may be configured to select between said first system clock and a second system clock in response to a control signal. | 04-02-2015 |
20150102842 | Apparatuses and Methods for Conversion of Radio Frequency (RF) Signals to Intermediate Frequency (IF) Signals - Various embodiments implement apparatuses and methods for conversion of radio frequency (RF) signals to intermediate frequency (IF) signals. More particularly, some embodiments are directed toward down conversion of RF signals to IF signals in a multi-band radio receiver, such as a satellite receiver, using a single oscillator for different frequency bands. For example, some of the apparatuses and methods presented are suitable for integration into monolithic RF integrated circuits in low-cost satellite receivers for home entertainment use. | 04-16-2015 |
20150349782 | RECONFIGURABLE FRACTIONAL DIVIDER - Aspects of a reconfigurable frequency divider circuit are provided. A reconfigurable frequency divider can include a frequency divider that is configured to receive an input signal. The frequency divider can also include a delay circuit that is configured to receive a divided signal produced by the frequency divider. The frequency divider can also include a frequency multiplier that is configured to produce an output signal based on the delayed signal produced by the delay circuit, wherein the delay circuit is configured to receive the output signal. | 12-03-2015 |
20160072509 | MULTI-MODULUS FREQUENCY DIVIDER AND ELECTRONIC APPARATUS INCLUDING THE SAME - A multi-modulus frequency divider includes a frequency division module, a frequency selection module, and a retiming module. The frequency division module is configured to receive an input signal and perform mufti-mode frequency processing on the input signal, so as to generate and output a plurality of divided signals to the frequency selection module. The frequency selection module is configured to receive the plurality of divided signals from the frequency division module, select a divided signal having a desired frequency from among the plurality of divided signals, and output the selected divided signal to the retiming module. The retiming module is configured to receive the selected divided signal from the frequency selection module, perform a retiming operation on the selected divided signal, and output a retimed selected divided signal. | 03-10-2016 |
20160380642 | DIVISOR CONTROL CIRCUIT, FRACTIONAL FREQUENCY DIVISION DEVICE, FREQUENCY SYNTHESIZER AND FREQUENCY SYNTHESIS METHOD - A divisor control circuit allows a frequency divider to have a fractional divisor. The divisor control circuit includes: a multiplexer, arranged to select one of a first clock signal and a second clock signal as a multiplexed signal according to a selection signal, and accordingly provide the multiplexed signal to the frequency divider, wherein there is a phase difference between the first clock signal and the second clock signal; and a selection signal generation circuit, coupled to the multiplexer, arranged to generate the selection signal according to a frequency-divided signal outputted by the frequency divider. The multiplexer alternately selects the first clock signal and the second clock signal as the multiplexed signal during a period of the frequency-divided signal. | 12-29-2016 |