| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327116000 | Frequency multiplication | 14 |
| 20080278203 | SYSTEMS AND METHODS FOR PROVIDING A CLOCK SIGNAL - Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate. The controller can be configured to receive the phase detection signal and to enable the output gate when the value of the phase shift corresponds to a predetermined value. The output gate can provide the output signal when enabled. | 11-13-2008 |
| 20080297210 | CLOCK MULTIPLIER AND CLOCK GENERATOR HAVING THE SAME - A clock multiplier includes a phase-frequency detector, a voltage-current converter, a duty ratio control circuit, a plurality of variable delay cells and an edge combiner. The phase-frequency detector generates control signals. The voltage-current converter converts the control signals to generate first and second current control voltages. The duty ratio control circuit modifies the duty ratio of an input clock signal based on the first and second current control voltages. Each of the variable delay cells generates a triangular wave voltage based on the modified input signal, generates a square wave voltage based on the triangular wave voltage to generate a delay signal. The edge combiner generates a plurality of multiplied clocks based on the delay signals from the variable delay cells. | 12-04-2008 |
| 20090091360 | Delay-locked loop control - This invention relates to devices, a chip, a method and a computer-readable medium for controlling operation of a delay-locked loop. A delay-locked loop unit is adapted to trigger generation of first-type edges of a target signal. A main control unit is adapted to control operation of the delay-locked loop unit in a way that the delay-locked loop unit is turned on before generation of each first-type edge of the target signal and turned off after generation of each first-type edge. | 04-09-2009 |
| 20090189652 | Frequency Multiplier - A frequency multiplier is disclosed. A plurality of voltage regulators each regulate levels of voltages at first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line. An input buffer charges the first node or discharges the second node in response to a feedback signal. An output buffer regulates a level of a voltage at an output node and outputs a frequency-multiplied clock signal and the feedback signal corresponding to the voltage level of the output node. A discharge circuit discharges the first node before a rising edge of each of the input signals from the voltage-controlled delay line is inputted. A charge circuit charges the second node before the rising edge of each of the input signals from the voltage-controlled delay line is inputted. | 07-30-2009 |
| 20100225366 | SIGNAL GENERATOR WITH OUTPUT FREQUENCY GREATER THAN THE OSCILLATOR FREQUENCY - Systems and methods for design and operation of signal generator circuitry with output frequencies greater than the oscillator frequency. Accordingly, in a first method embodiment, a method of producing an output periodic electronic signal comprises accessing four signals having a quadrature phase relationship. First and second pairs of these signals having a one half cycle phase relationship are averaged to produce two signals having an improved duty cycle and a one-quarter cycle phase relationship. The first and second averaged periodic electronic signals are combined in an exclusive OR circuit to produce the output periodic electronic signal at twice the oscillator frequency. Advantageously, the periodic signal may comprise a desirable duty cycle of 50 percent. | 09-09-2010 |
| 20120038395 | Frequency multiplier system and method of multiplying frequency - A frequency multiplier system, for outputting a single phase clock of N multiplied frequency after processing an inputted clock, N≧2, includes a frequency divider receiving the inputted clock, an interpolator connected with the frequency divider, a phase equalizer connected with the interpolator, and a combinational logic circuit connected with the phase equalizer, wherein the frequency divider outputs an orthogonal clock having a two-phases frequency that is a half of the inputted clock to the interpolator, the interpolator outputs a 2N-phases clock to the phase equalizer, the phase equalizer homogenizes a phase skew of the 2N-phases clock, the combinational logic circuit synthesizes the homogenized 2N-phases clock into a single phase clock of N multiplied frequency. And a method of multiplying frequency is provided. The present invention does not need feedback circuits, and therefore is stable and fast-speed , saves area, and reduces energy consumption. | 02-16-2012 |
| 20120074990 | Injection-Locked Oscillator - A signal generator for generating an output signal with a frequency that is a multiple of a frequency of a reference signal, the signal generator including an oscillator configured to generate the output signal in dependence on the reference signal and a control signal and a control circuit configured to generate the control signal to comprise a series of pulses in which one or more of the pulses is offset in phase relative to the reference signal, the control circuit thereby being capable of controlling the frequency and/or phase of the output signal. | 03-29-2012 |
| 20120313672 | Down-Conversion using Square Wave Local Oscillator Signals - In a method of frequency down-converting an input signal to an output signal, a first local oscillator signal is generated as a square wave having a duty cycle of 1/3 or 2/3, and the input signal is mixed with the first oscillator signal to achieve a first down-converted signal, A second local oscillator signal is generated as a modified square wave having the same period time and a duty cycle of 2/3, of which one part has a positive amplitude and another part has a negative amplitude. The input signal is mixed with the second oscillator signal to achieve a second down-converted signal. The first oscillator signal has a delay of 1/4 of the period time to achieve a phase shift of π/2 between the oscillator signals, and at least one down-converted signal is multiplied by a pre-calculated factor. The resulting down-converted signals are added to achieve the output signal. | 12-13-2012 |
| 20130135015 | INTEGRATED CIRCUIT COMPRISING FRACTIONAL CLOCK MULTIPLICATION CIRCUITRY - Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO. | 05-30-2013 |
| 20160028384 | FREQUENCY MULTIPLICATION CIRCUIT, ELECTRONIC DEVICE AND MOVING OBJECT - A frequency multiplication circuit includes a delay circuit that has a clock signal having a period input thereto and delays the signal by a time, an exclusive OR circuit that has the clock signal and a signal from the delay circuit input thereto and outputs a signal serving as an exclusive OR between the clock signal and the signal from the delay circuit, and a signal correction circuit that has a signal from the exclusive OR circuit input thereto and corrects the input signal to output the resultant. The length of the time is a length other than n×T/4 (n is an integer). The signal correction circuit attenuates a signal having a second frequency based on T/2, rather than a signal having a first frequency based on the time τ. | 01-28-2016 |
| 20160164507 | APPARATUS AND METHOD FOR GENERATING QUADRUPLED REFERENCE CLOCK FROM SINGLE-ENDED CRYSTAL OSCILLATOR - A method, an apparatus, and a computer program product are provided. The apparatus outputs a sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the sinusoidal signal, generates a second digital signal having a 25% duty cycle based on the sinusoidal signal, combines the first digital signal and the second digital signal to generate a combined digital signal having a 50% duty cycle and a second clock frequency that is double the first clock frequency, and doubles the second clock frequency of the combined digital signal to generate an output signal having a third clock frequency that is quadruple the first clock frequency. The apparatus further generates a first control voltage and a second control voltage for the first buffer and a third control voltage for the second buffer based on the output signal. | 06-09-2016 |
| 20160164530 | TIME-TO-DIGITAL CONVERTER USING A CONFIGURABLE MULTIPLIER - A fractional error correction circuit includes a time-to-digital converter (TDC) configured to detect a phase difference between a reference clock signal and a variable clock signal, and a configurable multiplier coupled with the TDC. The configurable multiplier has a selectable bit size, the selectable bit size being based on a minimum number of bits needed to obtain a reciprocal of a period of the variable clock signal. The TDC is configured to output a fractional error correction value based on the detected phase difference and the reciprocal of the period. | 06-09-2016 |
| 20160181980 | SYSTEMS AND METHODS FOR GENERATING INJECTION-LOCKED, FREQUENCY-MULTIPLIED OUTPUT SIGNALS | 06-23-2016 |
| 20190149141 | CLOCK DOUBLERS WITH DUTY CYCLE CORRECTION | 05-16-2019 |
