Entries |
Document | Title | Date |
20080224741 | Waveform generating circuit and spread spectrum clock generator - A spread spectrum clock generator is provided which improves the spread spectrum effect with little increasing the circuit cost by modifying the shape of a triangular wave used for frequency modulation by a simple method. The output signal of the modulation waveform generating circuit has such a modulation waveform as indicated by solid lines in FIG. | 09-18-2008 |
20080290912 | ANALOG PSEUDO RANDOM BIT SEQUENCE GENERATOR - A Pseudo Random Bit Sequence (PRBS) generator is provided with components to enable operation at very high microwave frequencies with inexpensive components. The PRBS generator initially replaces the D flip-flops of a conventional PRBS generator with delay lines connected in a similar manner. Further, an exclusive OR (EXOR) gate used in a conventional device is replaced in one embodiment by a mixer and amplifier. In another embodiment, the EXOR gate is replaced by a Gilbert Cell. In some embodiments, complementary outputs of an EXOR gate are connected to separate delay lines to reduce components needed for the PRBS generator. | 11-27-2008 |
20090174440 | FREQUENCY-HOPPING PULSE-WIDTH MODULATOR FOR SWITCHING REGULATORS - A frequency-hopping pulse-width modulator is disclosed, which facilitates a switching regulator to use smaller-size inductive and capacitive elements, to have an improved power efficiency at light load, as well as predictable spectrum at different load levels. The improved modulator automatically determines the switching frequency of a switching regulator according to the load current delivered by the switching regulator from a number of pre-defined frequencies, which are all multiples of a fundamental frequency. By designing the maximum switching frequency of frequency-hopping pulse-width modulator in the MHz range, a switching regulator is able to use smaller-size inductive and capacitive elements. Light-load efficiency of the switching regulator with the frequency-hopping pulse-width modulator is also greatly improved as switching frequency of such switching regulator is reduced with decreased load current. More importantly, spectrum of a switching regulator with the frequency-hopping pulse-width modulator is as predictable as spectrum of a switching regulator with a conventional pulse-width modulator operated at the fundamental frequency. | 07-09-2009 |
20090179673 | DELAY STABILIZATION FOR SKEW TOLERANCE - In an integrated circuit with at least two separate timing circuits, for example both a serializer and a deserializer, a trim value correction factor is developed and applied at the testing of the chip. The correction trim value brings the VCO frequency of the serializer into specifications, but the trim value may also be used to alter the delay between a received clock and data in the deserializer. Since both the serializer and the deserializer were made with the same process, the received clock delay may be corrected by substantially the same correction factor as that applied to the VCO. Illustratively the trim values may be stored on the IC. | 07-16-2009 |
20100264960 | CIRCUIT FOR CHANGING FREQUENCY OF A SIGNAL AND FREQUENCY CHANGE METHOD THEREOF - A signal frequency change circuit is presented. The signal frequency change circuit includes a delay line, a detector, a controller, a multiplexer, and an output unit. The delay line delays a clock signal by a first delay time corresponding to a delay control signal to generate a delay signal and delays the clock signal by a second delay time shorter than a first delay time to generate a pre-frequency change clock signal. The detector generates a phase locked completion signal. The controller sequentially shifts the delay control signal and a multiplexing control signal. The multiplexer selects and outputs one of the pre-frequency change clock signals. The output unit generates a frequency change clock signal. | 10-21-2010 |
20100295582 | CLOCK CIRCUIT FOR DIGITAL CIRCUIT - A method of saving power in a digital circuit driven by a clock running at a rate R, comprising reducing said rate R to a lower rate R′ during periods when said digital circuit is operating at a capacity less than its maximum capacity, and wherein the change from rate R to rate R′ is carried out as a smooth transition. | 11-25-2010 |
20110032008 | PULSE WIDTH MODULATION FREQUENCY CONVERSION - A pulse width modulation (PWM) frequency converter converts an input PWM signal to an output PWM signal having a different frequency while maintaining a substantially equal duty ratio. The PWM frequency converter samples the input PWM signal for a PWM cycle using a sampling clock. A filter module filters the resulting set of one or more PWM parameters to compensate for noise introduced by potential clock mismatch, clock jitter, ambient variations, and other non-deterministic issues, thereby generating filtered PWM parameters. The sampling employed by the filter module compares a difference between the one or more current PWM parameters and previous (or historical) PWM parameters from an earlier sampled PWM cycle to a predetermined change threshold in determining a filtered set of one or more PWM parameters. The filtered set of one or more PWM parameters then is used to generate one or more corresponding PWM cycles of the output signal. | 02-10-2011 |
20120038394 | SWITCHING REGULATOR DEVICE AND METHOD WITH ADAPTIVE FREQUENCY FOLDBACK - A device and method for regulating the output of a power circuit is provided, which in one embodiment includes a pulsewidth modulation (PWM) circuit that produces pulses each having a period of at least a minimum duration, a comparator circuit that produces a control signal, a timer initiated at the output of each pulse and operable to expire no later than expiration of twice the minimum pulsewidth duration, and wherein the PWM circuit is operable to reduce the frequency of outputted pulses in response to receiving the control signal having a first state at expiration of the first timer initiated at the output of a first pulse. | 02-16-2012 |
20120229177 | MIXING CIRCUIT - There is provided a mixing circuit in which a rise of the consumption current can be suppressed while decreasing a non-linear component. The mixing circuit includes: an input unit | 09-13-2012 |
20130015890 | METHOD AND SYSTEM FOR CALIBRATING FREQUENCYAANM CHOU; MING-HUNGAACI TAIPEI CITYAACO TWAAGP CHOU; MING-HUNG TAIPEI CITY TWAANM HSIEH; CHING-FENGAACI TAIPEI CITYAACO TWAAGP HSIEH; CHING-FENG TAIPEI CITY TW - A method for calibrating frequency, applicable to calibrating a frequency signal generated by a frequency generating unit of an apparatus at a preset frequency, includes obtaining the cycle number of the clock rate of a frequency signal based on a reference signal and a clock mask synchronous with the frequency signal; obtaining a frequency of the frequency signal based on the cycle number; correcting the frequency according to a plurality of phase shift signals generated based on the reference signal; and minimizing an error of the frequency of the frequency signal by increasing the quantity of the phase shift signals, so as to calibrate the frequency signal generated by the frequency generating unit. | 01-17-2013 |
20130082747 | VARIABLE FREQUENCY RATIOMETRIC MULTIPHASE PULSE WIDTH MODULATION GENERATION - Groups of phase shifted PWM signals are generated that maintain their duty-cycle and phase relationships as a function of the period of the PWM signal frequency. The multiphase PWM signals are generated in a ratio-metric fashion so as to greatly simplify and reduce the computational workload for a processor used in a PWM system. The groups of phase shifted PWM signals may also be synchronized with and automatically scaled to match external synchronization signals. | 04-04-2013 |
20130113527 | CLOCK CIRCUIT FOR PROVIDING AN ELECTRONIC DEVICE WITH A CLOCK SIGNAL, ELECTRONIC DEVICE WITH A CLOCK CIRCUIT AND METHOD FOR PROVIDING AN ELECTRONIC DEVICE WITH A CLOCK SIGNAL - This invention relates to a clock circuit for providing an electronic device with a clock signal having an adjustable clock frequency. The clock circuit is adapted to receive information regarding a context level of the electronic device and to dynamically control the clock frequency of the clock signal according to the context level. The dynamical control of the clock circuit output frequency based on the context level enables automated power-to-performance control of the electronic device. The invention also relates to an electronic device comprising a context setting unit adapted to set a context level in which the electronic device is operated and a clock circuit. Furthermore, it relates to a method of providing an electronic device with a clock signal having an adjustable clock frequency, wherein a clock circuit receives information regarding a context level of the electronic device; and wherein the clock circuit dynamically controls the clock frequency of the clock signal according to the context level. | 05-09-2013 |
20140333349 | CLOCK CORRECTION CIRCUIT AND CLOCK CORRECTION METHOD - An operation clock generation circuit performs calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock. | 11-13-2014 |
20150084675 | METHODS OF CONTROLLING CLOCKS IN SYSTEM ON CHIP INCLUDING FUNCTION BLOCKS, SYSTEMS ON CHIPS AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero. | 03-26-2015 |
20150116010 | Semiconductor Device, Radio Communication Terminal Using Same, and Clock Frequency Control Method - A semiconductor device | 04-30-2015 |
20160028388 | APPARATUS AND METHOD FOR PROCESSING SIGNAL - An apparatus of processing a signal or a biosignal, and a method of processing a signal or a biosignal are provided. The method of processing signal involves receiving a first reference signal having a frequency component of a measurement signal to be applied to a subject, receiving a second reference signal having a frequency component within a frequency bandwidth of an amplifier, and converting a first signal measured from the subject to a second signal within the frequency bandwidth of the amplifier, based on the first reference signal and the second reference signal. | 01-28-2016 |
20160036421 | ELECTRONIC DEVICE AND CLOCK CONTROL METHOD THEREOF - A user terminal device and a display method thereof are provided. A method for controlling a clock according to an exemplary embodiment includes generating a clock, generating a comparison clock corresponding to a frequency of an external alternating current (AC) power source, counting a number of clock cycles according to the comparison clock, and controlling a generation period of the clock according to the counted number of clock cycles. | 02-04-2016 |
20160105167 | ELECTRONIC DEVICE AND METHOD OF CONTROLLING CLOCK FREQUENCY OF ELECTRONIC DEVICE - A method of controlling a clock frequency of an electronic device and an electronic device using the same is provided. The electronic device includes a check module that is configured to check a clock frequency of at least one Radio Frequency (RF) band, and a control module that is configured to shift a clock frequency of a high speed signal such that a noise generation clock frequency and the clock frequency of the at least one RF band checked by the check module are not identical, when an interface of the high speed signal is used. | 04-14-2016 |
20160112034 | CLOCK CORRECTION CIRCUIT AND CLOCK CORRECTION METHOD - An operation clock generation circuit performs a calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock. | 04-21-2016 |