| Entries |
| Document | Title | Date |
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| 20080197891 | Frequency synthesizer using two phase locked loops - The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency oscillator for outputting a signal having a reference frequency, an integer-N phase locked loop to generate a first output frequency signal based on the reference frequency signal, a fractional-N phase locked loop to generate a second output frequency based on the reference frequency signal and a circuit to generate an output frequency signal by combining the first output frequency and the second output frequency. | 08-21-2008 |
| 20080231328 | Method and Circuit for Local Clock Generation and Smartcard Including it Thereon - One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal φ( | 09-25-2008 |
| 20080238494 | METHOD AND APPARATUS FOR ON-THE-FLY MINIMUM POWER STATE TRANSITION - The invention includes a novel scan chain structure for LSSD or GSD IC operation. The scan chain structure includes a first flip-flop (L | 10-02-2008 |
| 20080238495 | FREQUENCY SYNTHESIZER AND WIRELESS COMMUNICATION DEVICE UTILIZING THE SAME - A frequency synthesizer includes a voltage-controlled oscillator to output an oscillation signal of a oscillating frequency in correspondence with a oscillation controlling voltage that is input to the oscillator, a first frequency-divider to subject the oscillation signal to frequency-division and output a first frequency signal, a second frequency-divider to subject the first frequency signal to frequency-division and output a second frequency signal, a controlling voltage generator to generate the oscillation controlling voltage corresponding to a phase difference between a reference clock signal and the second frequency signal, a frequency detector to detect a frequency difference between the second frequency signal and the reference clock signal, and a controller which controls a free-running frequency of the first frequency divider to minimize the frequency difference. | 10-02-2008 |
| 20080258777 | Method and Apparatus for Generating Multiple Analog Signals Using a Single Microcontroller Output Pin - A method and apparatus are disclosed for generating multiple separate analog signals using a single microcontroller output pin. The microcontroller generates a waveform that is used to concurrently generate multiple separate analog signals. The microcontroller outputs a waveform that includes a first signal from one of the microcontroller's output pins. The first signal is used to produce a first analog signal. The microcontroller then outputs a delineating signal, as part of the waveform, from the microcontroller's output pin. The delineating signal indicates the start of a next signal in the waveform. The microcontroller then outputs a second signal, as part of the waveform, from its output pin. The second signal is used to produce a second analog signal. The waveform includes the first signal that is followed by the delineating signal that is followed by the second signal. | 10-23-2008 |
| 20080284470 | Direct Digital Synthesizer and Nuclear Magnetic Resonance Instrument Using the Same - A DDS (direct digital synthesizer) remarkably increased in the number of frequencies which can be output while maintaining the phase coherency, and an NMR instrument using such a DDS are provided. A DDS including phase accumulators and a phase-to-amplitude modulator is provided with a plurality of phase accumulators operating with fixed phase implements which are equal to powers of 2, a controller for outputting each bit of a frequency tuning word as control data, a plurality of switches for outputting an output of an associated one of the phase accumulators when an associated one of the control data supplied from the controller is 1 and outputting 0 when the associated one of the control data is 0, and an adder for adding up outputs of the switches. | 11-20-2008 |
| 20090015296 | DIGITAL FREQUENCY SYNTHESIZER AND METHOD THEREOF - A digital frequency synthesizer and a method thereof are provided. In the digital frequency synthesizer, a plurality of multiphase signals (MPSs) is generated by a phase delay locked loop array, and a transition reference values is generated by a programmable transition value generator. An operation result obtained according to an input signal and an accumulated value is compared with the transition reference values to generate a phase selection control signal. A phase signal is selected among the MPSs according to the phase selection control signal. After that, a sampling control is performed to the selected phase signal to generate a synthetic signal. The digital frequency synthesizer and the method thereof are flexible and are easy to produce tiny analytic phase, thus, not only fine tuning phases is added but also the resolution of the synthetic signal is improved. | 01-15-2009 |
| 20090027088 | HIGH RESOLUTION TIME DETECTING APPARATUS USING INTERPOLATION AND TIME DETECTING METHOD USING THE SAME - A high resolution time detecting apparatus using interpolation and a time detecting method using the same are provided. The time detecting apparatus includes a delayer which generates delayed signals by sequentially delaying a reference signal using a plurality of delay elements, a latch unit which outputs latch signals using the delayed signals, and an interpolation unit which outputs interpolated signals using input and output signals of the delay elements. As a result, a high resolution TDC using an interpolation and a time detecting method using the same provide improved performance of digital PLL, high resolution digital signal output at a low power consumption, and controlled circuit size. | 01-29-2009 |
| 20090033374 | Clock generator - A frequency divider, comprising an input for receiving an input clock signal having a first frequency; a divider, for generating an output signal having an instantaneous frequency equal to the first frequency divided by an instantaneous division ratio; and a sequence generator, for generating a sequence of instantaneous division ratios by adding a sequence of instantaneous dither values to an integer value. The instantaneous division ratios in the sequence have a mean value that is equal to an integer desired ratio, but none of the instantaneous division ratios in the sequence is equal to the integer desired ratio. | 02-05-2009 |
| 20090039926 | Apparatus for Providing AC Voltage - The invention is directed to an apparatus for providing an AC voltage, comprising synthesizer means for generating at least one periodic output voltage signal, each periodic output voltage signal having an output frequency, wherein the synthesizer means is supplied by an input AC voltage having an input frequency, wherein the synthesizer is configured such that each output frequency differs from the input frequency. | 02-12-2009 |
| 20090045850 | RTWO-BASED DOWN CONVERTER - A multiphase mixer using a rotary traveling wave oscillator is disclosed. In addition to the oscillator, the mixer includes first and second mixer circuits. The rotary traveling wave oscillator generates a first set of N/2 phase and a second set of N/2 phases, where each phase has a frequency that is a factor of N/2 less than the incoming radio frequency signal. The first set of phases are sine signals and the second set of phases are cosine signals. The first mixer circuit generates a first down-converted signal from the first set of phases and the incoming rf signal. The second mixer circuit generates a second down-converted signal from the second set of phases and the rf signal. | 02-19-2009 |
| 20090121749 | Generation of an Analog Gaussian Noise Signal Having Predetermined Characteristics - The present invention relates to a method and system for providing an analog Gaussian noise signal having the predetermined probability distribution function, bandwidth and center frequency. A band-limited digital noise signal indicative of a Gaussian noise signal having a predetermined Gaussian probability distribution function is ΣΔ modulated generating a pulse-density modulated 1-bit sequence representing a Gaussian noise signal having a predetermined probability distribution function, bandwidth and center frequency. Using an analog low-pass filter the pulse-density modulated 1-bit sequence is then converted into a respective analog Gaussian noise signal having the predetermined probability distribution function, bandwidth and center frequency. The method and system are successfully employed in numerous applications such as in histogram testing and probabilistic digitization. | 05-14-2009 |
| 20090160493 | System and Method for Generating a Spread-Spectrum Clock Signal - A circuit for, and method of, generating a spread-spectrum clock signal. In one embodiment, the circuit includes: (a) a modulator configured to generate a modulated control value, and (b) a frequency synthesizer coupled to the modulator and configured to generate a spread-spectrum clock signal based on a variation of the modulated control value, the frequency synthesizer having a directly-derivable frequency response output. | 06-25-2009 |
| 20090167366 | Audio clock regenerator with precise parameter transformer - It is difficult to implement a conventional phase lock loop circuit in a sink device within an HDMI system because the low frequency input causes the conventional phase lock loop circuit to absorb unnecessary noise during a long waiting period. Therefore, the present invention provides a low jitter clock regenerator comprises: an input clock; a divider to divide said input clock into a slower clock; a phase lock loop circuit to regenerate said slower clock to a reference clock; and a parameter transformer to tune said divider and said phase lock loop circuit to increase the adjustment speed of said phase lock loop circuit. The present invention also provides a method to reorganize parameters in order to create new parameters which are better suitable for a clock recovery circuit in a sink device within an HDMI system. | 07-02-2009 |
| 20090167367 | Frequency Synthesizer - An object of the present invention provides a frequency synthesizer having a broad frequency entraining range which can finely set a frequency over a broad band by a novel principle. | 07-02-2009 |
| 20090184736 | FLEXIBLE WAVEFORM GENERATOR WITH EXTENDED RANGE CAPABILITY - A frequency synthesizer includes a first clock running at a frequency f | 07-23-2009 |
| 20090189651 | High Speed Arbitrary Waveform Generator - A high-speed arbitrary waveform generator (AWG) that utilizes multiple digital-to-analog converters (D/A converters) and overcomes bandwidth limitations of individual D/A converters to produce high-speed waveforms. | 07-30-2009 |
| 20090289667 | Clock Generation Using a Fractional Phase Detector - Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output clock signal. The frequency of the output clock signal is a product from multiplying the frequency for the input signal and an integer ratio. The circuit includes an accumulator, a fractional phase detector, and a loop filter. The accumulator periodically adds a numerical offset value to a numerical phase value. The output clock signal is generated from this numerical phase value. The fractional phase detector generates from the numerical phase value a respective numerical phase error for each of the transitions of the input signal. The loop filter generates the numerical offset value from a filtering of the respective numerical phase errors. | 11-26-2009 |
| 20090302896 | SIGNAL CONDITIONING CIRCUIT WITH A SHARED OSCILLATOR - A circuit for signal conditioning including a first stage with a digital/analog converter, a second stage with an I/Q-modulator, and at least one third stage with a mixer. Instead of a multiplicity of independent oscillators, a shared oscillator is provided for the first, second, and third stages, from an output signal of which a respective oscillator signal and clock-pulse signal for each stage of the first, second, and third stages is derived. The oscillator signal and respective clock-pulse signal of the oscillator are supplied via a frequency divider to at least one stage of the first, second, and third stages, or the oscillator signal of the oscillator is supplied via a frequency multiplier to at least one stage. Also, the oscillator signal of the oscillator is supplied as a reference signal to a frequency synthesizer of at least one stage of the first, second, and third stages. | 12-10-2009 |
| 20100013521 | SYNTHESIZER FOR DOHERTY AMPLIFIER - A synthesizer is constructed by constituting a first λ/4 line of a first strip line and by constituting a second λ/4 line of a second strip line, so that it is formed into a chip shape (or a chip part) in a dielectric substrate. A first shield electrode is formed on the upper face of the dielectric substrate, and a second shield electrode is formed on the lower face of the dielectric substrate, so that the first λ/4 line and the second λ/4 line are formed between the first shield electrode and the second shield electrode. | 01-21-2010 |
| 20100019805 | VOLTAGE SYNTHESIS USING VIRTUAL QUADRATURE SOURCES - Voltage synthesis using virtual quadrature sources may be provided. First, a quadrature wave form may be created. The quadrature wave form may have the same frequency as an input voltage and may be ninety degrees out of phase with the input voltage. Next, a harmonic wave form may be created. The harmonic wave form may be based upon an even harmonic of the input voltage and may comprise a triplen wave form. Then, the quadrature wave form and the harmonic wave form may be added to create a resultant wave form. The resultant wave form may be contained within an envelope defined by the input voltage. Next, duty cycle control may be applied to the resultant wave form to create an output voltage. The duty cycle control may be applied without using an energy storage device. | 01-28-2010 |
| 20100045348 | OSCILLATOR, TRANSMITTER-RECEIVER AND FREQUENCY SYNTHESIZER - An output terminal | 02-25-2010 |
| 20100073035 | SYNCHRONOUS FREQUENCY SYNTHESIZER - An apparatus for clock generation is presented. In one embodiment, the apparatus comprises a phase interpolator that generates an output with a phase value within reference phases associated with two input clocks. Logic units are coupled to determine a number of phase settings for the phase interpolator. A divider is coupled to the phase interpolator to generate an output clock based on a modifiable divider setting. | 03-25-2010 |
| 20100079173 | Synthesized Local Oscillator And Method Of Operation Thereof - A method for controlling a synthesized local oscillator (SLO) includes: receiving a control input specifying a desired SLO output; receiving reference clock signal; generating a predefined set of dynamic clock signals from the reference clock signal; selecting a dynamic clock signal from the predefined set of dynamic clock signals in response to the control input; using the dynamic clock signal as an input to a direct digital synthesizer (DDS) module to generate a DDS output signal; selecting a DDS output band in response to the control input, the DDS output band including one of a baseband and an alias band; and processing the DDS output band to generate the SLO output. | 04-01-2010 |
| 20100079174 | FREQUENCY SYNTHESIZER AND METHOD FOR SYNTHESIZING FREQUENCY - A frequency synthesizer includes a multi-signal comparing phase frequency detector/converter, a loop filter, a controllable oscillator, and a frequency divider. The multi-signal comparing phase frequency detector/converter simultaneously receives N input reference frequency signals and N feedback reference frequency signals. Frequencies of the input reference frequency signals are equivalent to one another while phases thereof are different from one another. Frequencies of the feedback reference frequency signals are equivalent to one another while phases thereof are different from one another. The multi-signal comparing phase frequency detector/converter compares the input reference frequency signals and corresponding feedback reference frequency signals, and then outputs a comparison control signal according to the comparison result. The frequency synthesizer of the present invention is adapted to depress a reference spur, thus achieving an ideal output frequency signal. | 04-01-2010 |
| 20100109714 | Frequency synthesizer having a plurality of independent output tones - Described is an apparatus that includes a frequency source and a plurality of time domain direct digital synthesizers each having an input connected to an output of the frequency source and an output providing an output frequency signal. A particular time domain direct digital synthesizer includes a sigma-delta modulator that functions as a second order multi-stage noise shaping sigma-delta modulator. In one exemplary embodiment sigma-delta modulator outputs provide a unitary-weighted word used to switch certain unit capacitors that comprise part of a delay modulator to produce a time-varying delay having a time-averaged value that directly corresponds to a binary value appearing on a plurality of phase accumulator outputs. | 05-06-2010 |
| 20100141303 | Digitally controlled frequency generator - A digitally controlled frequency generator includes an oscillator module for generating a first clock signal having an oscillating frequency, a programmable control module operable so as to generate a control signal corresponding to a desired frequency, and a direct digital frequency synthesizer coupled to the oscillator module and the programmable control module for receiving the first clock signal and the control signal therefrom, and for generating a second clock signal having the desired frequency based on the first clock signal from the oscillator module and the control signal from the programmable control module. | 06-10-2010 |
| 20100148828 | PEAK POWER REDUCTION METHOD - A technique wherein when signals, the modulation schemes of which are different, are to be combined, performing the peak suppression using amounts of the respective modulation schemes can effectively reduce the PAPR of a resulting combined signal. A peak suppressing method for use in a peak suppressing circuit, which combines input signals of different modulation schemes in a time domain to provide a combined signal, comprises detecting, as a peak, that portion of the combined signal which excesses a threshold value to generate a peak signal in accordance with the peak; converting the peak signal into a frequency domain signal and then dividing it into signals originating from the input signals to use these input-signal-originated signals as respective suppression signals; and adding, to the input signals, the suppression signals having different suppression amounts for the respective modulation schemes, thereby performing the peak suppression. | 06-17-2010 |
| 20100156472 | Transversal Agile Local Oscillator Synthesizer - A representative integrated circuit comprises a clock signal generator that generates a clock signal, a code pattern generator that generates digital pattern data based on the clock signal, and a transversal digital-to-analog conversion (T-DAC) unit that includes a plurality of registers and a unary modulator (Umod) array. The T-DAC unit provides frequency selection ranges covering wide operational bands based on the digital pattern data and the clock signal. | 06-24-2010 |
| 20100213984 | AUTOMATIC FREQUENCY CALIBRATION APPARATUS AND METHOD FOR A PHASE-LOCKED LOOP BASED FREQUENCY SYNTHESIZER - An automatic frequency calibration apparatus and a method thereof for a phase-locked loop based frequency synthesizer are disclosed. The apparatus includes a frequency-to-digital converter configured to convert a frequency of a VCO output signal to a first digital value, a target value setting section configured to provide a second digital value corresponding to a target frequency, and a finite state machine configured to calibrate the frequency of the VCO output signal by using the difference of the first digital value and the second digital value. Accordingly, the calibration speed and a frequency resolution of the automatic frequency calibration apparatus in a frequency synthesizer may be enhanced. | 08-26-2010 |
| 20100225361 | FREQUENCY DIVIDER, FREQUENCY SYNTHESIZER AND APPLICATION CIRCUIT - A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control signal. The modulus dividers operate at a second frequency less than the first frequency. | 09-09-2010 |
| 20100244903 | TUNEABLE FILTER - A tuneable filter is provided in which a received signal in a first frequency range is translated to a signal of a higher frequency range by a switchable frequency oscillator signal, filtered in a narrow band filter and then down-converted, possibly to the first frequency range. The switchable frequency oscillator signals are generated by a synthesizer which operates by mixing oscillator signals of different frequencies, selected by fast-switching microwave switches, in order to generate the required range of oscillator signal frequencies. | 09-30-2010 |
| 20100283513 | RF SENSING CIRCUIT WITH A VOLTAGE-CONTROLLED OSCILLATOR - An RF sensing circuit with a voltage-controlled oscillator comprises a low noise amplifier (LNA), a voltage-controlled oscillator (VCO), a frequency demodulating unit, a bandpass filter (BPF) and a digital signal processing unit. The VCO has an injection signal input port and a voltage input port, wherein the injection signal input port is electrically connected with an output of the LNA. The frequency demodulating unit is electrically connected with an output of the VCO and the BPF is electrically connected with an output of the frequency demodulating unit. The digital signal processing unit is electrically connected with an output of the BPF and the voltage input port of the VCO. | 11-11-2010 |
| 20100308871 | DELAY CHAIN CIRCUIT - A delay chain circuit including at least two delay elements, wherein each delay element is configured to: receive a first signal; output a second signal after a delay period; and be operable in at least two modes of operation wherein in a first mode of operation each delay element has a first delay period and in a second mode of operation each delay element has a second delay period. | 12-09-2010 |
| 20100321068 | Frequency Synthesizer - An object of the present invention provides a frequency synthesizer having a broad frequency entraining range which can finely set a frequency over a broad band by a novel principle. | 12-23-2010 |
| 20110032005 | Frequency synthesizer - A frequency synthesizer in which a satisfactory frequency stability can be obtained over the entire long period of service immediately after power activation is disclosed. The reference signal generation circuit includes an OCXO, a TCXO, weight converters which regulate weights with respect to outputs, and an adder which adds up the outputs from the weight converters to output the added output as a reference signal. The CPU controls weight converters B and C so that the weight of the TCXO is set to 100% and the weight of the OCXO is set to 0% at the time of the power activation, so that the weight of the OCXO gradually rises, and so that the weight of the TCXO is set to 0% and the weight of the OCXO is set to 100% after preset time, whereby the frequency can quickly be stabilized after the power activation. | 02-10-2011 |
| 20110037501 | High agility frequency synthesizer phase-locked loop - A highly agile low phase noise frequency synthesizer is provided for rapid generation of frequency specific signals. The frequency synthesizer is capable of rapidly generating signals at different output frequencies while maintaining low cross-coupling. Two or more signal generators utilize a reference frequency to generate two or more signals. These signals are limit processed to reduce cross-coupling prior to being presented to a switch. Responsive to a control signal, the switch outputs one of the signals to a frequency modification device, such as a frequency divider or multiplier. Responsive to a control signal, the frequency modification device scales the frequency of the switch output to convert the frequency of the switch output signal to a desired output frequency. By maintaining sufficient frequency separation between the switch input signals cross-coupling and phase noise is minimized and implementation on an integrated circuit may be achieved. | 02-17-2011 |
| 20110037502 | DIGITAL HIGH-FREQUENCY GENERATOR CIRCUIT - A high-frequency generator circuit comprises a signal generating circuit, a delay unit, a selector, a synthesizer circuit, and a controller. The signal generating circuit generates a signal having the same frequency as an output signal. The delay unit includes a plurality of delay circuits, and delays the signal generated by the signal generating circuit. The selector selects an output signal of the delay circuits. The synthesizer circuit synthesizes the signal selected by the selector, and outputs the output signal. The controller controls the selector based on data for setting a waveform of the output signal and a control signal for setting at least amplitude, phase and frequency of the output signal. | 02-17-2011 |
| 20110080191 | System and Method for Clock-Synchronized Triangular Waveform Generation - A triangular waveform generator is converted to a free running oscillator controlled by a calibration code. The free running oscillator can be synchronized to an external clock signal by comparing the external clock frequency to the frequency of the triangular waveform and adjusting the calibration code until the discrepancy in frequency is minimized. | 04-07-2011 |
| 20110084732 | UNIVERSAL CMOS CURRENT-MODE ANALOG FUNCTION SYNTHESIZER - The universal CMOS current-mode analog function synthesizer is based on approximating the required function using its sixth-order Taylor series expansion. These approximations can be implemented by adding the weighted output currents of a number of basic building blocks built around a basic current squarer, and a constant current. The circuit can simultaneously realize thirty-two different mathematical functions and can be easily expanded to accommodate many others. | 04-14-2011 |
| 20110121866 | FREQUENCY DIFFERENCE DETECTION APPARATUS AND METHOD, FREQUENCY DISCRIMINATION APPARATUS AND METHOD, AND FREQUENCY SYNTHESIS APPARATUS AND METHOD - An apparatus having a complex sine wave generating circuit ( | 05-26-2011 |
| 20110169533 | FREQUENCY SYNTHESIZER - The provision of a technique capable of determining a state where PLL control does not operate normally instantly or in advance in a frequency synthesizer that frequency-divides, A/D converts, and quadranture-detects a frequency signal from a voltage controlled oscillating unit, and extracts a rotation vector rotating at a frequency difference between the frequency signal used for the detection and the A/D converted frequency signal, and integrates a difference between a frequency of the above rotation vector and a set frequency to set an integration result as a control voltage to the voltage controlled oscillating unit. | 07-14-2011 |
| 20110199127 | Phase Accumulator Generating Reference Phase for Phase Coherent Direct Digital Synthesis Outputs - A phase accumulator generates phase data for a direct digital synthesis (DDS) device based on a reference phase to provide analog sinusoidal outputs that are locked to the reference phase and thus phase coherent. The frequency of a sinusoidal DDS output may be controlled by changing a frequency control word (FCW) provided to the phase accumulator without affecting the incrementing reference phase. The sinusoidal DDS output is based on a multiple of the FCW and the reference phase and thus remains locked to the reference phase, providing phase coherency even when the FCW changes to change the frequency. | 08-18-2011 |
| 20110260757 | METHOD AND SYSTEM FOR GENERATING A PULSE SIGNAL OF THE ULTRA WIDE BAND TYPE - System for generating a pulsed signal of the ultra wideband type, comprising a device for direct digital frequency synthesis (DDS) comprising a phase accumulator (ACCP) able to deliver at a first frequency (Fclk) phases coded on i bits and spaced apart by a phase increment (Δp) differing by a power of two and situated in the vicinity of 2 | 10-27-2011 |
| 20110291706 | ELIMINATION OF FRACTIONAL N BOUNDARY SPURS IN A SIGNAL SYNTHESIZER - A portable frequency synthesizer is provided with fine tuning over a broad bandwidth using a Fractional N type Delta Sum Phase Locked Loop circuit that enables elimination of boundary value spurs. In the system, frequencies where spurs occur are calculated to define a region of fractional N values that cannot be used with a first time base. To avoid the boundary spurs, a second time base reference is selected that can generate boundary spurs that do not overlap with the first time base. Circuitry is provided to select the appropriate time base and the fractional N values to generate desired output frequencies throughout the synthesizer range while avoiding the boundary spurs. | 12-01-2011 |
| 20110304361 | TIME-TO-DIGITAL CONVERTER WITH CALIBRATION - Time-to-digital converter arrangements and corresponding methods as well as applications thereof are described. The time-to-digital converter in a first mode is coupled with a calibration signal generator and in a second mode is coupled with signal input. | 12-15-2011 |
| 20120001660 | SOFTWARE-DEFINED RADIO - Present software-defined radios (SDR) employ front end circuits that contain multiple receivers and transmitters for each band of interest, which is inflexible, expensive and power inefficient. A programmable front end circuit is implemented on a CMOS device and is configurable to transmit and receive signals in a wide band of frequencies, thereby providing an adaptable transmitter and receiver operable with current and future wireless networking technologies. | 01-05-2012 |
| 20120081155 | Dual-Mode Voltage Controlled Oscillator, Frequency Synthesizer and Wireless Receiving Device - The invention provides a dual-mode voltage-controlled oscillator (DMVCO), a frequency synthesizer and a wireless receiving device, and pertains to the technical field of integrated circuit of radio frequency wireless receiver. The DMVCO and the frequency synthesizer can operate in a wideband mode and a quadrature mode. When operating in the quadrature mode, a quadrature signal is provided for a Single Sideband Mixer of the frequency synthesizer by a quadrature coupling of a first voltage-controlled oscillator unit and a second voltage-controlled oscillator unit in the DMVCO in the overlapped frequency band so that the frequency synthesizer can cover a higher output frequency band. Therefore, the tuning range of the DMVCO of the invention is wide, and the frequency synthesizer using the DMVCO is low in power consumption, simple in structure and has good frequency spur performance. | 04-05-2012 |
| 20120105110 | Signal level adjusting device and high-frequency apparatus - To provide, in a frequency synthesizer including: a variable attenuator provided at a subsequent stage of a voltage controlled oscillator; a detector; and a control unit outputting a control voltage for adjusting an attenuation amount of the variable attenuator via a digital/analog converter in accordance with a detection voltage, a technology with which a spurious due to a change in an output of the digital/analog converter can be suppressed. A low-pass filter is provided between an output side of a digital/analog converter and a variable attenuator to cut a frequency component corresponding to an overshoot generated when an output of the digital/analog converter is changed. Further, a period of time from when a control unit outputs a control voltage to when it reads a signal level detected by a detector is set to a period of time longer than a time constant of the low-pass filter determined by a cut-off frequency of the low-pass filter so that no influence is exerted on an operation of automatically controlling the signal level. | 05-03-2012 |
| 20120139586 | FREQUENCY SYNTHESIZER AND FREQUENCY SYNTHESIZING METHOD - The present invention relates to a frequency synthesizer comprising:
| 06-07-2012 |
| 20120235709 | UNIFIED FREQUENCY SYNTHESIZER FOR DIRECT CONVERSION RECEIVER OR TRANSMITTER - Method and system for direct conversion receiver ( | 09-20-2012 |
| 20120249187 | CURRENT SOURCE CIRCUIT - According to one embodiment, a current source circuit comprises a first circuit, a second circuit, and a current synthesizing circuit. The first circuit generates a first current having a positive temperature characteristic. The second circuit includes a feedback circuit configured to receive a first voltage having a negative temperature characteristic, and output a second voltage equal to the first voltage, and generates a second current having the negative temperature characteristic based on the second voltage. The current synthesizing circuit generates a constant current having an arbitrary temperature characteristic by adding the first and second currents. | 10-04-2012 |
| 20120306542 | FREQUENCY SYNTHESIZER, METHOD OF GENERATING OUTPUT FREQUENCY THEREOF AND METHOD OF CORRECTING CONVERSION GAIN THEREOF - A frequency synthesizer includes: a delta sigma modulator that outputs an input value to a sequentially changing digital value; an analog path unit that converts the digital value to an analog value according to a first conversion gain; an accumulator that accumulates a difference between the input and digital values; a digital to analog converter (DAC) that compensates an output value of the accumulator according to a second conversion gain; a correction loop that extracts analog tendency by adding an output of the analog path unit and an output of the DAC and that extracts digital tendency from an output of the accumulator and adjusts the second conversion gain by comparing the analog and digital tendency; and a voltage control oscillator that generates an output frequency by adding an output of the analog path unit and an output according to an adjusted second conversion gain of the DAC. | 12-06-2012 |
| 20130043909 | PHASE ADJUSTMENT APPARATUS AND CLOCK GENERATOR THEREOF AND METHOD FOR PHASE ADJUSTMENT - A phase adjustment apparatus for providing a clock signal to a core circuit is provided. The core circuit is powered by a core voltage. The phase adjustment apparatus includes two clock receiving ends, a plurality of digital receiving ends and a combination circuit. The two clock receiving ends receive two original clocks having a same frequency while the two original clock signals possess different phases. The digital receiving ends receive a plurality of phase selection signals. The synthesizing circuit is powered by a first voltage lower than the core voltage, and generates the clock signal according to the phase control signals and the two original clock signals. | 02-21-2013 |
| 20130093468 | METHOD AND APPARATUS FOR MANAGING ARBITRARY FREQUENCIES - Frequency synthesizers for use with oscillators that generate an arbitrary frequency are described, as well as related devices and methods. Divider information can be generated or otherwise accessed for use in configuring a phase lock loop device that is adapted for coupling with the oscillator, where the phase lock loop device can include a plurality of integer dividers without utilizing a fractional divider, where the divider information can include frequency deviations corresponding to groups of integer divider settings for the phase lock loop device, and where each deviation of the frequency deviations can be based on a frequency differential between a standard operating frequency and an output frequency for the phase lock loop utilizing one group of integer divider settings from the groups of integer divider settings. | 04-18-2013 |
| 20130127499 | FRACTIONAL-N SYNTHESIZER - One embodiment of the present invention provides a synthesizer. The synthesizer includes one or more tunable oscillators, a frequency-dividing circuit coupled to the tunable oscillators, and a multiplexer coupled to the frequency-dividing circuit. The frequency-dividing circuit includes a number of frequency dividers, and is configured to generate a number of frequency-dividing outputs. At least one frequency-dividing output has a different frequency division factor. The multiplexer is configured to select a frequency-dividing output | 05-23-2013 |
| 20130154690 | NESTED DIGITAL DELTA-SIGMA MODULATOR - Methods and systems are disclosed that provide a radio frequency synthesizer that generates precise frequencies over a large radio frequency range. The radio frequency synthesizer can provide a high resolution of frequency generation and still provide precise frequencies over a range of radio frequencies. The precision and resolution while maintaining a large operating range come from the ability of the frequency synthesizer to generate frequencies as a product of a plurality of moduli. For example, the frequency can be generated from a reference frequency using a first modulus and a second modulus. The plurality of modulo can be implemented using nested digital delta-sigma modulators in a fractional-N frequency synthesizer. | 06-20-2013 |
| 20130169315 | METHOD FOR ENCODER FREQUENCY-SHIFT COMPENSATION - A method for encoder frequency-shift compensation includes determining frequency values of an input encoder signal, determining repeatable frequency-shifts of the frequency values and generating a frequency-shift compensated clock using the repeatable frequency-shifts. A frequency-shift compensated clock includes a synthesizer configured to generate a frequency-shift compensated clock signal using repeatable frequency shifts and encoder clock signals. | 07-04-2013 |
| 20130176059 | Methods and systems for determining an offset term for a synthesizer signal, and methods and systems for producing a phase-corrected digital signal - A fractional-N PLL synthesizer has an up-down counter counting up for positive edges of a frequency-divided signal produced by a frequency divider with a fractional divide ratio in a feedback path of the synthesizer and down for positive edges of a reference signal. A phase offset between portions of the synthesizer signal before and after a loss-of-lock interval is then assessed as a numerical value proportional to the product of the divide ratio and the cycle difference registered by the up-down counter ( | 07-11-2013 |
| 20130241600 | RANDOM SPREAD SPECTRUM MODULATION - Representative implementations of devices and techniques provide a spread spectrum clocking signal. In a frequency synthesizer, a sequence of values may be generated and used to modulate a frequency of an input signal to the frequency synthesizer. | 09-19-2013 |
| 20130278295 | APPARATUSES FOR MEASURING HIGH SPEED SIGNALS AND METHODS THEREOF - An apparatus for measuring a high speed signal may comprise a plurality of Analog-Digital converters (AD converter) that are arranged in parallel to each other to sample an input signal at different frequencies; a plurality of frequency synthesizers configured to provide each AD converter with a different sampling frequency; a signal processor configured to receive an output of the plurality of AD converters to reconstruct the input signal; and/or a controller configured to receive and process a trigger signal. | 10-24-2013 |
| 20130307588 | PLL BANDWIDTH CORRECTION WITH OFFSET COMPENSATION - A method and system for compensating for offsets when measuring parameters of a phase-locked loop (PLL). In one embodiment, a proportional path in the PLL is temporarily shut off, a measurement is made of a real time-to-zero crossing in the PLL to measure a defined parameter of the PLL, the proportional path is switched on, and the defined loop parameter is adjusted based on this measurement. In one embodiment, the real time-to-zero crossing is measured after introducing a phase step into the PLL between a reference signal and an output signal of the PLL. In an embodiment, two phase steps, having opposite polarities, are successively introduced into the PLL, and the time-to-crossing measurements resulting from these two phase steps may be averaged, and this average is used to determine a loop parameter. | 11-21-2013 |
| 20130314130 | Frequency Synthesizer with Zero Deterministic Jitter - A frequency synthesizer system may generate two intermediate clock signals, each intermediate clock signal having the same nominal frequency (f | 11-28-2013 |
| 20130321031 | CMOS PROGRAMMABLE NON-LINEAR FUNCTION SYNTHESIZER - The CMOS programmable non-linear function synthesizer utilizes CMOS current-mode electronics to provide synthesis of arbitrary analog functions. The circuit approximates a seventh-order Taylor series expansion to synthesize an arbitrary nonlinear function. Each term of the Taylor series expansion is realized using a current-mode basic building block, and the output weighted currents of these basic building blocks are algebraically added in addition to a DC current, if needed. The CMOS current mode electronic circuit can be easily integrated, extended to include higher order terms of the Taylor series, and programmed to generate arbitrary nonlinear functions. | 12-05-2013 |
| 20140015569 | FREQUENCY SYNTHESIZER TUNING - A frequency synthesizer circuit includes a phase determinator configured to output a phase difference signal based on a phase difference between an output signal and a reference signal. The frequency synthesizer circuit may further include a voltage controlled oscillator configured, during a fine tuning mode, to generate the output signal based on the phase difference signal and a value of a frequency band signal. The voltage controlled oscillator may be further configured, during a coarse tuning mode, to generate the output signal based on a voltage and the value of the frequency band signal. The frequency synthesizer circuit may further include a control unit configured to generate the frequency band signal. The value of the frequency band signal may be static during the fine tuning mode and changing during the coarse tuning mode based on a frequency difference between the reference signal and the output signal. | 01-16-2014 |
| 20140077843 | Pipelined Bus-Splitting Digital Delta-Sigma Modulator for Fractional-N Frequency Synthesizer System and Method - The invention provides a digital modulator system for use in a fractional-N frequency synthesizer, said system comprising: a first pipelined modulator configured to receive a digital signal via a bus signal; a second pipelined modulator configured to receive a part of said digital signal; and said system is adapted to split the bus signal by passing least significant bits (LSBs) of said digital signal through the second modulator, combining the output of said second modulator with the most significant bits (MSBs) of said digital signal, and adapted to pass the combined signal through said first pipelined modulator. The combination of bus-splitting and pipelining in the modulator system is configured to provide an output signal to maximize the update rate of a multi-modulus divider of said fractional-N frequency synthesizer. | 03-20-2014 |
| 20140077844 | SIGNAL LEVEL ADJUSTING DEVICE AND HIGH-FREQUENCY APPARATUS - To provide, in a frequency synthesizer including: a variable attenuator provided at a subsequent stage of a voltage controlled oscillator; a detector; and a control unit outputting a control voltage for adjusting an attenuation amount of the variable attenuator via a digital/analog converter in accordance with a detection voltage, a technology with which a spurious due to a change in an output of the digital/analog converter can be suppressed. A low-pass filter is provided between an output side of a digital/analog converter and a variable attenuator to cut a frequency component corresponding to an overshoot generated when an output of the digital/analog converter is changed. Further, a period of time from when a control unit outputs a control voltage to when it reads a signal level detected by a detector is set to a period of time longer than a time constant of the low-pass filter determined by a cut-off frequency of the low-pass filter so that no influence is exerted on an operation of automatically controlling the signal level. | 03-20-2014 |
| 20140097875 | Non-Linear-Error Correction in Fractional-N Digital PLL Frequency Synthesizer - The present disclosure relates to a frequency synthesizer. The frequency synthesizer includes a phase comparator having first and second input nodes. The first input node receives a reference signal having a reference frequency. A channel control block has an input that receives a channel word and an output coupled to the second input node of the phase comparator. A local oscillator (LO) output node provides an LO signal having an LO frequency based on the reference frequency and the channel word. A feedback back couples the LO output node to the second input node of the phase comparator through the channel control block. A non-linear error correction element is operably coupled on a coupling path extending between the phase comparator and the DCO. | 04-10-2014 |
| 20140152347 | VARIABLE PHASE SHIFTER, SEMICONDUCTOR INTEGRATED CIRCUIT AND PHASE SHIFTING METHOD - A variable phase shifter. The variable phase shifter includes: a transmission line that outputs quadrature signals from a pair of output ports in response to an input signal of a specific frequency; a synthesizer that includes a first transistor connected to a first port of the pair of output ports and a second transistor connected to a second port of the pair of output ports, and that on input of the input signal takes signals output from the pair of output ports of the transmission line with a phase according to their respective load impedances and employs the first and the second transistors to amplify and combine the signals; and a phase controller that controls the phase of the output signal that is combined and output by the synthesizer by controlling the amplification operation of each of the first and second transistors of the synthesizer. | 06-05-2014 |
| 20140184274 | FRACTIONAL-N FREQUENCY SYNTHESIZER WITH LOW QUANTIZATION NOISE - A fractional-N frequency synthesizer with low quantization noise includes a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator a divider and a Delta-Sigma modulator. The Delta-Sigma modulator computes “N” to the loop filter in the output current of the charge pump. Quantization step size in the form of current is narrowed, and that reduces the absolute energy of quantization noise reduced, resulting in wider loop bandwidth which has advantages for the fractional-N frequency synthesizer over the lock time, energy saving, and alleviates voltage controlled oscillator design constraints. Even more, frequency synthesizer achieves high frequency transmission in direct modulation transmitter. | 07-03-2014 |
| 20140191782 | ON-CHIP R AND C CALIBRATION USING ON-BOARD SUPPLY BYPASS CAPACITANCE - A technique for calibration of on-chip resistance (R) and capacitance (C) values using an on-board bypass capacitor may include configuring an on-chip switch to selectively couple an on-chip calibration circuit to an on-chip port. The on-chip calibration circuit may include an RC oscillator having an RC time constant (RCTC). The on-board bypass capacitor may be coupled to the on-chip calibration circuit, by using the on-chip port. The on-chip R and C values may be calibrated using the on-chip calibration circuit and the on-board bypass capacitor. | 07-10-2014 |
| 20140197867 | Circuits and Methods for Using a Flying-Adder Synthesizer as a Fractional Frequency Divider - An open loop clock divider circuit includes (a) a first divider configured to receive an incoming clock signal and output a first divided clock signal, (b) a flying-adder synthesizer configured to fractionally divide the first divided clock signal and output a fractionally divided clock signal, and (c) a second divider configured to receive the fractionally divided clock signal and output a second divided clock signal. The open loop clock divider circuit advantageously provides a fractional divider in which there is no feedback loop between the source frequency (f | 07-17-2014 |
| 20140253178 | SEMICONDUCTOR DEVICE INCLUDING CLOCK SIGNAL GENERATION UNIT - A semiconductor device for stably generating a clock signal from a strobe signal includes a processor, a clock signal generation unit receiving a first strobe signal and a second strobe signal to generate the clock signal, and a data reception unit receiving at least one data signal to provide the received data signal to the processor. The clock signal generation unit may comprise a strobe comparator comparing a voltage of a first input terminal with that of a second input terminal to output logic high or logic low, a first switch selectively connecting one of a first and a second signal line to the first input terminal, a second switch selectively connecting one of the second signal line and a reference line to the second input terminal, and a voltage stabilizing circuit pulling up/down at least one of a voltage of the first and the second signal line. | 09-11-2014 |
| 20140266318 | PHASE INTERPOLATOR BASED OUTPUT WAVEFORM SYNTHESIZER FOR LOW-POWER BROADBAND TRANSMITTER - Exemplary embodiments of the present invention relate to an output waveform synthesizer using phase interpolators and an on-chip eye opening monitoring (EOM) circuit for a low-power transmitter. In order to achieve both small area and low-power consumption in the transmitter design, a single-stage multiphase multiplexer operating in subrate is employed. The multiphase multiplexer is composed of parallelized open-drain NAND gates. In subrate transmitter architecture, the phase mismatch among multiphase clock signals degrades jitter performance significantly and is a critical bottleneck for its widespread use despite low power consumption. In order to overcome such mismatch problem, an area-and-power-efficient phase interpolator based waveform synthesizing scheme is developed. | 09-18-2014 |
| 20140292376 | FRACTIONAL-N SYNTHESIZER - One embodiment of the present invention provides a synthesizer. The synthesizer includes one or more tunable oscillators, a frequency-dividing circuit coupled to the tunable oscillators, and a multiplexer coupled to the frequency-dividing circuit. The frequency-dividing circuit includes a number of frequency dividers, and is configured to generate a number of frequency-dividing outputs. At least one frequency-dividing output has a different frequency division factor. The multiplexer is configured to select a frequency-dividing output | 10-02-2014 |
| 20150109029 | METHOD AND APPARATUS FOR GENERATING A DIGITAL SIGNAL OF TUNABLE FREQUENCY AND FREQUENCY SYNTHESIZER EMPLOYING SAME - A method for generating a digital signal of tunable frequency may include generating a periodic first analog signal, determining a sign of a first difference between a value of the first analog signal and a first control value to determine sign flips, wherein the first control value is a variable value, and generating the digital signal of tunable frequency on the basis of the determined sign of the first difference, wherein the digital signal of tunable frequency is generated such that a subset of switches of the signal level are coincident with a respective sign flip of the determined sign of the first difference. | 04-23-2015 |
| 20150293555 | PHASE DISCIPLINED, DIRECT DIGITAL SYNTHESIZER BASED, COHERENT SIGNAL GENERATOR - A phase coherent signal generator apparatus is disclosed that outputs a coherent continuous phase signal that includes fast switched multiple different frequency bursts. The apparatus comprises: a clock generator including an input to receive a reference clock signal, and outputs to independently supply a master clock signal and a slave clock signal; an accumulating digital synthesizer that includes independent inputs to receive the slave clock signal, a digital frequency tune word signal, a phase tune word signal, and a reset signal, and an output that supplies a digital coherent continuous phase signal; a master digital synthesizer that includes independent inputs to receive the master clock signal and the digital frequency tune word signal, and independent outputs to supply the digital phase tune word signal and the reset signal; and a converter that receives the digital coherent continuous phase signal and supplies the coherent continuous phase signal. | 10-15-2015 |
| 20150294794 | PARALLEL CAPACITOR AND HIGH FREQUENCY SEMICONDUCTOR DEVICE - Certain embodiments provide a parallel capacitor including a substrate configured by a dielectric, upper electrodes, and a lower electrode. The upper electrodes are provided in an upper electrode region on a surface of the substrate. The lower electrode is provided on an entire surface of a lower electrode region including a region corresponding to the upper electrode region of an underside of the substrate, the lower electrode region being wider than the region. A single-operation capacity of each capacitor on both ends is smaller than the single-operation capacity of a capacitor in a center portion. The capacitors on the both ends are configured by the upper electrodes arranged on both ends of the substrate, the lower electrode, and the substrate. The capacitor in the center portion is configured by the upper electrode arranged in a center portion of the substrate, the lower electrode, and the substrate. | 10-15-2015 |
| 20150303929 | LOW SPURIOUS SYNTHESIZER CIRCUIT AND METHOD - An offset phase locked loop synthesizer comprising: an input; an output; a voltage controlled oscillator (VCO), the VCO output coupled to the synthesizer output; a phase frequency detector having a reference input, a feed-back input, and an output; a mixer having a first mixer input coupled to the synthesizer input and a second mixer input coupled to the VCO output; a first divider for frequency dividing a signal by a first value and having an input coupled to the mixer output and an output coupled to the second input of the phase frequency detector; a second divider for frequency dividing a signal by a second value and having an input coupled to the synthesizer input and an output coupled to the reference input of the phase frequency detector; and a low pass filter coupled between the output of the phase frequency detector and the VCO input. | 10-22-2015 |
| 20150326228 | Current Synthesizer Correction - An adjustable current-synthesizer may generate synthesized current representative of an actual current, according to a model of a circuit that produces the actual current. The current synthesizer may under-sample a current sense signal derived from the actual current to obtain a few samples of the actual current, which are then used to adjust the synthesized current, thereby ensuring accuracy of the synthesized current. Sample values of the actual current are compared with corresponding generated values of the synthesized current to obtain offset values. In order to maintain monotonicity in the synthesizer results, the offset values are used to make adjustments to the slope of the synthesized current. The slope of the synthesized current may also be adjusted according to the slope of the actual current. Sub-Nyquist sampling of the actual current may be performed on the down-slope, with up-slope adjustments made based on the offset adjustment and down-slope adjustment. | 11-12-2015 |
| 20150365095 | Wide Range Frequency Synthesizer with Quadrature Generation and Spur Cancellation - A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals. | 12-17-2015 |
| 20160043728 | RF CIRCUIT - An RF circuit for providing phase coherent signals, an RF heating apparatus comprising the RF circuit and a method for providing phase coherent signals in an RF circuit. The RF circuit has a first frequency synthesiser including a fractional-N phase locked loop and a second frequency synthesiser including an integer-N phase locked loop. An output of the first frequency synthesiser is connected to a phase frequency detector of the integer-N phase locked loop of the second frequency synthesiser via a synchronisation signal divider for distributing a synchronisation signal from the first frequency synthesiser to the second frequency synthesiser. The integer-N phase locked loop of the second frequency synthesiser comprises a frequency divider of the same modulus as the synchronisation signal divider. | 02-11-2016 |
| 20160105190 | FREQUENCY SYNTHESIS DEVICE AND METHOD - A frequency synthesis device, including: a first generator configured to generate a periodical signal with a frequency f | 04-14-2016 |
| 20160105191 | FREQUENCY SYNTHESIZER - The output of a reference frequency generator is connected to the input of a high-order frequency multiplier, the output of which is connected to the input of an additional frequency multiplier and to a first input of a frequency converter. The output of the additional frequency multiplier is connected to the input of a frequency divider, the output of which is connected to a reference input of a frequency-phase detector. The output of the frequency converter is connected to the input of a frequency divider with a variable division ratio, the output of which is connected to another input of the frequency-phase detector. The output of the frequency-phase detector is connected to an error signal filter, the output of which is connected to the input of a controlled generator. A second input of the frequency converter is connected to the output of the controlled generator. The main technical result is an increase in the frequency resolution and spectral purity of an output signal. | 04-14-2016 |
| 20160156361 | Frequency Synthesizing Module and Related Frequency Gain Determining Method | 06-02-2016 |
| 20160182072 | NOISE-SHAPING CIRCUIT, DIGITAL-TO-TIME CONVERTER, ANALOG-TO-DIGITAL CONVERTER, DIGITAL-TO-ANALOG CONVERTER FREQUENCY SYNTHESIZER, TRANSMITTER, RECEIVER, TRANSCEIVER, METHOD FOR SHAPING NOISE IN AN INPUT SIGNAL | 06-23-2016 |
| 20160254802 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME | 09-01-2016 |
| 20170237443 | PHASE-LOCKED LOOP AND FREQUENCY SYNTHESIZER | 08-17-2017 |
