| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 326122000 | Complementary FET`s | 10 |
| 20090115458 | CMOS COMPARATOR WITH HYSTERESIS - A complementary metal oxide semiconductor (CMOS) comparator circuit includes a plurality of p-type metal-oxide-semiconductor (PMOS) transistors receiving an input voltage signal, a plurality of n-type metal-oxide-semiconductor (NMOS) transistors operatively connected to the PMOS transistors and adapted to receive the input voltage signal, and an inverter adapted to invert the input voltage signal into an output voltage signal. An effective aspect ratio of the PMOS and NMOS transistors may be dependent on the level of the output voltage signal from the inverter. When a digital output of the inverter is “1”, the effective aspect ratio of the NMOS transistor is increased by turning on a second NMOS transistor, and a threshold voltage of the inverter is decreased. | 05-07-2009 |
| 20090167359 | CURRENT MODE LOGIC CIRCUIT AND CONTROL APPARATUS THEREFOR - Embodiments relate to a current mode logic circuit, which may include a first NMOS transistor whose drain may be coupled to a first load and whose gate may be coupled to an input terminal through which data may be inputted, a second NMOS transistor whose drain may be coupled to a second load and gate may be coupled to an input terminal through which a negative reference voltage may be applied, and a third NMOS transistor whose drain may be coupled to a source of each of the first and the second NMOS transistors and whose gate may be coupled to an input terminal through which a reference voltage may be applied. Bulk biases of the first, second, and third NMOS transistors may be independently adjusted to control at least one of a leakage current and an operation speed of the NMOS transistors. | 07-02-2009 |
| 20090184734 | Method of Producing and Operating a Low Power Junction Field Effect Transistor - A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter. | 07-23-2009 |
| 20100007382 | Inverter circuit and balanced input inverter circuit - A balanced input inverter circuit includes a first P-type MOS transistor including a gate terminal connected to an input, a source terminal connected to a first power source potential, and a drain terminal connected to an output, a first N-type MOS transistor including a gate terminal connected to the input, a drain terminal connected to the output, and a source terminal connected to a second power source potential, a first inverter circuit including an input terminal connected to an inverted input, and an output terminal connected to a back gate terminal of the first N-type MOS transistor, a first diode connected between the first power source potential and a first power source terminal of the first inverter circuit, a second inverter circuit including an input terminal connected to the inverted input, and an output terminal connected to a back gate terminal of the first P-type MOS transistor, and a second diode connected between the second power source potential and a second power source terminal of the second inverter circuit. | 01-14-2010 |
| 20100026346 | HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD EFFECT TRANSISTORS - Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced. | 02-04-2010 |
| 20100301903 | BUILDING BLOCK FOR A SECURE CMOS LOGIC CELL LIBRARY - A logical building block and method of using the building block to design a logic cell library for CMOS (Complementary Metal Oxide Silicon) ASICs (Application Specific Integrated Circuits) is disclosed. Different logic gates, built with the same building block as described in this invention, will have the same schematics of transistor connection and also the same physical layout so that they appear to be physically identical under optical or electron microscopy. An ASIC designed from a library of such logic cells is strongly resistant to a reverse engineering attempt. | 12-02-2010 |
| 20110309861 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor included in a latch circuit, a second transistor that is included in the latch circuit and is formed in a well in which the first transistor is formed, the second transistor having a conduction type identical to that of the first transistor, and a well contact that is provided between the first transistor and the second transistor and connects a power supply to the well. | 12-22-2011 |
| 20120182048 | RADIATION HARDENED CIRCUIT DESIGN FOR MULTINODE UPSETS - This invention relates to Multiple Interlocked Cells (MICE) design as a hardening technique for CMOS logic gates consisting of two or more redundant nodes with node isolation components. This technique is used to modify existing standard CMOS logic gates or create new complex logic gates using common mask layers existing at ultra-deep sub-micron CMOS foundries. For single node upset immunity in logic or register, a primary cell and a redundant cell are used. For multi-node immunity, the primary cell is combined with two or more redundant nodes are used with physical layout spacing techniques which will insure that a single particle track cannot upset all three nodes simultaneously, and logic circuits built using this technique are immune to upsets in any environment. Circuits built using the MICE technique are also immune to single event transients without requiring the large time delays used in other hardening techniques. | 07-19-2012 |
| 20120229166 | Semiconductor Device and a Display Device - A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side, and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small. | 09-13-2012 |
| 20120229167 | Twin-Drain Spatial Wavefunction Switched Field-Effect Transistors - A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned. | 09-13-2012 |
| 20090115458 | CMOS COMPARATOR WITH HYSTERESIS - A complementary metal oxide semiconductor (CMOS) comparator circuit includes a plurality of p-type metal-oxide-semiconductor (PMOS) transistors receiving an input voltage signal, a plurality of n-type metal-oxide-semiconductor (NMOS) transistors operatively connected to the PMOS transistors and adapted to receive the input voltage signal, and an inverter adapted to invert the input voltage signal into an output voltage signal. An effective aspect ratio of the PMOS and NMOS transistors may be dependent on the level of the output voltage signal from the inverter. When a digital output of the inverter is “1”, the effective aspect ratio of the NMOS transistor is increased by turning on a second NMOS transistor, and a threshold voltage of the inverter is decreased. | 05-07-2009 |
| 20090167359 | CURRENT MODE LOGIC CIRCUIT AND CONTROL APPARATUS THEREFOR - Embodiments relate to a current mode logic circuit, which may include a first NMOS transistor whose drain may be coupled to a first load and whose gate may be coupled to an input terminal through which data may be inputted, a second NMOS transistor whose drain may be coupled to a second load and gate may be coupled to an input terminal through which a negative reference voltage may be applied, and a third NMOS transistor whose drain may be coupled to a source of each of the first and the second NMOS transistors and whose gate may be coupled to an input terminal through which a reference voltage may be applied. Bulk biases of the first, second, and third NMOS transistors may be independently adjusted to control at least one of a leakage current and an operation speed of the NMOS transistors. | 07-02-2009 |
| 20090184734 | Method of Producing and Operating a Low Power Junction Field Effect Transistor - A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter. | 07-23-2009 |
| 20100007382 | Inverter circuit and balanced input inverter circuit - A balanced input inverter circuit includes a first P-type MOS transistor including a gate terminal connected to an input, a source terminal connected to a first power source potential, and a drain terminal connected to an output, a first N-type MOS transistor including a gate terminal connected to the input, a drain terminal connected to the output, and a source terminal connected to a second power source potential, a first inverter circuit including an input terminal connected to an inverted input, and an output terminal connected to a back gate terminal of the first N-type MOS transistor, a first diode connected between the first power source potential and a first power source terminal of the first inverter circuit, a second inverter circuit including an input terminal connected to the inverted input, and an output terminal connected to a back gate terminal of the first P-type MOS transistor, and a second diode connected between the second power source potential and a second power source terminal of the second inverter circuit. | 01-14-2010 |
| 20100026346 | HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD EFFECT TRANSISTORS - Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced. | 02-04-2010 |
| 20100301903 | BUILDING BLOCK FOR A SECURE CMOS LOGIC CELL LIBRARY - A logical building block and method of using the building block to design a logic cell library for CMOS (Complementary Metal Oxide Silicon) ASICs (Application Specific Integrated Circuits) is disclosed. Different logic gates, built with the same building block as described in this invention, will have the same schematics of transistor connection and also the same physical layout so that they appear to be physically identical under optical or electron microscopy. An ASIC designed from a library of such logic cells is strongly resistant to a reverse engineering attempt. | 12-02-2010 |
| 20110309861 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor included in a latch circuit, a second transistor that is included in the latch circuit and is formed in a well in which the first transistor is formed, the second transistor having a conduction type identical to that of the first transistor, and a well contact that is provided between the first transistor and the second transistor and connects a power supply to the well. | 12-22-2011 |
| 20120182048 | RADIATION HARDENED CIRCUIT DESIGN FOR MULTINODE UPSETS - This invention relates to Multiple Interlocked Cells (MICE) design as a hardening technique for CMOS logic gates consisting of two or more redundant nodes with node isolation components. This technique is used to modify existing standard CMOS logic gates or create new complex logic gates using common mask layers existing at ultra-deep sub-micron CMOS foundries. For single node upset immunity in logic or register, a primary cell and a redundant cell are used. For multi-node immunity, the primary cell is combined with two or more redundant nodes are used with physical layout spacing techniques which will insure that a single particle track cannot upset all three nodes simultaneously, and logic circuits built using this technique are immune to upsets in any environment. Circuits built using the MICE technique are also immune to single event transients without requiring the large time delays used in other hardening techniques. | 07-19-2012 |
| 20120229166 | Semiconductor Device and a Display Device - A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side, and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small. | 09-13-2012 |
| 20120229167 | Twin-Drain Spatial Wavefunction Switched Field-Effect Transistors - A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned. | 09-13-2012 |
