| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 326119000 | MOSFET (i.e., metal-oxide semiconductor field-effect transistor) | 33 |
| 20090189643 | CONSTANT VOLTAGE GENERATING DEVICE - A constant voltage generator device provides a first and a second transistor having their main current path coupled serially via a common terminal for providing a constant output voltage at the common terminal of said transistors. The device provides one or more potential dividers having a plurality of serially connected resistive elements. A first voltage is obtained from a first combination of resistive elements of the potential divider and a second voltage obtained from a second combination of resistive elements of the potential divider. The first and the second voltages are supplied to the first and the second voltage at the control terminals of the first and the second transistors, respectively. | 07-30-2009 |
| 20090315590 | Logic circuits, inverter devices and methods of operating the same - An inverter device includes at least a first transistor connected between a power source node and ground. The first transistor includes a first gate and a first terminal that are internally capacitive-coupled to control a boost voltage at a boost node. The first terminal is one of a first source and a first drain of the first transistor. | 12-24-2009 |
| 20130027085 | ADJUSTABLE SCHMITT TRIGGER - A circuit comprises an inverter, a first transistor, a second transistor, and at least one switching circuit. The inverter has a first node and a second node. The first transistor has a first terminal, a second terminal, and a third terminal. The second transistor has a fourth terminal, a fifth terminal, and a sixth terminal. The at least one switching circuit is configured to switch a connection of at least one of the first transistor and the second transistor to the inverter. The second terminal and the fifth terminal are coupled to the first node. The third terminal and the sixth terminal are coupled to the second node. The first transistor and the second transistor are configured to cause a plurality of time delays at the second node. | 01-31-2013 |
| 20140070848 | POWER EFFICIENT MULTIPLEXER - A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs. | 03-13-2014 |
| 326120000 | Depletion or enhancement | 9 |
| 20100079169 | Inverter, method of operating the same and logic circuit comprising inverter - Provided are an inverter, a method of operating the inverter, and a logic circuit including the inverter. The inverter may include a load transistor and a driving transistor, and at least one of the load transistor and the driving transistor may have a double gate structure. A threshold voltage of the load transistor or the driving transistor may be adjusted by the double gate structure, and accordingly, the inverter may be an enhancement/depletion (E/D) mode inverter. | 04-01-2010 |
| 20100117684 | Inverter and logic device comprising the same - The inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses. The channel region of the driving transistor may be thinner than the channel region of the load transistor. A channel layer of the driving transistor may have a recessed region between a source and a drain which contact both ends of the channel layer. The driving transistor may be an enhancement mode transistor and the load transistor may be a depletion mode transistor. | 05-13-2010 |
| 20100188120 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The present invention provides a semiconductor integrated circuit device in which characteristics of an SOI transistor are effectively used to achieve higher speed, higher degree of integration, and also reduction in voltage and power consumption. The semiconductor integrated circuit device according to the present invention has a configuration in which a plurality of external power supply lines and body voltage control lines are alternately arranged in one direction so as to extend over the entire chip, which supply power and a body voltage to logic circuits, an analog circuit and memory circuits. A body voltage control type logic gate is fully applied in the logic circuit, whereas the body voltage control type logic gate is partially applied in the memory circuit. | 07-29-2010 |
| 20100264956 | Inverter, method of manufacturing the same, and logic circuit including the inverter - Provided are an inverter, a method of manufacturing the inverter, and a logic circuit including the inverter. The inverter may include a first transistor and a second transistor having different channel layer structures. A channel layer of the first transistor may include a lower layer and an upper layer, and a channel layer of the second transistor may be the same as one of the lower layer and the upper layer. At least one of the lower layer and the upper layer may be an oxide layer. The inverter may be an enhancement/depletion (E/D) mode inverter or a complementary inverter. | 10-21-2010 |
| 20100283509 | Inverter, logic circuit including an inverter and methods of fabricating the same - An inverter, a logic circuit including the inverter and method of fabricating the same are provided. The inverter includes a load transistor of a depletion mode, and a driving transistor of an enhancement mode, which is connected to the load transistor. The load transistor may have a first oxide layer as a first channel layer. The driving transistor may have a second oxide layer as a second channel layer. | 11-11-2010 |
| 20100295579 | Inverter and logic device comprising the same - The inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses. The channel region of the driving transistor may be thinner than the channel region of the load transistor. A channel layer of the driving transistor may have a recessed region between a source and a drain which contact both ends of the channel layer. The driving transistor may be an enhancement mode transistor and the load transistor may be a depletion mode transistor. | 11-25-2010 |
| 20110221475 | LOGIC CIRCUIT - An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor | 09-15-2011 |
| 20120319733 | SEMICONDUCTOR DEVICE - A semiconductor device includes two unit circuits and a control unit. A middle point between the unit circuits is coupled with an inductive load. Each unit circuit includes a first switching element and a free wheel diode coupled in inverse-parallel with the first switching element. At least one of the unit circuits further includes a bypass section coupled in parallel with the first switching element and the free wheel diode. The bypass section includes a second switching element and a resistor coupled in series. The controller alternately turns on the first switching elements with a dead time during which both the first switching elements are turned off. The controller controls the second switching element coupled in parallel with one of the first switching elements to be an on-state when the one of the first switching elements transitions from an off-state to an on-state in the dead time. | 12-20-2012 |
| 20160028398 | NAND GATE CIRCUIT, DISPLAY BACK PLATE, DISPLAY DEVICE AND ELECTRONIC DEVICE - The NAND gate circuit includes at least two input transistors, at least two pull-up modules and at least two input control transistors. A first electrode of each input transistor is connected to a second level output end via the pull-up module. The input control transistor is configured to enable a potential of the control end of the pull-up module connected to the first electrode of the input transistor to be the first level when the input signal connected to the gate electrode of the input control transistor is at a second level. The at least two pull-up modules are configured to cut off the connection between the second level output end and the NAND gate output end when all the input signals are at the second level, and enable the connection therebetween when none of the input signals is at the second level. | 01-28-2016 |
| 326121000 | CMOS | 20 |
| 20080204082 | Apparatus And Method For Generating A Constant Logical Value In An Integrated Circuit - An apparatus for generating a constant logical value in an integrated circuit includes a first logic network having n outputs, the n outputs providing 2 | 08-28-2008 |
| 20080258775 | NAND/NOR Registers - A register receives an input signal and provides output signals that represent true complementary logic values of the input signal. One implementation of the register includes: a first stage circuit and a second stage circuit. After the output signals are derived, the second stage circuit provides feedback signals to block further propagation of the logic value of the input signal from the first stage circuit to the second stage circuit. | 10-23-2008 |
| 20090072864 | OUTPUT CIRCUIT - An output circuit including an input terminal; an output terminal; a PMOS transistor connected with a positive side of a power voltage and the output terminal; a NMOS transistor connected with a negative side of the power supply voltage and the output terminal; a first inverter, to which a gate voltage of the PMOS transistor is input and which exhibits hysteresis in threshold voltage; and a second inverter, to which a gate voltage of the NMOS transistor is input and which exhibits hysteresis in threshold voltage, wherein an OR logic signal of the input signal and a signal obtained by inverting an output signal from the second inverter is input to a gate of the PMOS transistor, and an AND logic signal of the input signal and a signal obtained by inverting an output signal from the first inverter is input to a gate of the NMOS transistor. | 03-19-2009 |
| 20090108877 | Logic Gate and Semiconductor Integrated Circuit Device Using the Logic Gate - A disclosed logic gate including a CMOS circuit having a p-channel MOS transistor and an n-channel MOS transistor and also includes a resistance device connected in series with a source or a drain of at least one of the p-channel MOS transistor and the n-channel MOS transistor, a switching device connected in parallel with the resistance device and configured to switch on and off, and a switching control circuit configured to control the switching on and off of the switching device according to an output signal output from the CMOS circuit. | 04-30-2009 |
| 20090295431 | INTEGRATED NANOTUBE AND FIELD EFFECT SWITCHING DEVICES - Hybrid switching devices integrate nanotube switching elements with field effect devices, such as NFETs and PFETs. A switching device forms and unforms a conductive channel from the signal input to the output subject to the relative state of the control input. In embodiments of the invention, the conductive channel includes a nanotube channel element and a field modulatable semiconductor channel element. The switching device may include a nanotube switching element and a field effect device electrically disposed in series. According to one aspect of the invention, an integrated switching device is a four-terminal device with a signal input terminal, a control input terminal, a second input terminal, and an output terminal. The devices may be non-volatile. The devices can form the basis for a hybrid NT-FET logic family and can be used to implement any Boolean logic circuit. | 12-03-2009 |
| 20090295432 | CMOS BACK-GATED KEEPER TECHNIQUE - A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (V | 12-03-2009 |
| 20090302894 | DUAL GATE TRANSISTOR KEEPER DYNAMIC LOGIC - A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation. | 12-10-2009 |
| 20100148825 | Semiconductor devices and methods of fabricating the same - Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may be a complementary device including a p-type oxide TFT and an n-type oxide TFT. The semiconductor device may be a logic device such as an inverter, a NAND device, or a NOR device. | 06-17-2010 |
| 20100194438 | SEMICONDUCTOR DEVICE - It is intended to provide a semiconductor device which comprises an SGT-based, highly-integrated, high-speed, at least two-stage CMOS inverter cascade circuit configured to allow a pMOS SGT to have a gate width two times greater than that of an nMOS SGT. A semiconductor device of the present invention comprises a CMOS inverter cascade circuit having at least two-stage CMOS inverter, wherein: a first CMOS inverter includes two pMOS SGT arranged at respective ones of an intersection of the 1st row and the 1st column and an intersection of the 2nd row and the 1st column, and an nMOS SGT arranged at an intersection of the 1st row and the 2nd column; and a second CMOS inverter includes two pMOS SGT arranged at respective ones of an intersection of the 1st row and the 3rd column and an intersection of the 2nd row and the 3rd column, and an nMOS SGT arranged at an intersection of the 2nd row and the 2nd column. An output terminal line is connected to an input terminal line, wherein the output terminal line is arranged to interconnect a drain diffusion layer of each of the two SGTS at respective ones of the intersection of the 1st row and the intersection of the 2nd row and the 1st column and the 1st column, and a drain diffusion layer of the SGT at the intersection of the 1st row and the 2nd column, through an island-shaped semiconductor lower layer, and the an input terminal line is arranged to interconnect a gate of each of the two SGTs at respective ones of the intersection of the 1st row and the 3rd column and the intersection of the 2nd row and the 3rd column, and a gate of the SGT at and the intersecting of the 2nd row and 2nd column. | 08-05-2010 |
| 20100194439 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the n-type transistor network is connected to the second dedicated logic terminal, and the first network gate connection of the n-type transistor network is connected to the second logic input. The inner diffusion connections of the p-type network and of the n-type network are connected together to form a common diffusion logic terminal. | 08-05-2010 |
| 20100225356 | LATCH CIRCUIT - A latch circuit includes an input part receiving an external input signal; a plurality of CMOS inverter circuits divided into a first group that includes a first CMOS inverter circuit and a second CMOS inverter circuit outputting inverted data with respect to the input signal, and a second group that includes a third CMOS inverter circuit and a fourth CMOS inverter circuit outputting the same data as the input signal; and a feedback path through which the input signal is fed back to the input part via the plurality of CMOS inverter circuits, wherein a second-polarity drain belonging to one of the first CMOS inverter circuit and the second CMOS inverter circuit is arranged between a first-polarity drain belonging to the first CMOS inverter circuit and a first-polarity drain belonging to the second CMOS inverter circuit. | 09-09-2010 |
| 20100231263 | Logic Circuit and Method of Logic Circuit Design - A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The first dedicated logic terminal is connected to the outer diffusion connection of the p-type transistor, the second dedicated logic terminal is connected to the outer diffusion connection of the n-type transistor, the inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor is connected to form a common diffusion logic terminal, the high-voltage terminal is connected to the bulk connection of the p-type transistor, and the low-voltage terminal is connected to the bulk connection of the n-type transistor. | 09-16-2010 |
| 20110241731 | Electro Static Discharge Clamping Device - Electrostatic discharge clamp devices are described. In one embodiment, the semiconductor device includes a first transistor, the first transistor including a first source/drain and a second source/drain, the first source/drain coupled to a first potential node, the second source/drain coupled to a second potential node. The device further includes a OR logic block, a first input of the OR logic block coupled to the first potential node through a capacitor, the first input of the OR logic block being coupled to the second potential node through a resistor, and a second input of the OR logic block coupled to a substrate pickup node of the first transistor. | 10-06-2011 |
| 20110267107 | CIRCUIT FOR REDUCING NEGATIVE BIAS TEMPERATURE INSTABILITY - A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode. | 11-03-2011 |
| 20120081151 | DELAY CIRCUIT AND INVERTER FOR SEMICONDUCTOR INTEGRATED DEVICE - An inverter of a delay circuit in a semiconductor integrated device that has a high resistance to an electrostatic discharge. The delay circuit includes at least one inverter. Each inverter has high and low potential parts. The low potential part includes a pair of FETs. A source terminal of one FET is connected to a drain terminal of the other FET at a first common node. The high potential part includes another pair of FETs, with a source terminal of one FET being connected to a drain terminal of the other FET at a second common node. A power supply potential is applied to the first common node when the inverter output becomes a high potential. A ground potential is applied to the second common node when the inverter output becomes a low potential. | 04-05-2012 |
| 20130002303 | CMOS CIRCUIT WITH DYNAMIC PARASITIC NET PULLDOWN CIRCUIT - A complementary metal oxide semiconductor (CMOS) circuit is described. The CMOS circuit includes a plurality of CMOS gates, a plurality of logic inputs and a logic output. Each CMOS gate is connected to a negative power supply terminal (Vss) and a positive power supply terminal (Vdd). The CMOS circuit further includes parasitic nets connected to the CMOS gates, and net pulldown circuits for eliminating a charge accumulation on the parasitic nets while avoiding potential short circuit conditions. The CMOS gates may be OR-AND-INVERT (OAI) gates or AND-OR-INVERT (AOI) gates. | 01-03-2013 |
| 20150022239 | Multiplexing for Systems with Multiple Supply Sources - A system includes an inverter element to gate forward current flow from a first signal source, and a reverse current inhibition element to block reverse current flow towards the first signal source from a second signal source. | 01-22-2015 |
| 20150102839 | LOW POWER INVERTER CIRCUIT - A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another. | 04-16-2015 |
| 20160065214 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: an inverter gate circuit which inverts and outputs a logic level of an input signal, the inverter gate circuit includes a constant current source and a switch unit which are connected in series between a first power supply wiring and a second power supply wiring, and, according to the control signal, the switch unit switches real values of a gate length and a gate width of a switch transistor configured by a transistor to which a current outputted from the constant current source is applied among a plurality of transistors. | 03-03-2016 |
| 20180026612 | SEMICONDUCTOR DEVICE | 01-25-2018 |
