| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 326112000 |
Field-effect transistor (e.g., JFET, etc.)
| 101 |
| 326105000 |
Decoding
| 19 |
| 326111000 |
Space discharge device (e.g., vacuum tube, etc.) | 3 |
| 20130249598 | MICROSCALE DIGITAL VACUUM ELECTRONIC GATES - Systems and methods in accordance with embodiments of the invention implement microscale digital vacuum electronic gates. In one embodiment, a microscale digital vacuum electronic gate includes: a microscale field emitter that can emit electrons and that is a microscale cathode; and a microscale anode; where the microscale field emitter and the microscale anode are disposed within at least a partial vacuum; where the microscale field emitter and the microscale anode are separated by a gap; and where the potential difference between the microscale field emitter and the microscale anode is controllable such that the flow of electrons between the microscale field emitter and the microscale anode is thereby controllable; where when the microscale anode receives a flow of electrons, a first logic state is defined; and where when the microscale anode does not receive a flow of electrons, a second logic state is defined. | 09-26-2013 |
| 20130335118 | ELECTRONIC DEVICE AND METHODE FOR IMPLEMENTING LOGIC FUNCTIONS AND FOR GUIDING CHARGED PARTICLES - A device and method are presented for implementing one or more logic functions. The device comprises one or more basic blocks, each comprising a predetermined number of charged particle inputs, at least one interaction zone defining a function space, and at least one charged particle output at a certain distance from the interaction zone. The logic function is a result of an affected interaction between the charged particles. | 12-19-2013 |
| 20160380634 | PRINTED LOGIC GATE - An additively manufactured apparatus having a gas filled sealed cavity containing at least two additively manufactured cathodes and an additively manufactured anode spaced from the cathodes such that a continuous electric discharge of the gas stimulated between at least one of the cathodes and the anode provides a Boolean function output at the anode corresponding to electrical input signals at two of the cathodes. | 12-29-2016 |
| 326133000 |
Diode | 2 |
| 20090009218 | Literal Gate Using Resonant Tunneling Diodes - The present invention relates to a literal gate using resonant tunneling diodes; and, more particularly, to a literal gate using only resonant tunneling diodes (RTDs). | 01-08-2009 |
| 20120249183 | POWER MANAGEMENT DEVICE - A power management device for controlling a power supply device includes a pulse generator, a delay unit, a first XOR gate, an OR gate, and a second XOR gate. The pulse generator generates a pulse signal, the delay unit, the first XOR gate, the OR gate, and the second XOR gate cooperatively generate an enabling signal corresponding to the pulse signal to enable and disable the power supply, and receive an output voltage of the power supply device as a feedback signal. Upon receiving the feedback signal, the power management device can stay at correct enabled and disabled statuses of the power supply device. | 10-04-2012 |
| 326124000 |
Bipolar transistor (e.g., RTL, DCTL, etc.) | 1 |
| 20090322378 | Electrical Device For Performing Logic Functions - An electronic device is presented for performing at least one logic function. The device comprises an electron emission based electrode arrangement associated with an electron extractor. The electrode arrangement comprises at least one basic unit including a photocathode, an anode, and one or more gates arranged aside a cavity defined between the photocathode and the anode. Said one or more gates are connectable to a voltage supply unit to be operated by one or more input voltages signals corresponding to one or more logical values, respectively. Said anode is operable as a floating electrode from which an electrical output of the device indicative of a resulted logic function is read. The anode is electrically connected to a photocathode of another cathode-anode unit of the same device, or is connected to an electrode of another electronic device. | 12-31-2009 |
| 326109000 |
Bipolar and FET | 1 |
| 20120112793 | Low-Current Logic-Gate Circuit - A circuit includes E-mode transistors with gate-source junction, a D-mode transistor with gate-source junction. A component generates a voltage drop between the source of the D-mode transistor and the drain of an E-mode transistor provided as a signal output. A connection is made between this drain of the E-mode transistor and the gate of the D-mode transistor, and a signal input at the gates of the E-mode transistors. | 05-10-2012 |
| Entries |
| Document | Title | Date |
|---|
| 20080197884 | Kick Gate - Feedback is reduced by routing an input signal through a kick gate that opens for a predetermined time period then closes. The gate may be kept closed for a predetermined minimum time period before being allowed to open again. The gate is triggered open based on the input signal and may include a plurality of triggering conditions. | 08-21-2008 |
| 20080258773 | UNIVERSAL LOGIC GATE UTILIZING NANOTECHNOLOGY - A universal logic gate apparatus is disclosed, which include a plurality of self-assembling chains of nanoparticles having a plurality of resistive connections, wherein the plurality of self-assembling chains of nanoparticles comprise resistive connects utilized to create A plasticity mechanism is also provided, which is based on a plasticity rule for creating stable connections from the plurality of self-assembling chains of nanoparticles for use with the universal, reconfigurable logic gate. The plasticity mechanism can be based, for example, on a 2-dimensional binary input data stream, depending upon design considerations. A circuit is also associated with the plurality of self-assembling chains of nanoparticles, wherein the circuit provides a logic bypass that implements a flip-cycle for second-level logic. Additionally, an extractor logic gate is associated with the plurality of self-assembling chains of nanoparticles, wherein the extractor logic gate provides logic functionalities. | 10-23-2008 |
| 20090033369 | ARBITRARY QUANTUM OPERATIONS WITH A COMMON COUPLED RESONATOR - A quantum logic gate is formed from multiple qubits coupled to a common resonator, wherein quantum states in the qubits are transferred to the resonator by transitioning a classical control parameter between control points at a selected one of slow and fast transition speeds, relative to the characteristic energy of the coupling, whereby a slow transition speed exchanges energy states of a qubit and the resonator, and a fast transition speed preserves the energy states of a qubit and the resonator. | 02-05-2009 |
| 20090085609 | MULTIPLEXOR WITH LEAKAGE POWER REGULATOR - A circuit for a multiplexer includes a pair of NAND gates with outputs coupled to an OAI gate constructed from a complementary circuit formed from solid state devices. A current flow controller formed from solid state devices is coupled to one of the NAND gates. When activated the controller inhibits the flow of current through the NAND gate and a portion of the OAI gate to which the controller is connected. As a consequence, leakage power is not consumed within the multiplexer. Several of the applications in which the circuit is used are also demonstrated in the specification. | 04-02-2009 |
| 20090091352 | NANOTUBE-BASED SWITCHING ELEMENTS WITH MULTIPLE CONTROLS - Nanotube-based switching elements with multiple controls and circuits made from such. A switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node. The control structure includes a control electrode and a release electrode, disposed on opposite sides of the nanotube channel element. The control and release may be used to form a differential input, or if the device is constructed appropriately to operate the circuit in a non-volatile manner. The switching elements may be arranged into logic circuits and latches having differential inputs and/or non-volatile behavior. | 04-09-2009 |
| 20090189642 | Nanowire Crossbar Implementations of logic Gates using configurable, tunneling resistor junctions - Various embodiments of the present invention are directed to nanowire crossbars that use configurable, tunneling resistor junctions to electronically implement logic gates. In one embodiment of the present invention, a method for implementing a logic gate comprises: providing a first layer of approximately parallel nanowires; interconnecting the first layer of approximately parallel nanowires with a second layer of approximately parallel nanowires through configurable, tunneling resistor junctions; selecting nanowires from among the first and second layer of nanowires to carry input and output electrical signals representing logical values; applying electrical signals representing input logical values to the input nanowires; and detecting an electrical signal representing an output logical value on the output nanowires. | 07-30-2009 |
| 20090206882 | Thermal Electric NOR Gate - A thermal electric (TE) binary NOR gate logic circuit is provided with a method for NOR logic gating. The method accepts a first input voltage representing an input binary logic state and generates a first thermal electric (TE) temperature in response to the first input voltage. A second input voltage is accepted representing an input binary logic state, and a second TE temperature is generated in response to the second input voltage. In response to the first and second TE temperatures, a NOR logic state output voltage is generated. More explicitly, a first control voltage is generated in response to the first TE temperature, and a second control voltage is generated in response to the second TE temperature. Then, a third TE temperature is generated in response to the first and second control voltages, which in turn generates the output voltage. | 08-20-2009 |
| 20090206883 | Thermal Electric NAND Gate - A thermal electric (TE) binary NAND gate logic circuit is provided with a method for NAND logic gating. The method accepts a first input voltage representing an input binary logic state and generates a first thermal electric (TE) temperature in response to the first input voltage. A second input voltage is accepted representing an input binary logic state, and a second TE temperature is generated in response to the second input voltage. In response to the first and second TE temperatures, a NAND logic state output voltage is generated. More explicitly, a first control voltage is generated in response to the first TE temperature, and a second control voltage is generated in response to the second TE temperature. Then, a third TE temperature is generated in response to the first and second control voltages, which in turn generates the output voltage. | 08-20-2009 |
| 20090256594 | NANOELECTROMECHANICAL DIGITAL INVERTER - A digital inverter formed by three carbon nanotubes (CNTs) extending vertically from a substrate, one CNT functioning as first source (S | 10-15-2009 |
| 20090289663 | CIRCUIT FOR COMPARING TWO N-DIGIT BINARY DATA WORDS - The invention relates to a circuit for comparing two n-digit binary data words x[1](t), . . . , x[n](t) and x′[1](t), . . . , x′[n](t), which in the error-free case are either identical or inverted bit-by-bit with respect to each other, with a series connection of a combinatorial circuit for implementing a first combinatorial function, a controllable register and a combinatorial circuit for implementing another combinatorial function. | 11-26-2009 |
| 20100033212 | Multiplexing using Product-of-Sums and Sum-of-Products - A method for and the results of implementing a tree of multiplexing are disclosed. At each level of the tree, a sum-of-products or a product-of-sums representation is chosen to maximize inter-level optimizations. | 02-11-2010 |
| 20100148824 | CIRCUIT ARRANGEMENT FOR PRODUCING SHORT ELECTRICAL PULSES - A circuit arrangement for producing short electrical pulses, including a logic gate ( | 06-17-2010 |
| 20100156468 | Even-number-stage pulse delay device - The even-number-stage pulse delay includes a ring delay line constituted of an even number of inverter circuits connected in a ring around which main edge and a reset edge circulate together. The even-number-stage pulse delay is provided with an operation monitoring section configured to detect whether or not the main and reset edges are circulating around the ring delay line. | 06-24-2010 |
| 20100164548 | Implementing Logic Functions With Non-Magnitude Based Physical Phenomena - An n-valued switch with n≧2 and n>2 and n>7, with an input enabled to receive a signal in one of n states, an output enabled to provide a signal in one of at least 2 states, under control of a control signal having one of at least 2 states is disclosed. Signals are instances of a physical phenomenon, an instance representing a state. N-valued inverters are also disclosed. Different types of signals are disclosed, including optical signals with different wavelengths, electrical signals with different frequencies and signals represented by a presence of a material. A kit including an n-valued switch is also disclosed. | 07-01-2010 |
| 20100219862 | RECONFIGURABLE AND RELIABLE LOGIC CIRCUIT ELEMENTS THAT EXPLOIT NONLINEARITY AND NOISE - A logic gate is adapted to implement logical expressions. The logic gate includes at least one input that is adapted to receive an input signal and at least one control signal. At least one of the input signal and the control signal is a noise signal. At least one output is adapted to produce an output signal. A nonlinear updater operates as a dynamically configurable element and produces multiple different logic gates as selected by the control signal based at least in part on the noise signal. The nonlinear updater is electrically coupled to the input and is also electrically coupled to the output. The nonlinear updates is configured to apply a nonlinear function to the input signal in response to the control signal to produce the output signal representing a logical expression being implemented by one of the multiple different logic gates on the input signal. | 09-02-2010 |
| 20110043252 | SELF-TIMED TRIGGER WITH SINGLE-RAIL DATA INPUT - A self-timed implementation of single-stage and two-stage self-timed triggers with single-rail data input is provided. This is achieved by a circuit containing storage unit with element indicating transition termination, single-rail data input, control input, data output, and indication output, into which a conversion unit is added which converts single-rail data input and control input signals and has data input, control input, data output and control output. An additional feedback output allows for speeding-up transition of device, which is a source of the single-rail data input of the trigger. | 02-24-2011 |
| 20110062993 | NANOTUBE-BASED SWITCHING ELEMENTS AND LOGIC CIRCUITS - Nanotube-based switching elements and logic circuits are disclosed. Under one embodiment of the invention, a Boolean logic circuit includes at least one input terminal and an output terminal, and a network of nanotube switching elements electrically disposed between said at least one input terminal and said output terminal. The network of nanotube switching elements effectuates a Boolean function transformation of Boolean signals on said at least one input terminal. The Boolean function transformation includes a Boolean inversion within the function, such as a NOT or NOR function. | 03-17-2011 |
| 20110156756 | COUNTERMEASURE METHOD AND DEVICE FOR PROTECTING DATA CIRCULATING IN AN ELECTRONIC COMPONENT - A countermeasure in a logic circuit having a logic gate supplying a binary output signal, the method including supplying binary data having random values to inputs of logic circuit during a precharge phase; supplying data to process to inputs of the logic circuit during a data processing phase; supplying on input of the logic circuit a precharge command signal launching a precharge phase; and under the effect of the precharge command signal, adapting the functioning of a logic gate of the logic circuit, statistically unbalanced, so that the output signal of the logic gate is in a binary state with a same probability as the random binary data supplied on input of the logic circuit during the precharge phase. | 06-30-2011 |
| 20120194220 | Frequency Divider with Synchronous Range Extension Across Octave Boundaries - A frequency divider based on a series of divide-by-2/3 cells and divide-by-1/2/3 cells using extended division range is disclosed. The frequency divider uses modified divide-by-1/2/3 cells and additional circuit elements to correctly divide an input frequency by a divisor on successive output cycles while the divisor transitions across an octave boundary. The frequency divider creates a divide-by-1 mode for unused divide-by-1/2/3 cells in the series of cells. The divide-by-1 mode passes the input clock in the unused latches of each unused divide-by-1/2/3 cell as opposed to having each unused divide-by-1/2/3 cell implement divide-by-3 mode. | 08-02-2012 |
| 20120293211 | DELAY LINE OFF-STATE CONTROL WITH POWER REDUCTION - A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state. | 11-22-2012 |
| 20120313664 | Semiconductor Device Having Features to Prevent Reverse Engineering - It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices. | 12-13-2012 |
| 20120313665 | BANDGAP READY CIRCUIT - A bandgap ready circuit for an RFID tag includes a bandgap circuit for providing a bandgap voltage, a first comparator for monitoring first and second voltages in the bandgap circuit and for providing a first logic signal, a second comparator for monitoring third and fourth voltages in the bandgap circuit and for providing a second logic signal, and a logic circuit for combining the first and second logic signals to provide a bandgap ready logic signal. | 12-13-2012 |
| 20120319732 | MAGNETIC LOGIC DEVICE - The present disclosure provides for magnetic logic devices and methods of operating such a device. In one embodiment, the device includes a bottom electrode configured to receive a first input current and a second input current, a bottom magnetic layer disposed over the bottom electrode, a nonmagnetic layer disposed over the bottom magnetic layer, a top magnetic layer disposed over the nonmagnetic layer, and a top electrode disposed over the top magnetic layer, the top electrode and the bottom electrode configured to provide an output voltage which is dependent on the first and second input currents and which follows an AND gate logic or an OR gate logic. | 12-20-2012 |
| 20130002302 | COUNTERMEASURE METHOD AND DEVICE FOR PROTECTING DATA CIRCULATING IN AN ELECTRONIC COMPONENT - A countermeasure in a logic circuit having a logic gate supplying a binary output signal, the method including supplying binary data having random values to inputs of logic circuit during a precharge phase; supplying data to process to inputs of the logic circuit during a data processing phase; supplying on input of the logic circuit a precharge command signal launching a precharge phase; and under the effect of the precharge command signal, adapting the functioning of a logic gate of the logic circuit, statistically unbalanced, so that the output signal of the logic gate is in a binary state with a same probability as the random binary data supplied on input of the logic circuit during the precharge phase. | 01-03-2013 |
| 20130063180 | MASTER-SLAVE INTERLEAVED BCM PFC CONTROLLER AND CONTROL METHOD THEREOF - The present invention relates to a master-slave interleaved BCM PFC controller for controlling a PFC circuit with master and slave channels. In one embodiment, the PFC controller can include: a master channel controller that generates a master channel control signal and an inverted master channel control signal; a first phase shifter that provides a first phase shift for the master channel control signal, and generates a delayed opening signal therefrom; a second phase shifter that provides a second phase shift for the inverted master channel control signal, and generates a delayed shutdown signal therefrom; a slave channel controller that receives the delayed opening signal, the delayed shutdown signal, and a slave channel inductor current zero-crossing signal, and generates a slave channel control signal therefrom. | 03-14-2013 |
| 20130154687 | Semiconductor Device Having Features to Prevent Reverse Engineering - It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices. | 06-20-2013 |
| 20130181743 | Binary Logic Unit and Method to Operate a Binary Logic Unit - A binary logic unit to apply any Boolean operation on two input signals (v | 07-18-2013 |
| 20130187680 | Complementary Logic Device Comprising Metal-to-Insulator Transition Material - A complementary logic technology is disclosed whereby a logic gate comprises at least two metal-to-insulator transition (MIT) elements and at least two thermoelectric elements, each MIT element being thermally coupled to a corresponding thermoelectric element. In logic gates, each electric signal at an input terminal of a logic gate is first converted into two complementary thermal signals, and these thermal signals in turn determine the status of the output terminal of the logic gate, thereby generating an electrical output signal inverse to the electrical input signal or an output signal which is a Boolean operation on input signals. The parallel connection(s) of thermoelectric elements of the logic gate is used to create corresponding thermal signals for each electrical input signal. The MIT elements of the logic gate are then arranged to, in response to the associated thermal signals, execute a Boolean operation. | 07-25-2013 |
| 20140035620 | LOGIC GATE - A logic gate including a first resistive non-volatile memory device and a second resistive non-volatile memory device is provided. When top electrodes of the first and the second resistive non-volatile memory devices are coupled to an output terminal of the logic gate, bottom electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to a first input terminal and a second input terminal of the logic gate. When the bottom electrodes of the first and the second resistive non-volatile memory devices are coupled to the output terminal of the logic gate, the top electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to the first input terminal and the second input terminal of the logic gate. | 02-06-2014 |
| 20140097870 | NANO-ELECTRO-MECHANICAL-SWITCH ADIABATIC DYNAMIC LOGIC CIRCUITS - A dynamic logic gate includes a nano-electro-mechanical-switch, preferably a four-terminal-nano-electro-mechanical-switch. The invention further refers to dynamic logic cascade circuits comprising such a dynamic logic gate. In particular, embodiments of the invention concern dynamic logic cascade circuits comprising single or dual rail dynamic logic gates. | 04-10-2014 |
| 20140232432 | DEVICE AND METHOD FOR DUAL-MODE LOGIC - A dual-mode logic gate, for selectable operation in either of static and dynamic modes, includes: a static gate which includes at least one logic input and a logic output; a mode selector, configured for outputting a turn-off signal to select static mode operation and for outputting a dynamic clock signal to select dynamic mode operation; and a switching element associated with the mode selector static gate, comprising a first input connected to a constant voltage, a second input for inputting the mode selection signal from the mode selector, and an output connected to a logic output of the static gate. The switching elements switches the logic gate operation from static to dynamic mode, by applying the appropriate signal to the switching element. | 08-21-2014 |
| 20150008959 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit may include a plurality of fuse boxes, each suitable for selectively outputting a first input signal and a reverse input signal obtained by inverting the first input signal; and a first output signal generator suitable for selectively receiving the first input signal and the reverse input signal from the fuse boxes, and generating a first output signal by performing a logical combination operation on the received input signals, a second input signal, and a third input signal. | 01-08-2015 |
| 20150381175 | SEMICONDUCTOR APPARATUS AND REDUCED CURRENT AND POWER CONSUMPTION - A semiconductor apparatus may include a mode control circuit configured to output differential output signals which swing in a current mode logic (CML) area and a first control signal, in response to a power-down mode signal; a first circuit unit configured to be provided with the differential output signals, and operate in a power-down mode; and a second circuit unit configured to be provided with the differential output signals, and be interrupted in its operation in the power-down mode. | 12-31-2015 |
| 20180026645 | Magnetoelectric Computational Devices | 01-25-2018 |
