| Entries |
| Document | Title | Date |
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| 20080238486 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN APPARATUS - A semiconductor integrated circuit design method includes a step (L) of providing layout information for laying out elements making up a logical circuit on a semiconductor substrate; a step (P) of providing logical circuit information; a step (a) of classifying logical circuits in response to the logical circuit propagation route of a signal based on the logical circuit information and a step (b) of isolating the logical circuits forming the route obtained in the classifying step (a) for each number of stages; a step (c) of classifying the elements making up the logical circuit according to substrate voltage for each number of stages of the logical circuit; and a layout correction step (d) of correcting the layout information so that each element with the larger stage number of the logical circuit is placed at a point closer to a substrate contact. | 10-02-2008 |
| 20090033368 | LOGIC BLOCK, A MULTI-TRACK STANDARD CELL LIBRARY, A METHOD OF DESIGNING A LOGIC BLOCK AND AN ASIC EMPLOYING THE LOGIC BLOCK - A logic block, a cell library, a method of designing a logic block and an ASIC including the logic block. The invention provides a logic block including rows of standard cells having different track heights. In one embodiment, the invention provides a logic block including: (1) a first row of standard cells having a first track height and (2) a second row of standard cells adjacent to the first row and having a second track height that differs from the first track height. | 02-05-2009 |
| 20090091351 | CHIP IDENTIFICATION SYSTEM AND METHOD - Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key. | 04-09-2009 |
| 20090184733 | LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL - This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (≦90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors. | 07-23-2009 |
| 20090212819 | METHOD AND SYSTEM FOR CHANGING CIRCUITS IN AN INTEGRATED CIRCUIT - A method for modifying an integrated circuit and integrated circuits are provided. The method includes: providing an integrated circuit design comprising a plurality of circuit books having a first threshold voltage; and replacing at least one of the plurality of circuit books with at least one gate array book having a second threshold voltage that is lower than the first threshold voltage. | 08-27-2009 |
| 20090278569 | Semiconductor Device and its Manufacturing Method, Semiconductor Manufacturing Mask, and Optical Proximity Processing Method - An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area ( | 11-12-2009 |
| 20090322377 | METHOD AND SYSTEM FOR SIZING FLOW CONTROL BUFFERS - A system that includes a first buffer and a second buffer, wherein the first buffer and the second buffer are connected to the same input, wherein a size of the first buffer is defined by a distance of the first buffer from the input and a transfer rate of data, wherein a size of the second buffer is defined by a distance of the second buffer from the input and the transfer rate of data, and wherein the distance between the first buffer and the input is different from the distance between the second buffer and the input. | 12-31-2009 |
| 20100052729 | DIGITAL DATA INVERSION FLAG GENERATOR CIRCUIT - An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained in a data word to be transmitted from the memory cells is greater than a threshold number. The digital flag generator circuit includes a first digital stage including a first plurality of binary logic circuits. Each of the binary logic circuits is configured to receive a subset of the data word. | 03-04-2010 |
| 20100066411 | LOGIC CIRCUIT USING METAL-INSULATOR TRANSITION (MIT) DEVICE - Provided is a logic circuit comprising a metal-insulator transition (MIT) device, including: an MIT device unit including an MIT thin film, an electrode thin film contacting the MIT thin film, and at least one MIT device undergoing a discontinuous MIT at a transition voltage V | 03-18-2010 |
| 20100073031 | NANOTUBE-BASED SWITCHING ELEMENTS WITH MULTIPLE CONTROLS AND LOGIC CIRCUITS HAVING SAID ELEMENTS - Boolean logic circuits comprising nanotube-based switching elements with multiple controls. The Boolean logic circuits include input and output terminals and a network of nanotube switching elements electrically disposed between said at least one input terminal and said output terminal. Each switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel along the nanotube channel element. At least one nanotube switching element non-volatilely retains an informational state and at least one nanotube switching elements volatilely retains an informational state. The network of nanotube switching elements effectuates a Boolean function transformation of Boolean signals on said at least one input terminal. Dual rail cascode logic circuits may also be constructed from the nanotube switching elements. | 03-25-2010 |
| 20100123481 | Semiconductor integrated circuit - A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other. | 05-20-2010 |
| 20100127732 | CMOS-Process-Compatible Programmable Via Device - Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided comprising a substrate; a dielectric layer on the substrate; a heater on at least a portion of a side of the dielectric layer opposite the substrate; a first oxide layer over the side of the dielectric layer opposite the substrate and surrounding at least a portion of the heater; a first capping layer over a side of the first oxide layer opposite the dielectric layer; at least one programmable via extending through the first capping layer and the first oxide layer and in contact with the heater, the programmable via comprising at least one phase change material; a second capping layer over the programmable via; a second oxide layer over a side of the first capping layer opposite the first oxide layer; a pair of first conductive vias, each extending through the first and second oxide layers and the first capping layer, and in contact with the heater; and a second conductive via, located between the pair of first conductive vias, extending through the second oxide layer and in contact with the second capping layer. | 05-27-2010 |
| 20100148822 | FIELD PROGRAMMABLE GATE ARRAY UTILIZING DEDICATED MEMORY STACKS IN A VERTICAL LAYER FORMAT - A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips. | 06-17-2010 |
| 20100201400 | METHOD FOR IMPLEMENTING FUNCTIONAL CHANGES INTO A DESIGN LAYOUT OF AN INTEGRATED DEVICE, IN PARTICULAR A SYSTEM-ON-CHIP, BY MEANS OF MASK PROGRAMMABLE FILLING CELLS - A System-on-Chip (SoC) may include logic blocks connected to each other and to external connections, and a hardware debug infrastructure logic connected to the logic blocks and for performing functional changes to a design layout of the SoC. The hardware debug infrastructure logic may include software re-configurable modules based upon the logic blocks obtained from substituting a mask programmable ECO base cell configured as a functional logic cell for a logic cell in the design layout. | 08-12-2010 |
| 20100225354 | LOOKUP TABLE, SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD FOR MAKING LOOKUP TABLE AND METHOD FOR MAKING SEMICONDUCTOR INTEGRATED CIRCUIT - A lookup table includes a single via layer having 2 | 09-09-2010 |
| 20100231261 | Apparatus and Method for Mixed Single-Rail and Dual-Rail Combinational Logic with Completion Detection - A computer readable storage medium includes executable instructions to receive a specification of a combinational logic circuit. The specification of the combinational logic circuit is converted to a Single-Rail un-encoded circuit and a Dual-Rail encoded circuit, which periodically encodes a null value, a first valid state and a second valid state on two wires. A logic operation of the Single-Rail un-encoded circuit transpires during processing of a null value by the Dual-Rail encoded circuit. | 09-16-2010 |
| 20100264955 | METAL PROGRAMMABLE LOGIC AND MULTIPLE FUNCTION PIN INTERFACE - Some of the embodiments of the present invention provide an integrated circuit device including a first metal interconnect, an end of which is coupled to a core of the integrated circuit device, a second metal interconnect, an end of which is coupled to a first input/output (I/O) pin, and a third metal interconnect configured to be coupled to the first metal interconnect and to the second metal interconnect. Other embodiments are also described and claimed. | 10-21-2010 |
| 20100271071 | Universal Inter-Layer Interconnect for Multi-Layer Semiconductor Stacks - A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. Based upon a standardized placement of the inter-layer interface region in each circuit layer, and a standardized arrangement of electrical conductors associated with the inter-layer bus, each circuit layer may designed using a standardized template upon which the design features necessary to implement the inter-layer bus are already provided, thereby simplifying circuit layer design and the interconnection of functional units to the inter-layer bus. In addition, vertically-oriented supernodes may be defined within a semiconductor stack to provide multiple independently-operating nodes having functional units disposed in multiple circuit layers of the stack. | 10-28-2010 |
| 20100283508 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A semiconductor chip includes a plurality of pads, input circuits or output circuits that are electrically connected to the pads, a main control unit that outputs a read access signal, the read access signal controlling reading of signals from an external circuit or an internal circuit, and activation control units that control activation of the input circuits or the output circuits that are electrically connected to the pads based on the read access signal, the pads receiving the signals from the external circuit or the internal circuit. | 11-11-2010 |
| 20100301901 | UNIVERSAL TWO-INPUT LOGIC GATE THAT IS CONFIGURABLE AND CONNECTABLE IN AN INTEGRATED CIRCUIT BY A SINGLE MASK LAYER ADJUSTMENT - A spare logic circuit for implementing any one of a plurality of logic gates includes a multiplexer circuit whose select inputs are utilized as logic gate inputs, and whose output is utilized as a logic gate output. Each of a plurality of data inputs of the multiplexer circuit is configured to receive one of first and second logic voltage levels which define the desired logic function. By modifying a single photolithographic mask, the spare logic gate can be: configured to perform the desired logic function; connected into a target logic circuit; or both configured and connected into a target logic circuit. | 12-02-2010 |
| 20110025378 | SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD THEREOF - A layout method for a semiconductor integrated circuit includes, generating logic cell layout data by arranging logic cells and signal lines connected to said logic cells, by using an automatic place and root tool, generating variable capacitor cell layout data by arranging variable capacitor cells and control lines for controlling capacitance value of the variable capacitor cells, by using the automatic place and root tool, and generating layout data of the semiconductor integrated circuit, based on the logic cell layout data and the variable capacitor cell layout data. The generating variable capacitor cell layout data includes, arranging the control lines so as to be same as said signal lines in a resistance of a unit length in one wiring layer. | 02-03-2011 |
| 20120032704 | INTEGRATION OF OPEN SPACE/DUMMY METAL AT CAD FOR PHYSICAL DEBUG OF NEW SILICON - An access pad is used to provide access to a functional block of an integrated circuit (IC) device. The access pad is formed using dummy metal in an open space in a metallization level that is between a top metallization level and a base level on which the functional block is formed in the IC device. The access pad at the metallization level provides a contact to access an underlying circuit of the functional block so that the functional integrity of the functional block of the IC device can be verified during probing. | 02-09-2012 |
| 20120081150 | Method of adapting standard cells - A method of adapting a layout of a standard cell of an integrated circuit is provided. A current collection path in the standard cell is selected which connects components within the standard cell to an output connection, wherein the current collection path is arranged to collect current from the components at a plurality of current collection points arranged along its length. A maximum current location on the current collection path is determined at which a maximum possible current flow in the current collection path will occur if the output connection is connected there, the maximum possible current flow being a sum of current contributions from the current collection points. A maximum width of the current collection path at the maximum current location is determined such that the maximum width satisfies a minimum path width requirement with respect to the maximum possible current flow. Then a local width of the current collection path at a selected distance from the maximum current location is determined, the local width being less than or equal to the maximum width, such that the local width satisfies the minimum path width requirement with respect to a maximum local current that will occur at the selected distance, the maximum local current being a sum of the current contributions from those current collection points which contribute to the local current. | 04-05-2012 |
| 20120119785 | INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR - One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides. | 05-17-2012 |
| 20120161814 | STACKED DEVICE IDENTIFICATION ASSIGNMENT - Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled to the dice. The connection may be configured to transfer control information to the first die during an assignment of a first identification to the first die and to transfer the control information from the first die to the second die during an assignment of a second identification to the second die. | 06-28-2012 |
| 20120194217 | INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR - One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides. | 08-02-2012 |
| 20120249182 | Power Routing in Standard Cell Designs - A cell-based architecture for an integrated circuit. A row of cell instances borders a first adjacent row of cell instances along a first boundary and a second adjacent row of cell instances along a second boundary. A first power rail (e.g., carrying an auxiliary voltage) extends along the first boundary. A second power rail (e.g., VSS) extends along the second boundary. The second power rail is wider than the first power rail. Additionally, a third power rail (e.g., VDD) extends across the interior of the second row of cells. | 10-04-2012 |
| 20120293206 | PROGRAMMABLE LOGIC DEVICE - An object is to provide a programmable logic device having logic blocks connected to each other by a programmable switch, where the programmable switch is characterized by an oxide semiconductor transistor incorporated therein. The extremely low off-state current of the oxide semiconductor transistor provides a function as a non-volatile memory due to its high ability to hold a potential of a gate electrode of a transistor which is connected to the oxide semiconductor transistor. The ability of the oxide semiconductor transistor to function as a non-volatile memory allows the configuration data for controlling the connection of the logic blocks to be maintained even in the absence of a power supply potential. Hence, the rewriting process of the configuration data at starting of the device can be omitted, which contributes to the reduction in power consumption of the device. | 11-22-2012 |
| 20130257481 | TREE BASED ADAPTIVE DIE ENUMERATION - A system and method for efficiently addressing dies in a three-dimensional stacked integrated circuit. Multiple stacked dies may be included in a single package or module. At least two of the dies are vertically stacked. One or more of the dies may include die enumeration logic that generates a unique die address space identifier (ID) for a particular die. Unless a die is a base die, each die receives a unique die ID for itself from a die placed below itself. The die then generates a unique die ID for one or more dies placed above itself and sends these die IDs to the dies located on top of itself. If a die is a base die, then the logic may receive a root value for a first unique die ID within the vertical stack from the package substrate or silicon based interposer beneath it. | 10-03-2013 |
| 20140021982 | NANOELECTROMECHANICAL LOGIC DEVICES - Nanoelectromechanical logic devices can include a plurality of flexible bridges having control and logic electrodes. Voltages applied to control electrodes can be used to control flexing of the bridges. The logic electrodes can provide logical functions of the applied voltages. | 01-23-2014 |
| 20140028351 | Nanomagnetic Logic Gate and an Electronic Device - A nanomagnetic logic gate arranged on a substrate according to an embodiment includes at least one nanomagnetic first structure, at least one nanomagnetic second structure and at least two layers including a first layer and a second layer, wherein at least one first structure is arranged in the first layer on or parallel to a main surface of the substrate, wherein at least one second structure is arranged in the second layer parallel to the first layer, and wherein at least one second structure includes an artificial nucleation center arranged such that a magnetic field component essentially perpendicular to the main surface provided by at least one first structure couples to the artificial nucleation center such that a magnetization of the second structure is changeable in response to the magnetic field component coupled into the artificial nucleation center, when a predetermined condition is fulfilled. | 01-30-2014 |
| 20140043063 | SEMICONDUCTOR DEVICE - A gate interconnection portion includes a first gate interconnection portion, a second gate interconnection portion, and a third gate interconnection portion. The first gate interconnection portion is formed in parallel to a Y axis direction toward a power supply interconnection and extends to a prescribed position within an element formation region. The second gate interconnection portion is formed in parallel to a direction obliquely bent with respect to the Y-axis direction from the first gate interconnection portion toward the power supply interconnection, and extends across a boundary between the element formation region and an element isolation insulating film, which is in parallel to an X axis direction. The third gate interconnection portion further extends in parallel to the Y-axis direction from the second gate interconnection portion toward the power supply interconnection. | 02-13-2014 |
| 20140139265 | HIGH SPEED PRECESSIONALLY SWITCHED MAGNETIC LOGIC - High speed precessionally switched magnetic logic devices and architectures are described. In a first example, a magnetic logic device includes an input electrode having a first nanomagnet and an output electrode having a second nanomagnet. The spins of the second nanomagnet are non-collinear with the spins of the first nanomagnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes. In a second example, a magnetic logic device includes an input electrode having an in-plane nanomagnet and an output electrode having a perpendicular magnetic anisotropy (PMA) magnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes. | 05-22-2014 |
| 20140167818 | Method and System for Multiple I/O Regions - Methods and/or associated devices and/or systems for creating integrated circuits (IC's) that have multiple connected I/O regions that can be designed and implemented using commonly available standard I/O libraries in conjunction with standard IC design flows and tools and in combination with one or more novel standardized I/O region interconnect cells for interconnecting between or through otherwise separated I/O regions. Specific embodiments support a wide variety of IC's that can be developed using standard libraries and design flows including: application specific integrated circuits (ASIC's), programmable logic devices (PLDs), custom IC's, analog IC's, CPU's, GPU's, and other IC's that require large numbers of input/ouput (IO) circuits while having relatively small core circuitry areas. Specific embodiments may involve innovative I/O cell functions, innovative IC topologies, and innovative IC packaging solutions for single die packages and multiple die packages. | 06-19-2014 |
| 20140327471 | STANDARD CELLS FOR PREDETERMINED FUNCTION HAVING DIFFERENT TYPES OF LAYOUT - An integrated circuit is manufactured by a predetermined manufacturing process having a nominal minimum pitch of metal lines. The integrated circuit includes a plurality of metal lines extending along a first direction and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines is separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. The plurality of standard cells includes a first standard cell configured to perform a predetermined function and having a first layout and a second standard cell configured to perform the predetermined function and having a second layout different than the first layout. The first and second standard cells have a cell height (H) along the second direction, and the cell height being a non-integral multiple of the nominal minimum pitch. | 11-06-2014 |
| 20140354331 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region. | 12-04-2014 |
| 20150318856 | GRAPHENE-BASED NON-BOOLEAN LOGIC CIRCUITS - A dual-gate transistor having a negative differential resistance (NDR) region is disclosed. The dual-gate transistor includes a back-gate, a zero-bandgap graphene layer disposed on the back-gate, a top-gate disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate, and a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate and displaced from the source. Also included is a dynamic bias controller configured to simultaneously sweep a source-drain voltage and a top-gate voltage across a Dirac point to provide operation within the NDR region. Operation within the NDR region is employed to realize non-Boolean logic functions. Graphene-based non-Boolean logic circuits are constructed from pluralities of the disclosed dual-gate transistor. Pattern recognition circuitry for operation between 100 GHz and 500 GHz is also disclosed via the graphene-based non-Boolean logic circuits. | 11-05-2015 |
| 20150341036 | HIGH SPEED PRECESSIONALLY SWITCHED MAGNETIC LOGIC - High speed precessionally switched magnetic logic devices and architectures are described. In a first example, a magnetic logic device includes an input electrode having a first nanomagnet and an output electrode having a second nanomagnet. The spins of the second nanomagnet are non-collinear with the spins of the first nanomagnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes. In a second example, a magnetic logic device includes an input electrode having an in-plane nanomagnet and an output electrode having a perpendicular magnetic anisotropy (PMA) magnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes. | 11-26-2015 |
