| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 326026000 | Output switching noise reduction | 45 |
| 20080218199 | OUTPUT LEVEL STABILIZATION CIRCUIT AND CML CIRCUIT USING THE SAME - An output level stabilization circuit being an output level stabilization circuit for a CML circuit, the output level stabilization circuit includes: a replica circuit constituted of transistors respectively having the same characteristics as one of differential-pair transistors of the CML circuit and a current source transistor; a comparison circuit which compares an output of the replica circuit with a reference voltage and supplies the comparison result as a control voltage for the current source transistor of the replica circuit; and a variable impedance circuit arranged between the output of the replica circuit and an input of the comparison circuit. | 09-11-2008 |
| 20080278191 | Leakage Power Management with NDR Isolation Devices - A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device raises the voltage at the virtual ground node above an isolation voltage, which causes NDR isolation device isolates the virtual ground node from ground. The virtual ground control device can then raise the voltage at the virtual ground node to the positive supply voltage to eliminate sub-threshold leakage currents the logic block. Alternatively, the virtual ground control device can raise the voltage at the virtual ground node to the positive supply voltage minus a retention voltage so that storage elements in the logic block can retain state information while still greatly reducing sub-threshold leakage current. | 11-13-2008 |
| 20080284464 | TIME BASED DRIVER OUTPUT TRANSITION (SLEW) RATE COMPENSATION - Apparatus controlling the driver output slew rate that includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A delay circuit having a time delay proportional to a desired transition time of the driver output signal is coupled to the output of the driver circuit. A first comparator detects when the driver output signal rises through a specified level, and a second comparator detects when the driver output falls through a second specified level. A phase detector is coupled to outputs of the first and second comparators and an output of the delay circuit for aligning the phases of the comparator outputs and the delayed comparator outputs by adjusting the driver output slew rate. | 11-20-2008 |
| 20080297192 | TECHNIQUES FOR OPTIMIZING DESIGN OF A HARD INTELLECTUAL PROPERTY BLOCK FOR DATA TRANSMISSION - Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block. | 12-04-2008 |
| 20080303545 | Low Power and Low Noise Differential Input Circuit - A differential input circuit with lower power consumption and noise is disclosed. Rather than completely discharging output nodes differential circuits, the present invention equalizes the output nodes to conserver power and to reduce noise. Specifically, an equalization circuit is coupled between the output nodes of the low power and low noise differential input circuit. | 12-11-2008 |
| 20090153184 | OUTPUT DRIVER CIRCUIT WITH OUTPUT PRESET CIRCUIT AND CONTROLLING METHOD THEREOF HAVING LOWER POWER CONSUMPTION - The configurations of an output preset circuit for an output driver circuit and the controlling methods thereof are provided. The proposed output preset circuit includes a latch generating an latch output signal and a pull-up circuit receiving an preset enable signal and the latch output signal, in which the pull-up circuit increases an output voltage of the output driver circuit from a ground level to a first level when the preset enable signal is at a low level and the latch output signal is at the high level. | 06-18-2009 |
| 20100102847 | MODULATED SUPPLY SPREAD SPECTRUM - A system reduces a received RF signal from EMI generated by a digital electronic system that includes a clock. In the present invention the clock frequency, that generates signals and strobes data out, is purposely changed or modulated, by, illustratively, driving the power node of the clock. The typical filter circuit between the clock power node and the power supply is used to advantage in that the filter impedance allows a buffer to more easily drive the clock power node since the low impedance of the power supply is isolated by the filter circuit. The changing of the clock frequency spreads the EMI RF harmonics over a spectrum so that any harmonics received by an RF receiver will be short lived and therefore of small magnitude. | 04-29-2010 |
| 20100213971 | PSEUDO-DIFFERENTIAL INTERFACING DEVICE HAVING A SWITCHING CIRCUIT - The invention relates to an interfacing device for pseudo-differential transmission through interconnections used for sending a plurality of electrical signals. The interfacing device of the invention includes signal terminals and a common terminal. A transmitting circuit receives the input signals of the transmitting circuit coming from a source. The output of the transmitting circuit delivers, when the transmitting circuit is in the activated state, voltages between one of the signal terminals and the reference terminal (ground). A receiving circuit delivers, when the receiving circuit is in the activated state, output signals of the receiving circuit determined each by the voltage between one of the signal terminals and the common terminal, to the destination. In the closed state, the common terminal switching circuit is, for the common terminal, equivalent to a voltage source delivering a constant voltage, connected in series with a passive two-terminal circuit element presenting a low impedance. | 08-26-2010 |
| 20110062983 | REDUCING SWITCHING NOISE - Described herein are various principles for operating a transmitter circuit to reduce noise affecting a signal being generated and reducing jitter. In some embodiments, a circuit is operated in a way that switching occurs at or above a bit rate of transmission, such that at least one switch changes state at least for every bit. Operating the circuit in such a way leads to a switching rate that is above a resonant frequency of the circuit and prevents large oscillations and noise from being inserted into the signal and causing communication problems. | 03-17-2011 |
| 20110234257 | OUTPUT DRIVER ROBUST TO DATA DEPENDENT NOISE - Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment. | 09-29-2011 |
| 326027000 | With field effect-transistor | 19 |
| 20090102509 | REDUCED AREA ACTIVE ABOVE-GROUND AND BELOW-SUPPLY NOISE SUPPRESSION CIRCUITS - A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal. | 04-23-2009 |
| 20090146682 | DATA OUTPUT DRIVING CIRCUIT AND METHOD FOR CONTROLLING SLEW RATE THEREOF - A data output driving circuit capable of optimizing a slew rate of data according to the variation of operational conditions and a method for controlling a slew rate thereof includes a slew rate control signal generating unit configured to generate slew rate control signals by using a code signal, and a plurality of drivers configured to output data by driving the data at a slew rate set according to the slew rate control signals. | 06-11-2009 |
| 20090206873 | DATA OUTPUT DRIVER - A data output driver device includes a noise detecting unit configured to output a noise detection signal to detect variations of power supply voltage due to noise, and a driver circuit unit configured to drive and output data with the variable driving capability in response to the noise detection signal. | 08-20-2009 |
| 20090212815 | TRIPLE LATCH FLIP FLOP SYSTEM AND METHOD - A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch. | 08-27-2009 |
| 20090237108 | Semiconductor integrated circuit - Provided is a semiconductor integrated circuit including: an output circuit connected between a power supply (VDD0) and a ground (GND0), having an input connected to an input terminal, and having an output connected to an output terminal; and a power-supply-noise cancelling circuit connected between the input terminal and the output terminal to generate a current that cancels a current flowing from the power supply (VDD0) to the output terminal or a current flowing from the output terminal to the ground (GND0), based on a potential difference between the input terminal and the output terminal. | 09-24-2009 |
| 20090273363 | OUTPUT DRIVER CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE OUTPUT DRIVER CIRCUIT, AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY DEVICE - Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device, including a pre-driver to generate a pull-up control signal and a pull-down control signal according to a logic value of data to output, and to adjust and output a slew rate of the pull-up control signal and a slew rate of the pull-down control signal according to a termination resistance setting information, a pull-up driver to output logic high data in response to the pull-up control signal and a pull-down driver to output logic low data in response to the pull-down control signal. | 11-05-2009 |
| 20090302885 | TWO TRANSISTOR TIE CIRCUIT WITH BODY BIASING - A circuit for body biasing is provided. The circuit includes: (1) a p-type transistor having a first current terminal, which is coupled to a first voltage supply, a second current terminal, a control terminal, and a bulk terminal; and (2) an n-type transistor having a first current terminal, which is coupled to a second voltage supply different from the first voltage supply, a second current terminal, a control terminal, and a bulk terminal, wherein the bulk terminal of the p-type transistor, the second current terminal of the p-type transistor, and the control terminal of the n-type transistor is coupled to a first node, wherein the control terminal of the p-type transistor, the bulk terminal of the n-type transistor, and the second current terminal of the second transistor is coupled to a second node different from the first node. | 12-10-2009 |
| 20100052728 | LOAD SENSE AND ACTIVE NOISE REDUCTION FOR I/O CIRCUIT - An I/O circuit includes load sense and active noise reduction features that result in high speed output signal transitions with very low noise. Capacitive feedback control circuitry controls the point and time at which feedback capacitors are applied to the gate drive of the I/O circuit output stage. Active device feedback control controls the output stage gate drive. | 03-04-2010 |
| 20100194427 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a driver that receives a power supply voltage and drives an external load with a driving capability; a measurement unit that measures a level of the power supply voltage; a code table that stores the level of the power supply voltage and code information for determining the driving capability of the driver; and a controller that reads the code information in accordance with the level of a measured power supply voltage in reference to the code table and controls the driving capability of the driver in accordance with the code information. | 08-05-2010 |
| 20100219856 | OUTPUT BUFFER CIRCUIT AND DIFFERENTIAL OUTPUT BUFFER CIRCUIT, AND TRANSMISSION METHOD - In an output buffer circuit including Inverter | 09-02-2010 |
| 20100253384 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. A pull-up slew rate controller receives a first driving control signal generated in a first mode of operation, a second driving control signal generated in a second mode of operation, and data, and upon a first transition of the data, sequentially activates the data and a first pull-up delayed signal having different delay times in the first mode of operation and sequentially activates the data and the first to third pull-up delayed signals having different delay times in the second mode of operation. A pull-up driving unit sequentially pulls a data output terminal up in response to the data and the first to third pull-up delayed signals. A pull-down slew rate controller, upon a second transition of the data, sequentially activates the data and the first pull-down delayed signal having different delay times in the first mode of operation and sequentially activates the data and the first to third pull-down delayed signals having different delay times in the second mode of operation. A pull-down driving unit sequentially pulls the data output terminal down in response to the data and the first to third pull-down delayed signals. | 10-07-2010 |
| 20100308859 | Local Interconnect Network Transceiver Driver - Various driver circuit apparatuses and methods for driving an electrical signal are disclosed herein. For example, some embodiments provide a driver circuit including a controlled-slew rate input circuit, a buffer that is connected to the controlled-slew rate input circuit, and an output driver that is connected to the buffer. The driver circuit is adapted to drive an output signal from the output driver based on an input signal to the controlled-slew rate input circuit. The impedance at the input of the output driver is lower than the impedance at the output of the controlled-slew rate input circuit. | 12-09-2010 |
| 20100308860 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of data driving units, each configured to drive a corresponding data output pad by a power supply voltage supplied through a power supply voltage input pin and a ground voltage supplied through a ground voltage input pin, in response to a corresponding bit of a data code, a pattern sensing unit configured to sense a bit pattern of the data code and generate a pattern sensing signal, and a phantom driving unit configured to form a current path between the power supply voltage input pin and the ground voltage input pin and to drive the current path by a driving force determined in response to the pattern sensing signal. | 12-09-2010 |
| 20110248741 | Semiconductor integrated circuit - A semiconductor integrated circuit includes a macro connected between a first power supply line and a second power supply line to drive a load, and a power-supply-noise cancelling circuit connected between an input and an output of the macro to generate a current for canceling one of a current flowing from the first power supply line to the output of the macro and a current flowing from the output of the macro to the second power supply line, on the basis of a potential difference between the input and the output of the macro. The macro and the power-supply-noise cancelling circuit are mounted in a same chip. | 10-13-2011 |
| 20120025866 | SEMICONDUCTOR DEVICE - A semiconductor device includes a slew rate controller configured to receive a mode register set signal and data and to activate a driving strength control signal for controlling the driving strength of a driving unit using the data in response to a code value of the mode register set signal. The driving unit is configured to pull a data output terminal up and down in response to the driving strength control signal. | 02-02-2012 |
| 20140375354 | Low Leakage and Data Retention Circuitry - An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry. | 12-25-2014 |
| 20090102509 | REDUCED AREA ACTIVE ABOVE-GROUND AND BELOW-SUPPLY NOISE SUPPRESSION CIRCUITS - A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal. | 04-23-2009 |
| 20090146682 | DATA OUTPUT DRIVING CIRCUIT AND METHOD FOR CONTROLLING SLEW RATE THEREOF - A data output driving circuit capable of optimizing a slew rate of data according to the variation of operational conditions and a method for controlling a slew rate thereof includes a slew rate control signal generating unit configured to generate slew rate control signals by using a code signal, and a plurality of drivers configured to output data by driving the data at a slew rate set according to the slew rate control signals. | 06-11-2009 |
| 20090206873 | DATA OUTPUT DRIVER - A data output driver device includes a noise detecting unit configured to output a noise detection signal to detect variations of power supply voltage due to noise, and a driver circuit unit configured to drive and output data with the variable driving capability in response to the noise detection signal. | 08-20-2009 |
| 20090212815 | TRIPLE LATCH FLIP FLOP SYSTEM AND METHOD - A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch. | 08-27-2009 |
| 20090237108 | Semiconductor integrated circuit - Provided is a semiconductor integrated circuit including: an output circuit connected between a power supply (VDD0) and a ground (GND0), having an input connected to an input terminal, and having an output connected to an output terminal; and a power-supply-noise cancelling circuit connected between the input terminal and the output terminal to generate a current that cancels a current flowing from the power supply (VDD0) to the output terminal or a current flowing from the output terminal to the ground (GND0), based on a potential difference between the input terminal and the output terminal. | 09-24-2009 |
| 20090273363 | OUTPUT DRIVER CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE OUTPUT DRIVER CIRCUIT, AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY DEVICE - Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device, including a pre-driver to generate a pull-up control signal and a pull-down control signal according to a logic value of data to output, and to adjust and output a slew rate of the pull-up control signal and a slew rate of the pull-down control signal according to a termination resistance setting information, a pull-up driver to output logic high data in response to the pull-up control signal and a pull-down driver to output logic low data in response to the pull-down control signal. | 11-05-2009 |
| 20090302885 | TWO TRANSISTOR TIE CIRCUIT WITH BODY BIASING - A circuit for body biasing is provided. The circuit includes: (1) a p-type transistor having a first current terminal, which is coupled to a first voltage supply, a second current terminal, a control terminal, and a bulk terminal; and (2) an n-type transistor having a first current terminal, which is coupled to a second voltage supply different from the first voltage supply, a second current terminal, a control terminal, and a bulk terminal, wherein the bulk terminal of the p-type transistor, the second current terminal of the p-type transistor, and the control terminal of the n-type transistor is coupled to a first node, wherein the control terminal of the p-type transistor, the bulk terminal of the n-type transistor, and the second current terminal of the second transistor is coupled to a second node different from the first node. | 12-10-2009 |
| 20100052728 | LOAD SENSE AND ACTIVE NOISE REDUCTION FOR I/O CIRCUIT - An I/O circuit includes load sense and active noise reduction features that result in high speed output signal transitions with very low noise. Capacitive feedback control circuitry controls the point and time at which feedback capacitors are applied to the gate drive of the I/O circuit output stage. Active device feedback control controls the output stage gate drive. | 03-04-2010 |
| 20100194427 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a driver that receives a power supply voltage and drives an external load with a driving capability; a measurement unit that measures a level of the power supply voltage; a code table that stores the level of the power supply voltage and code information for determining the driving capability of the driver; and a controller that reads the code information in accordance with the level of a measured power supply voltage in reference to the code table and controls the driving capability of the driver in accordance with the code information. | 08-05-2010 |
| 20100219856 | OUTPUT BUFFER CIRCUIT AND DIFFERENTIAL OUTPUT BUFFER CIRCUIT, AND TRANSMISSION METHOD - In an output buffer circuit including Inverter | 09-02-2010 |
| 20100253384 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. A pull-up slew rate controller receives a first driving control signal generated in a first mode of operation, a second driving control signal generated in a second mode of operation, and data, and upon a first transition of the data, sequentially activates the data and a first pull-up delayed signal having different delay times in the first mode of operation and sequentially activates the data and the first to third pull-up delayed signals having different delay times in the second mode of operation. A pull-up driving unit sequentially pulls a data output terminal up in response to the data and the first to third pull-up delayed signals. A pull-down slew rate controller, upon a second transition of the data, sequentially activates the data and the first pull-down delayed signal having different delay times in the first mode of operation and sequentially activates the data and the first to third pull-down delayed signals having different delay times in the second mode of operation. A pull-down driving unit sequentially pulls the data output terminal down in response to the data and the first to third pull-down delayed signals. | 10-07-2010 |
| 20100308859 | Local Interconnect Network Transceiver Driver - Various driver circuit apparatuses and methods for driving an electrical signal are disclosed herein. For example, some embodiments provide a driver circuit including a controlled-slew rate input circuit, a buffer that is connected to the controlled-slew rate input circuit, and an output driver that is connected to the buffer. The driver circuit is adapted to drive an output signal from the output driver based on an input signal to the controlled-slew rate input circuit. The impedance at the input of the output driver is lower than the impedance at the output of the controlled-slew rate input circuit. | 12-09-2010 |
| 20100308860 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of data driving units, each configured to drive a corresponding data output pad by a power supply voltage supplied through a power supply voltage input pin and a ground voltage supplied through a ground voltage input pin, in response to a corresponding bit of a data code, a pattern sensing unit configured to sense a bit pattern of the data code and generate a pattern sensing signal, and a phantom driving unit configured to form a current path between the power supply voltage input pin and the ground voltage input pin and to drive the current path by a driving force determined in response to the pattern sensing signal. | 12-09-2010 |
| 20110248741 | Semiconductor integrated circuit - A semiconductor integrated circuit includes a macro connected between a first power supply line and a second power supply line to drive a load, and a power-supply-noise cancelling circuit connected between an input and an output of the macro to generate a current for canceling one of a current flowing from the first power supply line to the output of the macro and a current flowing from the output of the macro to the second power supply line, on the basis of a potential difference between the input and the output of the macro. The macro and the power-supply-noise cancelling circuit are mounted in a same chip. | 10-13-2011 |
| 20120025866 | SEMICONDUCTOR DEVICE - A semiconductor device includes a slew rate controller configured to receive a mode register set signal and data and to activate a driving strength control signal for controlling the driving strength of a driving unit using the data in response to a code value of the mode register set signal. The driving unit is configured to pull a data output terminal up and down in response to the driving strength control signal. | 02-02-2012 |
| 20140375354 | Low Leakage and Data Retention Circuitry - An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry. | 12-25-2014 |
| 326028000 | With clocking | 3 |
| 20080204070 | Reduced power output buffer - A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor. | 08-28-2008 |
| 20100033208 | SHIFT REGISTER UNITS, DISPLAY PANELS UTILIZING THE SAME, AND METHODS FOR IMPROVING CURRENT LEAKAGE THEREOF - A shift register comprising at least one shift register unit. The shift register unit comprises an input unit, at least one first TFT, and at least one second TFT. The input unit receives an input signal from the input terminal and outputs a switching control signal in accordance with a first clock signal. The gate of the first TFT is for receiving the switching control signal, the drain of the first TFT is for receiving a second clock signal, and the source of the first TFT is coupled to the output terminal. The gate and drain of the second TFT are coupled to the output terminal, and the source of the second TFT is coupled to the input unit. | 02-11-2010 |
| 20130009665 | Integrated Circuit Elementary Cell with a Low Sensitivity to External Disturbances - The present invention relates to an integrated electronic circuit including elements enabling to implement a logic function and means for attenuating the sensitivity of said elements to external disturbances, said attenuation means being disconnectable during phases of intentional modification of the state of said elements. | 01-10-2013 |
| 326027000 | With field-effect transistor | 16 |
| 20090102509 | REDUCED AREA ACTIVE ABOVE-GROUND AND BELOW-SUPPLY NOISE SUPPRESSION CIRCUITS - A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal. | 04-23-2009 |
| 20090146682 | DATA OUTPUT DRIVING CIRCUIT AND METHOD FOR CONTROLLING SLEW RATE THEREOF - A data output driving circuit capable of optimizing a slew rate of data according to the variation of operational conditions and a method for controlling a slew rate thereof includes a slew rate control signal generating unit configured to generate slew rate control signals by using a code signal, and a plurality of drivers configured to output data by driving the data at a slew rate set according to the slew rate control signals. | 06-11-2009 |
| 20090206873 | DATA OUTPUT DRIVER - A data output driver device includes a noise detecting unit configured to output a noise detection signal to detect variations of power supply voltage due to noise, and a driver circuit unit configured to drive and output data with the variable driving capability in response to the noise detection signal. | 08-20-2009 |
| 20090212815 | TRIPLE LATCH FLIP FLOP SYSTEM AND METHOD - A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch. | 08-27-2009 |
| 20090237108 | Semiconductor integrated circuit - Provided is a semiconductor integrated circuit including: an output circuit connected between a power supply (VDD0) and a ground (GND0), having an input connected to an input terminal, and having an output connected to an output terminal; and a power-supply-noise cancelling circuit connected between the input terminal and the output terminal to generate a current that cancels a current flowing from the power supply (VDD0) to the output terminal or a current flowing from the output terminal to the ground (GND0), based on a potential difference between the input terminal and the output terminal. | 09-24-2009 |
| 20090273363 | OUTPUT DRIVER CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE OUTPUT DRIVER CIRCUIT, AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY DEVICE - Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device, including a pre-driver to generate a pull-up control signal and a pull-down control signal according to a logic value of data to output, and to adjust and output a slew rate of the pull-up control signal and a slew rate of the pull-down control signal according to a termination resistance setting information, a pull-up driver to output logic high data in response to the pull-up control signal and a pull-down driver to output logic low data in response to the pull-down control signal. | 11-05-2009 |
| 20090302885 | TWO TRANSISTOR TIE CIRCUIT WITH BODY BIASING - A circuit for body biasing is provided. The circuit includes: (1) a p-type transistor having a first current terminal, which is coupled to a first voltage supply, a second current terminal, a control terminal, and a bulk terminal; and (2) an n-type transistor having a first current terminal, which is coupled to a second voltage supply different from the first voltage supply, a second current terminal, a control terminal, and a bulk terminal, wherein the bulk terminal of the p-type transistor, the second current terminal of the p-type transistor, and the control terminal of the n-type transistor is coupled to a first node, wherein the control terminal of the p-type transistor, the bulk terminal of the n-type transistor, and the second current terminal of the second transistor is coupled to a second node different from the first node. | 12-10-2009 |
| 20100052728 | LOAD SENSE AND ACTIVE NOISE REDUCTION FOR I/O CIRCUIT - An I/O circuit includes load sense and active noise reduction features that result in high speed output signal transitions with very low noise. Capacitive feedback control circuitry controls the point and time at which feedback capacitors are applied to the gate drive of the I/O circuit output stage. Active device feedback control controls the output stage gate drive. | 03-04-2010 |
| 20100194427 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a driver that receives a power supply voltage and drives an external load with a driving capability; a measurement unit that measures a level of the power supply voltage; a code table that stores the level of the power supply voltage and code information for determining the driving capability of the driver; and a controller that reads the code information in accordance with the level of a measured power supply voltage in reference to the code table and controls the driving capability of the driver in accordance with the code information. | 08-05-2010 |
| 20100219856 | OUTPUT BUFFER CIRCUIT AND DIFFERENTIAL OUTPUT BUFFER CIRCUIT, AND TRANSMISSION METHOD - In an output buffer circuit including Inverter | 09-02-2010 |
| 20100253384 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. A pull-up slew rate controller receives a first driving control signal generated in a first mode of operation, a second driving control signal generated in a second mode of operation, and data, and upon a first transition of the data, sequentially activates the data and a first pull-up delayed signal having different delay times in the first mode of operation and sequentially activates the data and the first to third pull-up delayed signals having different delay times in the second mode of operation. A pull-up driving unit sequentially pulls a data output terminal up in response to the data and the first to third pull-up delayed signals. A pull-down slew rate controller, upon a second transition of the data, sequentially activates the data and the first pull-down delayed signal having different delay times in the first mode of operation and sequentially activates the data and the first to third pull-down delayed signals having different delay times in the second mode of operation. A pull-down driving unit sequentially pulls the data output terminal down in response to the data and the first to third pull-down delayed signals. | 10-07-2010 |
| 20100308859 | Local Interconnect Network Transceiver Driver - Various driver circuit apparatuses and methods for driving an electrical signal are disclosed herein. For example, some embodiments provide a driver circuit including a controlled-slew rate input circuit, a buffer that is connected to the controlled-slew rate input circuit, and an output driver that is connected to the buffer. The driver circuit is adapted to drive an output signal from the output driver based on an input signal to the controlled-slew rate input circuit. The impedance at the input of the output driver is lower than the impedance at the output of the controlled-slew rate input circuit. | 12-09-2010 |
| 20100308860 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of data driving units, each configured to drive a corresponding data output pad by a power supply voltage supplied through a power supply voltage input pin and a ground voltage supplied through a ground voltage input pin, in response to a corresponding bit of a data code, a pattern sensing unit configured to sense a bit pattern of the data code and generate a pattern sensing signal, and a phantom driving unit configured to form a current path between the power supply voltage input pin and the ground voltage input pin and to drive the current path by a driving force determined in response to the pattern sensing signal. | 12-09-2010 |
| 20110248741 | Semiconductor integrated circuit - A semiconductor integrated circuit includes a macro connected between a first power supply line and a second power supply line to drive a load, and a power-supply-noise cancelling circuit connected between an input and an output of the macro to generate a current for canceling one of a current flowing from the first power supply line to the output of the macro and a current flowing from the output of the macro to the second power supply line, on the basis of a potential difference between the input and the output of the macro. The macro and the power-supply-noise cancelling circuit are mounted in a same chip. | 10-13-2011 |
| 20120025866 | SEMICONDUCTOR DEVICE - A semiconductor device includes a slew rate controller configured to receive a mode register set signal and data and to activate a driving strength control signal for controlling the driving strength of a driving unit using the data in response to a code value of the mode register set signal. The driving unit is configured to pull a data output terminal up and down in response to the driving strength control signal. | 02-02-2012 |
| 20140375354 | Low Leakage and Data Retention Circuitry - An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry. | 12-25-2014 |
| 20090102509 | REDUCED AREA ACTIVE ABOVE-GROUND AND BELOW-SUPPLY NOISE SUPPRESSION CIRCUITS - A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal. | 04-23-2009 |
| 20090146682 | DATA OUTPUT DRIVING CIRCUIT AND METHOD FOR CONTROLLING SLEW RATE THEREOF - A data output driving circuit capable of optimizing a slew rate of data according to the variation of operational conditions and a method for controlling a slew rate thereof includes a slew rate control signal generating unit configured to generate slew rate control signals by using a code signal, and a plurality of drivers configured to output data by driving the data at a slew rate set according to the slew rate control signals. | 06-11-2009 |
| 20090206873 | DATA OUTPUT DRIVER - A data output driver device includes a noise detecting unit configured to output a noise detection signal to detect variations of power supply voltage due to noise, and a driver circuit unit configured to drive and output data with the variable driving capability in response to the noise detection signal. | 08-20-2009 |
| 20090212815 | TRIPLE LATCH FLIP FLOP SYSTEM AND METHOD - A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch. | 08-27-2009 |
| 20090237108 | Semiconductor integrated circuit - Provided is a semiconductor integrated circuit including: an output circuit connected between a power supply (VDD0) and a ground (GND0), having an input connected to an input terminal, and having an output connected to an output terminal; and a power-supply-noise cancelling circuit connected between the input terminal and the output terminal to generate a current that cancels a current flowing from the power supply (VDD0) to the output terminal or a current flowing from the output terminal to the ground (GND0), based on a potential difference between the input terminal and the output terminal. | 09-24-2009 |
| 20090273363 | OUTPUT DRIVER CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE OUTPUT DRIVER CIRCUIT, AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY DEVICE - Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device, including a pre-driver to generate a pull-up control signal and a pull-down control signal according to a logic value of data to output, and to adjust and output a slew rate of the pull-up control signal and a slew rate of the pull-down control signal according to a termination resistance setting information, a pull-up driver to output logic high data in response to the pull-up control signal and a pull-down driver to output logic low data in response to the pull-down control signal. | 11-05-2009 |
| 20090302885 | TWO TRANSISTOR TIE CIRCUIT WITH BODY BIASING - A circuit for body biasing is provided. The circuit includes: (1) a p-type transistor having a first current terminal, which is coupled to a first voltage supply, a second current terminal, a control terminal, and a bulk terminal; and (2) an n-type transistor having a first current terminal, which is coupled to a second voltage supply different from the first voltage supply, a second current terminal, a control terminal, and a bulk terminal, wherein the bulk terminal of the p-type transistor, the second current terminal of the p-type transistor, and the control terminal of the n-type transistor is coupled to a first node, wherein the control terminal of the p-type transistor, the bulk terminal of the n-type transistor, and the second current terminal of the second transistor is coupled to a second node different from the first node. | 12-10-2009 |
| 20100052728 | LOAD SENSE AND ACTIVE NOISE REDUCTION FOR I/O CIRCUIT - An I/O circuit includes load sense and active noise reduction features that result in high speed output signal transitions with very low noise. Capacitive feedback control circuitry controls the point and time at which feedback capacitors are applied to the gate drive of the I/O circuit output stage. Active device feedback control controls the output stage gate drive. | 03-04-2010 |
| 20100194427 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a driver that receives a power supply voltage and drives an external load with a driving capability; a measurement unit that measures a level of the power supply voltage; a code table that stores the level of the power supply voltage and code information for determining the driving capability of the driver; and a controller that reads the code information in accordance with the level of a measured power supply voltage in reference to the code table and controls the driving capability of the driver in accordance with the code information. | 08-05-2010 |
| 20100219856 | OUTPUT BUFFER CIRCUIT AND DIFFERENTIAL OUTPUT BUFFER CIRCUIT, AND TRANSMISSION METHOD - In an output buffer circuit including Inverter | 09-02-2010 |
| 20100253384 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. A pull-up slew rate controller receives a first driving control signal generated in a first mode of operation, a second driving control signal generated in a second mode of operation, and data, and upon a first transition of the data, sequentially activates the data and a first pull-up delayed signal having different delay times in the first mode of operation and sequentially activates the data and the first to third pull-up delayed signals having different delay times in the second mode of operation. A pull-up driving unit sequentially pulls a data output terminal up in response to the data and the first to third pull-up delayed signals. A pull-down slew rate controller, upon a second transition of the data, sequentially activates the data and the first pull-down delayed signal having different delay times in the first mode of operation and sequentially activates the data and the first to third pull-down delayed signals having different delay times in the second mode of operation. A pull-down driving unit sequentially pulls the data output terminal down in response to the data and the first to third pull-down delayed signals. | 10-07-2010 |
| 20100308859 | Local Interconnect Network Transceiver Driver - Various driver circuit apparatuses and methods for driving an electrical signal are disclosed herein. For example, some embodiments provide a driver circuit including a controlled-slew rate input circuit, a buffer that is connected to the controlled-slew rate input circuit, and an output driver that is connected to the buffer. The driver circuit is adapted to drive an output signal from the output driver based on an input signal to the controlled-slew rate input circuit. The impedance at the input of the output driver is lower than the impedance at the output of the controlled-slew rate input circuit. | 12-09-2010 |
| 20100308860 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of data driving units, each configured to drive a corresponding data output pad by a power supply voltage supplied through a power supply voltage input pin and a ground voltage supplied through a ground voltage input pin, in response to a corresponding bit of a data code, a pattern sensing unit configured to sense a bit pattern of the data code and generate a pattern sensing signal, and a phantom driving unit configured to form a current path between the power supply voltage input pin and the ground voltage input pin and to drive the current path by a driving force determined in response to the pattern sensing signal. | 12-09-2010 |
| 20110248741 | Semiconductor integrated circuit - A semiconductor integrated circuit includes a macro connected between a first power supply line and a second power supply line to drive a load, and a power-supply-noise cancelling circuit connected between an input and an output of the macro to generate a current for canceling one of a current flowing from the first power supply line to the output of the macro and a current flowing from the output of the macro to the second power supply line, on the basis of a potential difference between the input and the output of the macro. The macro and the power-supply-noise cancelling circuit are mounted in a same chip. | 10-13-2011 |
| 20120025866 | SEMICONDUCTOR DEVICE - A semiconductor device includes a slew rate controller configured to receive a mode register set signal and data and to activate a driving strength control signal for controlling the driving strength of a driving unit using the data in response to a code value of the mode register set signal. The driving unit is configured to pull a data output terminal up and down in response to the driving strength control signal. | 02-02-2012 |
| 20140375354 | Low Leakage and Data Retention Circuitry - An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry. | 12-25-2014 |
