| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 324719000 | With semiconductor or IC materials quality determination using conductivity effects | 16 |
| 20080231293 | DEVICE AND METHOD FOR ELECTRICAL CONTACTING FOR TESTING SEMICONDUCTOR DEVICES - A device and method for electrical contacting for the testing of semiconductor devices is disclosed. One embodiment provides for the electrical connection of the semiconductor device with a test system, including devices for the contacting of connection pins or contact pads of the semiconductor device to be tested. The devices for the contacting of the connection pins or the contact pads of the semiconductor device to be tested include contact holders with at least one exchangeable contact tip. | 09-25-2008 |
| 20080284452 | SEMICONDUCTOR DEVICE AND METHOD OF MEASURING SHEET RESISITANCE OF LOWER LAYER CONDUCTIVE PATTERN THEREOF - Contact holes (openings) ( | 11-20-2008 |
| 20080297180 | DEVICE FOR MEASURING METAL/SEMICONDUCTOR CONTACT RESISTIVITY - A device for measuring the resistivity ρ | 12-04-2008 |
| 20090058434 | METHOD FOR MEASURING A PROPERTY OF INTERCONNECTIONS AND STRUCTURE FOR THE SAME - A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad. | 03-05-2009 |
| 20090058435 | HIGH-SENSITIVE RESISTANCE MEASURING DEVICE AND MONITORING METHOD OF SOLDER BUMP - According to an aspect of an embodiment, a high-sensitive resistance measuring device of solder bumps comprises a resistance variation detection unit which detects a differential voltage (□V=V | 03-05-2009 |
| 20090079446 | Method to Accurately Estimate the Source and Drain Resistance of a MOSFET - Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs in probing transistors that are partially fabricated or deprocessed, accurate estimates of external resistances are also required. This invention comprises a method for estimating series resistances of MOSFETs, including resistances associated with connections to the MOSFET, such as probe contacts. This method is applicable to any MOSFET which can be accessed on source, drain, gate and substrate terminals, and does not require other test structures or special connections, such as Kelvin connections. | 03-26-2009 |
| 20090091339 | Method for detection and analysis of impurity content in refined metallurgical silicon - This invention discloses a method for detection and analysis of impurity content of refined metallurgical silicon, comprising: (1) select the measuring points on the crystal rods or crystal ingots along the crystallization direction, measuring the resistivity at each measuring point and acquire the measured value of resistivity according to the distribution of crystallized fraction; (2) get the estimated value of the content of boron and phosphorus at each measuring point and calculate the estimated net redundant carrier concentration and the measured value of resistivity; (3) compare the estimated value of net redundant carrier concentration with that of the measured value, and adjust the estimated value of impurity content in the silicon material to get the new estimated net redundant carrier concentration, and use regression analysis to determine the impurity content distribution of boron and phosphorus; (4) get the average impurity content of boron and phosphorus in the silicon material according to the distribution status of impurity based on all the measuring points. This invention can detect accurately the impurity contents of boron and phosphorus in refined metallurgical silicon, while the operation is simple, low-cost and suitable for industrial applications. | 04-09-2009 |
| 20090102493 | Power Integrated Circuit with Bond-Wire Current Sense - An integrated circuit product includes: 1) a package, 2) a semiconductor die mounted within the package, 3) a first terminal and a second terminal for connecting the integrated circuit product to an external circuit, 4) one or more bond wires for transferring a current received at the first terminal to the second terminal; and 5) a circuit included in the semiconductor die that measures a voltage difference attributable to the resistance of the bond wires to measure the magnitude of the current passing through the first terminal. | 04-23-2009 |
| 20100052706 | CONSISTANT AND QUANTITATIVE METHOD FOR TCO DELAMINATION EVALUATION - A method and apparatus for manufacturing photovoltaic cells is provided. In one embodiment, a method for evaluating transparent conductive oxide (TCO) delamination from a substrate is provided. The method comprises providing a glass substrate with a TCO film laminated on a first surface of the glass substrate, depositing a metal layer on a second surface of the glass substrate opposite the first surface, heating the substrate while applying a bias to the substrate, cooling the substrate in a humidity controlled environment for a fixed time period, dividing the TCO film into a plurality of electrically insulated channels using a laser scribing process, and measuring a resistance of each of the plurality of electrically insulated channels. | 03-04-2010 |
| 20100134125 | BUILT-IN COMPLIANCE IN TEST STRUCTURES FOR LEAKAGE AND DIELECTRIC BREAKDOWN OF DIELECTRIC MATERIALS OF METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES - In a test structure for determining dielectric breakdown events of a metallization system of semiconductor devices, a built-in compliance functionality may allow reliable switching off of the test voltage prior to causing high leakage currents, which may conventionally result in significant damage. Consequently, further failure analysis may be possible after the occurrence of a dielectric breakdown event. | 06-03-2010 |
| 20100207648 | Contact Resistance Test Structure and Method Suitable for Three-Dimensional Integrated Circuits - A contact resistance test structure, a method for fabricating the contact resistance test structure and a method for measuring a contact resistance while using the contact resistance test structure are all predicated upon two parallel conductor lines (or multiples thereof) that are contacted by one perpendicular conductor line absent a via interposed there between. The test structure and related methods are applicable within the context of three-dimensional integrated circuits. | 08-19-2010 |
| 20100295567 | Resistance measuring device, display panel, and measuring method of bonding resistance - The resistance measuring device of the present invention includes switch transistors and switch conductive lines disposed between the bonding pads on a first substrate and between the bumps on a second substrate, such that the bonding pads and the bumps are conducted when the transistors are turned on, and the bonding resistance between at least one of the bonding pads and its corresponding bump can be directly measured. | 11-25-2010 |
| 20100327890 | QUALITY CONTROL PROCESS FOR UMG-SI FEEDSTOCK - A quality control process for determining the concentrations of boron and phosphorous in a UMG-Si feedstock batch is provided. A silicon test ingot is formed by the directional solidification of molten UMG-Si from a UMG-Si feedstock batch. The resistivity of the silicon test ingot is measured from top to bottom. Then, the resistivity profile of the silicon test ingot is mapped. From the resistivity profile of the silicon test ingot, the concentrations of boron and phosphorous of the UMG-Si silicon feedstock batch are calculated. Additionally, multiple test ingots may be grown simultaneously, with each test ingot corresponding to a UMG-Si feedstock batch, in a multi-crucible crystal grower. | 12-30-2010 |
| 20110133761 | QUALIFYING CIRCUIT BOARD MATERIALS - A test structure for testing electrical properties of a material comprises a first loop and a second loop, which are connected to form a closed test loop. A signal generator, for generating a test signal, is coupled to the first loop and the second loop. A signal propagation switching logic is coupled to the first loop and to the second loop for alternatingly flipping the test signal between the first and second loops, such that the test signal moves uninterrupted through the closed test loop. A probe logic detects any degradation of the test signal as the test signal travels along the closed test loop. | 06-09-2011 |
| 20150346252 | INTEGRATED CIRCUIT AND ASSOCIATED METHODS FOR MEASUREMENT OF AN EXTERNAL IMPEDANCE - An integrated circuit includes an output circuit having a first terminal adapted to couple to an external power supply, a second terminal adapted to couple to a reference potential, and a third, control terminal. The first and second terminals of the output circuit provide output terminals of the integrated circuit. The integrated circuit further includes an impedance measurement circuit responsive to the external power supply to generate a control signal for coupling to the control terminal of the output circuit. The control signal controls a current level associated with the output circuit. A corresponding method is also described. | 12-03-2015 |
| 20160187414 | DEVICE HAVING FINFETS AND METHOD FOR MEASURING RESISTANCE OF THE FINFETS THEREOF - A semiconductor device with FinFETs is provided, including a plurality of fin structures and a plurality of gate structures. The fin structures are disposed on a substrate, stretching along a first direction and spaced from each other by a first space. The fin structures comprise a selected fin structure. The gate structures are disposed on the substrate, stretching along a second direction. The gate structures comprise a first gate structure and a second gate structure which is adjacent to the first gate structure. A part of the selected fin structure and a part of the first gate structure form a first FinFET. A part of the selected fin structure and a part of the second gate structure form a second FinFET. The first FinFET is in depletion mode and the second FinFET is in enhancement mode. A method for measuring a resistance of FinFETs in a semiconductor device is provided. | 06-30-2016 |
