| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257697000 | Pin grid type | 16 |
| 20080265398 | SUBSTRATE WITH PIN, WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE - A substrate with pins comprises pins, and a holding substrate in which through holes to which the pins are attached are formed. Head parts of the pins are arranged in the through holes. The pins are attached by pressing the head parts in the through holes. | 10-30-2008 |
| 20080272481 | Pin grid array package substrate including slotted pins - An electrically conductive pin comprising a pin stem and a pin head attached to the pin stem. The pin head is adapted to be mounted onto a surface of a microelectronic substrate to support the pin stem. The pin head defines at least one slot therein, the at least one slot being configured to allow gases to escape therethrough from a region at an underside of the pin head. | 11-06-2008 |
| 20080283999 | Chip Package with Pin Stabilization Layer - Various methods and apparatus for semiconductor packing are disclosed. In one aspect, a method of manufacturing is provided that includes coupling first ends of plural conductor pins to a first surface of a semiconductor chip package substrate. A layer is formed on the first surface that engages and resists lateral movement of the conductor pins while leaving second ends of the conductor pins exposed. | 11-20-2008 |
| 20080296752 | SUBSTRATE WITH PIN, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PRODUCT - A semiconductor product is constructed of a wiring substrate in which pads for pin connection are formed, and a substrate with pins in which pins are disposed. The substrate with the pins is formed so that one end of the pin is exposed to one surface of a resin substrate formed by resin molding and the other end of the pin extends from the other surface of the resin substrate and one end of the pin is bonded to a pad of the wiring substrate through a conductive material. | 12-04-2008 |
| 20080303135 | Pin Grid Array Package Substrate Including Pins Having Curved Pin Heads - An electrically conductive pin comprising a pin stern and a pin head attached to the pin stem. The pin head is adapted to be mounted onto a surface of a microelectronic substrate to support the pin stem. The pin head has an underside surface defining a continuous curve configured to allow gases to escape from a pin-attach solder region adjacent the underside surface | 12-11-2008 |
| 20090127695 | SURFACE MOUNT PACKAGE WITH ENHANCED STRENGTH SOLDER JOINT - A substrate pad in a semiconductor package having a geometry and structure that facilitates providing a solder joint to the pad that has enhanced structural integrity and resistance to mechanical impact. The pad may include a plated metal stud that anchors the solder to the pad interface, providing a more compliant solder joint, even when lead-free solder is used. | 05-21-2009 |
| 20090289348 | SOLUTION FOR PACKAGE CROSSTALK MINIMIZATION - A method of minimizing crosstalk in an IC package including (A) routing a first signal between first pads and a first trace layer in an congested area, (B) routing the first signal between the first and second trace layers in an non-congested area, (C) routing the first signal between the second trace layer and first pins in the non-congested area, (D) routing a second signal between second pads and the first trace layer in the congested area, (E) routing the second signal between the first and the second trace layers in the congested area and (F) routing the second signal between the second trace layer and second pins in the non-congested area, wherein (i) all of the first and second pins are arranged along a line and (ii) the first pins are offset from the second pins by a gap of at least two inter-pin spaces. | 11-26-2009 |
| 20090315171 | PIN SUBSTRATE AND PACKAGE - A semiconductor die package. Embodiments of the package can include a substrate with solid conductive pins disposed throughout. A semiconductor die can be attached to a surface of the substrate. Electrical connection to the semiconductor die can be provided by the solid conductive pins. | 12-24-2009 |
| 20100001394 | CHIP PACKAGE WITH ESD PROTECTION STRUCTURE - A chip package comprises a semiconductor chip, a plurality of pins coupled to the semiconductor chip, and a conductive structure configured to form an electrical connection between the pins, wherein the electrical connection is configured to be disabled as the chip package is inserted into a socket. Since the pins are electrically connected by the conductive structure, the surge current caused by an ESD event can be distributed to all pins rather than to a single pin as the ESD event occurs. Consequently, all ESD protection circuits connected to the pins can be used to dissipate the surge current during the ESD event, and the circuit damage caused by the ESD can be dramatically reduced. | 01-07-2010 |
| 20100052152 | Semiconductor package transformer - The present invention relates to a semiconductor package transformer. There is provided a semiconductor package transformer including: a case where an opening into which a semiconductor package having a chip mounted on a substrate is inserted is formed on its front surface and an open part exposing is formed on its upper surface; and a plurality of holes that are formed on the bottom surface of the case. | 03-04-2010 |
| 20100052153 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package of the present invention, includes a wiring substrate, a lead pin fixed to a connection pad on one surface side of the wiring substrate by solder, and a reinforcing resin layer formed on a surface of the wiring substrate on which the lead pin is provided and having a projection-shaped resin portion which projects locally around the lead pin and covers a side surface of a base portion side of the lead pin. The projection-shaped resin portion has a top surface extending from an outer peripheral portion of the lead pin to an outside, and a side surface constituting a non-identical surface to the top surface. | 03-04-2010 |
| 20110057303 | Package for an Integrated Circuit - According to various illustrative embodiments of the present invention, a device for an integrated circuit includes a monolithic frame having a plurality of alignment features disposed thereon, the monolithic frame having a mounting surface disposed thereon for the integrated circuit, the monolithic frame also having a thermal interface area disposed thereon for the integrated circuit. The device also includes an electrical interface capable of providing an electrical connection for the integrated circuit, the plurality of alignment features being substantially independent of the electrical interface, and an adhesive layer disposed between the monolithic frame and the electrical interface. | 03-10-2011 |
| 20110074009 | Isostress grid array and method of fabrication thereof - An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate. The non-uniformity of length in the wire columns reduces stress in the package leads after attachment of the package to a carrier substrate, such as a printed circuit board. | 03-31-2011 |
| 20110140265 | Packaging of Silicon Wafers and Mating Pieces - By creating a package (MVLC) that has a redundant set of pins, twice as many points of contact are generated. More contacts create more routing and component placement options. | 06-16-2011 |
| 20140110833 | POWER MODULE PACKAGE - Disclosed herein is a power module package. The power module package includes a substrate having one surface formed with a circuit pattern including a chip mounting pad and an external connection pad and the other surface; a semiconductor chip mounted on the chip mounting pad; and an external connection terminal having one terminal and the other terminal, the one terminal being connected to the external connection pad and the other terminal protruding to the outside, in which the external connection pad and the external connection terminal are bonded to each other by welding. | 04-24-2014 |
| 20160064308 | SEMICONDUCTOR MODULE - A semiconductor module includes first and second semiconductor elements connected to pins, respectively; a first pin wiring substrate having first and second metal films bonded to the pin on the upper and lower surfaces; a first DCB substrate having third and fourth metal films on the upper and lower surfaces, the third metal film being bonded to the lower surface of the first semiconductor element; a second DCB substrate having fifth and sixth metal films respectively provided on the lower and upper surfaces, the fifth metal film being bonded to the upper surface of the second semiconductor element; a second pin wiring substrate having seventh and eighth metal films bonded to the pin, on the upper and lower surfaces; a connection member connected to the second and fifth metal films; a first cooler connected to the fourth metal film; and a second cooler connected to the sixth metal film. | 03-03-2016 |
