| Entries |
| Document | Title | Date |
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| 20080203555 | Universal substrate and semiconductor device utilizing the substrate - A universal substrate and a semiconductor device utilizing the substrate are disclosed in the present invention. The universal substrate mainly comprises a plurality of inner pads and a plurality of outer pads. A plurality of bifurcate wirings and a plurality of fuses are formed on a surface of the substrate. The fuses are connected with the bifurcate wirings in series. By the bifurcate wirings and the fuses, each of the inner pads is electrically connected to all of the outer pads to provide optional electrical disconnections therebetween. Accordingly, the universal substrate can be utilized for connecting chips having various serial arrangements of bonding pads without replacing or manufacturing another substrate. | 08-28-2008 |
| 20080217759 | Chip package substrate and structure thereof - A chip package substrate includes multiple pairs of connection pads. Both pads of a connection pad pair are separated from each other with a distance, which is smaller than the side length of a chip. An insulation layer is configured on the connection pads but exposes a portion of the surface of each of connection pads, and then a contact pad is configured on the exposed surface of each of connection pads. Thus, the connection pads are moved inwardly to under the chip carrier area to reduce the size of the chip package. | 09-11-2008 |
| 20080217760 | Semiconductor device and method of manufacturing same - A semiconductor device includes an outer resin case having a peripheral wall and terminal mounting holes formed in the peripheral wall, and a layer assembly provided in the outer resin case. The layer assembly includes a semiconductor chip, an insulating circuit board on which the semiconductor chip is mounted, and a heat-dissipating metal base. External terminals having leg portions are arranged in mounting holes of the peripheral wall, and are press-fitted into the terminal-mounting holes. Bonding wires connect the terminal leg portions and a conductive pattern of the insulating circuit board or the semiconductor chip. | 09-11-2008 |
| 20080224300 | Semiconductor Module With Semiconductor Chips And Method For Producing It - A semiconductor module has at least two semiconductor chips ( | 09-18-2008 |
| 20080230889 | SEMICONDUCTOR PACKAGE - A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive. | 09-25-2008 |
| 20080237834 | CHIP PACKAGING STRUCTURE AND CHIP PACKAGING PROCESS - A chip packaging structure comprising a chip, a plurality of conductive pillars surrounding the chip, an encapsulation encapsulating the chip and the conductive pillars, and a connecting layer is provided. The encapsulation has a first side and a second side corresponding to the first side. The connecting layer is disposed at the first side of the encapsulation and electrically connected between the chip and the conductive pillars. Furthermore, a chip packaging process accompanying the chip packaging structure is also provided. The chip packaging structure is more useful and powerful and is suitable for various chip packaging applications, and the chip packaging process can reduce the manufacturing time and save the production cost. | 10-02-2008 |
| 20080246139 | Polar hybrid grid array package - A grid array package includes a rectangular pattern of electrical contacts around a perimeter of the package. The grid array package also includes a polar pattern of electrical contacts inside of, and concentric with, the rectangular pattern. The grid array package also includes additional electrical contacts arranged between the rectangular pattern and the polar pattern. | 10-09-2008 |
| 20080272480 | Land grid array semiconductor package - An LGA (Land Grid Array) semiconductor package mainly comprises a substrate, a chip, a soldering layer and a foot stand. The chip is disposed on a top surface of the substrate and is electrically connected to a plurality of metal pads formed on a bottom surface of the substrate. The soldering layer is disposed on the metal pads with a first thickness slightly protruded from the bottom surface of the substrate. Additionally, the foot stand is disposed under the substrate with a second thickness protruded from the bottom surface of the substrate, wherein the second thickness is greater than the first thickness. Therefore, the soldering layer of the LGA semiconductor package is free from scratches and damages during shipping and handling processes. Moreover, the LGA semiconductor package can be surface-mounted to a printed circuit board with pre-applied solder or pre-mounted solder balls to increase the implementations of LGA semiconductor packages. | 11-06-2008 |
| 20080277773 | CIRCUIT STRUCTURES AND METHODS WITH BEOL LAYER(S) CONFIGURED TO BLOCK ELECTROMAGNETIC INTERFERENCE - Back end of line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic interference. One such BEOL circuit structure includes one or more semiconductor substrates supporting one or more integrated circuits, and one or more BEOL layers disposed over the semiconductor substrate(s). At least one BEOL layer includes a conductive pattern defined at least partially by a plurality of elements arrayed in a first direction and a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in at least one of the first and second directions to block electromagnetic interference of a particular wavelength from passing therethrough. In one implementation, a first conductive pattern of a first BEOL layer polarizes electromagnetic interference, and a second conductive pattern of a second BEOL layer blocks the polarized electromagnetic interference. | 11-13-2008 |
| 20080277774 | POWER SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, LEAD FRAME MEMBER, AND METHOD OF MAKING POWER SEMICONDUCTOR DEVICE - The power semiconductor device according to the present invention comprises a power element, a package encapsulating the power element with resin, a power element mounting portion used for mounting the power element, and a plurality of lead pins brought out of the package, including a power element lead pin brought out of the power element mounting portion. The power semiconductor device comprises a heat dissipating member having, adjacent the power element lead pin, a heat dissipating lead pin integrally connected to the power element lead pin and heat dissipating portion integrally connected to the heat dissipating lead pin. | 11-13-2008 |
| 20080290496 | WAFER LEVEL SYSTEM IN PACKAGE AND FABRICATION METHOD THEREOF - There is provided a system-in-package (SiP), which includes a substrate obtained by cutting a wafer for each unit system; one or more first electronic devices mounted on the substrate by a heat radiation plate; a plurality of interlayer dielectrics sequentially formed on the substrate; and one or more second electronic devices buried between or in the interlayer dielectrics on the substrate. A heat sink may be additionally attached to the bottom surface of the substrate. In this case, a thermal conduction path including heat pipes connecting the heat radiation plate on the substrate and the heat sink is formed. In the SiP, various types of devices are buried at a wafer level, so that a more integrated semiconductor device is implemented corresponding to demand for a fine pitch. Further, the heat radiation of a device required in high-speed operation and high heat generation is maximized due to the multi-stepped heat radiation structure, and thus the operation of the device is more stabilized. | 11-27-2008 |
| 20080296751 | Semiconductor package - A semiconductor package is revealed, primarily comprising a substrate, a chip disposed on the substrate, and an encapsulant to encapsulate the chip. The substrate has a plurality of dimples formed in its top surface thereof without penetrating through the substrate and located at a non-wiring region outside a chip mounting region. Therefore, without changing the appearance of the semiconductor package, the diffusion path of moisture and the adhesive strength between the encapsulant and the substrate can be increased to achieve functions of anti-humidity and anti-delamination. | 12-04-2008 |
| 20080315397 | DIE MOUNTING STRESS ISOLATOR - One method of the present invention includes preparing a die with traces and pads as desired for the intended use of the die. A MEMS device is mounted to the die. The die is then mounted to a substrate of the same material as the die. The substrate is then mounted to a package. The die and/or the substrate may be flip-chip mounted. | 12-25-2008 |
| 20080315398 | PACKAGING SUBSTRATE WITH EMBEDDED CHIP AND BURIED HEATSINK - An embedded chip package includes a substrate having a dielectric interposer, a first metal foil on a first surface and a second metal foil on a second surface of the substrate, wherein the substrate has a cavity recessed into the first surface; a metal heatsink embedded within the cavity; a semiconductor die mounted on a flat bottom of the metal heatsink; a dielectric layer covering the first surface of the substrate; at least one built-up circuit trace layer on the dielectric layer; a solder resist layer on the built-up circuit trace layer and on the dielectric layer; a heat-dissipating metal layer on the second metal foil; and heat-dissipating plugs connecting the flat bottom of the metal heatsink and the heat-dissipating metal layer. | 12-25-2008 |
| 20090001549 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SYMMETRIC PACKAGING - An integrated circuit package system comprising: providing a substrate having a first substrate surface and a second substrate surface; forming a first package connector and a second package connector over substantially opposite locations of the first substrate surface and the second substrate surface; and attaching a first integrated circuit and a second integrated circuit adjacent the first package connector over the first substrate surface and the second package connector over the second substrate surface. | 01-01-2009 |
| 20090008768 | SEMICONDUCTOR PACKAGE SYSTEM WITH PATTERNED MASK OVER THERMAL RELIEF - A semiconductor package system including: providing a substrate having a thermal relief thereon; depositing a mask on the substrate and the thermal relief, the mask deposited on the thermal relief and having a regular pattern to partially cover the thermal relief; and die attaching a semiconductor die over the thermal relief. | 01-08-2009 |
| 20090032933 | REDISTRIBUTED CHIP PACKAGING WITH THERMAL CONTACT TO DEVICE BACKSIDE - Redistributed Chip Packaging with Thermal Contact to Device Backside An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board. | 02-05-2009 |
| 20090039496 | METHOD FOR FABRICATING A SEMICONDUCTOR AND SEMICONDUCTOR PACKAGE - A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer. | 02-12-2009 |
| 20090039497 | SEMICONDUCTOR DEVICE PACKAGE HAVING A BACK SIDE PROTECTIVE SCHEME - The present invention provides a semiconductor device package, comprising a die having a back surface and an active surface formed thereon; an adhesive layer formed on the back surface of the die; a protection substrate formed on the adhesive layer; and a plurality of bumps formed on the active surface of the die for electrically connection. The present invention further provides a method for forming a semiconductor device package, comprising providing a plurality of die having a back surface and an active surface on a wafer; forming an adhesive layer on the back surface of the die; forming a protection substrates on the adhesive layer; forming a plurality of bumps on the active surface of each die; and dicing the plurality of die into individual die for singulation. | 02-12-2009 |
| 20090045501 | STRUCTURE ON CHIP PACKAGE TO SUBSTANTIALLY MATCH STIFFNESS OF CHIP - Chip packages and a related method are disclosed that provide a structure on a side opposite a chip on a carrier of a chip package to substantially match a stiffness of the chip. In one embodiment, a chip package includes a chip coupled to a carrier; and a structure on a side opposite the chip on the carrier, the structure having a first stiffness to substantially match a second stiffness of the chip. | 02-19-2009 |
| 20090045502 | CHIP SCALE PACKAGE WITH THROUGH-VIAS THAT ARE SELECTIVELY ISOLATED OR CONNECTED TO THE SUBSTRATE - A semiconductor chip scale package formed with through-vias, which can be either isolated or electrically connected to a substrate, and a method of producing the semiconductor chip scale package with through-vias, which can be isolated or electrically connected to the substrate. | 02-19-2009 |
| 20090045503 | Multidirectional Semiconductor Device Package Thermal Enhancement Systems and Methods - The invention provides thermally-enhanced semiconductor device package systems and associated methods for reducing thermal resistance for improved heat egress. In one disclosed embodiment of the invention, a semiconductor device package system includes a packaged semiconductor device having operable contacts for external electrical coupling. The packaged device has an exposed surface, and a heat spreader is affixed to the exposed device surface. The heat spreader includes a portion extending in a configuration coplanar with the device contacts. In another example of a preferred embodiment of the invention, a semiconductor device package system includes an external heat sink affixed to a heat spreader, the heat spreader having a portion extending in a configuration coplanar with the device contacts. According to exemplary systems and methods of the invention package systems are provided with a heat spreader so configured that the junction-to-board thermal resistance and junction-to-case thermal resistance are both reduced. | 02-19-2009 |
| 20090057871 | Ball Grid Array Package Enhanced With a Thermal and Electrical Connector - Ball grid array (BGA) packages are provided. A BGA package includes a substrate that has a surface and a stiffener that has a surface and a protruding portion. The surface of the substrate has an opening therein. The protruding portion is located on the surface of the stiffener. The surface of the stiffener is coupled to the surface of the substrate. The protruding portion extends through the opening. An area of the surface of the stiffener is less than an area of the surface of the substrate. A surface of the protruding portion is capable of attachment to a printed circuit board (PCB) when the BGA package is mounted to the PCB. | 03-05-2009 |
| 20090065927 | Semiconductor Device and Methods of Manufacturing Semiconductor Devices - This application relates to a semiconductor device comprising a semiconductor chip, a molded body covering the semiconductor chip wherein the molded body comprises an array of recesses in a first surface of the molded body, first contact elements, and elastic elements in the recesses that connect the first contact elements with the molded body. | 03-12-2009 |
| 20090085189 | POWER SEMICONDUCTOR MODULE - One embodiment provides a semiconductor module with an electrically insulating substrate. A conductor track is arranged on the substrate. A semiconductor chip and sleeve member are arranged on the substrate and electrically connected to the conductor track. The sleeve member includes a rim with a maximum inner diameter. The module further includes a contact element. The contact element includes a first end arranged within and electrically connected to the sleeve member, a second end providing an external contact of the module, and a section arranged between the first end and the second end. The section includes a maximum outer diameter that is larger than the maximum inner diameter of the rim. The contact element is in mechanical contact with the sleeve member such that the section between both ends of the contact element is arranged outside the sleeve member and borne on the rim of the sleeve member. | 04-02-2009 |
| 20090091018 | Electronic Component Sealing Substrate, Electronic Component Sealing Substrate to be Divided Into a Plurality of Pieces, Electronic Apparatus Including Electronic Component Sealing Substrate, and Method for Producing Electronic Apparatus - An electronic component sealing substrate capable of configuring an electronic apparatus in which the influence of electromagnetic coupling and radio frequency noises between an electrical connection path and a micro electronic mechanical system is suppressed is provided. An electronic component sealing substrate ( | 04-09-2009 |
| 20090108436 | SEMICONDUCTOR PACKAGE - In a semiconductor package, a semiconductor chip is adhered with an adhesive member, with a circuit face of the semiconductor chip facing upward, onto a circuit board including a plurality of interconnections, a plurality of through holes, wire bonding pads and a solder resist for protecting the interconnections and the through holes. A plurality of electrodes of the semiconductor chip are electrically connected to the plural wire bonding pads of the circuit board through wires. A concave is formed in the solder resist of the circuit board correspondingly to every through hole of the circuit board, and concaves present in a region opposing a rim portion of the semiconductor chip and a region surrounding the semiconductor chip are buried with a resin so as to attain a flat top face. | 04-30-2009 |
| 20090121339 | SEMICONDUCTOR MODULE AND IMAGE PICKUP APPARATUS - In a semiconductor module including multiple semiconductor devices, a signal that flows through a bonding wire connected to one semiconductor device is prevented from acting as noise which affects another semiconductor device, thereby improving the operation reliability of the semiconductor module. A second semiconductor device provided alongside a first semiconductor device includes a current output electrode via which large current is output. The current output electrode is electrically connected to a substrate electrode provided to a first wiring layer via a bonding wire such as a gold wire. The bonding wire is provided across the side E2 of the second semiconductor device. The bonding wire connected to the first semiconductor device is provided across a side of the first semiconductor device that corresponds to the side El of the second semiconductor device, i.e., the side F2, F3, or F4 of the first semiconductor device. | 05-14-2009 |
| 20090127693 | SEMICONDUCTOR MODULE AND IMAGE PICKUP APPARATUS - In a semiconductor module including multiple semiconductor devices, a signal that flows through a bonding wire connected to one semiconductor device is prevented from acting as noise which affects another semiconductor device, thereby improving the operation reliability of the semiconductor module. A second semiconductor device provided alongside a first semiconductor device includes a current output electrode via which large current is output. The current output electrode is electrically connected to a substrate electrode provided to a first wiring layer via a bonding wire such as a gold wire or the like. The bonding wire is provided across the side E | 05-21-2009 |
| 20090127694 | SEMICONDUCTOR MODULE AND IMAGE PICKUP APPARATUS - A semiconductor module including multiple semiconductor devices prevents a signal that flows through a bonding wire connected to one semiconductor device from acting as noise which affects the other semiconductor devices, thereby improving the operation reliability of the semiconductor module. A second semiconductor device layered on a first semiconductor device includes a current output electrode via which large current is output. The current output electrode is electrically connected to a substrate electrode provided to a first wiring layer via a bonding wire. The bonding wire is provided across the side E | 05-21-2009 |
| 20090140412 | SEMICONDUCTOR DEVICE HAVING IMPROVED SOLDER JOINT AND INTERNAL LEAD LIFETIMES - A semiconductor chip is mounted on a flexible wiring board through the interposition of an elastmer. The flexible wiring board is made up of a tape on which wiring is fixed. A part of the wiring is projected beyond the edge of the tape, extended in the direction of the thickness of the elastmer and connected to an electrode of the semiconductor chip. The edge of the tape beyond which the wiring is projected protrudes beyond the edge of the elastmer by a length no smaller than the thickness of the elastmer. | 06-04-2009 |
| 20090166844 | METAL COVER ON FLIP-CHIP MATRIX-ARRAY (FCMX) SUBSTRATE FOR LOW COST CPU ASSEMBLY - In some embodiments, a metal cover on flip-chip matrix-array (FCMX) substrate for low cost CPU assembly is presented. In this regard, an apparatus is introduced comprising a plurality of integrated circuit dice coupled with a substrate, a thermal interface material on top surfaces of the dice, and a metal plate on top of the thermal interface material on top of the dice. Other embodiments are also disclosed and claimed. | 07-02-2009 |
| 20090184412 | RESIN-SEAL TYPE SEMICONDUCTOR DEVICE - There is provided a resin-seal type semiconductor device (BGA type semiconductor device) whose heat dissipating characteristic is improved, so that it is prevented from deteriorating in reliability. This BGA type semiconductor device includes a wiring substrate on a predetermined area on which a semiconductor chip is mounted; a plurality of metal bumps that are formed to be arranged at predetermined intervals in an area of the substrate different from the area on which the semiconductor chip is mounted; and a sealing resin layer that covers at least the semiconductor chip. Each of the plurality of metal bumps is covered with the sealing resin layer described above, with a part thereof exposed at a top face of the sealing resin layer. | 07-23-2009 |
| 20090206469 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device has a plurality of wafers which are laminated to each other, wherein: each wafer includes an lamination surface to which another wafer is laminated and a substrate having an element formed thereon; the lamination surface is provided with an electric signal connecting portion that electrically connects to said another wafer so as to form a semiconductor circuit; at least one of the electrical signal connecting portions facing each other is a protruding connection portion that protrudes from a region which exposes the substrate on the lamination surface; and a reinforcing protruding portion that is insulated from the semiconductor circuit, and is formed of the same material as the substrate to protrude from the lamination surface with a height equal to the length of a gap between the lamination surfaces of wafers facing each other is provided in an area where the protruding connection portion is not disposed on the lamination surface formed with the protruding connection portion. | 08-20-2009 |
| 20090218676 | SEMICONDUCTOR DEVICE - A small-sized surface mount package having a low on-resistance is achieved, in which a power MOSFET etc. is sealed. In one side a molding resin, two silicon chips are sealed. On one side of the molding resin, three source leads and one gate lead are arranged. The three source leads are joined each other inside the molding resin, and the joined portion and a source pad of the silicon chip are electrically coupled each other via two Al ribbons. Moreover, a gate pad of the silicon chip is electrically coupled to the gate lead via one Au wire. | 09-03-2009 |
| 20090230541 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device in which a chip is embedded in a wiring board and bump electrodes formed over the front surface of the semiconductor chip are flip-chip coupled to wiring formed in the wiring board and the entire back surface of the semiconductor chip functions well as a back electrode and a method of manufacturing the semiconductor device. A semiconductor chip is embedded inside a wiring board. The semiconductor chip is flip-chip coupled (face down) to a base substrate as the core layer of the wiring board through bump electrodes. A conductive film is formed over the semiconductor chip's surface reverse to the surface over which bump electrodes are formed. The conductive film functions as a back electrode which supplies a reference voltage to the integrated circuit in the semiconductor chip. The conductive film is electrically coupled to third-layer wiring through vias. | 09-17-2009 |
| 20090243081 | SYSTEM AND METHOD OF FORMING A WAFER SCALE PACKAGE - A system and method for forming a wafer level package (WLP) (i.e., wafer level chip size package) is disclosed. The WLP includes a silicon integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof and a plurality of polymer laminates positioned thereon. Each of the polymer laminates is comprised of a separate pre-formed laminate sheet and has a plurality of vias formed therein that correspond to a respective die pad. A plurality of metal interconnects are formed on each of the plurality of polymer laminates so as to cover a portion of a top surface of a polymer laminate and extend down through the via and into contact with a metal interconnect on a neighboring polymer laminate positioned below. An input/output (I/O) system interconnect is positioned on a top surface of the wafer level package and is attached to the plurality of metal interconnects. | 10-01-2009 |
| 20090273075 | SEMICONDUCTOR DEVICE AND MANUFACTURING OF THE SEMICONDUCTOR DEVICE - A semiconductor device. In one embodiment the device includes a carrier. A first material is deposited on the carrier. The first material has an elastic modulus of less than 100 MPa. A semiconductor chip is placed over the first material. A second material is deposited on the semiconductor chip, the second material being electrically insulating. A metal layer is placed over the second material. | 11-05-2009 |
| 20090294951 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device that can be readily manufactured, can include a large number of pads, and can be thin, and a method for manufacturing the same are provided. The semiconductor device is characterized in that the semiconductor device includes an LSI chip, an insulating layer provided on the LSI chip and made of a nonphotosensitive resin, the insulating layer including a via hole in the position corresponding to an externally connected pad, and a wiring layer extending along the insulating layer through the via hole to the externally connected pad, and at least part of the via hole is formed by irradiating the insulating layer with laser light. | 12-03-2009 |
| 20090302453 | CONTACT PADS FOR SILICON CHIP PACKAGES - A method for manufacturing a silicon chip package for a circuit board assembly provides a package with a silicon chip and an array of first contact pads that are provided by a first conductive material. A plurality of second contact pads are provided from a gold material having a hardness different than that of the first contact pads. The second contact pads are soldered to the first contact pads of the package. A circuit board assembly is assembled by providing a circuit board substrate with at least one socket with contact pads. The second contact pads of the package are assembled to the circuit board substrate contact pads. | 12-10-2009 |
| 20100013084 | Surface mount package with high thermal conductivity - A package for use in encapsulating an electronic device is disclosed. In some embodiments, the package includes the following: a dielectric frame having first and second sides, an aperture, a raised shelf portion defined along an internal perimeter of the dielectric frame and extending outwardly from the second side, the raised shelf portion defining a first thickness of the dielectric frame, and a raised sidewall extending outwardly from the second side along an external perimeter of the dielectric frame, the raised sidewall defining a second thickness of the frame, the second thickness being greater than the first thickness; a metallic component bonded to the dielectric frame and extending across the aperture; and a seam weldable, low-profile metallic seal ring bonded to the raised sidewall of the dielectric frame. In some embodiments, the package includes the following: a dielectric frame having first and second sides and an aperture, the dielectric frame having an aperture thickness bordering the aperture; a metallic insert positioned within the aperture, the metallic insert having first and second sides, the metallic insert being sized so as to be movable within the aperture and the metallic insert having an insert thickness that is greater than the aperture thickness of the dielectric frame; a first metallic component bonded to the first side of the metallic insert and extending across the aperture; and a second metallic component bonded to the second side of the metallic insert and extending across the aperture. | 01-21-2010 |
| 20100013085 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes power semiconductor elements joined to wiring patterns of a circuit substrate, cylindrical external terminal communication sections, and wiring means for forming electrical connection between, for example, the power semiconductor elements and the cylindrical external terminal communication sections. The power semiconductor elements, the cylindrical external terminal communication sections, and the wiring means are sealed with transfer molding resin. The cylindrical external terminal communication sections are arranged on the wiring patterns so as to be substantially perpendicular to the wiring patterns, such that external terminals are insertable and connectable to the cylindrical external terminal communication sections, and such that a plurality of cylindrical external terminal communication sections among the cylindrical external terminal communication sections are arranged two-dimensionally on each of wiring patterns that act as main circuits. | 01-21-2010 |
| 20100013086 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device with improved productivity, reduced size and reduction of amounting area therefore is provided. In the provided power semiconductor device, an external terminal does not limit an increase in current. The power semiconductor device is sealed with transfer molding resin. In the power semiconductor device, a cylindrical external terminal communication section is arranged on a wiring pattern so as to be substantially perpendicular to the wiring pattern. An external terminal can be inserted and connected to the cylindrical external terminal communication section. The cylindrical external terminal communication section allows the inserted external terminal to be electrically connected to the wiring pattern. A taper is formed at, at least, one end of the cylindrical external terminal communication section, which one end is joined to the wiring pattern. | 01-21-2010 |
| 20100019374 | BALL GRID ARRAY PACKAGE - A thermally conductive ball grid array (BGA) package for integrated circuits having improved ground path employs a printed circuit substrate. The substrate has an array of solder balls disposed on the bottom side. There is an opening in the substrate corresponding to the integrated circuit die. A grounding ring covers the vertical walls of the opening and includes an upper ground collar on the top side of the substrate and a lower ground collar on the bottom side of the substrate. A thermally and electrically conductive heat spreader is attached to the lower ground collar on the bottom side of the BGA package, covering the opening in the substrate. The integrated circuit die is mounted on the heat spreader, with the active side up, within the opening in the substrate. Ground pads on the active side of the die are attached to the upper ground collar by wire bonds, to provide a continuous ground path from the ground pads to the heat spreader. Molded plastic covers the semiconductor device and the top side of the substrate. | 01-28-2010 |
| 20100019375 | Housing for a semiconductor component - A housing for a semiconductor component, in which the housing has a plurality of pins which are provided at the edge of the housing at distances, the pins each having a width, a thickness and a length. In order to create a housing for a semiconductor component whose characteristic frequencies are outside a range in which the characteristic frequencies of the housing negatively influence the semiconductor component, either at least one of the distances lies outside the range of 1.24 mm to 1.30 mm, at least one of the widths lies outside the range of 0.33 mm to 0.51 mm, at least one of the thicknesses lies outside the range of 0.23 to 0.32 mm, or at least one of the lengths lies outside the range of 2.05 to 4.12 mm. | 01-28-2010 |
| 20100025843 | Optical semiconductor apparatus - An optical semiconductor apparatus composed of a cap and a base, includes: a metal package including a plurality of openings penetrating through the base from outside to inside, a lead with its end portion protruding to the inside of the base and an insulator covering a side surface of the lead being inserted into each of the openings, and the lead being insulated from the base; an insulating film with its backside bonded to the inside of the base; and a semiconductor component placed on the base or on the insulating film. The insulating film covers the opening up to the vicinity of the side surface of the lead. | 02-04-2010 |
| 20100025844 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There is provided a low-cost semiconductor device that commercial and quality-assured (inspected) chip size packages can be stacked and has a small co-planarity value and a high mounting reliability. A semiconductor device in which a flexible circuit substrate is adhered to at least a part of a lateral side of a semiconductor package, and the flexible circuit substrate, which is on a side facing solder balls of the semiconductor package, is folded at a region inside of an edge of the semiconductor package. | 02-04-2010 |
| 20100044854 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME AND A MOUNTING STRUCTURE OF A SEMICONDUCTOR DEVICE - A semiconductor device is disclosed which includes a tab ( | 02-25-2010 |
| 20100065960 | RESIN SHEET, CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a circuit device manufacturing method for coating a bottom surface of a circuit board with a thin coating of sealing resin. In the present invention, a circuit board having a circuit element such as a semiconductor element embedded therein is placed in a molding die, and a resin sheet containing a thermosetting resin is interposed between the circuit board and a bottom surface of an inner wall of the molding die. Under this condition, the molding die is heated to about 180° C., and a sealing resin in liquid form is injected through a gate. Thereby, the bottom surface of the circuit board can be coated with a thin coating of the sealing resin made of the molten resin sheet. | 03-18-2010 |
| 20100072608 | Semiconductor device - A semiconductor device is disclosed which includes a metal base, a semiconductor chip, a lead, and a sealant. The semiconductor chip has an opposite pair of first and second electrode surfaces and a side surface. The semiconductor chip is fixed on the metal base with the first electrode surface solder-connected to the metal base. The lead is solder-connected to the second electrode surface of the semiconductor chip. The sealant seals, at least, the side surface of the semiconductor chip and solders connecting the metal base, the semiconductor chip, and the lead. Further, the lead has a small-cross-section portion which has a smaller cross-sectional area perpendicular to the longitudinal direction of the lead than other portions of the lead adjacent to the small-cross-section portion. | 03-25-2010 |
| 20100078803 | SEMICONDUCTOR FLAT PACKAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor flat package device capable of attaining a favorable operation and ensuring a sufficient spreading quality of solder for the lead top end is provided. A semiconductor chip | 04-01-2010 |
| 20100090333 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND MANUFACTURING METHOD OF SEMICONDUCTOR MODULE - An improvement is achieved in the mounting reliability of a semiconductor device. A semiconductor chip is mounted over an upper surface of a wiring substrate. A plurality of solder balls are disposed individually over a plurality of lands formed on a lower surface of the wiring substrate. The plural lands include a first land group arranged in a plurality of rows and arranged along a peripheral edge portion of the lower surface of the wiring substrate, and a second land group arranged inside the first land group in the lower surface of the wiring substrate. The lands in the first land group are arranged with a first pitch, and the lands in the second land group are arranged with a second pitch higher than the first pitch. | 04-15-2010 |
| 20100090334 | Electronic Part Manufacturing Method - The objective of this invention is to prevent the generation of defects pertaining to placement of solder balls on the terminal placement parts of the electronic part main body. The solder ball | 04-15-2010 |
| 20100102438 | Semiconductor device and method of manufacturing the same - A semiconductor device includes: a substrate having first and second surfaces, the first surface comprising first and second regions; a first semiconductor chip covering the first region; a first seal covering the second region and the first semiconductor chip; and a second seal covering the second surface. | 04-29-2010 |
| 20100102439 | SEMICONDUCTOR DEVICE WITH PROTECTIVE SCREEN - A multi-layer substrate has a front face with external pads. An integrated-circuit chip is positioned inside of the multi-layer substrate. An electronic and/or electric component is also positioned inside of the substrate above the integrated-circuit chip. An electrical connection network is formed in the multi-layer substrate to selectively connect the integrated-circuit chip and component together and to the external pads. A first screen is positioned within the multi-layer substrate between the integrated-circuit chip and the electrical connection network, this first screen being connected by vias to the external pads. A second screen is position on a top (external) surface of the multi-layer substrate above the component and electrical connection network, this second screen being connected by vias to the external pads. The integrated-circuit chip is position to be inside the first and second screens. | 04-29-2010 |
| 20100109150 | METHOD OF ASSEMBLY OF A SEMICONDUCTOR PACKAGE FOR THE IMPROVEMENT OF THE ELECTRICAL TESTING YIELD ON THE PACKAGES SO OBTAINED - A method of assembly of a semiconductor package includes treating the electrical contacts thereof by the application on the electrical contacts of a chemical composition comprising at least one ionic polar surfactant. A semiconductor package has a coating on the electrical contacts thereof, the coating comprising at least one ionic polar surfactant. A device includes a semiconductor package with electrical contacts on a circuit board, the electrical contacts having a coating that includes an ionic surfactant. | 05-06-2010 |
| 20100117218 | Stacked wafer level package and method of manufacturing the same - The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost. | 05-13-2010 |
| 20100117219 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device in which transfer molding resin seals: a metallic circuit substrate; a power semiconductor element joined to a wiring pattern; and a side surface of a cylindrical external terminal communication section provided on the wiring pattern and to which an external terminal can be inserted and connected. The cylindrical external terminal communication section is substantially perpendicular to a surface on which the wiring pattern is formed. An outer surface of a metal plate of the metallic circuit substrate and a top portion of the cylindrical external terminal communication section are exposed from the transfer molding resin. The transfer molding resin is not present within the cylindrical external terminal communication section. | 05-13-2010 |
| 20100127385 | METHOD FOR MANUFACTURING AN ELEMENT HAVING ELECTRICALLY CONDUCTIVE MEMBERS FOR APPLICATION IN A MICROELECTRONIC PACKAGE - A microelectronic package ( | 05-27-2010 |
| 20100133681 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a power semiconductor module having cylindrical conductors which are joined to a wiring pattern so as to be substantially perpendicular to the wiring pattern and whose openings are exposed at a surface of transfer molding resin, and an insert case having a ceiling portion and peripheral walls, the ceiling portion being provided with external terminals that are fitted into, and passed through, the ceiling portion, the external terminals having outer-surface-side connecting portions at the outer surface side of the ceiling portion and inner-surface-side connecting portions at the inner surface side of the ceiling portion. The power semiconductor module is set within the insert case such that the inner-surface-side connecting portions of the external terminals are inserted into the cylindrical conductors. | 06-03-2010 |
| 20100140785 | SEMICONDUCTOR DEVICE - A method of assembling a semiconductor device includes providing a chip attached to an elastic carrier, and supporting the elastic carrier with a stiffener. The method additionally includes removing the stiffener from the elastic carrier after attaching the elastic carrier to a board. | 06-10-2010 |
| 20100140786 | SEMICONDUCTOR POWER MODULE PACKAGE HAVING EXTERNAL BONDING AREA - Provided is a semiconductor power module package including a bonding area on a direct bonding cupper (DBC) board. The semiconductor power module package includes: one or more semiconductor chips; a sealing member sealing the one or more semiconductor chips; a plurality of leads electrically connected to the one or more semiconductor chips and exposed from the sealing member; and an external bonding member electrically connected to the one or more semiconductor chips and electrically connecting an external circuit board exposed from the sealing member. | 06-10-2010 |
| 20100140787 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE FOR USE THEREIN, AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a substrate for mounting and fixing a semiconductor chip thereon and a connecting pattern. The substrate is provided with an elongate opening formed therein. The semiconductor chip is fixed with its surface being mounted on the substrate and with its electrode being aligned within the elongate opening. The electrode of the semiconductor chip is electrically connected to the connecting pattern via wires through the elongate opening. The elongate opening and the wires are sealed with resin. | 06-10-2010 |
| 20100193935 | INTEGRATED ANTENNAS IN WAFER LEVEL PACKAGE - A semiconductor module comprises components in one wafer level package. The module comprises an integrated circuit (IC) chip embedded within a package molding compound. The package comprises a molding compound package layer coupled to an interface layer for integrating an antenna structure and a bonding interconnect structure to the IC chip. The bonding interconnect structure comprises three dimensional interconnects. The antenna structure and bonding interconnect structure are coupled to the IC chip and integrated within the interface layer in the same wafer fabrication process. | 08-05-2010 |
| 20100193936 | SEMICONDUCTOR DEVICE - A novel structure capable of reducing the stress in the insulating layer in the semiconductor element and thereby securing reliability is provided. When the semiconductor element and the substrate are connected with a solder, the stress generated in the insulating layer is reduced by placing a spherical core made of a material having a greater rigidity inside the solder and satisfying the following inequalities: 1 GPa<(Young's modulus of a encapsulation resin)<30 GPa, 20 ppm/k<(linear coefficient of expansion of the encapsulation resin)<200 ppm/k, and 10 MPa<(yield stress of the solder at room temperature)<30 MPa. At the time of connection, the thickness of the solder to be placed between the land on the surface of the semiconductor element and the core is adjusted to 1/10 or less of the terminal pitch. | 08-05-2010 |
| 20100193937 | SEMICONDUCTOR MODULE - A wiring layer including external connection regions is provided on a main surface of an insulating resin layer on a side opposite to that of a semiconductor device mounting face. The wiring layer is coated with a protection layer. An opening is provided to the protection layer such that each external connection region is exposed. Each external connection region has a curved surface recessed toward the insulating resin layer side. The entire area of each opening is filled with a solder ball for mounting a substrate, and the recess of each external connection region is filled with the solder ball, thereby connecting each solder ball to the intermediate layer. | 08-05-2010 |
| 20100193938 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CONSTITUENT AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor constituent having a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. An under-layer insulating film is provided under and around the semiconductor constituent. A plurality of under-layer wires are provided under the under-layer insulating film and electrically connected to the electrodes for external connection of the semiconductor constituent. An insulating layer is provided around the semiconductor constituent and on the under-layer insulating film. A frame-like insulating substrate is embedded in an upper surface of the insulating layer and positioned around the semiconductor constituent. A plurality of upper-layer wires are provided on the insulating substrate. A base plate on which the semiconductor constituent and the insulating layer are mounted is removed. | 08-05-2010 |
| 20100213599 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a flat plate; a semiconductor chip which is disposed on one main surface of the flat plate and whose surface opposite an element circuit surface is fixedly bonded; a single layer of an insulating material layer formed continuously on the element circuit surface of the semiconductor chip and on the main surface of the flat plate; an opening formed at a position, in the insulating material layer, above an electrode disposed on the element circuit surface of the semiconductor chip; a conductive part formed in the opening so as to be connected to the electrode of the semiconductor chip; a wiring layer formed on the insulating material layer so as to be connected to the conductive part, and partly led out to a peripheral area of the semiconductor chip; and external electrodes formed on the wiring layer. Also adoptable is a structure in which a flat plate having a cavity is used, a semiconductor chip is disposed in the cavity, and an insulating material layer is filled and formed in a gap in the cavity. A semiconductor device high in yields and connection reliability, adaptable to a microscopic pitch of electrodes of a semiconductor chip, and excellent in electric characteristic is obtained at low cost. | 08-26-2010 |
| 20100213600 | Apparatus having thermal-enhanced and cost-effective 3D IC integration structure with through silicon via interposers - An apparatus having a three-dimensional integrated circuit structure is described herein. The apparatus include an interposer for carrying a plurality of high and low-power chips. The high-power chips are attached and connected to one side of the interposer, while the low-power chips are attached and connected to the other side of the interposer. In generally, the high-power chips produce more heat than does the low-power chip during their operations. The interposer further include through silicon vias and redistribution layers for connecting the chips on both surfaces. In addition, the interposer assembly is attached and connected to a substrate layer, which is in turn attached and connected to a printed circuit board. In order to provide improve thermal management, the interposer surface carrying the high-power chips are oriented away from the circuit board. A heat spreader is attached to the back sides of the high-power chips for dissipating the heat. | 08-26-2010 |
| 20100219525 | Semiconductor device - Disclosed is a semiconductor device having improved heat dissipation efficiency. The semiconductor device includes a silicon interposer having a first surface and a second surface opposite the first surface. A plurality of semiconductor chips are provided on the first surface side of the silicon interposer. The silicon interposer has a plurality of via holes extending from the first surface to the second surface. An N type semiconductor and a P type semiconductor constituting a Peltier element are provided in each two of the via holes. | 09-02-2010 |
| 20100224987 | STRESS BUFFERING PACKAGE FOR A SEMICONDUCTOR COMPONENT - The present invention relates to a stress buffering package for a semiconductor component, wherein a stress buffering means comprises individual stress buffering elements that do not influence the stress buffering effect from each other. Furthermore the invention relates a method for manufacturing a stress buffering package for a semiconductor component. | 09-09-2010 |
| 20100224988 | SEMICONDUCTOR PACKAGE SUBSTRATE, SEMICONDUCTOR PACKAGE USING THE SUBSTRATE, AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE SUBSTRATE - A semiconductor package substrate comprises a substrate core layer, and a land formed on one surface of the substrate core layer for mounting an external electrode terminal thereon. Then, a hole having a diameter smaller than that of the land is dug into the substrate core layer from a position in contact with the land, and the hole is filled with a low modulus resin exhibiting a modulus of elasticity lower than that of a material of the substrate core layer. In this way, the present invention accomplishes a reduction in size of a semiconductor package and improved electrical resistance of a semiconductor package during board level thermal cycle testing. | 09-09-2010 |
| 20100224989 | MICROELECTRONIC DEVICES HAVING INTERMEDIATE CONTACTS FOR CONNECTION TO INTERPOSER SUBSTRATES, AND ASSOCIATED METHODS OF PACKAGING MICROELECTRONIC DEVICES WITH INTERMEDIATE CONTACTS - Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed herein. A packaged microelectronic device configured in accordance with one embodiment of the invention includes a microelectronic die attached to an interconnecting substrate. The microelectronic die includes an integrated circuit electrically coupled to a plurality of terminals. Each of the terminals is electrically coupled to a corresponding first contact on the die with an individual wire-bond. Each of the first contacts on the die is electrically coupled to a corresponding second contact on the interconnecting substrate by a conductive coupler such as a solder ball. | 09-09-2010 |
| 20100230802 | METALLIC SOLDERABILITY PRESERVATION COATING ON METAL PART OF SEMICONDUCTOR PACKAGE TO PREVENT OXIDE - Embodiments of the present invention are directed to metallic solderability preservation coating on connectors of semiconductor package to prevent oxide. Singulated semiconductor packages can have contaminants, such as oxides, on exposed metal areas of the connectors. Oxidation typically occurs on the exposed metal areas when the semiconductor packages are not stored in appropriate environments. Copper oxides prevent the connectors from soldering well. An anti-tarnish solution of the present invention is used to coat the connectors during sawing, after sawing, or both of a semiconductor array to preserve metallic solderability. The anti-tarnish solution is a metallic solution, which advantageously allows the semiconductor packages to not need be assembled immediately after fabrication. | 09-16-2010 |
| 20100230803 | ELECTRONIC DEVICE PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode. | 09-16-2010 |
| 20100244232 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH Z-INTERCONNECTS HAVING TRACES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a carrier; mounting an integrated circuit on the carrier; mounting a z-interconnect on the carrier, the z-interconnect for supporting a trace cantilevered over the integrated circuit; encapsulating the integrated circuit with an encapsulation; removing the carrier; and depositing a substrate below the integrated circuit. | 09-30-2010 |
| 20100244233 | Chip stack package and method of fabricating the same - Provided is a chip stack package and a method of manufacturing the same. A chip stack package may include a base chip including a base substrate, a base through via electrode penetrating the base substrate, a base chip pad connected to the base through via electrode, and a base encapsulant. The chip stack package may further include at least one stack chip on a surface of the base substrate. The chip stack package may also include an external connection terminal connected to the base through via electrode and the base chip pad and protruding from the base encapsulant, and an external encapsulant surrounding and protecting outer surfaces of the base chip and the at least one stack chip, wherein the chip through via electrode and the chip pad are connected to the base through via electrode and the base chip pad of the base chip. | 09-30-2010 |
| 20100244234 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - The present invention provides a semiconductor device which includes a semiconductor chip formed with an electrode pad on one surface thereof, a wiring board having a wiring pattern, with its one surface opposing the other surface of the semiconductor chip, a wire for electrically connecting the electrode pad of the semiconductor chip with the wiring pattern of the wiring board, an external terminal arranged on the other surface of the wiring board for electrical connection with the electrode pad through the wire and wiring pattern, and a sealant for fixing the semiconductor chip on one surface of the wiring board such that a hollow is formed between the other surface of the semiconductor chip and the one surface of the wiring board. The wiring board includes a throughhole communicating with the hollow. | 09-30-2010 |
| 20100289135 | SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package is disclosed. One embodiment provides at least one semiconductor chip including contact elements on a first surface of the chip. An encapsulation layer covers the semiconductor chip. A metallization layer is applied above the first surface of the chip and the encapsulation layer. The metallization layer includes contact areas connected with the contact elements of the chip. External pins are connected with the contact areas. | 11-18-2010 |
| 20100295167 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes an insulating substrate, a semiconductor chip, an insulating layer, and a sealing layer. The insulating substrate has an opening. A semiconductor chip is disposed in the opening. An insulating layer is disposed on a first surface of the insulating substrate. The insulating layer covers the opening. The sealing layer is disposed on a second surface of the insulating substrate. The sealing layer seals the semiconductor chip and the opening. | 11-25-2010 |
| 20100301469 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER INTERCONNECTIONS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; and forming an encapsulation that encapsulates the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure. | 12-02-2010 |
| 20100314747 | ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE - A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers. | 12-16-2010 |
| 20100314748 | Chip packaging method and structure thereof - The present invention relates to a chip packaging method and structure, in which bonding pads provided on the chip are connected by a plurality of metal wires via bonding, each of the metal wires is bending in the middle part to be higher than a predetermined height, and its ends are respectively electrically connected with two of the bonding pads. A molding layer is packaged on the chip and the molding layer is higher than the predetermined height. The molding layer is sliced at the predetermined height. Two upper breakpoints of each metal wire are exposed and a substrate is attached onto the molding layer. A plurality of circuit contacts of the substrate are respectively electrically coupled with the upper breakpoints. Whereby, the invention is capable of reducing the length of the metal wires in order to improve transmission speed, but also to reduce the volume of the packaging structure. | 12-16-2010 |
| 20100320593 | Chip Package Structure and Manufacturing Methods Thereof - A chip package structure includes a chip module, a plurality of pre-patterned structures, a filling material layer, and a redistribution layer. The chip module includes a chip including an upper surface, a side surface, and an active surface. The pre-patterned structures are disposed around the chip. Each of the pre-patterned structures includes a circuit, a first surface, an upper surface opposite the first surface, and a side surface. The filling material layer encapsulates the chip and the pre-patterned structures. The filling material layer includes a second surface, and encapsulates the upper and side surfaces of the chip, and the upper and side surfaces of each of the pre-patterned structures. The active surface, each first surface, and the second surface are substantially co-planar. The redistribution layer is disposed on the active surface, each first surface, and the second surface. The redistribution layer electrically connects the chip and each circuit. | 12-23-2010 |
| 20100320594 | SEMICONDUCTOR DEVICE WITH REINFORCEMENT PLATE AND METHOD OF FORMING SAME - A semiconductor device includes a reinforcement plate having an accommodating hole and a through hole extending from a first surface to a second surface, a semiconductor chip including a chip core and a pad formed on a pad surface of the chip core, the semiconductor chip disposed in the accommodating hole with the pad surface flush with the first surface, the chip core having substantially the same thickness as the reinforcement plate and including a semiconductor substrate, a through-hole electrode disposed in the through hole, resin sealing the semiconductor chip and the reinforcement plate, a interconnection pattern disposed on the first-surface side of the reinforcement plate to connect between the through-hole electrode and the pad, and a interconnection pattern disposed on the second-surface side of the reinforcement plate to be connected to the through-hole electrode, wherein the reinforcement plate is made of the same material as the semiconductor substrate. | 12-23-2010 |
| 20110001230 | Systems and Methods of Improved Heat Dissipation with Variable Pitch Grid Array Packaging - Adequate heat dissipation is essential for semiconductor devices. When a device exceeds a specified junction temperature, the device can be damaged, not perform correctly, or can have a reduced operating life. Semiconductor packages must dissipate heat from the chip to the external environment (i.e. to the PCB, air, etc) to keep the semiconductor device below a certain temperature threshold. For most devices, the most efficient way to dissipate the heat is through the package external I/O connections and into the PCB that it is mounted to. For Ball Grid Array (BGA) packages, the external I/Os are solder balls. Variable pitch packages pose advantages in heat dissipation without introducing significant costs. | 01-06-2011 |
| 20110001231 | SEMICONDUCTOR PACKAGE HAVING NON-UNIFORM CONTACT ARRANGEMENT - A semiconductor package has a non-uniform contact arrangement in which clustered contacts (e.g., a group of ground contacts, a group of power contacts, and/or a group of heatslug contacts) are placed closer together than I/O contacts. In one embodiment, I/O contacts near a cluster have a pitch in at least one direction that is larger than other I/O contacts. A local increase in the pitch of I/O contacts may be used to increase the line width and/or spacing of traces that fan out from corresponding pads on a printed circuit board. | 01-06-2011 |
| 20110012251 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a base substrate, at least one semiconductor chip provided above the base substrate, and a resin case covering the semiconductor chip and supported by the base substrate. A partition plate holds back extension of a crack occurring in the resin case being provided in the resin case. | 01-20-2011 |
| 20110018123 | Semiconductor package and method of manufacturing the same - The present invention relates to a semiconductor package and a method of manufacturing the same. The semiconductor package may include: an insulator that has first and second opening parts; an active element that is disposed inside the first opening part; a passive element that is disposed inside the second opening part; a protective member that is disposed at a lower part of the insulator and covers a lower part of the passive element; a build-up layer that is disposed on the insulator and electrically connected to the active element; and an external connection unit that is electrically connected to the build-up layer. | 01-27-2011 |
| 20110031610 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, PRINTED CIRCUIT BOARD AND ELECTRONIC DEVICE - Provided is a semiconductor device including a flexible circuit board which includes a first external electrode provided on a first face and second and third external electrodes provided on a second face; a plurality of memory devices and passive components; a supporter which is provided with a groove on one face; and a computing processor device. The memory devices and the passive components are connected to the first external electrode, the one face of the supporter is bonded on the first face of the flexible circuit board so that the groove houses the memory devices and the passive components. The flexible circuit board is bent along a perimeter of the supporter to be wrapped around a side face and another face of the supporter. On the flexible circuit board, the second external electrode is provided on the second face which is opposite to the first external electrode, and the third external electrode is provided on the second face which is bent to the another face of the supporter. The computing processor device is connected to the second external electrode, and a bump is formed on the third external electrode. | 02-10-2011 |
| 20110037163 | DEVICE INCLUDING A RING-SHAPED METAL STRUCTURE AND METHOD - A device includes a semiconductor chip with a ring-shaped metal structure extending along the contour of a first main surface of the semiconductor chip. An encapsulation body encapsulates the semiconductor chip and defines a second main surface. An array of external contact pads attaches to the second main surface of the encapsulation body, and at least one external contact pad of the array of external contact pads electrically couples to the ring-shaped metal structure. | 02-17-2011 |
| 20110057301 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires. | 03-10-2011 |
| 20110057302 | IMPEDANCE OPTIMIZED CHIP SYSTEM - A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips. | 03-10-2011 |
| 20110062577 | SUBSTRATE AND PACKAGE WITH MICRO BGA CONFIGURATION - A substrate of a micro-BGA package is revealed, primarily comprising a substrate core, a first trace, and a second trace where the substrate core has a slot formed between a first board part and a second board part. The first trace is disposed on the first board part and has a suspended inner lead extended into the slot where the inner lead has an assumed broken point. The second trace is disposed on the second board part and is integrally connected to the inner lead at the assumed broken point. More particularly, a non-circular through hole is formed at the assumed broken point and has two symmetric V-notches away from each other and facing toward two opposing external sides of the inner lead so that the inner lead at two opposing external sides does not have the conventional V-notches cutting into the inner lead from outside. Moreover, the inner lead will not unexpectedly be broken and the inner lead can easily and accurately be broken at the assumed broken point during thermal compression processes. | 03-17-2011 |
| 20110068458 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A LEADED PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a first device having a first exposed side and a first inward side; connecting a second device having a second exposed side and a second inward side facing the first inward side to the first device, the second device having planar dimensions less than planar dimensions of the first device; connecting a system connector to a perimeter of the first inward side, the system connector having an exposed leg partially vertical and an exposed foot partially horizontal; and applying an encapsulant exposing the first exposed side, the second exposed side, the exposed leg, and the exposed foot, the exposed leg offset from the encapsulant, the exposed foot on an end of the system connector opposite the first device. | 03-24-2011 |
| 20110089557 | Area reduction for die-scale surface mount package chips - Using side-wall conductor leads to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of die-scale surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance. | 04-21-2011 |
| 20110108976 | STACKED INTEGRATED CIRCUIT AND PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing a stacked integrated circuit and package system includes: attaching a high temperature resistant layer on a top substrate; mounting a first top integrated circuit on the high temperature resistant layer; mounting a second top integrated circuit on the first top integrated circuit; molding an encapsulant over the first top integrated circuit, the second top integrated circuit and the top substrate; mounting a third top integrated circuit over the first top integrated circuit on a surface opposite the second top integrated circuit; mounting a fourth top integrated circuit on the third top integrated circuit; molding an encapsulant over the third top integrated circuit, the fourth top integrated circuit and the top substrate; forming top electrical connectors on a lower surface of the top substrate; and mounting a bottom package to the top electrical connectors. | 05-12-2011 |
| 20110115069 | ELECTRONIC DEVICE INCLUDING A PACKAGING SUBSTRATE AND AN ELECTRICAL CONDUCTOR WITHIN A VIA AND A PROCESS OF FORMING THE SAME - An electronic device can include a packaging substrate that including an organic material and a hole extending into the packaging substrate. An electrically conductive member can include a via within the hole, and a lead lying along a major surface of the packaging substrate and electrically connected to the via. In an embodiment, the electrically conductive material can be plated, printed, or otherwise formed within and over the organic material, and a leadframe and a corresponding formation of a molding compound around the leadframe are not necessary. | 05-19-2011 |
| 20110121444 | EMBEDDED CHIP PACKAGES - Embodiments of the present disclosure provide configurations for a semiconductor package and associated methods of fabricating the semiconductor package. A method of fabricating a semiconductor package includes attaching a semiconductor die to a first substrate, attaching a second substrate to the first substrate, wherein the semiconductor die is embedded in between the first substrate and the second substrate, and forming an electrically insulative structure to substantially encapsulate the semiconductor die, wherein forming the electrically insulative structure is performed subsequent to the second substrate being attached to the first substrate. Additional embodiments may be described and/or claimed. | 05-26-2011 |
| 20110121445 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a plural number of interconnects and a plural number of vias are stacked. A semiconductor element is enclosed in an insulation layer. At least one of the vias provided in insulation layers and/or at least one of interconnects provided in the interconnect layers are of cross-sectional shapes different from those of the vias formed in another one of the insulation layers and/or interconnects provided in another one of the interconnect layers. | 05-26-2011 |
| 20110127665 | INTEGRATED CIRCUIT MODULE - An integrated circuit module includes a carrier substrate, a semiconductor die disposed in the carrier substrate, a ground pad disposed on the carrier substrate, and an antenna partially embedded in the carrier substrate. The antenna includes a ground layer in thermal contact with the ground pad for dissipating heat generated from the semiconductor die. | 06-02-2011 |
| 20110140264 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There is provided a low-cost semiconductor device that commercial and quality-assured (inspected) chip size packages can be stacked and has a small co-planarity value and a high mounting reliability. A semiconductor device in which a flexible circuit substrate is adhered to at least a part of a lateral side of a semiconductor package, and the flexible circuit substrate, which is on a side facing solder balls of the semiconductor package, is folded at a region inside of an edge of the semiconductor package (FIG. | 06-16-2011 |
| 20110156241 | PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME - Disclosed herein are a package substrate and a method of fabricating the same. The package substrate includes a base part that includes a chip, a mold part surrounding the chip, and a connection unit formed inside the mold part to connect the chip to a terminal part formed on the outer surface of the mold part, and a buildup layer that is formed on one surface of the base part on which the terminal part is formed, including the side surfaces of the base part, but includes a circuit layer connected to the terminal part, thereby making it possible to minimize stress applied to chips during a buildup process and easily replace malfunctioning chips. | 06-30-2011 |
| 20110215461 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device according to one embodiment of the present invention includes a step of covering a plurality of base plates in which respective semiconductor chips are mounted, by means of a sealing resin such that a plurality of base plates are spaced apart from each other, and a step of cutting the sealing resin between a plurality of base plates. | 09-08-2011 |
| 20110215462 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing semiconductor devices is provided, in which a resin sealing structure includes an interconnection substrate board, semiconductor chips, a heat radiation plate, and sealing resin. The method is achieved by cutting the heat radiation plate by a plate cutting blade in a first direction along a first heat radiation plate cutting line; by cutting the heat radiation plate by the plate cutting blade in a second direction along a second heat radiation plate cutting line, after cutting in the first direction by the plate cutting blade; and by cutting the interconnection substrate board and the sealing resin along first and second interconnection substrate board cutting lines by a substrate board cutting blade in the first direction and the second direction, respectively. The second heat radiation plate cutting line and the second interconnection substrate board cutting line correspond to each other in position in a third direction orthogonal to the first direction and the second direction. The first heat radiation plate cutting line is displaced from the first interconnection substrate board cutting line by a preset displacement amount in a direction opposite to the second direction. | 09-08-2011 |
| 20110233754 | Encapsulated Semiconductor Chip with External Contact Pads and Manufacturing Method Thereof - A method includes providing a carrier; applying a dielectric layer to the carrier; applying a metal layer to the dielectric layer; placing a first semiconductor chip on the metal layer with contact pads of the first semiconductor chip facing the metal layer; covering the first semiconductor chip with an encapsulation material; and removing the carrier. | 09-29-2011 |
| 20110233755 | Semiconductor Housing Package, Semiconductor Package Structure Including The Semiconductor Housing Package, And Processor-Based System Including The Semiconductor Package Structure - A semiconductor housing package may be provided. The semiconductor housing package may include a mold layer, a housing chip, a redistribution structure, and a housing node. The mold layer may surround and partially expose the housing chip. The redistribution structure may be electrically connected to the housing chip and may be disposed on the mold layer. The housing node may be in contact with the redistribution structures. The semiconductor housing package may be disposed on a semiconductor base package and may constitute a semiconductor package structure along with the semiconductor base package. The semiconductor package structure may be disposed on a processor-based system. | 09-29-2011 |
| 20110241197 | Device and Method for Manufacturing a Device - A device includes a first semiconductor chip and a first encapsulant that encapsulates the first semiconductor chip and that includes a cavity. A carrier and an electrical component are mounted on the carrier. The carrier is arranged such that the electrical component is enclosed by the cavity. | 10-06-2011 |
| 20110260314 | DIE PACKAGE AND CORRESPONDING METHOD FOR REALIZING A DOUBLE SIDE COOLING OF A DIE PACKAGE - A die package is provided, including a die positioned on and in direct contact with a first heat sink element, and also including a package case and leads made of conductive material, protruding from the package case. The die package further includes a second heat sink element shaped as a spring element, in contact between the die and the leads, and emerging from a side of the package case opposite the first heat sink element. | 10-27-2011 |
| 20110285009 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a first terminal; connecting an integrated circuit to the first terminal; forming a second terminal connected over the first terminal and the integrated circuit by a vertical conductive post integral with the first terminal or the second terminal; and encapsulating the integrated circuit and the vertical conductive post leaving portions of the first terminal and the second terminal exposed. | 11-24-2011 |
| 20110291257 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; pressing an encapsulation onto the package carrier and with the integrated circuit therein; mounting a conductive frame, having a vertical pillar integral with a horizontal cover, through the encapsulation, over the integrated circuit, and the vertical pillar on the package carrier and the horizontal cover on the encapsulation; and forming a contact from the horizontal cover. | 12-01-2011 |
| 20110304036 | SEMICONDUCTOR PACKAGE WITH HEAT DISSIPATION DEVICES - A semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface, a heat dissipation member, defined with a cavity, disposed on the first surface of the first semiconductor chip and having a plurality of metal pillars which contact the first semiconductor chip, and one or more second semiconductor chips stacked on the first surface of the first semiconductor chip in the cavity to be electrically connected with one another and with the first semiconductor chip. | 12-15-2011 |
| 20110304037 | SEMICONDUCTOR DEVICE - A semiconductor device includes an enclosure of insulating material having an introduction portion and a discharge portion for an insulating refrigerant and also having an opening, filters mounted on the introduction portion and the discharge portion, respectively, so as to prevent conductive foreign matter from entering the enclosure, a power semiconductor element provided on the outside of the enclosure, a heat sink bonded to the power semiconductor element and extending through the opening and within the enclosure, and an insulator covering the portions of the power semiconductor element and the heat sink lying outside of the enclosure. | 12-15-2011 |
| 20120025366 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device comprises: forming a circuit pattern and a first metal film on a first major surface of a body wafer; forming a through-hole penetrating the body wafer from a second major surface of the body wafer and reaching the first metal film; forming a second metal film on a part of the second major surface of the body wafer, on an inner wall of the through-hole, and on the first metal film exposed in the through-hole; forming a recess on a first major surface of a lid wafer; forming a third metal film on the first major surface of the lid wafer including inside the recess of the lid wafer; with the recess facing the circuit pattern, and the first metal film contacting the third metal film, joining the lid wafer to the body wafer; and dicing the joined body wafer and lid wafer along the through-hole. | 02-02-2012 |
| 20120068328 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ACTIVE SURFACE HEAT REMOVAL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side. | 03-22-2012 |
| 20120068329 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device capable of selecting a desired circuit (step-down circuit (or step-up/step-down circuit) and step-up circuit) on the user side at low cost. A semiconductor device according to the present invention includes a diode element and a switching element (IGBT). An anode terminal of the diode element and one main electrode terminal of the switching element are adjacently arranged at a predetermined distance from each other. In addition, a cathode terminal of the diode element and the other main electrode terminal of the switching element are adjacently arranged at another predetermined distance from each other. | 03-22-2012 |
| 20120074557 | Integrated Circuit Package Lid Configured For Package Coplanarity - An integrated circuit package apparatus comprises a packaging substrate, an integrated circuit coupled to an upper side of the packaging substrate, an array of contacts coupled to an underside of the packaging substrate for electrically coupling the integrated circuit to a circuit board, and a lid coupled to the upper side of the packaging substrate. In one form, the lid includes a central portion lying on a first plane, corner areas lying on a second plane, and arcuate wall portions disposed between and interconnecting the corner areas and the central portion. Other forms of the lid are provided. | 03-29-2012 |
| 20120074558 | Circuit Board Packaged with Die through Surface Mount Technology - A package of a circuit board and a die are packed through surface mount technology (SMT). The shortest circuit is formed with at a low cost. Thus, the package can work in high speed and high frequency applications. | 03-29-2012 |
| 20120086115 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER INTERCONNECTIONS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component. | 04-12-2012 |
| 20120187554 | POWER SEMICONDUCTOR DEVICE, PRINTED WIRING BOARD, AND MECHANISM FOR CONNECTING THE POWER SEMICONDUCTOR DEVICE AND THE PRINTED WIRING BOARD - A power semiconductor device includes a conductive insertion member as an external terminal projecting from a surface of the power semiconductor device facing a printed wiring board. The printed wiring board includes a conductive fitting member mounted on a pad part of the printed wiring board. The fitting member receives the insertion member therein when the power semiconductor device is connected to the printed wiring board. The insertion member has a recessed portion formed on a side surface of the insertion member. The fitting member has a projecting portion with elasticity formed on an inner side surface of the fitting member. The elasticity causes the projecting portion of the fitting member to contact the recessed portion of the insertion member under pressure when the insertion member is inserted into the fitting member. | 07-26-2012 |
| 20120187555 | THERMALLY ENHANCED SEMICONDUCTOR PACKAGE SYSTEM - A semiconductor package system is provided including: a semiconductor chip; a substrate having a substrate opening and a vertical build-up wing, the substrate having the semiconductor chip mounted thereon with the vertical build-up wing circumscribed by vertical planes of a perimeter of, and spaced apart from, the semiconductor chip; a first heat slug attached above the substrate at a first horizontal plane and to a first surface of the semiconductor chip, the semiconductor chip at least partially encapsulated by the first heat slug; and a second heat slug attached to the substrate at a second horizontal plane above the first horizontal plane and to a second surface of the semiconductor chip through the substrate opening. | 07-26-2012 |
| 20120241937 | PACKAGE STRUCTURE HAVING MICRO-ELECTROMECHANICAL ELEMENT - Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above. | 09-27-2012 |
| 20120248594 | JUNCTION BOX AND MANUFACTURING METHOD THEREOF - The present disclosure relates to a junction box and a manufacturing method thereof. The junction box includes terminal member to which electric energy is supplied, a diode provided to the terminal member, and a heat sink brought into close contact with the diode by molding. The junction box may prevent malfunction and failure while achieving size reduction thereof. | 10-04-2012 |
| 20120256307 | SENSOR MODULE, SENSOR DEVICE, MANUFACTURING METHOD OF SENSOR DEVICE, AND ELECTRONIC APPARATUS - A sensor module includes a support member having a first flat surface, a second flat surface orthogonally connected to the first flat surface, a third flat surface orthogonally connected to the first flat surface and the second flat surface, and a fourth flat surface opposed to the first flat surface as an attachment surface to an external member, the first flat surface having a support surface depressed from the first flat surface, IC chips having connection terminals on active surface sides with inactive surface sides along the active surfaces respectively attached to the respective surfaces of the support member, and vibration gyro elements having connection electrodes, and the vibration gyro elements are provided on the active surface sides of the IC chips and the connection electrodes are attached to the connection terminals of the IC chips so that principal surfaces are respectively along the respective surfaces of the support member. | 10-11-2012 |
| 20130037929 | STACKABLE WAFER LEVEL PACKAGES AND RELATED METHODS - The present semiconductor device packages include a die, a redistribution layer and a plurality of conductive pillars electrically connected to the redistribution layer. A molding compound partially encapsulates the die and the pillars. A plurality of interconnect patterns on the molding compound are electrically connected to the pillars. The interconnect patterns provide electrical connections for a second, stacked semiconductor package. | 02-14-2013 |
| 20130037930 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip includes a body part having a first surface and a second surface facing away from the first surface, and an opening passing from the first surface to the second surface of the body part. | 02-14-2013 |
| 20130043580 | DIODE STRUCTURE - A diode structure includes a body, a first electrode, and a second electrode. The body has a longitudinal length and a transverse length. The first electrode has an end extending into the body along the longitudinal length, and has another end extending outwardly and horizontally from the body for a predetermined length. The second electrode lying on another side of the body to oppose the first electrode, has a tail extending into the body, and has another tail extending outward and horizontally from the body for the predetermined length. The predetermined length of the first electrode and the second electrode is no less than the longitudinal length of the body. Therefore, the diode structure features two electrodes with increased exposed surfaces and better heat dissipation. | 02-21-2013 |
| 20130082374 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid. | 04-04-2013 |
| 20130082375 | STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A system or microelectronic assembly can include one or more microelectronic packages each having a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region. | 04-04-2013 |
| 20130093074 | MULTI-DIE INTEGRATED CIRCUIT STRUCTURE WITH HEAT SINK - An integrated circuit structure can include a first die including a first surface and a second surface and a second die including a first surface and a second surface. The first surface of the first die can be coupled to the second surface of the second die. The integrated circuit structure also can include a heat sink coupled to the first surface of the first die and the first surface of the second die. | 04-18-2013 |
| 20130285231 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device has an insulation substrate formed with a conductive pattern; an independent terminal, which is an externally leading terminal, soldered to the conductive pattern of the insulation substrate; a case disposed over the insulation substrate such that a top surface of the independent terminal is exposed; an opening provided on a side surface of the case; a nut glove inserted from the opening so as to be below the independent terminal, and fix the independent terminal; and a first projection part formed on a side surface of the nut glove, and having tapers in a frontward direction and a rearward direction of insertion of the nut glove, respectively. The rearward taper of the first projection part is pressure contacting with a sidewall surface of the opening. | 10-31-2013 |
| 20130313699 | FAN-OUT HIGH-DENSITY PACKAGING METHODS AND STRUCTURES - A fan-out high-density packaging method includes providing a packaging substrate, forming a stripping film on the packaging substrate, and forming a first protection layer on the stripping film and pre-designed photolithography pattern openings on the first protection layer. The method also includes forming a metal redistribution layer on the surface of the first protection layer and in the photolithography pattern openings, forming a second protection layer on the first protection layer and partially exposing the metal redistribution layer, and forming at least one package layer on the second protection layer. Each of at least one package layer includes a straight mounting layer, a sealant layer, and a wiring layer formed in sequence, and the package layer connects the metal redistribution layer through the wiring layer. Further, the method includes forming at least one top-level package layer on top of the at least one package layer, removing the packaging substrate and the stripping film to expose the metal redistribution layer in the first protection layer, and planting metal solder balls on the exposed metal redistribution layer. | 11-28-2013 |
| 20130320516 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings. | 12-05-2013 |
| 20130341781 | HEAT TRANSFER MEMBER AND MODULE WITH THE SAME - A heat transfer member is disposed between a semiconductor element and an electrode plate. The heat transfer member comprises a metal portion extending between a first face at the semiconductor element side and a second face at the plate electrode side, and a ceramic portion surrounding the metal portion. An area of the first face is less than an area of the second face in the metal portion. | 12-26-2013 |
| 20140117526 | SEMICONDUCTOR POWER CONVERTER AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor power converter includes first and second electrical conductors opposed to each other, first and second semiconductor elements joined to a first joint surface of the first electrical conductor, first and second convex electrical conductors joined to the first and second semiconductor elements, a junction joined to the first and second convex electrical conductors and a second joint surface of the second electrical conductor, power terminals, signal terminals, and an envelope sealing the constituent members. The envelope includes a flat bottom surface which extends perpendicular to the semiconductor elements and in which first and second bottom surfaces of the electrical conductors are exposed. | 05-01-2014 |
| 20140197531 | COMPACT DEVICE PACKAGE - Various embodiments related to a compact device package are disclosed herein. In some arrangements, a flexible substrate can be coupled to a carrier having walls angled relative to one another. The substrate can be shaped to include two bends. First and second integrated device dies can be mounted on opposite sides of the substrate between the two bends in various arrangements. | 07-17-2014 |
| 20140217571 | LOW PROFILE ZERO/LOW INSERTION FORCE PACKAGE TOP SIDE FLEX CABLE CONNECTOR ARCHITECTURE - An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (I/O) pads formed on the top side of the package substrate. The I/O pads are electrically connected to the contact pads. The integrated circuit package also includes a flex cable receptacle electrically connected to the I/O pads on the top side of the package substrate. The flex cable receptacle is non-compressively attachable to a flex cable connector and includes receptacle connection pins electrically connected to the I/O pads. | 08-07-2014 |
| 20140217572 | Heat Sink Package - Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. | 08-07-2014 |
| 20140367842 | POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A power semiconductor element, a high-voltage electrode electrically connected to the power semiconductor element, a heat radiating plate connected to the power semiconductor element and having heat radiation property, a cooling element connected to the heat radiating plate with an insulating film being interposed, and a seal covering the power semiconductor element, a part of the high-voltage electrode, the heat radiating plate, the insulating film, and a part of the cooling element are included. The cooling element includes a base portion of which part is embedded in the seal and a cooling member connected to the base portion. The base portion and the cooling member are separate from each other, and the cooling member is fixed to the base portion exposed through the seal. | 12-18-2014 |
| 20150008572 | Power Semiconductor Package with Multiple Dies - A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive. | 01-08-2015 |
| 20150076682 | THINNED INTEGRATED CIRCUIT DEVICE AND MANUFACTURING PROCESS FOR THE SAME - A thinned integrated circuit device and manufacturing process for the same are disclosed. The manufacturing process includes forming a through-silicon via (TSV) on a substrate, a first terminal of the TSV is exposed on a first surface of the substrate, disposing a bump on the first surface of the substrate to make the bump electrically connected with the TSV, disposing an integrated circuit chip (IC) on the bump so that a first side of the IC is connected to the bump, disposing a thermal interface material (TIM) layer on a second side of the IC opposite to the first side of the IC, attaching a heat-spreader cap on the IC by the TIM layer, and backgrinding a second surface of the substrate to expose the TSV to the second surface of the substrate while carrying the heat-spreader cap. | 03-19-2015 |
| 20150091152 | EXTERNAL CONNECTION TERMINAL, SEMICONDUCTOR PACKAGE HAVING EXTERNAL CONNECTION TERMINAL AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are an external connection terminal, a semiconductor package having the external connection terminal, and a method of manufacturing the same. The external connection terminal includes an internal insulating material, an external insulating material formed to enclose the internal insulating material, and metal lines formed between the internal insulating material and the external insulating material. | 04-02-2015 |
| 20150115430 | SEMICONDUCTOR PACKAGE AND WIRING BOARD HAVING THE SEMICONDUCTOR PACKAGE THEREON - A semiconductor package includes a chip, a sealing body covering the chip, and a plurality of external connection terminals connected to the chip. The external connection terminals expose from a surface of the sealing body and are arranged in a grid on the surface of the sealing body. In the grid on the surface of the sealing body, each external connection terminal is adjacent to an area vacant of an other external connection terminal in at least one direction of eight directions from each external connection terminal, the eight directions including first linear directions along a row of the grid, second linear directions along a row of the grid perpendicular to the first linear directions, and four diagonal directions defined between the first linear directions and the second linear directions. | 04-30-2015 |
| 20150311147 | SEMICONDUCTOR PACKAGE WITH A SEMICONDUCTOR DIE EMBEDDED WITHIN SUBSTRATES - Embodiments of the present disclosure provide configurations for a semiconductor package and associated methods of fabricating the semiconductor package. A method of fabricating a semiconductor package includes attaching a semiconductor die to a first substrate, attaching a second substrate to the first substrate, wherein the semiconductor die is embedded in between the first substrate and the second substrate, and forming an electrically insulative structure to substantially encapsulate the semiconductor die, wherein forming the electrically insulative structure is performed subsequent to the second substrate being attached to the first substrate. Additional embodiments may be described and/or claimed. | 10-29-2015 |
| 20150332988 | Semiconductor Package with Multiple Dies - A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive. | 11-19-2015 |
| 20150357272 | INTEGRATED INTERPOSER SOLUTIONS FOR 2D AND 3D IC PACKAGING - An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die. | 12-10-2015 |
| 20150364454 | RECONFIGURED WIDE I/O MEMORY MODULES AND PACKAGE ARCHITECTURES USING SAME - In some embodiments, it is desirable to increase memory bandwidth using an integrated solution. In one embodiment, wide I/O memory may be used. Described herein are embodiments of systems and methods of reconfiguring wide I/O memory modules. The reconfigured memory modules may be configured such that the memory modules function in combination with current packaging architectures. | 12-17-2015 |
| 20150380331 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having a front electrode and a rear electrode; a conductive plate having a main surface connected to the rear electrode of the semiconductor chip; an insulating plate fixed to a surface of the conductive plate opposite to the main surface; and a ceramic case having first and second terminals buried therein, a cavity accommodating the semiconductor chip, the conductive plate, and the insulating plate, and an electrode surface opposite to an opening portion of the cavity. The first terminal has one end connected to the front electrode of the semiconductor chip, and another end exposed from the electrode surface. The second terminal has one end connected to the main surface of the conductive plate, and another end exposed from the electrode surface. The ceramic case and the insulating plate form a housing. | 12-31-2015 |
| 20150380338 | SEMICONDUCTOR DEVICE - In a semiconductor device, an insulated substrate is bonded with a cooling body with lowered thermal resistance without a holding unit. The semiconductor device includes an insulated substrate where a wiring pattern copper plate unit for forming a plurality of wiring patterns is disposed on one side of an insulating plate unit, and a heat radiation copper plate unit disposed on the other side of the insulating plate unit; a semiconductor chip mounted on the wiring pattern copper plate unit; a cooling body contacted with the heat radiation copper plate unit; and a wiring conductor plate connected between the semiconductor chip and the wiring pattern copper plate unit. The heat radiation copper plate unit and the cooling body are bonded with a metal sintered material, and thicknesses of the wiring pattern copper plate unit and the heat radiation copper plate unit are set to such thermal stress is relaxed. | 12-31-2015 |
| 20160005670 | SEMICONDUCTOR DEVICE - A semiconductor device includes a supporting plate including a first surface, a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface; and a semiconductor unit fixed to the first surface. The semiconductor unit includes an insulating plate, a circuit plate fixed to a front surface of the insulating plate, a semiconductor chip fixed to the circuit plate, and a protruding metal block fixed to a rear surface of the insulating plate and penetrating through the through hole to extend to the second surface. | 01-07-2016 |
| 20160027709 | POWER SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING THE SAME, AND POWER CONVERTER - A power semiconductor module includes a metal plate having a through hole with an eaves; an insulated metal block including a metal block having an element mounting region on an upper surface, and an insulating layer on surfaces other than the upper surface and a portion of the upper surface other than the element mounting region; a circuit pattern disposed over the metal plate with the insulating material interposed therebetween; a power semiconductor element fixed to the element mounting region of the upper surface of the metal block; and a connection conductor connecting the power semiconductor element and the circuit pattern. The insulated metal block is fitted into the through hole in the metal plate so that the insulating layer on the upper surface of the insulated metal block contacts the eaves of the through hole to electrically insulate between the metal block and the metal plate. | 01-28-2016 |
| 20160027762 | Power Semiconductor Module - A power semiconductor module includes a first main electrode, a second main electrode and a control terminal. The power semiconductor module includes controllable power semiconductor components arranged between the first main electrode and the second main electrode. At least some of the controllable power semiconductor components are arranged in a ring arrangement, wherein the controllable power semiconductor components of the ring arrangement are arranged at least approximately along a first circular line of the ring arrangement, and a control conductor track of the ring arrangement is arranged on the first main electrode, wherein the control conductor track runs at least approximately along a second circular line of the ring arrangement, and the second circular line runs concentrically relative to the first circular line. | 01-28-2016 |
| 20160035637 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; a semiconductor element disposed on the substrate; a plurality of electrodes disposed on the substrate separately from one another and arranged so as to surround the semiconductor element in a plan view; a lid that cover the semiconductor element, the lid including an inner portion and a periphery portion that is outer than the inner portion in a plan view, the lid including a plurality of first protruding members that is provided separately from one another, the first protruding members being disposed in the inner portion; and conductive members disposed between the plurality of electrodes and the plurality of protruding members disposed in positions opposed to the plurality of electrodes respectively, the conductive members being joined to the plurality of electrodes and the plurality of protruding members respectively. | 02-04-2016 |
| 20160035657 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - According to one embodiment, a semiconductor device includes a first base portion, a second base portion, a third base portion, and a semiconductor element. A first end portion of the first base portion is positioned closer to a side on which the semiconductor element is provided than a second end portion of the first base portion. A third end portion of the second base portion is positioned closer to the side on which the semiconductor element is provided than a fourth end portion of the second base portion. A fifth end portion of the third base portion is positioned closer to the side on which the semiconductor element is provided than a sixth end portion of the third base portion in the third direction. | 02-04-2016 |
| 20160056132 | Low-Inductance Circuit Arrangement Comprising Load Current Collecting Conductor Track - A circuit arrangement includes at least two semiconductor chip having first and second load terminals that are each connected to one another, a first load current collecting conductor track, and also an external terminal electrically conductively connected thereto. For each of the semiconductor chips there is at least one electrical connection conductor electrically conductively connected to the first load terminal of the relevant semiconductor chip and also to the first load current collecting conductor track. The total inductance of all the connection conductors with which the first load terminal of the second of the semiconductor chips is connected to the first load current collecting conductor track has at least twice the inductance of that section of the first load current collecting conductor track which is formed between the second connection location of the first of the semiconductor chips and the second connection location of the second of the semiconductor chips. | 02-25-2016 |
| 20160099206 | WAFER LEVEL PACKAGING OF ELECTRONIC DEVICE - Wafer level packaged semiconductor device with enhanced heat dissipation properties. The semiconductor device includes a top and a bottom face and at least one metal pad is positioned on the top and the bottom faces. A top cover is affixed to the top face of the semiconductor device and a bottom cover is affixed to the bottom face of the semiconductor device. Vias extend through the top and bottom covers and an electroplated metal layer extends from an external face of the covers, through the visas to the metal pads on the semiconductor device. | 04-07-2016 |
| 20160099231 | SEMICONDUCTOR PACKAGE ASSEMBLY - The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package stacked on the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure. A first semiconductor die is coupled to the first RDL structure. A first molding compound surrounds the first semiconductor die, and is in contact with the RDL structure and the first semiconductor die. The second semiconductor package includes a second redistribution layer (RDL) structure. A first dynamic random access memory (DRAM) die without through silicon via (TSV) interconnects formed passing therethrough is coupled to the second RDL structure. | 04-07-2016 |
| 20160104650 | ELECTRONIC COMPONENT HOUSING PACKAGE AND ELECTRONIC DEVICE - An electronic component housing package has an input/output member that is bonded to a hole part of a frame body via a brazing material. This input/output member has a top surface that is bonded to first side wall parts and a second side wall part inside the first side wall parts, and the top surface is provided with a narrow part having a narrow width at a portion that is bonded to the first side wall part. When the input/output member is bonded, the flow of the brazing material on the top surface can be controlled by the narrow part. | 04-14-2016 |
| 20160126154 | Power Semiconductor Module and Method for Producing a Power Semiconductor Module - A power semiconductor module includes a module housing and a circuit carrier having a dielectric insulation carrier and an upper metallization layer applied onto an upper side of the dielectric insulation carrier. A semiconductor component is arranged on the circuit carrier. The power semiconductor module also has an electrically conductive terminal block connected firmly and electrically conductively to the circuit carrier and/or to the semiconductor component. The terminal block has a screw thread that is accessible from an outer side of the module housing. A method for producing such a power semiconductor module is also provided. | 05-05-2016 |
| 20160126157 | DOUBLE-SIDED COOLING POWER MODULE AND METHOD FOR MANUFACTURING THE SAME - A double-sided cooling power module may include a lower-end terminal, at least one pair of power semiconductor chips mounted on the lower-end terminal, at least one pair of horizontal spacers mounted on the at least one pair of power semiconductor chips, an upper-end terminal mounted on the at least one pair of horizontal spacers, and at least one pair of vertical spacers disposed between the upper-end terminal and the lower-end terminal | 05-05-2016 |
| 20160148853 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating substrate including a metal plate, an insulating plate, and a circuit plate laminated sequentially in order; a semiconductor element fixed to the circuit plate; a wiring member connected to an electrode provided on a surface of the semiconductor element, the circuit plate, or the electrode and the circuit plate; a plastic housing having a hollow shape to receive the insulating substrate, the semiconductor element, and the wiring member therein, the plastic housing having an inner frame on an inner surface and a step formed in a front end of the inner frame; and a sealing material made of a thermosetting resin to seal the insulating substrate, the semiconductor element, and the wiring member inside the plastic housing. | 05-26-2016 |
| 20160155679 | ELECTRONIC HARDWARE ASSEMBLY | 06-02-2016 |
| 20160172302 | PACKAGE ON PACKAGE (POP) DEVICE COMPRISING A HIGH PERFORMANCE INTER PACKAGE CONNECTION | 06-16-2016 |
| 20160190038 | COOLER AND SEMICONDUCTOR DEVICE HAVING COOLER - A cooler for cooling a semiconductor module includes a top plate; a jacket having a side plate and a bottom plate and firmly fixed to the top plate; a refrigerant inflow port through which a refrigerant flows into a space surrounded by the top plate and jacket; a refrigerant outflow port through which the refrigerant flows out from the space; a plurality of fins firmly fixed to the top plate and disposed separately on each of the left and right relative to a main refrigerant path in the jacket to be inclined toward the inflow side of the main refrigerant path; heat transfer pins disposed on the top plate on the refrigerant inflow sides of the fins; and a curved plate-like bimetal valve having one end connected to each respective heat transfer pin and another free end. | 06-30-2016 |
| 20160190072 | STACKED SEMICONDUCTOR PACKAGES WITH CANTILEVER PADS - One or more embodiments are directed to semiconductor packages, including stacked packages, with one or more cantilever pads. In one embodiment a recess is located in a substrate of the package facing the cantilever pad. The cantilever pad includes a conductive pad on which a conductive ball is formed. The cantilever pad is configured to absorb stresses acting on the package. | 06-30-2016 |
