| Entries |
| Document | Title | Date |
|---|
| 20080197468 | Package structure and manufacturing method thereof - A package structure and a manufacturing method thereof are provided. The package structure includes a substrate, a first chip, a cap structure, a second chip and a sealant. The first chip is disposed in an opening of the substrate and is electrically connected to the substrate. The cap structure is disposed on the substrate corresponding to the first chip. The second chip is disposed on the cap structure and is electrically connected to the substrate. The sealant encapsulates the first chip, the cap structure and the second chip. | 08-21-2008 |
| 20080197469 | Multi-chips package with reduced structure and method for forming the same - The present invention provides a structure of multi-chips package and Method of the same comprising a substrate with a pre-formed die receiving cavity formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and an elastic dielectric layer filled into a gap between the die and the substrate to absorb thermal mechanical stress; therefore the thickness of the package is reduced and the CTE mismatch of the structure is reduced. The present invention also provides a structure for SIP with higher reliability and lower manufacturing cost. the process is simpler and it is easy to form the multi-chips package than the traditional one. Therefore, the present invention discloses a fan-out WLP with reduced thickness and good CTE matching performance. | 08-21-2008 |
| 20080197470 | Stacked electronic component and manufacturing method thereof - A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed. | 08-21-2008 |
| 20080197471 | SEMICONDUCTOR CHIP MOUNTING SUBSTRATE, SEMICONDUCTOR CHIP MOUNTING BODY, SEMICONDUCTOR CHIP STACKED MODULE, AND SEMICONDUCTOR CHIP MOUNTING SUBSTRATE MANUFACTURING METHOD - There is provided a semiconductor chip mounting substrate including a substrate on which a mounting region for mounting a semiconductor chip and a connection region for interlayer connection of the semiconductor chip are formed, and a plurality of alignment marks for alignment at the time of stacking which are provided around or in the connection region on the substrate, wherein a reinforcing member as a reinforcing region for reinforcing a portion between the plurality of alignment marks is provided on the substrate. | 08-21-2008 |
| 20080197472 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE USING THE SAME - A semiconductor device includes a circuit board which has a first main surface having first connection pads, a second main surface having second connection pads, a first opening passing through a vicinity of the first connection pads, and a second opening passing through a vicinity of the second connection pads. A first semiconductor element is mounted in a face-down state on the first main surface of the circuit board. First electrode pads are exposed into the second opening and connected to the second connection pads through the second opening. A second semiconductor element is mounted in a face-up state on the second main surface of the circuit board. Second electrode pads are exposed into the first opening and connected to the first connection pads through the first opening. | 08-21-2008 |
| 20080203552 | Stacked Package and Method of Fabricating the Same - Disclosed herein is a stacked package. The stacked package includes two or more of a first BGA package and a second BGA package and a circuit board having a circuit pattern. The first BGA package is mounted on one face of the circuit board, and the second BGA package is mounted on the other face of the circuit board. A signal connection member is provided for transmitting signals of the first BGA package and the second BGA package to each other. The second BGA package is provided with a signal connection pad. One end of the signal connection member is bonded to the signal connection pad and the other end of the signal connection member is bonded to the circuit pattern of the circuit board. A method of fabricating the stacked package is also disclosed. | 08-28-2008 |
| 20080203553 | Stackable bare-die package - A stackable bare-die package primarily comprises a substrate, a chip, a plurality of bonding wires and an encapsulant. The substrate has a slot where a step is formed inside the slot where a plurality of inner fingers are disposed on the step. A plurality of outer pads are disposed on the bottom surface and a plurality of transfer pads on the top surface. The chip is disposed on the top surface and is electrically connected to the inner fingers by a plurality of bonding wires passing through the slot. An encapsulant is formed inside the slot to encapsulate the bonding wires. There is a height difference between the step and the bottom surface so that the loop height of the bonding wires will not exceed the bottom surface. Therefore, when stacking the stackable bare-die packages, the exposed back surface of the chip will not be touched nor stressed to avoid die crack issues. | 08-28-2008 |
| 20080203554 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided. | 08-28-2008 |
| 20080211077 | Low profile chip scale stacking system and method - The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers. In some preferred embodiments, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In other embodiments, a heat spreader is disposed between the CSP and the flex circuitry thus providing an improved heat transference function without the standardization of the form standard, while still other embodiments lack either a form standard or a heat spreader and may employ, for example, the flex circuitry as a heat transference material. | 09-04-2008 |
| 20080211078 | SEMICONDUCTOR PACKAGES AND METHOD OF MANUFACTURING THE SAME - A stacked semiconductor package can be formed according to principles of the present invention by stacking a plurality of semiconductor packages. A method of manufacturing the stacked semiconductor packages provides a simple manufacturing process. The stacked semiconductor package embodying these principles preferably includes a base substrate, one or more lower semiconductor packages, one or more upper semiconductor packages, and an external sealing agent. Each lower semiconductor package can include a first inner substrate, one or more first semiconductor chips electrically connected to and mounted on the first inner substrate, a first inner sealing agent sealing the first semiconductor chips, and a first contact portion. Each lower semiconductor package is preferably mounted on a portion of an upper surface of the base substrate and is electrically connected to the base substrate via the first contact portion. Each upper semiconductor package can include a second inner substrate, one or more second semiconductor chips electrically connected to and mounted on the second inner substrate, a second inner sealing agent sealing the second semiconductor chips, and a second contact portion which preferably does not contact the lower semiconductor package. Each upper semiconductor package is preferably mounted on and electrically connected to an upper surface of the base substrate via the second contact portion. One or more of the upper semiconductor packages can cover one or more of the lower semiconductor packages. The external sealing agent can cover the upper surface of the base substrate and seal the lower semiconductor package and the upper semiconductor package. A third contact portion can be formed on a lower surface of the base substrate to electrically connect the base substrate to the outside. Use of stacked semiconductor packages constructed according to these principles leads to low defect rates and high mechanical stability. | 09-04-2008 |
| 20080211079 | Heat dissipation methods and structures for semiconductor device - A semiconductor device with efficient heat dissipating structures is disclosed. The semiconductor device includes a first semiconductor chip that is flip-chip mounted on a first substrate, a heat absorption portion that is formed between the first semiconductor chip and the first substrate, an outer connection portion that connects the first semiconductor chip to an external device and a heat conduction portion formed between the heat absorption portion and the outer connection portion to dissipate heat generated by the first semiconductor chip. | 09-04-2008 |
| 20080217752 | Functional Device Package - A packaging structure for hermitically sealing a functional device by solder connection at a wafer level in which a first Si substrate having a concave portion metallized on its internal surface and a second Si substrate metallized at a position opposed to said concave portion are used, the metallization applied to the internal surface of the concave portion of the first Si substrate and the metallization applied to the second Si substrate at the position opposed to the concave portion are connected by molten solder to hermetically seal the functional device between the first Si substrate and the second Si substrate, whereby the wettability of the solder for the two Si substrates is improved, the bondability between the Si substrates is enhanced, and the yield at which the package is manufactured is improved. | 09-11-2008 |
| 20080224294 | MULTI-CHIP PACKAGE WITH A SINGLE DIE PAD - A multi-chip package with a single die pad is provided. The multi-chip package includes a leadframe having a die pad and a plurality of leads surrounding the die pad. Each of the leads includes an upper lead, a lower lead and an intermediate lead substantially perpendicularly connected to the upper and lower leads, wherein the upper and lower leads are substantially parallel to the die pad. The upper and lower surfaces of the die pad are attached with upper and lower chips respectively. The upper chip is electrically connected to the upper surface of one part of the upper leads by a plurality of first bonding wires and the lower chip is electrically connected to the lower surfaces of the other part of the upper leads by a plurality of second bonding wires. A sealant is used to encapsulate the chips and bonding wires to protect these elements from damage. | 09-18-2008 |
| 20080224295 | Package structure and stacked package module using the same - A package structure with chip embedded therein is disclosed, which comprises a circuit board having a first surface, an opposite second surface and a through cavity penetrating the circuit board, wherein the first surface of the circuit board has a plurality of first conductive pads and a plurality of wire bonding pads disposed thereon, and the second surface of the circuit board has a plurality of second conductive pads disposed thereon; and a chip embedded in the through cavity of the circuit board, wherein the gap between the through cavity and the chip is filled with a filling material, the chip has an active surface with a plurality of electrode pads and an inactive surface, and the electrode pads electrically connect to the wire bonding pads of the circuit board by a plurality of metal lines. The present invention further provides a package module using the aforementioned package structure. | 09-18-2008 |
| 20080230886 | Stacked package module - A stacked package module is disclosed, which comprises: a first package structure comprising a first circuit board with a first chip embedded therein, wherein the first chip has a plurality of electrode pads, the first circuit board comprises a first surface, an opposite second surface, a plurality of first conductive pads on the first surface, a plurality of second conductive pads on the second surface, a plurality of conductive vias, and at least one circuit layer, and the electrodes of the first chip directly electrically connect to the conductive pads on the surfaces of the circuit board through the conductive vias and the circuit layer within the circuit board; and a second package structure electrically connecting to the first package structure through a plurality of solder balls to make package on package. The stacked package module provided by this invention has characteristics of compact size, high performance, and high flexibility. | 09-25-2008 |
| 20080230887 | SEMICONDUCTOR PACKAGE AND THE METHOD OF MAKING THE SAME - The present invention relates to semiconductor package and the method of making the same. The method of the invention comprises the following steps: (a) providing a first substrate; (b) mounting a first chip onto a surface of the first substrate; (c) forming a plurality of conductive elements on the surface of the first substrate; (d) covering the conductive elements with a mold, the mold having a plurality of cavities accommodating top ends of each of the conductive elements; and (e) forming a first molding compound for encapsulating the surface of the first substrate, the first chip and parts of the conductive elements, wherein the height of the first molding compound is smaller than the height of each of the conductive elements. Thus, the first molding compound encapsulates the entire surface of the first substrate, so that the mold flush of the first molding compound will not occur, and the rigidity of the first substrate is increased. | 09-25-2008 |
| 20080230888 | Semiconductor device - A first memory chip ( | 09-25-2008 |
| 20080237824 | Stacked electronic component package having single-sided film spacer - A method of fabricating a stacked electronic component package includes placing a single-sided film spacer on an upper surface of a lower electronic component inward of bond pad with a pickup tool. After being adhered to the upper surface of the lower electronic component, the pickup tool is retracted from the single-sided film spacer. An upper surface of a film, e.g., an organic film, of the single-sided film spacer is nonadhesive. Accordingly, the single-sided film spacer does not stick to the pickup tool during retraction of the pickup tool from the single-sided film spacer. | 10-02-2008 |
| 20080237825 | STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONDUCTIVE SPACER - A stacked integrated circuit package system is provided including providing a first device and a second device with the first device, the second device, or a combination thereof having an integrated circuit die; forming a conductive spacer structure over the first device with the conductive spacer structure having a spacer filler around a conductive element; mounting the second device over the conductive spacer structure and the first device; and encapsulating the first device, the second device, and the conductive spacer structure. | 10-02-2008 |
| 20080237826 | Method for protecting encapsulated sensor structures using stack packaging - A method of protecting a micro-mechanical sensor structure embedded in a micro-mechanical sensor chip, in which the micro-mechanical sensor structure is fabricated with a protective membrane, the micro-mechanical sensor chip is arranged so that a surface of the protective membrane faces toward a second chip, and the micro-mechanical sensor chip is secured to the second chip. | 10-02-2008 |
| 20080246134 | Package-Borne Selective Enablement Stacking - The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices. In preferred embodiments, the plastic body of one or more leaded packaged ICs bear conductive traces that create circuitry to provide stacking related electrical interconnections between the constituent ICs of a stacked module without the use of separate interposers or carrier structures. Typically, the circuitry is borne by the body of the upper one of the ICs of a two-IC leaded package stack to implement stacking-related connections between the constituent ICs. | 10-09-2008 |
| 20080246135 | Stacked package module - A stacked package module is disclosed, which comprises: a first package structure comprising a first circuit board with a first chip embedded therein, wherein the first chip has a plurality of electrode pads; the first circuit board comprises a first surface, an opposite second surface, a plurality of exposed electro-connecting ends, a plurality of first conductive pads on the first surface, a plurality of conductive vias, and at least one circuit layer, therewith the electrode pads of the first chip electrically connecting to the electro-connecting ends and the first conductive pads directly through the conductive vias and the circuit layer; and a second package structure electrically connecting to the first package structure through a plurality of first solder balls to make a package on package. The stacked package module of this invention has characters of compact size, high performance, high flexibility, and detachability. | 10-09-2008 |
| 20080246136 | Chips having rear contacts connected by through vias to front contacts - A microelectronic unit is provided in which front and rear surfaces of a semiconductor element may define a thin region which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device may be present at the front surface, with a plurality of first conductive contacts at the front surface connected to the device. A plurality of conductive vias may extend from the rear surface through the thin region of the semiconductor element to the first conductive contacts. A plurality of second conductive contacts can be exposed at an exterior of the semiconductor element. A plurality of conductive traces may connect the second conductive contacts to the conductive vias. | 10-09-2008 |
| 20080251906 | Package-on-package secure module having BGA mesh cap - A package-on-package (POP) secure module includes a BGA mesh cap, a first BGA package, and a second BGA package. The first BGA package includes a first integrated circuit (for example, a microcontroller that includes tamper detect logic). The second BGA package includes a second integrated circuit (for example, a memory). The second BGA package is piggy-back mounted to the first BGA package and the BGA mesh cap is piggy-back mounted to the second BGA package. A printed circuit board substrate member of the BGA mesh cap includes an embedded anti-tamper mesh. This mesh is connected in a protected manner within the module to the first integrated circuit. When the module is in use, a mesh embedded in an underlying printed circuit board is coupled to the BGA cap mesh so that both anti-tamper meshes are controlled by the tamper detect logic. | 10-16-2008 |
| 20080258285 | Simplified Substrates for Semiconductor Devices in Package-on-Package Products - An insulating sheet-like substrate ( | 10-23-2008 |
| 20080258286 | High Input/Output, Low Profile Package-On-Package Semiconductor System - A package-on-package system ( | 10-23-2008 |
| 20080258287 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: solder balls provided on an upper package; and pads provided on a lower package and directly connected to the solder balls, wherein at least one of the pads serves as a fiducial mark. Further, a shape of at least one of the pads is different from that of other pads and an area of at least one of the pads is substantially equal to that of the other pads. | 10-23-2008 |
| 20080258288 | Semiconductor device stack package, electronic apparatus including the same, and method of manufacturing the same - In a semiconductor device stack package and a method of forming the same, the package comprises: a substrate; a plurality of lower chips stacked on the substrate and having an active surface oriented in a direction toward the substrate; and at least one upper chip disposed on the lower chips and connected to the substrate via a bump disposed between the lower chips. As no wire loops are formed, there is no increase in the height of the stack package, and the electrical path is shortened, thereby improving the electric performance of the stack package. Also, the semiconductor device stack package has a flip chip structure, and thus a plurality of semiconductor chips can be stacked in various manners. | 10-23-2008 |
| 20080265389 | Substrate for multi-chip stacking, multi-chip stack package utilizing the substrate and its applications - A substrate for multi-chip stacking and a multi-chip stack package utilizing the substrate and its applications are disclosed. The substrate comprises a first wire-bonding finger, a second wire-bonding finger, a trace configured for electrical transmission and a loop wiring on a same surface. The first wire-bonding finger and the second wire-bonding finger are adjacent each other and to a die-attaching area of the substrate. The loop wiring connects the first wire-bonding finger with the second wire-bonding finger in series and connected to the trace. The loop wiring can be selectively broken or not when at least two chips are stacked on the die-attaching area and electrically connected to the first and second wire-bonding fingers respectively. Accordingly, the chips can operate respectively and independently without mutual interference if one of the chips is fail. Moreover, there is merit to apply the multi-chip stack package utilizing the substrate because it can be repaired after molding and without removing any bonding wire during semiconductor packaging processes. | 10-30-2008 |
| 20080265390 | SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including a PMOS transistor and a NMOS transistor is described. The method facilitates obtaining a FUSI phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps. | 10-30-2008 |
| 20080265391 | ETCHED INTERPOSER FOR INTEGRATED CIRCUIT DEVICES - In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer. In one embodiment, the interposer | 10-30-2008 |
| 20080272476 | Through-Hole Via On Saw Streets - A semiconductor device is manufactured by, first, providing a wafer designated with a saw street guide. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A plurality of via holes is formed in the organic material. Each of the plurality of via holes is patterned to each of a plurality of bond pad locations on the plurality of dies. A conductive material is deposited in each of the plurality of via holes. | 11-06-2008 |
| 20080272477 | Package-on-Package Using Through-Hole Via Die on Saw Streets - A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package. | 11-06-2008 |
| 20080272478 | Circuit and method for interconnecting stacked integrated circuit dies - Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively. | 11-06-2008 |
| 20080283992 | Multi layer low cost cavity substrate fabrication for pop packages - In a method and system for fabricating a semiconductor device ( | 11-20-2008 |
| 20080283993 | Die stacking system and method - Die stacking systems and methods are disclosed. In an embodiment, a die has a surface that includes a passivation area, at least one conductive bond pad area, and a conductive stacked die receiving area sized to receive at least a second die. | 11-20-2008 |
| 20080283994 | Stacked package structure and fabrication method thereof - A stacked package structure and fabrication method thereof are disclosed, including providing a substrate having a plurality of stackable solder pads formed on surface thereof for allowing at least one semiconductor chip to be electrically connected to the substrate; forming an encapsulant for encapsulating the semiconductor chip and further exposing the stackable solder pads from the encapsulant, thus forming a lower-layer semiconductor package; forming conductive bumps on at least one stackable solder pad by means of wire bonding such that at least one upper-layer semiconductor package can be mounted via solder balls on the conductive bumps and the stackable solder pads of the lower-layer semiconductor package to form a stacked package structure, wherein, stacking height of the solder balls and the conductive bumps is greater than height of the encapsulant of the lower-layer semiconductor package, thus, when stacking fine pitch semiconductor packages or when warps occur to the upper-layer semiconductor package or the lower-layer semiconductor package, the conductive bumps can compensate for inadequate height caused by solder ball collapse or fill up gaps between the solder balls and the stackable solder pads caused by warps, thereby allowing the solder balls to be able to effectively contact and wet on the substrate of the lower-layer semiconductor package. | 11-20-2008 |
| 20080290491 | Semiconductor package and stacked layer type semiconductor package - In a stacked layer type semiconductor package constructed by stacking a plurality of packages with each other, the plurality of packages include a semiconductor package including: a semiconductor chip; a substrate in which a concave portion has been formed, the semiconductor chip being mounted in the concave portion; and a wiring line structure constructed in such a manner that the wiring line structure can be externally connected to the semiconductor chip at least just above and just under the semiconductor chip. | 11-27-2008 |
| 20080290492 | SEMICONDUCTOR PACKAGES WITH ENHANCED JOINT RELIABILITY AND METHODS OF FABRICATING THE SAME - Provided is a semiconductor package with enhanced joint reliability and methods of fabricating the same. The method includes: forming package units including a semiconductor chip interposed between a bottom layer and a top layer; and sequentially stacking the package units on a substrate. The bottom layer and the top layer are formed of a material having a lower modulus than the semiconductor chip. The semiconductor package includes: at least one package unit disposed on a substrate, the package unit including a semiconductor chip having a pad, a bottom layer and a top layer substantially surrounding the semiconductor chip, and a redistribution structure overlying the top layer. The redistribution structure is electrically connected to the pad. | 11-27-2008 |
| 20080290493 | STACKED CHIP SEMICONDUCTOR DEVICE - A stacked chip semiconductor device whose size is substantially reduced by high density packaging of two or more semiconductor chips. In the semiconductor device, four semiconductor chips are stacked over a printed wiring board. The bottom semiconductor chip has an interface circuit which includes a buffer and an electrostatic discharge protection circuit. All signals that these semiconductor chips receive and send are inputted or outputted through the interface circuit of the bottom semiconductor chip. Since the other semiconductor chips require no interface circuit, the semiconductor device is compact. | 11-27-2008 |
| 20080296748 | Transmission line stacking - A microelectronic unit has a structure including a microelectronic element such as a semiconductor chip with a first contact disposed remote from the periphery of the structure. The unit further includes first and second redistribution conductive pads disposed near a periphery of the structure and a conductive path incorporating first and second conductors extending toward the first contact, these conductors being connected to one another adjacent the first contact. The conductive path is connected to the first contact, and can provide signal routing from the periphery of the unit to the contact without the need for long stubs. A package may include a plurality of such units, which may be stacked on one another with the redistribution conductive pads of the various units connected to one another. | 12-04-2008 |
| 20080296749 | Package stacking through rotation - A packaged microelectronic element includes a package element that further includes a dielectric element having a bottom face and a top face, first and second bond windows extending between the top and bottom faces, a plurality of chip contacts disposed at the top face adjacent to the first and second bond windows, and first and second sets of package contacts exposed at diagonally opposite corner regions of the top face, wherein the first and second sets conductively connected to the chip contacts. There is also a microelectronic element adjacent to the bottom face of the dielectric element, as well as bond wires extending through the first and second bond windows to conductively connect the microelectronic element to the chip contacts. | 12-04-2008 |
| 20080303130 | Package on package structure - A package on package structure includes a first chip package, a second chip package and a conductive film. The first chip package has a portion of first conductive lead which is exposed to the encapsulation body of the first chip package. The conductive film is arranged between the first chip package and the second chip package to adhere to them and electrically connect the first conductive lead and the second chip package. The above-mentioned package on package structure can improve short-circuit phenomenon between leads. | 12-11-2008 |
| 20080303131 | ELECTRICALLY INTERCONNECTED STACKED DIE ASSEMBLIES - In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected. | 12-11-2008 |
| 20080303132 | Semiconductor chip packages having cavities - Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts. | 12-11-2008 |
| 20080308921 | MOLDED RECONFIGURED WAFER, STACK PACKAGE USING THE SAME, AND METHOD FOR MANUFACTURING THE STACK PACKAGE - A stack package includes at least two stacked package units. Each package unit comprises semiconductor chips having bonding pads on upper surfaces thereof; a molding part formed to surround side surfaces of the semiconductor chips; through-electrodes formed in the molding part; and re-distribution lines formed to connect the through-electrodes and adjacent bonding pads with each other. | 12-18-2008 |
| 20080315385 | Array molded package-on-package having redistribution lines - A semiconductor device with a sheet-like insulating substrate ( | 12-25-2008 |
| 20080315386 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor package, a second semiconductor package. The first semiconductor package includes a first semiconductor package base having a first cavity formed therein, a first mount component mounted in the first cavity, and a first magnet disposed on the first semiconductor package base. The second semiconductor package includes a second semiconductor package base having a second cavity formed therein, a second mount component mounted in the second cavity, and a second magnet disposed on the second semiconductor package base so as to adsorb the first magnet. The first semiconductor package and the second semiconductor package are stacked by an adsorption of magnetic force between the first magnet and the second magnet. | 12-25-2008 |
| 20080315387 | Semiconductor Package-on-Package System Including Integrated Passive Components - A semiconductor system ( | 12-25-2008 |
| 20090001539 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH TOP AND BOTTOM TERMINALS - An integrated circuit package system includes a die pad with leads; attaching an integrated circuit over the die pad; attaching a connector to the integrated circuit and the leads; and forming an encapsulant, over the integrated circuit, having a connection cavity over the leads leaving an exposed portion of the leads. | 01-01-2009 |
| 20090001540 | Stackable Package by Using Internal Stacking Modules - A semiconductor package has a substrate with solder balls. A first semiconductor die is disposed on the substrate. A first double side mold (DSM) internal stackable module (ISM) is in physical contact with the first semiconductor die through a first adhesive, such as a film on wire adhesive. A second DSM ISM is in physical contact with the first DSM ISM through a second adhesive. The arrangement of the first and second DSM ISM reduce headroom requirements for the package and increase device packing density. Each DSM ISM has semiconductor die disposed in cavities. An interposer is disposed above the top DSM ISM. Wire bonds connect the semiconductor die and DSM ISMs to the solder balls. An encapsulant surrounds the first semiconductor die and first DSM ISM with an exposed mold area in the encapsulant above the interposer. | 01-01-2009 |
| 20090001541 | Method and apparatus for stackable modular integrated circuits - Systems and methods for vertically stacking integrated circuit (IC) modules on a motherboard to conserve motherboard space and reduce power consumption are disclosed. IC modules can comprise processor circuitry, memory elements, communication circuitry, etc. Pins on each IC module can be directly inserted into lower IC module or into a socket layer that couples the IC modules. Heat generated by the IC modules can be dissipated by inserting heat dissipation layers into the vertical stack, between IC modules, or by placing a heat-dissipating sleeve around the stack. The IC modules themselves and/or heat-generating regions therein may be misaligned on their respective socket layers to further facilitate dissipating heat. Module stacks are scalable in that a user may add memory and/or processor modules as desired to increase device capability. | 01-01-2009 |
| 20090001542 | SEMICONDUCTOR PACKAGE AND MULTI-CHIP SEMICONDUCTOR PACKAGE USING THE SAME - Disclosed is a semiconductor package and a multi-chip semiconductor package. The semiconductor package includes a semiconductor chip having bonding pads located at a center portion thereof; redistribution patterns extending from the bonding pads toward one edge of the semiconductor chip; and dummy bump pads located adjacent to another edge of the semiconductor chip which is opposite the one edge. | 01-01-2009 |
| 20090001543 | LIGHTWEIGHT AND COMPACT THROUGH-SILICON VIA STACK PACKAGE WITH EXCELLENT ELECTRICAL CONNECTIONS AND METHOD FOR MANUFACTURING THE SAME - A through-silicon via stack package contains package units. Each package unit includes a semiconductor chip; a through-silicon via formed in the semiconductor chip; a first metal line formed on an upper surface and contacting a portion of a top surface of the through-silicon via; and a second metal line formed on a lower surface of the semiconductor chip and contacting a second portion of a lower surface of the through-silicon via. When package units are stacked, the second metal line formed on the lower surface of the top package unit and the first metal line formed on the upper surface of the bottom package unit are brought into contact with the upper surface of the through-silicon via of the bottom package unit and the lower surface of the through-silicon via of the top package unit, respectively. The stack package is lightweight and compact, and can form excellent electrical connections. | 01-01-2009 |
| 20090001544 | CHIP STACKED STRUCTURE AND METHOD OF FABRICATING THE SAME - A chip stacked structure and a method of fabrication the same that may include a first chip having first semiconductor devices and a first connection pad electrically connected to the first semiconductor devices, a second chip stacked on the first chip, the second chip having second semiconductor devices and a second connection pad electrically connected to the second semiconductor devices, and a connection member interposed between the first connection pad and the second connection pad to electrically connect the first connection pad and the second connection pad. The connection member has lower electric resistance than when the chips are unstacked, and thus, offers high reliability and performance. | 01-01-2009 |
| 20090008761 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLEX BUMP - An integrated circuit package system includes: forming a flex bump over an integrated circuit device structure, the flex bump having both a base portion and an offset portion over the base portion; forming a first ball bond of a first internal interconnect over the offset portion; and encapsulating the integrated circuit device structure, the flex bump, and the first internal interconnect. | 01-08-2009 |
| 20090008762 | ULTRA SLIM SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - There is provided an ultra slim semiconductor package comprising: a multilayer thin film layer including at least one or more dielectric layers and at least one or more redistribution layers; at least one semiconductor chip electrically connected to the redistribution layer and mounted on the multilayer thin film layer; conductive structures electrically connected to the redistribution layer and each formed in a post shape at one side of the multilayer thin film layer; a molding part formed on the multilayer thin film layer and at least partially covering the conductive structures and the semiconductor chip; and bumps for external connection formed on the molding part and electrically connected to the conductive structures. The semiconductor package according to the present invention enables mass production at wafer level, is easily stacked between the packages, and has an excellent electrical characteristic. Further, since the package thickness is very thin, the semiconductor package contributes to the slimming of diverse electronic products. | 01-08-2009 |
| 20090008763 | SEMICONDUCTOR PACKAGE - A semiconductor package, which may include a structure of a semiconductor package having a minimized mounting area and height. The semiconductor package may include a board, a first package comprising at least one first semiconductor chip, and disposed on the board so as to be supported, a second package comprising at least one second semiconductor chip, and disposed on the board so as be supported, and a third package that comprises at least one third semiconductor chip, the third package having a cross-sectional area greater than a cross-sectional area of the first package, the third package being disposed on the first package and the second package so as to be supported, wherein the cross-sectional areas of the third package and the first package are taken along a plane parallel to the board. | 01-08-2009 |
| 20090014857 | SEMICONDUCTOR WAFER STRUCTURE - One embodiment provides a semiconductor wafer structure including a semiconductor wafer and a spacer layer. The semiconductor wafer includes active areas. The spacer layer is configured to provide spacing between the semiconductor dice in a stacked die package and the spacer layer is disposed on one side of the semiconductor wafer. | 01-15-2009 |
| 20090014858 | PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES - Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites. | 01-15-2009 |
| 20090014859 | INTERCONNECTS FOR PACKAGED SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING SUCH DEVICES - Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a packaged semiconductor assembly includes a die attached to a support layer. A plurality of interconnects are embedded in and project from the support layer, such that the support layer at least partially retains the interconnects in a predetermined array. An encapsulant is molded around each of the interconnects and encases at least a portion of the die, support layer and interconnects. | 01-15-2009 |
| 20090014860 | Multi-chip stack structure and fabricating method thereof - A multi-chip stack structure and a manufacturing method thereof are provided. The fabrication method includes the steps of: providing a chip carrier having a first surface and a second surface opposing thereto and at least a first chip and a second chip mounted on the first surface; electrically connecting the chips to the chip carrier by a plurality of bonding wires; and stacking at least a third chip on the first and second chips by a film deposed therebetween, wherein the third chip is stepwise stacked on the first chip and at least a part of the bonding wire connected to the second chip is covered by the film, and electrically connecting the third chip and the chip carrier by a bonding wire, thereby enabling a plurality of chips to be stacked on the chip carrier to enhance the electrical performance of electronic products. | 01-15-2009 |
| 20090020863 | Stacked semiconductor devices and signal distribution methods thereof - A stacked semiconductor device includes a plurality of stacked chips, each having a plurality of elements to receive a signal. At least one first ladder main signal line for receiving the signal is arranged to pass through the chips. At least one second ladder main signal line is arranged to pass through the chips. A plurality of ladder buffers buffer the signal applied from the first ladder main signal line to the second ladder main signal line. The signal is uniformly distributed to the stacked chips using a ladder type circuit network technique. | 01-22-2009 |
| 20090026600 | MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS - Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an āLā shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a āCā shape and include a tiered portion that projects towards the lateral side of the second casing. | 01-29-2009 |
| 20090032926 | Integrated Support Structure for Stacked Semiconductors With Overhang - The present disclosure relates to an integrated circuit packaging, a strip having a plurality of integrated circuit packages, and method of manufacture thereof, and more particularly, to a substrate having an integrated overhang support structure to support a ledge created by stacking a large circuit die on a small circuit die. In one embodiment, the upper substrate surface comprises a protrusion as an integrated support structure. The structure may include passages to direct the flow of underfill into the limited support area to create an open area for vacuum or for placement of passive or active components. | 02-05-2009 |
| 20090032927 | SEMICONDUCTOR SUBSTRATES CONNECTED WITH A BALL GRID ARRAY - A stacked module has an upper semiconductor package that includes a substrate having opposed first and second surfaces. A cavity defined in the second surface receives at least a portion of a semiconductor mounted on the substrate of a lower semiconductor package. A plurality of solder bumps disposed between the first and second packages connect the two substrates. | 02-05-2009 |
| 20090032928 | Multi-chip stack structure having through silicon via and method for fabrication the same - The invention discloses a multi-chip stack structure having through silicon via and a method for fabricating the same. The method includes: providing a wafer having a plurality of first chips; forming a plurality of holes on a first surface of each of the first chips and forming metal posts and solder pads corresponding to the holes so as to form a through silicon via (TSV) structure; forming at least one groove on a second surface of each of the first chips to expose the metal posts of the TSV structure so as to allow at least one second chip to be stacked on the first chip, received in the groove and electrically connected to the metal posts exposed from the groove; filling the groove with an insulating material for encapsulating the second chip; mounting conductive elements on the solder pads of the first surface of each of the first chips and singulating the wafer; and mounting and electrically connecting the stacked first and second chips to a chip carrier via the conductive elements. The wafer, which is not totally thinned but includes a plurality of first chips, severs a carrying purpose during the fabrication process and thereby solves problems, namely a complicated process, high cost, and adhesive layer contamination, facing the prior art that entails repeated use of a carrier board and an adhesive layer for vertically stacking a plurality of chips and mounting the stacked chips on a chip carrier. | 02-05-2009 |
| 20090039490 | Mounting assembly of semiconductor packages prevent soldering defects caused by substrate warpage - A mounting assembly of semiconductor packages is revealed, primarily comprising at least a semiconductor package having a plurality of external terminals, a package carrier, and solder paste. The solder paste joints the external terminals to the package carrier. According to the distance to a central line on a substrate of the semiconductor package, the external terminals are divided into at least two different groups. In one of the embodiment, different groups of the external terminals are bumps with non-equal heights to achieve a uniform standoff plane to compensate the warpage of the substrate. The predicted substrate warpage can be compensated without causing any soldering defects. In another embodiment, a plurality of compensating bumps are selectively disposed on one group of the external terminals with larger stacking gaps. | 02-12-2009 |
| 20090039491 | SEMICONDUCTOR PACKAGE HAVING BURIED POST IN ENCAPSULANT AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip. | 02-12-2009 |
| 20090039492 | STACKED MEMORY DEVICE - A semiconductor memory device includes a stacked plurality of interposer chips, each interposer chip seating a smaller corresponding memory chip, wherein a lowermost interposer chip in the stacked plurality of interposer chips is mounted on a buffer chip. Each one of the stacked plurality of interposer chips includes a central portion having bond pads seating the corresponding memory device and a peripheral portion having a plurality of through silicon vias (TSVs). The respective pluralities of TSVs for adjacent interposer chips in the stacked plurality of interposer chips are connected via vertical connection elements to form multiple internal signal paths communicating write data from and read data to the buffer chip from respective memory chips. | 02-12-2009 |
| 20090039493 | Packaging substrate and application thereof - A packaging substrate is disclosed in the present invention, which includes a substrate body having a first surface and an opposite second surface. The first surface has a first cavity, and the second surface has a second cavity. The first cavity corresponds to and is interlinked to the second cavity. In order to provide a space for disposing a chip, the dimension of the second cavity is larger than that of the first cavity, such that there is a step at the interlinking region between the first cavity and the second cavity. Additionally, a plurality of wire bonding pads are disposed on the first surface around the first cavity. A package structure comprising the packaging substrate and the application thereof are also provided in the present invention. | 02-12-2009 |
| 20090045496 | STACKED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING STACKED MICROELECTRONIC DEVICES - Stacked microelectronic devices and methods of manufacturing stacked microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a plurality of electrically isolated, multi-tiered metal spacers on a front side of a first microelectronic die, and attaching a back-side surface of a second microelectronic die to individual metal spacers. In another embodiment, the method of manufacturing the microelectronic device may further include forming top-tier spacer elements on front-side wire bonds of the first die. | 02-19-2009 |
| 20090045497 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a wiring board having connection pads thereon and a semiconductor chip mounted on the wiring board. The wiring board and the semiconductor chip are covered with a sealing portion. Conductive members are extended upward from the connection pads and are exposed from the sealing portion. Rewiring lines are connected to the exposed conductive members. Land portions are arranged on the sealing portion and are electrically connected to the conductive members through the rewiring lines. | 02-19-2009 |
| 20090051023 | STACK PACKAGE AND METHOD OF FABRICATING THE SAME - Provided is a stack package comprising: a substrate comprising a cavity; a first semiconductor chip disposed in the cavity; and a second semiconductor chip stacked on the substrate and electrically connected to the substrate by a plurality of conductive external terminals such as conductive bumps. Since both a horizontal packaging method using bonding wires and a flip-chip packaging method are used and the bonding wires of the horizontal package and the conductive external terminals for the flip-chip bonding are formed on substantially the same plane, the total height of the stack package is reduced. | 02-26-2009 |
| 20090051024 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure relates to a chip-embedded semiconductor package electrically connected to a second semiconductor component. The semiconductor package structure comprises a first packaging substrate having a first surface, a second surface and at least a first cavity penetrating through the first surface and the second surface. The semiconductor package structure includes a first semiconductor component with electrode pads disposed in the first cavity. A first build-up circuit structure comprising a plurality of third and fourth conductive pads, and a second semiconductor component with electrode pads is disposed on surfaces of the third conductive pads by a first conductive element. The semiconductor package structure also includes a second conductive element disposed on the fourth conductive pads of the first build-up circuit structure of the first packaging substrate and a stacked structure electrically connecting the stacked structure to the first build-up circuit structure disposed on the first packaging substrate. | 02-26-2009 |
| 20090057862 | INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH CARRIER INTERPOSER - An integrated circuit package-in-package system includes: mounting an integrated circuit device over a package carrier; forming a subassembly including: providing an integrated circuit package system having a carrier interposer with an integrated circuit die thereover, and mounting a device under the carrier interposer; mounting the subassembly over the integrated circuit device; and encapsulating the subassembly and the integrated circuit device over the package carrier. | 03-05-2009 |
| 20090057863 | INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM WITH ANTI-MOLD FLASH FEATURE - An integrated circuit package-on-package system includes: mounting an integrated circuit package system having a mountable substrate over a package substrate; forming a package encapsulation having both a recess and an anti-mold flash feature over the package substrate and the integrated circuit package system including: forming the anti-mold flash feature having an extension width at the bottom of the recess, and partially exposing the mountable substrate in the recess with the anti-mold flash feature over mountable substrate; and mounting an integrated circuit device over the mountable substrate in the recess. | 03-05-2009 |
| 20090057864 | INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION - A method for manufacturing an integrated circuit package system includes: providing a base package including a first integrated circuit coupled to a base substrate by an electrical interconnect formed on one side; and mounting an offset package over the base package, the offset package electrically coupled to the base substrate via a system interconnect. | 03-05-2009 |
| 20090065918 | INTERCONNECTING ELECTRICAL DEVICES - An intercoupling component includes first male contacts, each first male contact received within a corresponding aperture of a first array of apertures and extending beyond a second surface of a first insulative support member toward a second insulative support member, each first male contact having a first axis; second contacts, each second contact received within a corresponding aperture of a second array of apertures, each second contact having a second axis; and an alignment member configured to establish a specified position of the first insulative support member relative to the second insulative support member. The first axis of each male contact is offset from the second axis of a corresponding second contact when the first insulative support member is in the specified position relative to the second insulative support member. | 03-12-2009 |
| 20090065919 | SEMICONDUCTOR PACKAGE HAVING RESIN SUBSTRATE WITH RECESS AND METHOD OF FABRICATING THE SAME - In one embodiment, a semiconductor package disclosed herein can be generally characterized as including a resin substrate having a first recess, a first interconnection disposed on a surface of the first recess, a first semiconductor chip disposed in the first recess, and an underfill resin layer substantially filling the first recess and covering a side surface of the first semiconductor chip. The first semiconductor chip is electrically connected to the first interconnection. | 03-12-2009 |
| 20090065920 | Semiconductor package embedded in substrate, system including the same and associated methods - A device includes a base substrate, a package including an encapsulated die, the package at least partially embedded in the base substrate, and a wiring portion on the package and extending across at least a portion of the base substrate adjacent to the package. | 03-12-2009 |
| 20090065921 | Electronic Package Device, Module, and Electronic Apparatus - There is provided an electronic device package and the like in which it is not likely that damage occurs in a wiring pattern of an interposer substrate in a gap section formed, for example, between an electronic device and an insertion substrate. The semiconductor package in accordance with the present invention is a package of fan-out type including an interposer substrate | 03-12-2009 |
| 20090065922 | SEMICONDUCTOR DEVICE PACKAGE STRUCTURE - A semiconductor chip mounted interposer ( | 03-12-2009 |
| 20090072373 | PACKAGED INTEGRATED CIRCUITS AND METHODS TO FORM A STACKED INTEGRATED CIRCUIT PACKAGE - Packaged integrated circuits and methods to form a thermal stacked integrated circuit package are disclosed. A disclosed method comprises attaching a first integrated circuit to at least one of a plurality of pads of a substrate, mounting a second integrated circuit above the first integrated circuit, placing a heat conductor in thermal contact with a top surface of the second integrated circuit, and encapsulating the first and second integrated circuits while leaving a surface of the heat conductor exposed to dissipate heat. | 03-19-2009 |
| 20090072374 | Electric Device, Stack of Electric Devices, and Method of Manufacturing a Stack of Electric Devices - According to one embodiment of the present invention, an electric device includes: a top surface and a bottom surface; a contact hole extending from the top surface through the device to the bottom surface; a conductive sealing element which seals the contact hole at or near the bottom surface; a conductive connection which is coupled to the conductive sealing element and which extends through the contact hole to the top surface; and solder material which is provided on a bottom surface of the conductive sealing element. | 03-19-2009 |
| 20090072375 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTI-CHIP MODULE - An integrated circuit package system with multi-chip module is provided including: providing an upper substrate having an upper chip thereon; positioning a lower chip under the upper chip, the lower chip having bottom interconnects thereon; encapsulating the upper chip and the lower chip with a chip encapsulant on the upper substrate with the bottom interconnects exposed; mounting the lower chip over a lower substrate with a gap between the chip encapsulant and the lower substrate; and filling the gap with a package encapsulant or chip attach adhesive. | 03-19-2009 |
| 20090072376 | Carrier Structure Stacking System and Method - The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent ICs are implemented in multi-layer interposers or carrier structures oriented along the leaded sides of the stack, with selected ones of the conductive transits electrically interconnected with other selected ones of the conductive transits. | 03-19-2009 |
| 20090079055 | METHOD AND STRUCTURE OF EXPANDING, UPGRADING, OR FIXING MULTI-CHIP PACKAGE - Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP. | 03-26-2009 |
| 20090085183 | INTEGRATED-CIRCUIT PACKAGE FOR PROXIMITY COMMUNICATION - Embodiments of a multi-chip module (MCM) are described. This MCM includes a first semiconductor die and a second semiconductor die, where a given semiconductor die, which can be the first semiconductor die or the second semiconductor die, includes proximity connectors proximate to a surface of the given semiconductor die. Moreover, the given semiconductor die is configured to communicate signals with the other semiconductor die via proximity communication through one or more of the proximity connectors. Furthermore, the MCM includes an alignment plate and a top plate coupled to the alignment plate. This alignment plate includes a first negative feature configured to accommodate the first semiconductor die and a second negative feature configured to accommodate the second semiconductor die, and the top plate includes a positive feature. Note that the positive feature is coupled to the first semiconductor die, and the positive feature facilitates mechanical positioning of the first semiconductor die. | 04-02-2009 |
| 20090085184 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same, and more particularly, a semiconductor package and a method of fabricating the semiconductor package. The semiconductor package includes a first package that comprises a first substrate, at least one first semiconductor chip stacked on the first substrate, and first conductive pads exposed on a top surface of the first substrate; a second package disposed below the first package such that the second package comprises a second substrate, at least one second semiconductor chip, and second conductive pads exposed on a bottom surface of the second substrate; and a connection unit that extends from the first conductive pads to the second conductive pads such that the connection unit covers a side surface of the first package and a side surface of the second package in order to electrically connect the first package to the second package. | 04-02-2009 |
| 20090085185 | STACK-TYPE SEMICONDUCTOR PACKAGE, METHOD OF FORMING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME - A stack-type semiconductor package, a method of forming the same, and an electronic system including the same are provided. The stack-type semiconductor package includes: a lower printed circuit board having a plurality of connection bumps disposed on an upper surface of the lower printed circuit board and a plurality of lower interconnections; at least one first lower chip sequentially stacked on the lower printed circuit board and electrically connected to the plurality of lower interconnections; a lower molding resin compound disposed on the lower printed circuit board and covering the first lower chips; a double-sided wiring board bonded to the lower molding resin compound and electrically connected to the connection bumps; and an upper chip package bonded to the double-sided wiring board and having upper bumps electrically connected to an interconnection pattern of the double-sided wiring board. | 04-02-2009 |
| 20090091015 | STACKED-TYPE CHIP PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A stacked-type chip package structure including a first package structure, a second package structure, and a first molding compound is provided. The first package structure includes a first substrate, and a first chip stacked thereon and electrically connected thereto. The second package structure is stacked on the first package structure, and includes a second substrate, a second chip, and a plurality of solder blocks. The second chip is electrically connected to the second substrate, and the second substrate is electrically connected to the first substrate. The second chip is fixed on the first chip through an adhesive layer. The solder blocks are disposed on the back of the second substrate. The first molding compound is disposed on the first substrate and encapsulates the first package structure and the second package structure. The first molding compound has a recess for exposing the solder blocks. | 04-09-2009 |
| 20090096075 | STACKED SEMICONDUCTOR PACKAGE THAT PREVENTS DAMAGE TO SEMICONDUCTOR CHIP WHEN WIRE-BONDING AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package includes a substrate having first and second contact pads. A first stacked package group is disposed on the substrate, and the first stacked package group includes first semiconductor chips stacked in a stair form to expose first edge bonding pads. First conductive wires are used to electrically couple the first edge bonding pads and the first contact pads. An adhesive member is disposed on the uppermost first semiconductor chip, and a second stacked package group is disposed on the adhesive member. The second stacked package group includes second semiconductor chips that are stacked in a stair form to expose second edge bonding pads. When the second stacked package group is disposed on the adhesive member, the bottommost second semiconductor chips is aligned with the uppermost first semiconductor chip. Second conductive wires are used to electrically couple the second edge bonding pads and the second contact pads. | 04-16-2009 |
| 20090096076 | STACKED SEMICONDUCTOR PACKAGE WITHOUT REDUCTION IN STATA STORAGE CAPACITY AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package includes a semiconductor chip module including at least two semiconductor chips with a semiconductor chip body having an upper surface, a lower surface, side surfaces coupling the upper surface and the lower surface, and a circuit part. The semiconductor chips include pads coupled to the circuit part and disposed at an edge of the upper surface. A recess parts are concavely formed in the side surfaces corresponding to each pad. Conductive connection patterns cover the recess parts, and each conductive connection pattern is electrically connected to a corresponding bonding pad. The semiconductor chip module is disposed on a substrate, and the contact pads of the semiconductor substrate are electrically connected to the conductive connection patterns. The stacked semiconductor package provides an improved structure that can contain a plurality of stacked semiconductor chips with no reduction in data storage capacity. | 04-16-2009 |
| 20090096077 | Tenon-and-mortise packaging structure - A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least one tenon projection, and the lower surface forms a mortise slot corresponding to the tenon projection in shape, size, and position, so that two carriers can be stacked on and jointed to each other by coupling the tenon projection to the corresponding mortise slot. The tenon projection and the mortise slot have conduction portions, respectively. When the tenon projection and the mortise slot are engaged with each other, the conduction portions are electrically connected with each other. At least one chip is embedded in the carrier. The chip has an active surface and a back side respectively and electrically connected with the top and the lower surfaces of the carrier. | 04-16-2009 |
| 20090102035 | Semiconductor Packaging Device - Embodiments of the invention relate to a semiconductor module and to a method for manufacturing a semiconductor module. In an embodiment of the invention, a semiconductor module for mounting to a board may include at least an integrated circuit having connections on at least one side of the integrated circuit, and at least a first layer which is applied to the side of the integrated circuit having the connections, wherein the free surface of the first layer facing away from the integrated circuit has a thermo-mechanical linear expansion in the in-plane direction of the surface which corresponds to the thermo-mechanical linear expansion of the board to which the semiconductor module is to be mounted. | 04-23-2009 |
| 20090102036 | Stacked semiconductor package having interposing print circuit board - A stacked semiconductor package including a number of solder ball pads formed on a lower surface of an interposing print circuit board, which is smaller than that of solder ball pads formed on an upper surface thereof, a pitch of the solder ball pads formed on the lower surface of the interposing print circuit board is greater than a pitch of the solder ball pads formed on the upper interposing print circuit board. | 04-23-2009 |
| 20090102037 | SEMICONDUCTOR PACKAGE, MODULE, SYSTEM HAVING SOLDER BALL COUPLED TO CHIP PAD AND MANUFACTURING METHOD THEREOF - A semiconductor package structure having a solder ball coupled to a chip pad and a manufacturing method thereof, a semiconductor package module, and a system. A circuit board includes a through hole therein, and a conductor is formed on a sidewall of the through hole. A first semiconductor chip including a first chip pad is mounted on the circuit board. A solder ball is disposed in the through hole and is bonded to the conductor and the first chip pad. Therefore, an underfill can be removed from a semiconductor package, and thus, the semiconductor package can be reduced in thickness. | 04-23-2009 |
| 20090102038 | CHIP SCALE STACKED DIE PACKAGE - A die prepared for stacking in a chip scale stacked die assembly, having interconnect sites in an area inward from a die edge and interconnect pads near at least one die edge. Second-level interconnection of the stacked die assembly can be made by way of connections between a first die in the assembly and circuitry on a support; and interconnection between die in the stack can be made by way of connection of z-interconnects with bonds pads in the die attach side of the support near or at one or more die edges. Methods for preparing the die include processes carried out to an advanced stage at the wafer level or at the die array level. | 04-23-2009 |
| 20090102039 | Package on package structure - The present invention relates to a package on package (PoP) structure, which comprises: a first packaging substrate having a plurality of conductive elements on its surface; a second packaging substrate having a plurality of conductive elements on its surface; and a surface-ceramic aluminum plate sandwiched between the first packaging substrate and the second packaging substrate. The surface-ceramic aluminum plate includes plural plated through holes extending through the layer. In addition, the first packaging substrate electrically conducts with the second packaging substrate through these plated through holes. The disclosed structure eliminates the warpage problem of PoP structure, and enhances the strength of PoP structure. | 04-23-2009 |
| 20090108428 | MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUBSTRATE HAVING A CONDUCTOR-FREE RECESS - A mountable integrated circuit package system includes: providing a carrier; mounting a first integrated circuit device over the carrier; mounting a substrate over the first integrated circuit device with the substrate having a conductor-free recess; connecting a first electrical interconnect under the conductor-free recess electrically connecting the carrier and the first integrated circuit device; and forming a package encapsulation over the carrier, the first integrated circuit device, the first electrical interconnect, the conductor-free recess, and partially exposing the substrate. | 04-30-2009 |
| 20090108429 | Flip Chip Packages with Spacers Separating Heat Sinks and Substrates - A package structure includes a substrate; a die over and flip bonded on the substrate; a heat sink over the die; and one or more spacer separating the heat sink from the substrate. | 04-30-2009 |
| 20090108430 | STACKED SEMICONDUCTOR PACKAGE IN WHICH SEMICONDUCTOR PACKAGES ARE CONNECTED USING A CONNECTOR - A stacked semiconductor package includes a semiconductor package module in which a plurality of semiconductor packages, which include a substrate and a semiconductor chip mounted over the substrate, are stacked. The stacked semiconductor package includes connectors for electrically connecting pairs of adjacent semiconductor packages so as to provide sequentially a signal from a lower semiconductor package of the semiconductor package module toward an upper semiconductor package. The stacked semiconductor package gives the semiconductor packages in the stacked semiconductor package the ability to cooperate with one another | 04-30-2009 |
| 20090108431 | Inverted package-on-package (POP) assemblies and packaging methods for integrated circuits - Integrated circuit package assemblies and packaging methods are provided. An integrated circuit package assembly includes a first circuit package including a first substrate having a top surface and a bottom surface, a first circuit die containing a programmable processor mounted to and electrically connected to the bottom surface of the first substrate, a bottom connector on the bottom surface of the first substrate and top circuit connections on the top surface of the first substrate, and a second circuit package mounted on the top surface of the first substrate and electrically connected to the top circuit connections of the first circuit package. | 04-30-2009 |
| 20090108432 | STACK PACKAGE MADE OF CHIP SCALE PACKAGES - A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip scale package face in the opposite direction to those of the lower stacked chip scale package, and the circuit patterns of the upper stacked chip scale package are electrically connected to the those of the lower stacked chip scale package by, for example, connecting boards. Therefore, it is possible to stack not only fan-out type chip scale packages, but to also efficiently stack ordinary area array type chip scale packages. | 04-30-2009 |
| 20090115042 | SEMICONDUCTOR DEVICE HAVING THREE-DIMENSIONAL STACKED STRUCTURE AND METHOD OF FABRICATING THE SAME - A three-dimensional stacked structured semiconductor device comprising semiconductor circuit layers stacked on a support substrate, and a method of fabricating the device are provided. | 05-07-2009 |
| 20090115043 | MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING INTERCONNECTS - A mountable integrated circuit package system includes: mounting a first integrated circuit device over a carrier; mounting a substrate over the first integrated circuit device, the substrate having a mounting interconnect; connecting a first electrical interconnect between the carrier and the substrate; and forming a package encapsulation covering the carrier, the first integrated circuit device, the first electrical interconnect, and the substrate with the mounting interconnect partially exposed from and surrounded by the package encapsulation within a cavity of the package encapsulation. | 05-07-2009 |
| 20090115044 | STRUCTURES AND METHODS FOR STACK TYPE SEMICONDUCTOR PACKAGING - Methods and structures for stack type semiconductor packaging are disclosed. In one embodiment, a semiconductor device includes a semiconductor chip mounted onto a substrate, a first resin molding portion formed on the substrate for sealing the semiconductor chip, and a through metal mounted on the substrate so as to pierce the first resin molding portion around the semiconductor chip. The semiconductor device further comprises an upper metal electrically coupled with the through metal and mounted on the first resin molding portion to extend from the through metal toward the semiconductor chip along an upper surface of the first resin molding portion, where the through metal and the upper metal are formed into an integral structure. | 05-07-2009 |
| 20090115045 | Stacked package module and method for fabricating the same - The present invention relates to a stacked package module and a method for fabricating the same. The stacked package module comprises: a first package structure, a second package structure, a ceramic-surfaced aluminum plate, and a metal paste. Herein, the ceramic-surfaced aluminum plate has a plurality of through holes filled with the metal paste to correspond with and electrically connect the first conductive pads of the first package structure and the second conductive pads of the second package structure; and the ceramic-surfaced aluminum plate further has a first cavity to receive a chip. Besides, the present invention provides a stacked package module, which can avoid warpage, omit the process for soldering, favor the shrinkage of size and pitch of the conductive pads, and also can reduce the height of the package. | 05-07-2009 |
| 20090121336 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package provides an enhanced data storage capacity along with an improved data processing speed. The stacked semiconductor package includes a substrate having chip selection pads and a connection pad; a semiconductor chip module including a plurality of semiconductor chips including data bonding pads, a chip selection bonding pad, and data redistributions electrically connected with the data bonding pads and a data through electrode passing through the data bonding pad and connected with the data redistribution, the semiconductor chips being stacked so as to expose the chip selection bonding pad; and a conductive wire for connecting electrically the chip selection pad and the chip selection bonding pads. | 05-14-2009 |
| 20090121337 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR - To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented. | 05-14-2009 |
| 20090121338 | ASSEMBLIES AND MULTI CHIP MODULES INCLUDING STACKED SEMICONDUCTOR DICE HAVING CENTRALLY LOCATED, WIRE BONDED BOND PADS - An assembly method that includes providing a first semiconductor device and positioning a second semiconductor device at least partially over the first semiconductor device is disclosed. Spacers space the active surface of the first semiconductor device substantially a predetermined distance apart from the back side of the second semiconductor device. Discrete conductive elements are extended between the active surface of the first semiconductor device and the substrate prior to positioning of the second semiconductor device. Intermediate portions of the discrete conductive elements pass through an aperture formed between the active surface of the first semiconductor device, the back side of the second semiconductor device, and two of the spacers positioned therebetween. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed. | 05-14-2009 |
| 20090127686 | Stacking die package structure for semiconductor devices and method of the same - The present invention disclosed a first multi-die package structure for semiconductor devices, the structure comprises a substrate having die receiving window and inter-connecting through holes formed therein; a first level semiconductor die formed under a second level semiconductor die by back-to-back scheme and within the die receiving window, wherein the first multi-die package includes first level contact pads formed under the first level semiconductor die having a first level build up layer formed there-under to couple to a first bonding pads of the first level semiconductor die; a second level contact pads formed on the second level semiconductor die having a second level build up layer formed thereon to couple to second bonding pads of the second level semiconductor die; and conductive bumps formed under the first level build up layer. | 05-21-2009 |
| 20090127687 | POP (package-on-package) semiconductor device - A semiconductor device having package-on-package (POP) configuration, primarily comprises a plurality of vertically stacked semiconductor packages and a plurality of electrical connecting components such as solder paste to electrically connect the external terminals of the semiconductor packages such as external leads of leadframes. Each semiconductor package has an encapsulant to encapsulate at least a chip where the encapsulant is movable with respect to the electrical connecting components to absorb the stresses between the vertically stacked semiconductor packages. In one embodiment, a stress-releasing layer is interposed between the vertically stacked semiconductor packages. | 05-21-2009 |
| 20090127688 | PACKAGE-ON-PACKAGE WITH IMPROVED JOINT RELIABILITY - Provided is a package-on-package (POP) having an improved joint reliability. The POP includes a lower package, an upper package that is mounted on the lower package, and a plurality of joint members that electrically connect the lower package to the upper package. The lower package includes a lower substrate and a lower semiconductor chip mounted on a first surface of the lower substrate. The upper package includes an upper substrate and at least one upper semiconductor chip mounted on the upper substrate. The joint members are arranged between the lower package and the upper package. The lower package further includes a lower sealing member that is completely filled in a space between the upper substrate of the upper package and the lower substrate of the lower package to surround the joint members and protect the lower semiconductor chips. | 05-21-2009 |
| 20090127689 | MICROELECTRONIC DEVICE PACKAGES, STACKED MICROELECTRONIC DEVICE PACKAGES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height. | 05-21-2009 |
| 20090134506 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND FLEXIBLE SUBSTRATE FOR MOUNTING SEMICONDUCTOR - A semiconductor device includes a second semiconductor package, which includes a substrate and at least one semiconductor package. The substrate includes a terminal group formed on a surface thereof. At least one first semiconductor package is stacked on the substrate, and includes a plurality of flexible substrates, each of which includes a wiring group on a surface thereof and each of which is bending-deformable. At least one first semiconductor package includes a plurality of semiconductor elements mounted on a plurality of flexible substrates. Electric conduction through the second semiconductor package is established by connecting the wiring group on each of a plurality of flexible substrates to the terminal group on the substrate. Further, at least one terminal of the terminal group on the substrate is electrically connected to all of the plurality of semiconductor elements on at least one first semiconductor package, and at least one other terminal of the terminal group is electrically connected only to particular semiconductor elements of the plurality of semiconductor elements. | 05-28-2009 |
| 20090134507 | Adhesive on wire stacked semiconductor package - A semiconductor package and a method of producing the same has a substrate. A first semiconductor chip is coupled to a surface of the substrate. The first semiconductor chip has a first and second surfaces which are substantially flat in nature. An adhesive layer is coupled to the second surface of the first semiconductor chip. A second semiconductor chip having first and second surfaces which are substantially flat in nature is further provided. An insulator is coupled to the first surface of the second semiconductor chip for preventing shorting of wirebonds. The second semiconductor chip is coupled to the adhesive layer by the insulator coupled to the first surface thereof. | 05-28-2009 |
| 20090140407 | INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM WITH ANTI-MOLD FLASH FEATURE - An integrated circuit package-on-package system includes: mounting an integrated circuit package system having a mountable substrate over a package substrate with the mountable substrate having a mold structure; forming a package encapsulation having a recess over the package substrate and the integrated circuit package system. The present invention also includes: forming an anti-mold flash feature with an extension portion of the package encapsulation and constrained by the mold structure at the bottom of the recess, and partially exposing the mountable substrate in the recess with the anti-mold flash feature formed with the mold structure; and mounting an integrated circuit device over the mountable substrate in the recess. | 06-04-2009 |
| 20090140408 | INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM WITH STACKING VIA INTERCONNECT - An integrated circuit package-on-package system includes: providing a bottom integrated circuit package system having a bottom substrate; mounting a top integrated circuit package system having a top substrate over the bottom integrated circuit package system; forming a top stacking via through the top substrate; forming a bottom stacking via into the bottom integrated circuit package system to the bottom substrate; and forming a stacking via interconnect with the top stacking via and the bottom stacking via aligned and connected. | 06-04-2009 |
| 20090140409 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having bumps on the backside thereof, a first semiconductor chip mounted on the surface of the substrate, a second semiconductor chip mounted on the first semiconductor chip above the surface of the substrate, a first bonding wire having a length L | 06-04-2009 |
| 20090146282 | Semiconductor Package and Method of Forming Similar Structure for Top and Bottom Bonding Pads - A semiconductor package has a first semiconductor die mounted on a substrate. A conductive via is formed through the substrate. A first RDL is formed on a first surface of the substrate in electrical contact with the conductive via and the first semiconductor die. A second RDL is formed on a second surface of the substrate opposite the first surface of the substrate die in electrical contact with the conductive via. A second semiconductor die can be mounted on the substrate and electrically connected to the second RDL. Bonding pads are formed over the first and second surfaces of the substrate in electrical contact with the first and second RDLs, respectively. The bonding pads on opposite surfaces of the substrate are aligned. Solder bumps or bond wires can be formed on the bonding pads. The semiconductor packages can be stacked and electrically connected through the aligned bonding pads. | 06-11-2009 |
| 20090146283 | STACKED-TYPE CHIP PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A stacked-type chip package structure in which stacked chips and stacked flexible circuit boards are disposed on a substrate. A plurality of spacer layers is respectively sandwiched between two adjacent chips and stacked on top of each other. In addition, conductive bumps are disposed on the substrate and between the stacked flexible circuit boards, such that the stacked flexible circuit boards are electrically connected to the substrate. Besides, conductive wires are electrically connected between the flexible circuit boards and the chips, so as to form a package structure with multi-layer chips on the substrate. Thereby, electrical performance and reliability of the chips are improved. | 06-11-2009 |
| 20090146284 | Molded Leadless Packages and Assemblies Having Stacked Molded Leadless Packages - Molded leadless packages having improved stacked structures are disclosed. An exemplary molded leadless package includes a die attaching pad, a plurality of leads spaced apart from the die attaching pad at a periphery region of the die attaching pad, a semiconductor chip on the die attaching pad, a plurality of bonding wires electrically connecting the leads to the semiconductor chip, and a sealing member fixedly enclosing the semiconductor chip and the bonding wires while partly exposing an outer surface of each of the leads. The sealing member fills gaps between the die attaching pad and the leads and includes at least one protrusion protruding downward from the die attaching pad and the leads. | 06-11-2009 |
| 20090146285 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - The present invention provides a semiconductor package and a fabrication method thereof. The method includes the steps of: providing a chip carrier module having a plurality of chip carriers, disposing a plurality of electrical connecting points on the chip carriers, performing chip mounting and molding on the chip carrier module to form an encapsulant encapsulating the semiconductor chip, exposing the electrical connecting points from the encapsulant; forming a patterned circuit layer on the encapsulant, electrically connecting the patterned circuit layer to the electrical connecting points, cutting and separating the chip carriers to form a plurality of semiconductor packages each having a circuit layer formed on the encapsulant such that the circuit layer provides extra electrical connecting points and thereby enhances electrical performance of electrical products. During a package stacking process, no package is limited by the design of another package below. | 06-11-2009 |
| 20090152700 | MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTABLE INTEGRATED CIRCUIT DIE - A mountable integrated circuit package system includes: mounting an integrated circuit die over a package carrier; connecting a first internal interconnect between the integrated circuit die and the package carrier; and forming a package encapsulation over the package carrier and the first internal interconnect, with the integrated circuit die partially exposed within a recess of the package encapsulation. | 06-18-2009 |
| 20090152701 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE INTEGRATION - An integrated circuit package system comprising: providing a package substrate; attaching a base package having a portion of the base package substantially exposed over the package substrate; forming a cavity through the package substrate to the base package; and attaching a device partially in the cavity and connected to the portion of the base package substantially exposed. | 06-18-2009 |
| 20090152702 | Coupling wire to semiconductor region - A first device has a surface and includes a micrometer-scale or smaller geometry doped semiconductor region extending along the surface. A second device has a surface opposite the surface of the first device and includes a micrometer-scale or smaller wire extending through the second device to a position in proximity to the surface of the second device. The first and second devices are displaceable between first and second positions relative to each other. The wire is not substantially electrically coupled to the doped semiconductor region in the first position and the wire is substantially electrically coupled to the doped semiconductor region in the second position. A potential applied to the wire affects the conductivity of the doped semiconductor region in the second position. | 06-18-2009 |
| 20090152703 | Semiconductor Components Having Through Interconnects And Backside Redistribution Conductors - A semiconductor component includes a semiconductor substrate having a circuit side with integrated circuits and substrate contacts and a back side, a plurality of through interconnects in the substrate, and redistribution conductors on the back side of the substrate. Each through interconnect includes a via aligned with a substrate contact, and a conductive layer at least partially lining the via in physical and electrical contact with the substrate contact. Each redistribution conductor is formed by a portion of the conductive layer. A system includes a supporting substrate and at least one semiconductor substrate having the through interconnects and the redistribution conductors. | 06-18-2009 |
| 20090152704 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER - An integrated circuit packaging system is provided including forming an interposer having a coupling slot, securing an upper die on the interposer, mounting the interposer over an integrated circuit, and coupling the integrated circuit to the upper die through the coupling slot. | 06-18-2009 |
| 20090160042 | Managed Memory Component - A system and method for combining a leaded package IC and a semiconductor die using a flex circuitry. The leaded packaged IC is disposed along an obverse side of a flex circuit. In a preferred embodiment, the lower surface of the body of the leaded packaged IC contacts the surface of the flex circuitry. The semiconductor die is disposed beneath the leaded package IC and, in preferred embodiments, disposed in a window that passes through at least a part of the flex circuitry and is attached to a conductive layer of the flex circuitry. In other embodiments, the semiconductor die is attached to the body of the leaded packaged IC. The flex circuitry preferably employs at least two conductive layers and, in preferred embodiments, the leaded packaged IC is connected to the flex circuitry at one layer while the semiconductor die is connected to the flex circuitry at the other conductive layer. In preferred modules, the leaded packaged IC is preferably a flash memory device and the semiconductor die is preferably a controller. | 06-25-2009 |
| 20090166834 | MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKING INTERPOSER - A mountable integrated circuit package system includes: forming a base integrated circuit package system includes: providing a first substrate, and forming a package encapsulation having a cavity over the first substrate with the first substrate partially exposed within the cavity; and mounting an interposer including a central aperture over the package encapsulation and the first substrate with the central aperture over the cavity. | 07-02-2009 |
| 20090166835 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERPOSER - An integrated circuit package system including: providing a base substrate; coupling a base integrated circuit on the base substrate; forming a double side molded interposer unit over the base integrated circuit including: providing an interposer substrate having an interposer top and an interposer bottom, mounting a first integrated circuit to the interposer bottom and electrically connected thereto, mounting a second integrated circuit to the interposer top and electrically connected thereto, and molding a first chip cover on the first integrated circuit and a second chip cover on the second integrated circuit; and coupling an external component to the double side molded interposer unit. | 07-02-2009 |
| 20090166836 | STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE - A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads. | 07-02-2009 |
| 20090166837 | COMBINATION OF CHIP PACKAGE UNITS - A combination includes a first chip package unit and a second chip package unit on which the first chip package unit is placed. Each of the first and second chip package units includes a substrate having a first surface, a second surface, a chip package electrically connected to the first surface, and a plurality of bonding pads formed on the first and second surfaces. The bonding pads on the first surface of the first chip package unit are respectively electrically connected with the bonding pads on the surface of the second chip package unit. The chip packages electrically connected to the first surfaces are enclosed by the substrates, and the bonding pads on the second surfaces are configured as interface terminals of the combination. | 07-02-2009 |
| 20090166838 | LAMINATED MOUNTING STRUCTURE AND MEMORY CARD - To provide a stacked mounting structure in which the number of semiconductor chips that can be stacked is greater than conventionally, as well as a method for fabricating the same, each semiconductor chip has electrodes provided at least at one end in the stacked mounting structure, and a board holding the semiconductor chips at the one end is folded with at least two of the semiconductor chips being stacked so as to at least partially overlap with each other. | 07-02-2009 |
| 20090166839 | SEMICONDUCTOR STACK DEVICE AND MOUNTING METHOD - A semiconductor stack device having semiconductor chips stacked therein, wherein pads | 07-02-2009 |
| 20090166840 | WAFER-LEVEL STACK PACKAGE - A wafer-level stack package includes semiconductor chips, first connection members, a second connection member, a substrate and an external connection terminal. The semiconductor chips have a power/ground pad and a signal pad. The first connection members are electrically connected to the power/ground pad and the signal pad of each of the semiconductor chips. The second connection member is electrically connected to at least one of the power/ground pads of each of the semiconductor chips, the power/ground pads being connected to the first connection members. The substrate supports the stacked semiconductor chips, the substrate including wirings that are electrically connected to the first connection members and the second connection member. The external connection terminal is provided on a surface of the substrate opposite to a surface where the semiconductor chips are stacked, wherein the external connection terminals are electrically connected to the wirings, respectively. | 07-02-2009 |
| 20090174051 | Semiconductor package and semiconductor device - A package structure which aims at improvement in function, miniaturization, and systematization of a semiconductor integrated circuit having been made into multichip is offered. | 07-09-2009 |
| 20090179318 | MULTI-CHANNEL STACKABLE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME, AND STACKING SUBSTRATE APPLIED TO THE SEMICONDUCTOR DEVICE - A multi-channel stackable semiconductor device and a method for fabricating the same, and a stacking substrate applied to the semiconductor device are provided. A plurality of stacking substrates and package members having known good dies are provided. Each stacking substrate includes a first surface, an opposite second surface, a plurality of electrical bond pads and ball pads formed on the first surface, and a plurality of electrical terminals formed on the second surface. The ball pads are electrically connected to the electrical terminals by conductive structures formed in the stacking substrate. A plurality of corresponding connection paths are provided between at least one of the electrical bond pads and at least some of the ball pads, so as to allow each of the electrical bond pads to be selectively electrically connected to the ball pads. A package member is mounted on and electrically connected to each stacking substrate. | 07-16-2009 |
| 20090179319 | STACKED SEMICONDUCTOR PACKAGE ASSEMBLY HAVING HOLLOWED SUBSTRATE - A stackable package substrate has an opening shaped and dimensioned to accommodate but not contact a mold cap of a package upon which the stackable package is to be mounted. On the die attach surface, the frame substrate accommodates a die attach margin adjacent at the edge of the opening; and a row of wire bond sites arranged along at an outer frame edge, for electrical interconnection. The frame substrate accommodates z-interconnect ball pads arranged to align with corresponding z-interconnect pads on the substrate of a package. A stackable package has a frame substrate. A stacked package assembly includes a second package mounted on a first package using peripheral solder ball z-interconnect, in which the first package includes a die enclosed by a mold cap and in which the second package includes one die mounted on the frame substrate. | 07-16-2009 |
| 20090184409 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CHIPS WITH DIFFERENT THICKNESS - In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip. | 07-23-2009 |
| 20090189266 | SEMICONDUCTOR PACKAGE WITH STACKED DICE FOR A BUCK CONVERTER - Disclosed in this specification is a buck converter package with stacked dice and a process for forming a buck converter. The package includes a die attach pad with a low side die mounted on one surface and a high side die mounted on the opposing surface. The die attach pad is conductive, such that the drain of the low side die is connected to the source of the high side die through the pad. A controller die controls the gates of the high and low side dies. A plurality of leads extends outside of the package to permit electrical connections to the inside of the package. The high side drain is exposed to one of the surfaces of the package. | 07-30-2009 |
| 20090189267 | SEMICONDUCTOR CHIP WITH CHIP SELECTION STRUCTURE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip with a chip selection structure suitable for a stacked semiconductor chip includes a semiconductor chip body and a chip selection structure. The chip selection structure includes a chip selection pad disposed over the semiconductor chip body, a main through electrode electrically connected to the chip selection pad, and a sub through electrode interposed between the main through electrode and the chip selection pad. A plurality of the semiconductor chips, each having the same chip selection structure, can be stacked by offsetting the stacked semiconductor chips. | 07-30-2009 |
| 20090189268 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Of three chips ( | 07-30-2009 |
| 20090200652 | METHOD FOR STACKING CHIPS IN A MULTI-CHIP PACKAGE - A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip. | 08-13-2009 |
| 20090200653 | MEMORY MODULES AND SYSTEMS INCLUDING THE SAME - Provided is a memory module. The memory module may include a mounting substrate including a plurality of first substrate pads disposed on a top surface of the mounting substrate, a first semiconductor package disposed on a top surface of the mounting substrate, the first semiconductor package having a first frame and first external connection terminals which extend through the outside of the first frame and are disposed on the first substrate pads, a first connection member including first connection terminals disposed between the first external connection terminals and the first substrate pads and a pressure fixing member compressing the first connection member to electrically connect the first external connection terminals and the first substrate pads by the medium of the first connection terminals. | 08-13-2009 |
| 20090206460 | Intermediate Bond Pad for Stacked Semiconductor Chip Package - The invention provides apparatus and methods by which, in a stacked semiconductor chip package, a continuous electrical path may be provided among bond pads by way of one or more intermediate bond pad electrically isolated from its underlying surface. | 08-20-2009 |
| 20090206461 | INTEGRATED CIRCUIT AND METHOD - An integrated circuit and method of fabricating an integrated circuit. One embodiment includes a circuit chip, a contact pad, and a projecting top contact. A signal line couples the contact pad to the projecting top contact, the contact pad, the projecting top contact. The signal line is arranged on a top face of the circuit chip. A substrate and a lower contact pad, the lower contact pad is arranged on a bottom face of the substrate and the circuit chip is arranged on a top face of the substrate. A bottom face of the circuit chip is facing the top face of the substrate. A connection couples the contact pad on the circuit chip to the lower contact pad. | 08-20-2009 |
| 20090206462 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device | 08-20-2009 |
| 20090206463 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC EQUIPMENT USING THE SAME - A semiconductor device includes a substrate | 08-20-2009 |
| 20090206464 | METHOD OF FORMING SEMICONDUCTOR CHIPS, THE SEMICONDUCTOR CHIPS SO FORMED AND CHIP-STACK PACKAGE HAVING THE SAME - Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate. | 08-20-2009 |
| 20090212407 | Infinitely Stackable Interconnect Device and Method - An infinitely stackable interconnect device and method having the capability for electrical, thermal, optical, and fluidic interconnections to various layers. Through-substrate vias in the interconnect device are filled to enable electrical and thermal connection or optionally hermetically sealed relative to other surfaces to enable fluidic or optical connection. Optionally, optical components may be placed within the via region in order to manipulate optical signals. Redistribution of electrical interconnection is accomplished on both top and bottom surfaces of the substrate of the interconnect chip. The method for fabricating the interconnect device includes the steps of: forming, insulating, and at least partially filling vias with conductive material; connecting vias to conductive traces on a top surface of the interconnect chip; connecting vias to conductive traces on a bottom surface of the interconnect chip; providing bump regions for electrical and mechanical interconnection to a subsequent interconnect device; and forming recessed regions to accommodate a subsequent die in a stack. The method simultaneously accomplishes interconnection and packaging of multiple semiconductor die to form a stack. | 08-27-2009 |
| 20090212408 | INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES - An integrated circuit package system comprising: providing a package die; and connecting a connector lead having a first connector end with a protruded connection surface and a lowered structure over the package die. | 08-27-2009 |
| 20090212409 | Stackable Semiconductor Package and Stack Method Thereof - A stackable semiconductor package is disclosed. In the stackable semiconductor package, land grid array (LGA) or ball grid array (BGA) semiconductor packages are stacked in the vertical direction. The stackable semiconductor package comprises: a first semiconductor package including a first substrate, at least one first semiconductor die mounted on the first substrate to be electrically connected to the first substrate, and a first encapsulant molded on the first substrate to surround the first semiconductor die; a second semiconductor package including a second substrate, at least one second semiconductor die mounted on the second substrate to be electrically connected to the second substrate, and a second encapsulant molded on the second substrate to surround the second semiconductor die; and one or more interposers positioned between the first and second semiconductor packages to electrically connect the first substrate to the second substrate so that the first and second semiconductor packages are stacked in the vertical direction. Further disclosed is stack method of semiconductor package. | 08-27-2009 |
| 20090212410 | STACK DIE PACKAGES - An integrated circuit package includes a substrate comprising a first contact. A first integrated circuit mechanically attached to the substrate. The first integrated circuit comprising a second contact. A first redistribution layer arranged on the first integrated circuit. The first redistribution layer includes a trace coupled to the second contact. A first wire connects the first contact to the second contact. A flip-chip integrated circuit comprises a third contact connected to the trace by a conductive bump. A second integrated circuit mechanically coupled to the flip-chip integrated circuit. The second integrated circuit comprises a fourth contact. A second wire connects the fourth contact to at least the second contact or the first contact. | 08-27-2009 |
| 20090218669 | MULTI-CHIP PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A method of fabricating a multi-chip package structure is provided. In the method, a number of cavities are formed on a predetermined cutting line of a first wafer by partly removing the first wafer and a first metal layer. Conductive walls of a first circuit layer are electrically connected to a cut cross-section of the first metal layer exposed by the cavities. In addition, conductive bumps of a second wafer are pressed into a cover layer and electrically connected to the first circuit layer. The first metal layer is then patterned to form a second circuit layer having a number of second pads. Next, the first wafer and the second wafer are cut along the predetermined cutting line to form a number of separated multi-chip package structures. | 09-03-2009 |
| 20090218670 | STORAGE MEDIUM AND SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip formed with a non-volatile semiconductor memory, a resin encapsulation that encapsulates the semiconductor chip, electrodes in a lattice (solder balls) formed and arrayed in a lattice on a bottom surface of the resin encapsulation. The solder balls include a signal electrode formed within the central region of the array and a dummy electrode formed outside the signal electrode. | 09-03-2009 |
| 20090218671 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In a semiconductor device of the present invention, semiconductor chips are stacked in multi-layers. Each of the semiconductor chip includes: through vias extending through a top main surface thereof to a bottom surface opposite to the top main surface; a circuit element surface formed on the top main surface; pads arranged on the circuit element surface; bumps formed on the pads; and via pads, formed on the bottom surface thereof, to which the bumps of its upper semiconductor chip are joined, and positions at which the bumps of each of the semiconductor chips are respectively arranged are different from those at which the bumps of its upper semiconductor chip are arranged. | 09-03-2009 |
| 20090224388 | SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT - A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality. | 09-10-2009 |
| 20090224389 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED DEVICES - An integrated circuit package system comprising: providing an integrated circuit die having an active side; forming a first internal stacked module and a second internal stacked module over the active side of the integrated circuit die; and coupling an electrical interconnect between the first internal stacked module or the second internal stacked module and the active side. | 09-10-2009 |
| 20090230532 | SYSTEM FOR SOLDER BALL INNER STACKING MODULE CONNECTION - An integrated circuit package-in-package system including: providing a substrate; mounting a structure over the substrate; supporting an inner stacking module cantilevered over the substrate by an electrical interconnect connected to the substrate, the electrical interconnect forming a gap between the inner stacking module and the structure controlled by the size of the electrical interconnect; and encapsulating the structure and inner stacking module with an encapsulation. | 09-17-2009 |
| 20090230533 | MANUFACTURING STACKED SEMICONDUCTOR DEVICE - A method in accordance with an embodiment of the invention can include forming fan-out wirings on an insulating layer formed on a wafer. Additionally, electrodes of a plurality of semiconductor chips stacked on the fan-out wirings can be electrically coupled with the fan-out wirings. The wafer can be removed. | 09-17-2009 |
| 20090230534 | SEMICONDUCTOR MEMORY APPARATUS - The semiconductor memory apparatus related to an embodiment of the present invention includes a wiring substrate arranged with a device mounting part and connection pads aligned along one exterior side of the wiring substrate, a plurality of semiconductor memory devices including electrode pads which are arranged along one external side of the wiring substrate, a semiconductor memory device group in which the plurality of semiconductor memory devices are stacked on the device mounting part of the wiring substrate so that pad arrangement sides all face in the same direction, and a controller device including the electrode pads arranged along at least one external side of the wiring substrate, wherein the electrode pads of the plurality of semiconductor memory devices and the electrode pads of the controller device are arranged parallel to an arrangement position of the connection pads of the wiring substrate. | 09-17-2009 |
| 20090236718 | PACKAGE-ON-PACKAGE SYSTEM WITH INTERNAL STACKING MODULE INTERPOSER - A package-on-package system includes: forming a first integrated circuit package including second top electrical contacts and first external electrical contacts on opposite sides thereof; forming an internal stacking module interposer including first top electrical contacts and base electrical connectors on opposite sides thereof; attaching the internal stacking module interposer to the first integrated circuit package with the first top electrical contacts connected to the second top electrical contacts; and molding a package encapsulant over the first integrated circuit package and around the internal stacking module interposer leaving a package encapsulant cavity for attaching a stacked package to the base electrical connectors. | 09-24-2009 |
| 20090236719 | PACKAGE IN PACKAGE SYSTEM INCORPORATING AN INTERNAL STIFFENER COMPONENT - The present invention is a package-in-package system, comprising: providing a bottom internal stacking module incorporating a semiconductor die and a package substrate, attaching an internal stiffening module with a die receptacle on the bottom internal stacking module, and attaching a top internal stacking module incorporating a semiconductor die and a package substrate upside-down on the internal stiffening module. | 09-24-2009 |
| 20090236720 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STEP MOLD RECESS - An integrated circuit package system includes: providing a stackable integrated circuit package system having a base encapsulation and a recess therein; stacking a top integrated circuit package system, having a top encapsulation with a protruding portion, with the stackable integrated circuit package system with the protruding portion aligned and matched within the recess; and connecting the top integrated circuit package system and the stackable integrated circuit package system. | 09-24-2009 |
| 20090236721 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device in accordance with one embodiment of the invention can include a substrate onto which a wiring pattern is formed. In addition, the semiconductor device can include a plurality of semiconductor packages. Each semiconductor package can include a lead frame that is coupled to an electrode of a semiconductor chip. Each lead frame can be located on a side surface and a bottom surface of the semiconductor package. In addition, the semiconductor device can include a pressure-contact section for receiving the plurality of semiconductor packages and for causing the plurality of semiconductor packages to come into contact with the wiring pattern. | 09-24-2009 |
| 20090236722 | SEMICONDUCTOR MEMORY CARD AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory card includes a wiring board having an outer shape where a cut-out portion is provided at a first long-edge. A second surface of the wiring board includes connection pads disposed along a portion except the cut-out portion of the first long-edge. A memory device is mounted on the second surface of the wiring board. The memory device includes electrode pads arranged along a long-edge positioning in a vicinity of the first long-edge of the wiring board, and one-sidedly disposed so as to correspond to disposed positions of the connection pads. A controller device is stacked on the memory device. | 09-24-2009 |
| 20090236723 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-IN-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package substrate, having a component side and a system side; mounting a first integrated circuit die on the component side of the package substrate; mounting a second integrated circuit die on the component side of the package substrate; mounting an internal package, having an internal die, over the first integrated circuit die; coupling chip interconnects between the first integrated circuit die, the second integrated circuit die, the internal die, the component side, or a combination thereof, and forming a stacked package body by encapsulating the component side, the first integrated circuit die, the second integrated circuit die, the internal package, and the chip interconnects. | 09-24-2009 |
| 20090243065 | Semiconductor Device and Method for Manufacturing Semiconductor Device - A semiconductor device ( | 10-01-2009 |
| 20090243066 | MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EXPOSED EXTERNAL INTERCONNECTS - The present invention provides a mountable integrated circuit package system comprising: providing an inner integrated circuit package including a first external interconnect having a shoulder; connecting an intraconnect between a second external interconnect and the shoulder; and forming an outer encapsulation over the inner integrated circuit package, the intraconnect, and partially exposing the first external interconnect on a top encapsulation side of the outer encapsulation and the second external interconnect on a bottom encapsulation side of the outer encapsulation. | 10-01-2009 |
| 20090243067 | MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUBSTRATE - A mountable integrated circuit package system includes: providing a substrate having an opening provided therein; providing an encapsulated integrated circuit package having an external leadfinger; mounting the encapsulated integrated circuit package by the external leadfinger proximate to the opening in the substrate; and connecting the external leadfinger and the substrate. | 10-01-2009 |
| 20090243068 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NON-SYMMETRICAL SUPPORT STRUCTURES - An integrated circuit package system including: providing a substrate with a wire-bonded die mounted thereover; mounting a first support structure and a second support structure of different size above the substrate; mounting a structure above the first support structure and the second support structure; and encapsulating the wire-bonded die, the first support structure and the second support structure with an encapsulation. | 10-01-2009 |
| 20090243069 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION - An integrated circuit package system comprising: forming a base package having a molded top; providing a surface contact on the base package; and patterning a redistribution layer on the molded top for coupling the surface contact. | 10-01-2009 |
| 20090243070 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORT STRUCTURE UNDER WIRE-IN-FILM ADHESIVE - An integrated circuit package in package system including: providing a substrate; mounting a wire bonded die with an active side over the substrate; connecting the active side to the substrate with bond wires; mounting a structure over the wire bonded die having a wire-in-film adhesive between the structure and the wire bonded die and overhangs at ends of the structure between the wire-in-film adhesive and the substrate; mounting support structures at the overhangs between the wire-in-film adhesive and the substrate; and encapsulating the wire bonded die and the structure with an encapsulation. | 10-01-2009 |
| 20090243071 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKING MODULE - An integrated circuit package system comprising: providing a module lead array; attaching a module integrated circuit adjacent the module lead array; attaching a module substrate over the module integrated circuit; and applying a module encapsulant over the module integrated circuit wherein the module lead array and the module substrate are partially exposed. | 10-01-2009 |
| 20090243072 | STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM - A stacked integrated circuit package system includes: providing a base integrated circuit package, and mounting a top integrated circuit package having a top interposer and a top encapsulation with a cavity therein or the cavity as a space between top intra-stack interconnects and the top interposer, with the top interposer exposed by the cavity, over the base integrated circuit package. | 10-01-2009 |
| 20090243073 | STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM - A stacked integrated circuit package system includes: providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; mounting an intermediate integrated circuit package over the base interposer, and mounting a top integrated circuit package over the intermediate integrated circuit package. | 10-01-2009 |
| 20090243074 | SEMICONDUCTOR THROUGH SILICON VIAS OF VARIABLE SIZE AND METHOD OF FORMATION - A through-silicon via structure is formed by providing a substrate having a first conductive catch pad and a second conductive catch pad formed thereon. The substrate is secured to a wafer carrier. A first etch of a first type is performed on the substrate underlying each of the first and second conductive catch pads to form a first partial through-substrate via of a first diameter underlying the first conductive catch pad and a second partial through-substrate via underlying the second conductive catch pad of a second diameter that differs from the first diameter. A second etch of a second type that differs from the first type is performed to continue etching the first partial through-substrate to form equal depth first and second through-substrate vias respectively to the first and second conductive catch pads. | 10-01-2009 |
| 20090243075 | MOUNTING STRUCTURE OF SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS USING SAME - A mounting structure comprises: at least one semiconductor device having solder bumps as outer terminals and a flexible wiring board with wiring formed thereon. The semiconductor device is structured to be wrapped by the flexible wiring board, the mounting structure is provided with outer electrodes on both sides of the flexible wiring board, one side being a side where outer terminals of the semiconductor device are formed, and the other side being an opposite side thereof. At least one wiring layer is formed on the flexible wiring board. A supporting member is provided covering side faces and a surface of the semiconductor device opposite to the side where the outer terminals are formed and protruding from the side faces of the semiconductor device and extending toward the surface on which the outer terminals are formed. | 10-01-2009 |
| 20090243076 | ELECTRONIC SYSTEM MODULES AND METHOD OF FABRICATION - This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths of 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is used to fabricate the interconnection circuits. A polymer base layer is formed on a glass carrier with an intermediate release layer. Alternate layers of metal and dielectric are formed on the base layer, and patterned to create an array of multi-layer interconnection circuits on the glass panel. A thick layer of polymer is deposited on the interconnection circuit, and openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings to form wells filled with solder. After dicing the glass carrier to form separated interconnection circuits, IC chips are stud bumped and assembled using flip chip bonding, wherein the stud bumps on the components are inserted into corresponding wells on the interconnection circuits. The IC chips are tested and reworked to form tested circuit assemblies. Methods for connecting to testers and to other modules and electronic systems are described. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server embodiment is also described. | 10-01-2009 |
| 20090250800 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device is provided that includes a semiconductor chip and a resin section that molds the semiconductor chip and has a first through-hole. A through electrode that is electrically coupled to the semiconductor chip, extends through the resin section, and extends between a top edge and a bottom edge of an inner surface of the first through-hole. A cavity which extends between planes corresponding to an upper surface and a lower surface of the resin section is formed inside the first through-hole. | 10-08-2009 |
| 20090250801 | Semiconductor device - A semiconductor device in which a plurality of semiconductor elements are stacked, yet realizing high speed operation of the semiconductor elements. The semiconductor device is provided with semiconductor packages, and a spacer. The semiconductor packages are stacked, with the spacer interposed therebetween. The semiconductor packages have, respectively, package boards, and semiconductor elements mounted on the package boards. The spacer has a plurality of conductive vias and a capacitor element. The semiconductor packages are electrically connected through the conductive vias. The capacitor element is electrically connected, among the conductive vias, to a conductive via that electrically connects the semiconductor element and power supply, and a conductive via that electrically connects the semiconductor element and ground. | 10-08-2009 |
| 20090256248 | CONFIGURATION TERMINAL FOR INTEGRATED DEVICES AND METHOD FOR CONFIGURING AN INTEGRATED DEVICE - A configuration terminal for integrated devices includes a first and a second portion structurally independent and connected to respective first and second terminals and it has at least one contact terminal suitable to be selectively connected to such first and second terminals. Also a method configures an integrated device that includes a plurality of address pads and respective supply pins. The method includes: realizing at least one configuration terminal having a first and a second portion structurally independent and connected to at least one contact terminal; providing the contact of such first and second portions with respective terminals; and configuring the device by a short-circuiting of the contact terminal with at least one of said terminals. | 10-15-2009 |
| 20090256249 | STACKED, INTERCONNECTED SEMICONDUCTOR PACKAGE - An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages. | 10-15-2009 |
| 20090261465 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A semiconductor device includes a substrate having a substrate wiring, a semiconductor chip provided on the substrate, a first electrical conductor electrically connecting the semiconductor chip and the substrate wiring, and an electrically conductive pad provided on the substrate. The semiconductor device further includes a wiring member electrically connected to the electrically conductive pad and serving as a wiring path different from the substrate wiring. | 10-22-2009 |
| 20090261466 | Semiconductor Device and Method of Forming Vertical Interconnect Structure Using Stud Bumps - A semiconductor device is made by forming a conductive layer over a temporary carrier. The conductive layer includes a wettable pad. A stud bump is formed over the wettable pad. The stud bump can be a stud bump or stacked bumps. A semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the stud bump. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure includes a first IPD and is electrically connected to the stud bump. The carrier is removed. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The second interconnect structure includes a second IPD. The first or second IPD includes a capacitor, resistor, or inductor. The semiconductor devices are stackable and electrically connected through the stud bump. | 10-22-2009 |
| 20090267205 | Zero-reflow TSOP stacking - The present invention mechanically integrates a flexible printed circuit pre-disposed with solder and flux and two or more leaded integrated circuit packages into an assembly that does not require a solder reflow process prior to the reflow cycle to attach the assembly to a printed circuit module. Each IC device includes: (1) a package having a top, a bottom and sides; and (2) external leads that extend out from one or more sides for electrical connectivity to a printed circuit module. Each flexible circuit includes: (1) a multi-segment pattern for each IC connection where there is a segment for: (a) attaching a package lead to the flexible printed circuit; (b) a segment for attaching a preformed piece of solder and flux; (c) a bridge for the solder to flow when heated to the package lead attach segment; (2) solder and flux and (3) adhesive to bond the flexible printed circuit to the packages and bond the packages together. | 10-29-2009 |
| 20090267206 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package includes a circuit board with a number of pads disposed thereon, and a number of package units stacked on the circuit board. Each of the package units includes a substrate, a chip, an anisotropic conductive layer, and a number of conductive elements. The substrate has a first surface facing to the circuit board and a second surface opposite to the first surface, both of the first surface and the second surface have a number of pads disposed thereon. The chip is disposed on the substrate and electrically connected with the substrate. The anisotropic conductive layer is disposed between the substrate and the chip, and is capable of fixing the chip on the substrate. The conductive elements electrically connect the pads on the first surface of the substrate with the pads on the second surface of an adjacent substrate and the pads on the circuit board. | 10-29-2009 |
| 20090267207 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor package having a molding unit that seals bonding wires connected to electrode pads of a semiconductor chip is provided with through electrode units comprising bonding wires embedded therein and penetrating the molding unit. A leading end of the respective through electrode units is exposed from an upper surface of the molding unit and a lower surface of the molding unit. | 10-29-2009 |
| 20090267208 | SEMICONDUCTOR PACKAGE HAVING CHIP SELECTION THROUGH ELECTRODES AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A stacked semiconductor package includes a plurality of stacked semiconductor chips each having a circuit unit, a data pad, and a chip selection pad. The plurality of stacked semiconductor chips also includes a plurality of chip selection through electrodes. The chip selection through electrodes penetrate the chip selection pads and the semiconductor chips, and the chip selection through electrodes receive chip selection signals. The chip selection pad of a semiconductor chip is electrically connected to the chip selection through electrode that receives the chip selection signal for selecting the semiconductor chip. The chip selection pad is electrically insulated from the chip selection through electrodes for receiving the chip selection signal for selecting a different semiconductor chip. | 10-29-2009 |
| 20090267209 | Semiconductor device - At a semiconductor device, an integrated circuit including an optoelectronic conversion device is formed on a front face of a sensor chip. A rewiring layer, which leads from pad electrodes, and post electrodes, on the rewiring layer, are formed on the sensor chip. At least a portion of surroundings of the rewiring layer and the post electrodes is sealed with sealing resin, so as to be open above the integrated circuit face. A light-transmissive substrate is disposed over the sealed sensor chip. Penetrating electrodes, corresponding with positions of the post electrodes disposed on the sensor chip, are formed in the light-transmissive substrate, and external terminals such as solder balls or the like are formed so as to electrically connect with the penetrating electrodes. | 10-29-2009 |
| 20090267210 | INTEGRATED CIRCUIT PACKAGE AND MANUFACTURING METHOD THEREOF - An integrated circuit package and a manufacturing method thereof are provided. The package includes a die pad, a plurality of first and second contact pads, a first die, a second die and a molding compound. The contact pads adjacent to at least one side of the die pad are arranged along an inner row and an outer row with respect to the die pad. The first die is fixed on the first die and electrically connected to the first contact pads by wire-bonding. The second die is fixed on the first die and electrically connected to the second contact pads by wire-bonding. The molding compound covers the second die, the first die, the die pad, the first contact pads and the second contact pads. The bottoms of the die pad, the first contact pads and the second contact pads are exposed at the bottom surface of the molding compound. | 10-29-2009 |
| 20090267211 | WAFER LEVEL PACKAGE AND METHOD OF FABRICATING THE SAME - Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages. | 10-29-2009 |
| 20090273068 | 3-D Integrated Circuit Lateral Heat Dissipation - By filling an air gap between tiers of a stacked IC device with a thermally conductive material, heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal material can be electrically insulating. Through silicon-vias (TSVs) can be constructed at certain locations to assist in heat dissipation away from thermally troubled locations. | 11-05-2009 |
| 20090273069 | LOW PROFILE CHIP SCALE STACKING SYSTEM AND METHOD - The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers. In some preferred embodiments, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In other embodiments, a heat spreader is disposed between the CSP and the flex circuitry thus providing an improved heat transference function without the standardization of the form standard, while still other embodiments lack either a form standard or a heat spreader and may employ, for example, the flex circuitry as a heat transference material. | 11-05-2009 |
| 20090278246 | SEMICONDUCTOR DEVICE - A plurality of LSI chips ( | 11-12-2009 |
| 20090278247 | BONDING PAD SHARING METHOD APPLIED TO MULTI-CHIP MODULE AND APPARATUS THEREOF - A multi-chip module (MCM) includes a first die and a second die. The first die supports a plurality of predetermined functions. The second die is coupled to the first die and comprises at least an option pad configured for a bonding option. The first die performs a predetermined function according to a bonding status of the option pad of the second die. | 11-12-2009 |
| 20090283888 | PACKAGE SYSTEM INCORPORATING A FLIP-CHIP ASSEMBLY - A package system including providing a first semiconductor die; mounting a second semiconductor die on the first semiconductor die using an inter-die interconnect to form a flip-chip assembly; and attaching the flip-chip assembly on a package substrate with a contact pad, a test connection, a z-bond pad, and a die receptacle, with the first semiconductor die in the flip-chip assembly fitting inside the die receptacle. | 11-19-2009 |
| 20090283889 | INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system includes: providing a heat spreader; attaching an upper substrate to the heat spreader, the upper substrate having an upper through-opening provided therein; attaching a top semiconductor die to the heat spreader through the upper through-opening, the top semiconductor die having a top die interconnect to the upper substrate; attaching a base substrate to the upper substrate, the base substrate having a base through-opening provided therein larger than the upper through-opening; and attaching an external interconnect connected to the base substrate. | 11-19-2009 |
| 20090283890 | SEMICONDUCTOR MULTI-PACKAGE MODULE INCLUDING TAPE SUBSTRATE LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE - A single metal layer tape substrate includes a patterned metal layer affixed to a patterned dielectric layer. The dielectric layer is patterned to provide openings exposing lands and bond sites on bond fingers on the land side of the metal layer. The metal layer is patterned to provide circuit traces as appropriate for interconnection with the die (on the die attach side) and with other elements (such as other packages in a multi-package module). Interconnection with a die is made by wire bonding to exposed traces on a die attach side of the metal layer, and bond fingers and lands for access to testing the package are provided on the opposite (land) side of the metal layer. | 11-19-2009 |
| 20090294941 | PACKAGE-ON-PACKAGE SYSTEM WITH HEAT SPREADER - A package-on-package system includes: providing a base substrate; mounting an integrated circuit on the base substrate; positioning a stacking interposer over the integrated circuit; and forming a heat spreader base around the integrated circuit by coupling the base substrate and the stacking interposer to the heat spreader base. | 12-03-2009 |
| 20090294942 | PACKAGE ON PACKAGE USING A BUMP-LESS BUILD UP LAYER (BBUL) PACKAGE - In some embodiments, package on package using a bump-less build up layer (BBUL) package is presented. In this regard, an apparatus is introduced comprising a microelectronic die having an active surface, an inactive surface parallel to said active surface, and at least one side, an encapsulation material adjacent said at least one microelectronic die side, wherein said encapsulation material includes a bottom surface substantially planar to said microelectronic die active surface and a top surface substantially planar to said microelectronic die inactive surface, a through via connection in said encapsulation material extending from said top surface to said bottom surface, a first dielectric material layer disposed on at least a portion of said microelectronic die active surface and said encapsulation material surface, a plurality of build-up layers disposed on said first dielectric material layer, and a plurality of conductive traces disposed on said first dielectric material layer and said build-up layers and in electrical contact with said microelectronic die active surface. Other embodiments are also disclosed and claimed. | 12-03-2009 |
| 20090294943 | Stacked structure of integrated circuits having space elements - A stacked structure of integrated circuits having spacer elements includes a substrate, a spacer element, a lower-layer integrated circuit, an upper-layer integrated circuit, and a molding layer. The substrate includes an upper surface on which the spacer element and the lower-layer integrated circuit are arrayed with each other. The lower-layer integrated circuit includes a solder-pad region and a non-solder-pad region adjacent to the spacer element. The upper-layer integrated circuit is disposed on the spacer element, and covers partly over the non-solder-pad region of the lower-layer integrated circuit. Therefore, the overall height of the stacked structure of integrated circuits can be lowered, making the packaging process simplified, the manufacturing process more stable, and the yield rate of production will be raised. Since the inlet end of the wire is electrically connected to the solder pad of the upper-layer integrated circuit, the height of the packaging can be reduced, and so the whole height of the stacked structure of integrated circuits. | 12-03-2009 |
| 20090294944 | SEMICONDUCTOR DEVICE ASSEMBLY AND METHOD THEREOF - A semiconductor device assembly includes a first semiconductor die, a second semiconductor die, at least one semiconductor package component or another semiconductor die, a first conductive element and a second conductive element. The first semiconductor die includes at least one bonding pad. The second semiconductor die includes a bonding pad module. The first conductive element is coupled between the bonding pad module of the second semiconductor die and the bonding pad of the first semiconductor die, and the second conductive element is coupled between the bonding pad module of the second semiconductor die and the semiconductor package component or the another semiconductor die, wherein the first semiconductor die is coupled to the semiconductor package component or the another semiconductor die via the bonding pad and the bonding pad module and the first and second conductive elements. | 12-03-2009 |
| 20090294945 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - The mounting height of a semiconductor device is reduced. A wiring substrate has an upper surface with multiple bonding leads formed therein and a lower surface with multiple lands formed therein. This wiring substrate is a multilayer wiring substrate and multiple wiring layers and multiple insulating layers are alternately formed on the upper surface side and on the lower surface side of the core material of the wiring substrate. The bonding leads are formed of part of the uppermost wiring layer and the lands are formed of part of the lowermost wiring layer. The insulating layers include second insulating layers containing fiber and resin and third insulating layers smaller in fiber content than the second insulating layers. The second insulating layers are formed on the upper surface side and on the lower surface side of the core material. The third insulating layers are formed on the upper surface side and on the lower surface side of the core material with the second insulating layers in-between. The uppermost wiring layer and the lowermost wiring layer are formed over the third insulating layers. | 12-03-2009 |
| 20090294946 | Package-Borne Selective Enablement Stacking - The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices. In preferred embodiments, the plastic body of one or more leaded packaged ICs bear conductive traces that create circuitry to provide stacking related electrical interconnections between the constituent ICs of a stacked module without the use of separate interposers or carrier structures. Typically, the circuitry is borne by the body of the upper one of the ICs of a two-IC leaded package stack to implement stacking-related connections between the constituent ICs. | 12-03-2009 |
| 20090294947 | CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A chip package structure includes a substrate, a chip, a thermal conductive layer, a plurality of signal contacts, and a molding compound. The substrate includes a plurality of first thermal conductive vias, a connecting circuit, and a plurality of signal vias electrically connected to the connecting circuit, and the substrate has a chip disposing region. The chip is disposed on the chip disposing region of the substrate and electrically connected to the signal vias through the connecting circuit. The thermal conductive layer is disposed over the substrate, connected to the first thermal conductive vias, and located above the chip disposing region. Besides, the thermal conductive layer has first openings exposing the signal vias. The signal contacts are respectively disposed in the first openings and connected to the signal vias. The molding compound encapsulates the chip. | 12-03-2009 |
| 20090294948 | Contrast Interposer Stacking System And Method - The present description provides increased contrast between interposer and leads in a stack embodiment that employs an interposer that extends beyond a boundary or perimeter established by the leads of the constituent IC devices. | 12-03-2009 |
| 20090302448 | Chip Stacked Structure and the Forming Method - A chip package structure is provided, includes a chip that having a plurality of pads and an adhesive layer on the back side; an encapsulated structure is covered around the four sides of the chip to expose the pads, and the through holes is formed within the encapsulated structure; a patterned first protective layer is formed on the portion surface of encapsulated structure, the portion of active surface of the chips, and the pads of the chip and the through holes are to be exposed; a metal layer is formed on the portion surface of the patterned first protective layer and formed to electrically connect the pads and to fill with the through holes; the patterned second protective layer is formed on the patterned first protective layer and the portion of metal layer, and the portion surface of metal layer is to be exposed; a patterned UBM layer is formed on the exposed surface of the metal layer and the portion surface of the patterned second protective layer; and the conductive elements is formed on the patterned UBM layer and electrically connect to the metal layer. | 12-10-2009 |
| 20090302449 | PACKAGED PRODUCTS, INCLUDING STACKED PACKAGE MODULES, AND METHODS OF FORMING SAME - An apparatus and a method for packaging semiconductor devices. The apparatus is a three-dimensional electronic package comprising one or more electronic components, a plurality of electrical contact pads, and a plurality of electrically conductive three-dimensional plugs formed through an encapsulant. Specific ones of the plurality of electrical contact pads are electrically coupled to the one or more electronic components on an uppermost surface of the plurality of electrical contact pads. The encapsulant is formed over and covers the one or more electronic devices. The plurality of three-dimensional plugs have a first end extending from at least the uppermost portion of one or more of the plurality of electrical contact pads and a second end extending substantially to an uppermost surface of the encapsulant. | 12-10-2009 |
| 20090309204 | BALL GRID ARRAY PACKAGE STACKING SYSTEM - A ball grid array package stacking system includes: providing a base substrate; coupling an integrated circuit to the base substrate; coupling a stacking substrate over the base substrate; mounting a heat spreader, having an access port, around the base substrate and the stacking substrate; and coupling a stacked integrated circuit to the stacking substrate through the access port. | 12-17-2009 |
| 20090309205 | Semiconductor chip package and multichip package - The present invention provides a multichip package wherein a plurality of semiconductor chip packages ( | 12-17-2009 |
| 20090309206 | SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING THE SAME - A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package includes a first package that a first semiconductor chip is mounted on a front side of a first substrate and a redistributed pad including a first redistributed pad electrically connected to the first substrate and a second redistributed pad electrically connected to the first redistributed pad is disposed on the first semiconductor chip and a second package that a second semiconductor chip is mounted on a front side of a second substrate, the second package including a connection member electrically connected to the second redistributed pad. The connection member electrically connected to the redistributed pad electrically connects the first and second packages to each other. | 12-17-2009 |
| 20090309207 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIE AND PACKAGE COMBINATION - An integrated package system with die and package combination includes forming a leadframe having internal leads and external leads, encapsulating a first integrated circuit on the leadframe, and encapsulating a second integrated circuit over the first integrated circuit. | 12-17-2009 |
| 20090315166 | STACKED SEMICONDUCTOR DEVICES AND A METHOD FOR FABRICATING THE SAME - The present invention provides a semiconductor device that includes semiconductor packages arranged in a stacked configuration. A plurality of leads are drawn from the stacked semiconductor packages and folded around the outer shape of each semiconductor package such that the leads extend over the upper surfaces of the semiconductor package. Holders affix the stacked semiconductor packages so that first and second leads contact each other, the first leads being drawn from a first one of the stacked semiconductor packages at a lower stacking stage, and the second leads being drawn from a second one of the stacked semiconductor packages at an adjacent, upper stacking stage. | 12-24-2009 |
| 20090315167 | SEMICONDUCTOR DEVICE - A semiconductor device in which a plurality of semiconductor chips is stacked. A first semiconductor chip is stacked in a region, on a second semiconductor chip, in which a circuit that generates noise is not disposed within said second semiconductor chip, and a wire of a circuit that easily receives noise within said first semiconductor chip is disposed so as not to extend over said circuit that generates noise. | 12-24-2009 |
| 20090315168 | THROUGH BOARD STACKING OF MULTIPLE LGA-CONNECTED COMPONENTS - A package design is provided where a chip module is connected to a printed circuit board (PCB) via a land grid array (LGA) on the top surface of the PCB, and where a power supply is connected to the PCB via a second LGA on the bottom surface of the PCB. The stack of the chip module, power supply, and LGA is held in place and compressed with actuation hardware forming an adjustable frame. The package allows field replacibility of either the module, or the PS, and provides the shortest possible wiring distance from the PS to the module leading to higher performance. | 12-24-2009 |
| 20090321907 | STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM - A stacked integrated circuit package system includes: forming a recessed integrated circuit package system having a first encapsulation over a first integrated circuit and an interior cavity in the first encapsulation; forming a mountable integrated circuit package system having a second integrated circuit over a carrier; and mounting the recessed integrated circuit package system over the mountable integrated circuit package system with the second integrated circuit within the interior cavity and the first integrated circuit coupled with the carrier. | 12-31-2009 |
| 20090321908 | STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTRA-STACK ENCAPSULATION - A stacked integrated circuit package system includes: mounting a first integrated circuit over a first carrier; mounting a second integrated circuit package system having a second carrier with an intra-stack interconnect attached thereto and with the intra-stack interconnect over the first carrier and the first integrated circuit; and forming an intra-stack encapsulation between the first carrier and the second carrier surrounding the intra-stack interconnect. | 12-31-2009 |
| 20090321909 | Active Thermal Control for Stacked IC Devices - Thermal conductivity in a stacked IC device can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired. | 12-31-2009 |
| 20090321910 | SEMICONDUCTOR PACKAGE, STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME, AND A METHOD FOR SELECTING ONE SEMICONDUCTOR CHIP IN A STACKED SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip having a circuit section. A first chip selection electrode passes through a first position of the semiconductor chip, and the first chip selection electrode has a first resistance and outputs a first signal. A second chip selection electrode passes through a second position of the semiconductor chip, and the second chip selection electrode has a second resistance greater than the first resistance and outputs a second signal. A signal comparison part is formed in the semiconductor chip and is electrically connected to the first and second chip selection electrodes. The signal comparison part compares the first signal applied from the first chip selection electrode to the second signal applied from the second chip selection electrode and outputs a chip selection signal to the circuit section depending upon the result of the comparison. | 12-31-2009 |
| 20090321911 | Semiconductor Package and Manufacturing Method Thereof - Provided are a semiconductor package and a manufacturing method thereof. A semiconductor package according to an embodiment comprises a chip part on a board, a mold member, and a plated layer on the mold member. The plated layer comprises an electrode pattern connected to a pattern of the board. The electrode pattern of the plated layer can be mounted at least one of at least one a chip part and at least one another semiconductor package. | 12-31-2009 |
| 20090321912 | Semiconductor device and method of manufacturing the same - A semiconductor device includes a substrate, a semiconductor chip, and first and second insulations. The substrate has at least a first region and a second region. The semiconductor chip structure covers the first region. The first insulation covers the second region. The first insulation has a first thermal expansion coefficient approximately equal to that of the semiconductor chip structure. The second insulation covers the semiconductor chip structure and the first insulation so that the semiconductor chip structure and the first insulation are sandwiched between the substrate and the second insulation. The second insulation has a second thermal expansion coefficient approximately equal to that of the substrate. | 12-31-2009 |
| 20100001390 | SYSTEM IN PACKAGE MODULE - A System in Package (SIP) module includes a printed circuit board with at least one cavity formed therein. The module also includes at least one first device mounted in the cavity and a circuit pattern formed on an undersurface of the cavity and electrically connected to the first device. The module further includes at least one second device mounted on a printed circuit board surface corresponding to the undersurface of the cavity. | 01-07-2010 |
| 20100001391 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORTED STACKED DIE - An integrated circuit package system provides a leadframe having a short lead finger, a long lead finger, and a support bar. A first die is placed in the leadframe. An adhesive is attached to the first die, the long lead finger, and the support bar. A second die is offset from the first die. The offset second die is attached to the adhesive. The first die is electrically connected to the short lead finger. The second die is electrically connected to at least the long lead finger or the short lead finger. At least portions of the leadframe, the first die, and the second die are encapsulated in an encapsulant. | 01-07-2010 |
| 20100007000 | PACKAGE STACKING SYSTEM WITH MOLD CONTAMINATION PREVENTION - A package stacking system includes: providing a package substrate; mounting an integrated circuit over the package substrate; forming a step-down interposer over the integrated circuit; and molding a stack package body, having a step profile, on the package substrate and the step-down interposer. | 01-14-2010 |
| 20100007001 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other. | 01-14-2010 |
| 20100007002 | MULTI-LAYER SEMICONDUCTOR PACKAGE - A semiconductor package comprises a base substrate with a semiconductor die mounted on a top side of the base substrate and an interposer substrate mounted on top of the die. The bottom side of the interposer substrate can be electrically coupled to the top side of the base substrate through vertical connectors. The top side of the interposer substrate is substantially exposed and comprises input/output (I/O) terminals for the mounting of additional electronic components. The base and interposer substrates can be configured with I/O terminals such that components mounted on the substrates can be electrically coupled through the vertical connectors. The base substrate also can be electrically coupled to an additional electronic component, such as a printed circuit board. Electrical connections can be āwrapped aroundā from the base substrate to the top of the interposer substrate. The vertical connectors can be positioned along multiple sides of the package. | 01-14-2010 |
| 20100013072 | STACKED PACKAGE AND METHOD FOR FORMING STACKED PACKAGE - The present invention provides an inexpensive semiconductor chip module enabling sufficient heat dissipation without complicating the manufacture process. | 01-21-2010 |
| 20100013073 | APPARATUS AND METHODS FOR CONSTRUCTING SEMICONDUCTOR CHIP PACKAGES WITH SILICON SPACE TRANSFORMER CARRIERS - Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration. | 01-21-2010 |
| 20100013074 | HIGH DENSITY STACKED DIE ASSEMBLIES, STRUCTURES INCORPORATED THEREIN AND METHODS OF FABRICATING THE ASSEMBLIES - A stacked semiconductor die assembly includes at least two partially offset semiconductor dice with bond pads located adjacent at least one peripheral side thereof supported on a redistribution element formed of a material of substantially similar CTE to that of the dice, and a paddle-less lead frame secured to the redistribution element during fabrication, including encapsulation. The assembly is configured to be substantially vertically symmetrical with respect to inner ends of lead fingers of the lead frame to facilitate uniform encapsulant flow. The semiconductor die assembly may be configured in a package with leads extending from two sides thereof, such as a thin small outline package (TSOP), or four sides thereof, such as a quad flat pack (QFP). | 01-21-2010 |
| 20100013075 | STACKED-TYPE SEMICONDUCTOR DEVICE PACKAGE - A stacked-type semiconductor device package is provided. The stacked-type semiconductor device package includes a plurality of stacked semiconductor chip packages with joining electrodes exposed on sides of the semiconductor chip packages and a flexible printed circuit board (flexible PCB) on which the stacked semiconductor chip packages are mounted. The flexible PCB includes a first surface having connecting electrodes corresponding to the joining electrodes of the stacked semiconductor chip packages and a second surface opposite the first surface. The flexible PCB covers the sides of the stacked semiconductor chip packages, and the connecting electrodes of the first surface are connected to the joining electrodes of the stacked semiconductor chip packages. | 01-21-2010 |
| 20100019368 | SEMICONDUCTOR CHIP PACKAGE, STACKED PACKAGE COMPRISING SEMICONDUCTOR CHIPS AND METHODS OF FABRICATING CHIP AND STACKED PACKAGES - A semiconductor chip package includes a substrate having a cavity, a stacked package comprising the semiconductor chip package, and methods of fabricating the chip and the stacked packages. According to an example embodiment, the semiconductor chip package includes a substrate comprising a substrate body having a first main surface, a second main surface, and a cavity that defines an opening in the first main surface, and a layer of electrically conductive material integral with the substrate body. The layer of electrically conductive material constitutes an interconnection pattern of the substrate. The semiconductor chip packages further includes a semiconductor chip disposed within the cavity and mounted to the substrate. The chip includes electrical contacts in the form of pads and the pads face in a direction towards the bottom of the cavity such that the chip has a flip-chip orientation with respect to the substrate. The pads are electrically conductively bonded to respective portions of the interconnection pattern. | 01-28-2010 |
| 20100019369 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFRAME SUBSTRATE - An integrated circuit package system is provided. A dual-type leadframe having first and second rows of leads is formed. A first row of bumps is formed on an integrated circuit chip. Solder paste is placed on the first row of leads, and the first row of bumps is pressed into the solder paste on the first row of leads. The solder paste is reflow soldered to form solder and connect the integrated circuit chip to the first row of leads, and the integrated circuit chip, the first row of bumps, the solder, and the leadframe are encapsulated. | 01-28-2010 |
| 20100025833 | RDL PATTERNING WITH PACKAGE ON PACKAGE SYSTEM - An integrated circuit package system includes: providing an internal device; encapsulating the internal device with an encapsulation having an outer surface; and forming a redistribution line having connection points on the outer surface of the encapsulation. | 02-04-2010 |
| 20100025834 | FAN-IN INTERPOSER ON LEAD FRAME FOR AN INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM - An integrated circuit package on package system includes: providing a lead having a wire-bonded die with a bond wire connected thereto; mounting a fan-in interposer over the wire-bonded die and the bond wire; connecting the fan-in interposer to the lead with the bond wires; and encapsulating the wire-bonded die, bond wires, and the fan-in interposer with an encapsulation leaving a portion of the fan-in interposer exposed. | 02-04-2010 |
| 20100025835 | INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM - An integrated circuit package stacking system includes: forming a flexible substrate by: providing an insulating material, forming a stacking pad on the insulating material, forming a coupling pad on the insulating material, and forming a trace between the stacking pad and the coupling pad; providing a package substrate; coupling an integrated circuit to the package substrate; and applying a conductive adhesive on the package substrate for positioning the flexible substrate over the integrated circuit and coupling the flexible substrate on the conductive adhesive. | 02-04-2010 |
| 20100025836 | MULTI-LAYER PACKAGE-ON-PACKAGE SYSTEM - A package-on-package system includes: providing a bottom package module incorporating a bottom package substrate; attaching a central internal stacking module, incorporating a central interposer, on top of the bottom package module; placing a spacer on the top surface of the central internal stacking module; mounting a first top package module, incorporating a first top interposer with an opening, on the spacer; and enclosing at least portions of the bottom package module, the central internal stacking module, and the first top package module with an encapsulant. | 02-04-2010 |
| 20100025837 | COMPOSITE SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND SPACER SHEET USED IN THE SAME, AND METHOD FOR MANUFACTURING COMPOSITE SEMICONDUCTOR DEVICE - The present invention relates to a complex type semiconductor device formed by laminating plural semiconductor packages, wherein it comprises:
| 02-04-2010 |
| 20100025838 | ELECTRONIC DEVICE PROTECTED AGAINST ELECTRO STATIC DISCHARGE - An embodiment of a method for manufacturing an electronic device realized on a semiconductor substrate and protected against electro static discharge by the provision of supporting means for the electronic device to keep it far from contacts with possible sources of an ESD event during the manufacturing phases. The supporting means are associated with said electronic device in all the manufacturing stages for instance when assembling the device, when picking and placing it in trays a first time, during the burning-in testing phases, when picking and placing it in trays a second time, or when picking and placing it in a scanner. In an embodiment, the supporting means are protective notches associated with the back side of the semiconductor substrate and provided at each edge corner of the semiconductor substrate. | 02-04-2010 |
| 20100032820 | Stacked Memory Module - Memory modules, computing systems, and methods of manufacturing memory modules are disclosed. In one embodiment, a memory module includes a substrate having a first side and a second side opposed to the first side. A plurality of pins is disposed on the first side of the substrate. A first plurality of memory chips are arranged in a first chip layer, the first chip layer overlying the second side of the substrate. Electrical contacts of the first plurality of memory chips are electrically coupled to the pins. A second plurality of memory chips is arranged in a second chip layer, the second chip layer overlying the first chip layer. Electrical contacts of the second plurality of memory chips are electrically coupled to the pins. | 02-11-2010 |
| 20100032821 | TRIPLE TIER PACKAGE ON PACKAGE SYSTEM - An integrated circuit package system includes: providing a first package having a first interposer mounted over a first integrated circuit and the first integrated circuit encapsulated by a first encapsulation; and connecting a second package over the first interposer and on the first encapsulation, the second package including a second integrated circuit having a wire-in-film adhesive thereover, a second interposer mounted on the wire-in-film adhesive and encapsulated by a second encapsulation encapsulating the second integrated circuit, the second interposer including an interconnection pad for connecting a third package to the top thereof. | 02-11-2010 |
| 20100038765 | Semiconductor package and method for manufacturing the same - Provided is a semiconductor package and a method for fabricating the semiconductor package. The semiconductor package may include a first package having a first semiconductor chip mounted on a first substrate and a second package having a second semiconductor chip mounted on a second substrate, the second substrate being bent to cover a side of the first package to contact the first substrate such that the first and second packages are connected electrically. | 02-18-2010 |
| 20100038766 | METHOD FOR FORMING TERMINAL OF STACKED PACKAGE ELEMENT AND METHOD FOR FORMING STACKED PACKAGE - A semiconductor chip module having high degree of freedom in assignment of a circuit to each semiconductor chip and in position of a connection terminal of each semiconductor chip is provided. The present invention relates to a semiconductor chip module in which a plurality of semiconductor chips each provided on the side face thereof with a part of a connection terminal coupled with a circuit pattern formed on the front face, have been stacked and bonded. Connection terminal portions on the side faces of the respective semiconductor chips are interconnected by a wiring pattern. The connection terminal on the semiconductor chip is led from the front face to the side face and formed by applying spraying of a conductive material in a mist state. | 02-18-2010 |
| 20100038767 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes a stacked semiconductor package in which end portions of a plurality of flexible substrates have bonded portions which are connected together by wirings and in which a plurality of semiconductor packages are electrically connected to a mother substrate via the bonded portions. In at least a part of a region of portions of the plurality of flexible substrates that extends from the side surfaces of each of the semiconductor elements, and that is present between side surfaces of each of the semiconductor elements and the bonded portions of the flexible substrates, the plurality of flexible substrates have a curved portion, and the shape of the curved portion of at least one flexible substrate is different from the shape of a curved portion of another flexible substrate adjacent to this flexible substrate. | 02-18-2010 |
| 20100038768 | INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND MANUFACTURING METHOD THEREOF - A stackable multi-chip package system is provided including forming an external interconnect having a base and a tip, connecting a first integrated circuit die and the base, stacking a second integrated circuit die over the first integrated circuit die in an active side to active side configuration, connecting the second integrated circuit die and the base, and molding the first integrated circuit die, the second integrated circuit die, and the external interconnect partially exposed. | 02-18-2010 |
| 20100038769 | WAFER STACKED PACKAGE WAVING BERTICAL HEAT EMISSION PATH AND METHOD OF FABRICATING THE SAME - A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality of semiconductor chips, and sealed; micro holes formed on the circumference of the cooling through-hole; and coolant filling the inside of the cooling through-hole. Accordingly, the WSP reduces a temperature difference between the semiconductor chips and quickly dissipates the heat generated by the stacked semiconductor chips. | 02-18-2010 |
| 20100044846 | THREE-DIMENSIONAL STRUCTURAL SEMICONDUCTOR DEVICE - A semiconductor device of three-dimensional structure in which the operating frequency of a chip can be raised while preventing the chip area from increasing. The three-dimensional structure semiconductor device have a first integrated circuit including a plurality of areas formed on a first conductor layer and a first wiring layer formed on the first conductor layer, a first insulating layer laminated on the first wiring layer, and a second integrated circuit including a plurality of areas formed on a second conductor layer which is laminated on the first insulating layer, and a second wiring layer formed on the second conductor layer. The first integrated circuit and the second integrated circuit are connected electrically by interconnection penetrating in the laminating direction and at least one of bidirectional communication of data, control signal supply, and clock signal supply between the first integrated circuit and the second integrated circuit is carried out through the penetrating interconnection. | 02-25-2010 |
| 20100044847 | SEMICONDUCTOR CHIP INCLUDING A CHIP VIA PLUG PENETRATING A SUBSTRATE, A SEMICONDUCTOR STACK, A SEMICONDUCTOR DEVICE PACKAGE AND AN ELECTRONIC APPARATUS INCLUDING THE SEMICONDUCTOR CHIP - A semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack thereof, a semiconductor device package thereof, and an electronic apparatus having the same are disclosed. The semiconductor chip comprising, a substrate including an inner semiconductor circuit, a conductive redistribution structure formed on the substrate including a conductive redistribution interconnection and a conductive redistribution via plug, wherein the redistribution via plug is connected to the inner semiconductor circuit; a conductive chip pad formed on the substrate, and a conductive chip via plug configured to penetrate the substrate and electrically connected to the redistribution structure. | 02-25-2010 |
| 20100044848 | SOLDER JOINT RELIABILITY IN MICROELECTRONIC PACKAGING - A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni. | 02-25-2010 |
| 20100044849 | STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a stacked integrated circuit package-in-package system includes forming a substrate with a top contact, mounting a first device having a first terminal over the substrate, stacking a second device having a second terminal over the first device in an offset configuration, connecting the first terminal to the top contact below the first terminal, and connecting the second terminal to the top contact below the second terminal. | 02-25-2010 |
| 20100052131 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION LAYER - An integrated circuit package system includes forming a first external interconnect having both a first side and a second side that is an opposing side to the first side; forming a first encapsulation around a first integrated circuit and the first external interconnect with the first side, the second side, and the first active side of the first integrated circuit exposed; forming a planar interconnect between the first active side and the second side; forming a second encapsulation covering the planar interconnect and the first active side; connecting a second integrated circuit over the first integrated circuit and the first side; and forming a top encapsulation over the second integrated circuit. | 03-04-2010 |
| 20100052132 | Semiconductor package - Provided is a semiconductor package including a first substrate including a first substrate pad and a second substrate pad spaced apart from each other, first semiconductor chips stacked on the first substrate and having a first side surface and a second side surface, first chip pads disposed on the first substrate pad and adjacent to the first side surface and provided to the respective first semiconductor chips in the peripheral circuit region and electrically connected to the first substrate pad, and a second semiconductor chip disposed toward the second side surface and including a second chip pad spaced apart from the first chip pad and electrically connected to the second substrate pad, and a heat insulation member provided to the first substrate between the at least one first substrate pad and the at least one second substrate pad. | 03-04-2010 |
| 20100052133 | STACK TYPE SEMICONDUCTOR DEVICE WITH REINFORCING RESIN - A semiconductor device includes a plurality of semiconductor packages each with a semiconductor element and a flexible board. The flexible board is wider than the semiconductor element and is electrically connected to the semiconductor element. The plurality of semiconductor packages are stacked on one surface of a mother board. The semiconductor element is positioned between the flexible boards of the semiconductor packages in adjacent layers. The flexible boards in the adjacent layers are joined together at junction portions positioned at a part of the flexible boards which sticks out from an area in which the semiconductor elements and the flexible boards overlap. A reinforcing resin is provided in at least a part of the area between the flexible boards in the adjacent layers and between the junction portion of the flexible boards and the corresponding semiconductor element. The reinforcing resin contacts at least a part of the adjacent flexible board. | 03-04-2010 |
| 20100052134 | 3-D INTEGRATED SEMICONDUCTOR DEVICE COMPRISING INTERMEDIATE HEAT SPREADING CAPABILITIES - In a three-dimensional chip configuration, a heat spreading material may be positioned between adjacent chips and also between a chip and a carrier substrate, thereby significantly enhancing heat dissipation capability. Furthermore, appropriately sized and positioned through holes in the heat spreading material may enable electrical chip-to-chip connections, while responding thermally conductive connectors may extend to the heat sink without actually contacting the corresponding chips. | 03-04-2010 |
| 20100052135 | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier - A semiconductor device is made by forming a photoresist layer over a metal carrier. A plurality of openings is formed in the photoresist layer extending to the metal carrier. A conductive material is selectively plated in the openings of the photoresist layer using the metal carrier as an electroplating current path to form wettable contact pads. A semiconductor die has bumps formed on its surface. The bumps are directly mounted to the wettable contact pads to align the die with respect to the wettable contact pads. An encapsulant is deposited over the die. The metal carrier is removed. An interconnect structure is formed over the encapsulant and electrically connected to the wettable contact pads. A plurality of conductive vias is formed through the encapsulant and extends to the contact pads. The conductive vias are aligned by the wettable contact pads with respect to the die to reduce interconnect pitch. | 03-04-2010 |
| 20100052136 | Three-Dimensional Package and Method of Making the Same - A package comprises a first unit including a semiconductor body, a hole, an isolation layer, a conductive layer and a solder. The semiconductor body has a first surface having a pad and a protection layer exposing the pad. The hole penetrates the semiconductor body. The isolation layer is disposed on the side wall of the hole. The conductive layer covers the pad, a part of the protection layer, and the isolation layer. The lower end of the conductive layer extends to below a second surface of the semiconductor body. The solder is disposed in the hole, and is electrically connected to the pad via the conductive layer. A second unit similar to the first unit and stacked thereon includes a lower end of a second conductive layer that extends to below a second surface of a second semiconductor body and contacts the upper end of the first solder. | 03-04-2010 |
| 20100059872 | Adhesive Tape, Connected Structure and Semiconductor Package - An adhesive tape | 03-11-2010 |
| 20100059873 | BALL GRID ARRAY PACKAGE STACKING SYSTEM - A ball grid array package stacking system includes: forming a heat spreader having a centrally located access port; mounting a substrate in the heat spreader for providing a connection pad in the centrally located access port; coupling an integrated circuit die to the substrate; and coupling a system interconnect to the integrated circuit die, the connection pad, or a combination thereof. | 03-11-2010 |
| 20100065953 | Semiconductor package - A semiconductor package according to the present invention includes a substrate; first and second semiconductor chips mounted on a first surface of the substrate; and a heat-radiation sheet. The heat-radiation sheet includes a heat-transferable conductive layer and first and second insulating layers formed on top and bottom surfaces of the heat-transferable conductive layer, respectively. The heat-radiation sheet includes a first portion arranged between the first semiconductor chip and the second semiconductor chip; and a second portion extending at least a side of the first portion. The second portion is connected to the substrate. The second insulating layer of the second portion is formed to expose a part of the heat-transferable conductive layer. | 03-18-2010 |
| 20100065954 | BOND PAD STRUCTURES AND SEMICONDUCTOR DEVICES USING THE SAME - A semiconductor device comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a at least one first bond pads formed on a peripheral region of the first semiconductor die, a at least one re-distributed layer (RDL) pads formed on a center region of the first semiconductor die, and a at least one wire routes interconnecting the first bond pads and the RDL pads. The second semiconductor die is disposed over the first semiconductor die, wherein the second semiconductor die has a at least one second bond pads electrically connecting to the RDL pads via bonding wires; wherein the RDL pad is supported by at least a buffer layer. | 03-18-2010 |
| 20100065955 | Integrated Circuit Devices with Stacked Package Interposers - An IC device includes a die and a first package interposer stacked over a second package interposer. The IC device includes a first conductive connection from a first bond pad of the die directly to a bond pad of the first interposer and a second conductive connection from a second bond pad of the die directly to a bond pad of the second interposer. Another IC device includes a second die stacked over a separate first die and a first package interposer stacked over a separate second package interposer. The first die is stacked over the first interposer. A first conductive connection exists from a bond pad of the first die directly to a bond pad of the first interposer and a second conductive connection exists from a bond pad of the second die directly to a bond pad of the second interposer. | 03-18-2010 |
| 20100072596 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING PLANAR INTERCONNECT - An integrated circuit package system includes: mounting an integrated circuit, having a planar interconnect, over a carrier with the planar interconnect at a non-active side of the integrated circuit and an active side of the integrated circuit facing the carrier; connecting the integrated circuit and the carrier; connecting the planar interconnect and the carrier; and forming an encapsulation over the integrated circuit, the carrier, and the planar interconnect. | 03-25-2010 |
| 20100072597 | INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES - An integrated circuit package system provides: forming a stack module including: providing a stack die and encapsulating the stack die with an insulating material having a protruding support and a pad connected to the stack die; mounting the stack module on a package base; connecting the pad to the package base; mounting a top die on the protruding support; connecting the top die to the package base; and encapsulating the top die, the package base, and the stack module with a package encapsulant. | 03-25-2010 |
| 20100072598 | SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip. | 03-25-2010 |
| 20100072599 | Semiconductor Device and Method of Forming a Wafer Level Package with Top and Bottom Solder Bump Interconnection - A semiconductor device is made by forming solder bumps over a copper carrier. Solder capture indentations are formed in the copper carrier to receive the solder bumps. A semiconductor die is mounted to the copper carrier using a die attach adhesive. The semiconductor die has contact pads formed over its active surface. An encapsulant is deposited over the copper carrier, solder bumps, and semiconductor die. A portion of the encapsulant is removed to expose the solder bumps and contact pads. A conductive layer is formed over the encapsulant to connect the solder bumps and contact pads. The conductive layer operates as a redistribution layer to route electrical signals from the solder bumps to the contact pads. The copper carrier is removed. An insulating layer is formed over the conductive layer and encapsulant. A plurality of semiconductor devices can be stacked and electrically connected through the solder bumps. | 03-25-2010 |
| 20100072600 | FINE-PITCH OBLONG SOLDER CONNECTIONS FOR STACKING MULTI-CHIP PACKAGES - A semiconductor PoP device ( | 03-25-2010 |
| 20100072601 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE - A semiconductor device of the present invention comprises a substrate and a first semiconductor element. The substrate comprises an inner layer conductor and a cavity comprising the bottom surface on which a part of the inner layer conductor is exposed. The first semiconductor element contacts, in the cavity, the inner layer conductor directly or via a good heat conductor material. | 03-25-2010 |
| 20100072602 | STACKED INTEGRATED CIRCUIT PACKAGE USING A WINDOW SUBSTRATE - An integrated circuit (IC) package is disclosed. The IC package includes a first substrate having a first surface having first substrate bond pads, a second surface having second substrate bond pads, and an opening that extends from the first surface to the second surface. The IC package further includes a first IC having a first IC surface that includes first bond pads and that is directly attached to the second surface of the first substrate, and a second IC surface. The first bond pads are accessible through the opening. The IC package also includes a second IC having a third IC surface that is directly attached to the second IC surface, and a fourth IC surface that includes second bond pads. At least one of the first bond pads is connected to at least one of the first substrate bond pads using one or more bond wires. At least one of the second bond pads is connected to at least one of the second substrate bond pads using one or more bond wires. The opening has a first side and a second side. The first substrate bond pads are located adjacent to only the first side of the opening. | 03-25-2010 |
| 20100078788 | PACKAGE-ON-PACKAGE ASSEMBLY AND METHOD - A package-on-package (PoP) assembly is provided. The package-on-package (PoP) assembly includes a first integrated circuit package and an anisotropic conductive film (ACF) disposed on a top surface of the first integrated circuit package, wherein the anisotropic conductive film comprises a plurality of conductive particles. The package-on-package (PoP) assembly also includes a second integrated circuit package disposed on a top surface of the anisotropic conductive film. | 04-01-2010 |
| 20100078789 | SEMICONDUCTOR PACKAGE SYSTEM WITH THROUGH SILICON VIA INTERPOSER - A semiconductor package system includes: providing a top package, a through silicon via interposer embedded in the top package; providing a bottom package having a bottom semiconductor die with a top connection adjacent the center active face thereof, a substrate interposer being embedded in the bottom package, the bottom semiconductor die being attached to the substrate interposer; and attaching the top package to the bottom package, the top package having the through silicon via interposer having a via connected to the top connection. | 04-01-2010 |
| 20100078790 | SEMICONDUCTOR DEVICE - In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI | 04-01-2010 |
| 20100078791 | SEMICONDUCTOR PACKAGE HAVING INK-JET TYPE DAM AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a substrate which includes a chip mounting unit disposed on a first surface thereof and a pad forming unit disposed on an outer region of the chip mounting unit. The semiconductor package further includes a plurality of pads disposed on the pad forming unit of the substrate, a semiconductor chip disposed on the chip mounting unit of the substrate, a dam disposed on the first surface of the substrate between the semiconductor chip and the pad forming unit, and wherein the dam separates at least a portion of the pads from the semiconductor chip. In addition, the semiconductor package further includes an underfill material disposed between an active surface of the semiconductor chip and the first surface of the substrate and wherein an upper surface of the dam is rounded due to surface tension. | 04-01-2010 |
| 20100078792 | BOND PAD REROUTING ELEMENT, REROUTED SEMICONDUCTOR DEVICES INCLUDING THE REROUTING ELEMENT, AND ASSEMBLIES INCLUDING THE REROUTED SEMICONDUCTOR DEVICES - A rerouting element for a semiconductor device includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerouting element is to be used. The conductive elements, which communicate with corresponding conductive vias, reroute the bond pad locations to corresponding contact pad locations adjacent to one peripheral edge or two adjacent peripheral edges of the rerouted semiconductor device. The rerouting element is particularly useful for rerouting centrally located bond pads of a semiconductor device, as well as for rerouting the peripheral locations of bond pads of a semiconductor device to one or two adjacent peripheral edges thereof. Methods for designing and using the rerouting element are also disclosed, as are semiconductor device assemblies including one or more rerouting elements. | 04-01-2010 |
| 20100078793 | SEMICONDUCTOR DEVICE ASSEMBLIES, ELECTRONIC DEVICES INCLUDING THE SAME AND ASSEMBLY METHODS - A semiconductor device is formed of two or more dice of similar dimensions and bond pad arrangements, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a high-density low-profile device. A particularly useful application is the formation of stacked mass storage flash memory package. | 04-01-2010 |
| 20100078794 | STACKED DIE SEMICONDUCTOR DEVICE HAVING CIRCUIT TAPE - A stacked die semiconductor package includes a first integrated circuit chip, a first circuit tape coupled to the first integrated circuit chip, a second integrated circuit chip coupled to the first circuit tape, and at least one component coupled to the first circuit tape. The at least one component may include one or more passive components, one or more active components, or a combination of passive and active components. The stacked die semiconductor package can also include a second circuit tape coupled to the second integrated circuit chip and a third integrated circuit chip coupled to the second circuit tape. The stacked die semiconductor package can also include an encapsulant. | 04-01-2010 |
| 20100084753 | MULTI-CHIP PACKAGE - A multi-chip package is presented which includes a substrate, a lower semiconductor, an upper semiconductor chip, metal wires, an encapsulant, and mounting units. The substrate has electrode terminals on an upper surface and ball lands on a lower surface. The lower semiconductor chip is placed face-down on the substrate. The lower semiconductor chip has first bonding pads, first connectors and metal patterns. The upper semiconductor chip is placed face-down type on the back surface of the lower semiconductor chip. The upper semiconductor has second bonding pads and second connectors. The metal wires electrically the lower semiconductor chip to the substrate. The encapsulant seals the substrate, the lower semiconductor chip, the upper semiconductor chip and the metal wires. The mounting units are on the lower surface of the substrate. | 04-08-2010 |
| 20100084754 | Semiconductor package - A semiconductor package which includes a first substrate having a pre-designed pattern formed thereon; a first chip mounted by a flip chip method on one side of the first substrate; a support formed to a predetermined thickness on an edge of the first substrate; an interposer having an edge thereof placed on the support, such that the interposer covers the first substrate and forms a cavity between the interposer and the first substrate, and having a pre-designed pattern formed respectively on both sides thereof; a via penetrating the support and the interposer; a second chip mounted on one side of the interposer facing the first substrate; a second substrate placed on the other side of the interposer with at least one conductive ball positioned in-between; and a third chip mounted on the second substrate. | 04-08-2010 |
| 20100090323 | COMPOSITE TYPE SEMICONDUCTOR DEVICE SPACER SHEET, SEMICONDUCTOR PACKAGE USING THE SAME, COMPOSITE TYPE SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND COMPOSITE TYPE SEMICONDUCTOR DEVICE - The present invention provides a spacer sheet for a complex type semiconductor device provided between the semiconductor packages of a complex type semiconductor device formed by laminating plural semiconductor packages, comprising through holes of an array corresponding to electrodes which can be provided onto a substrate of one semiconductor package and which are formed in order to connect and wire one semiconductor package with the other semiconductor package and a space part corresponding to a principal part of the above one semiconductor package mounted on the substrate or a principal part of the other semiconductor package opposed to the substrate and a production process for a complex type semiconductor device in which the above spacer sheet is used. It further provides a wiring and connecting method by using a spacer sheet which satisfies securing of a distance between connection terminals and a narrow pitch at the same time in a POP type semiconductor package and a complex type semiconductor device of a POP type which is increased in a packaging density by the above wiring and connecting method. | 04-15-2010 |
| 20100090324 | SEMICONDUCTOR PACKAGE HAVING SOLDER BALL WHICH HAS DOUBLE CONNECTION STRUCTURE - A semiconductor package having a solder ball having a double connection structure which reduces a total height of a package on package (POP). The semiconductor package includes a first semiconductor package in which a semiconductor device is mounted on a lower surface of a first substrate, and a through hole is formed in a solder ball pad region of the first substrate, a second semiconductor package in which a semiconductor device is mounted on an upper surface of a second substrate, and a solder ball pad of the second substrate is formed to correspond to the through hole of the first substrate and is mounted on the first substrate, and a common solder ball that is disposed below the first substrate and is connected to the solder ball pad of the second substrate through the through hole. | 04-15-2010 |
| 20100090325 | SEMICONDUCTOR DEVICE - In order to solve a problem of increased noise accompanying increased area of a return path in a stacked package structure, provided is a semiconductor device which is formed in a stacked package such as a PoP package, which realizes low noise without changing a package size. An additional power supply wiring that runs along a signal wiring between an upper PoP and a lower PoP is newly added in the lower PoP of a package having a PoP structure. | 04-15-2010 |
| 20100090326 | Stack package - A stack package may include a substrate having first and second faces opposite each other and an opening formed therein. The first semiconductor chip may be mounted on the first face of the substrate and include a through electrode in the middle region of the first semiconductor chip that is exposed through the opening. The second semiconductor chip may be stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by the through electrode of the first semiconductor chip. The circuit pattern may be formed on the second face of the substrate and include a bonding pad arranged adjacent to the opening and electrically connected to the through electrode of the first semiconductor chip through the opening, an outer connection pad spaced apart from the bonding pad and a connection wiring extending from the opening to the outer connection pad via the bonding pad. | 04-15-2010 |
| 20100090327 | SEMICONDUCTOR DEVICE WITH IMPROVED RESIN CONFIGURATION - A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer. | 04-15-2010 |
| 20100096737 | STACKABLE SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING SUCH ASSEMBLIES - Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die. The method further includes attaching a lead frame to the lateral contacts of the stacked first and second dies. | 04-22-2010 |
| 20100096738 | IC DIE HAVING TSV AND WAFER LEVEL UNDERFILL AND STACKED IC DEVICES COMPRISING A WORKPIECE SOLDER CONNECTED TO THE TSV - A method of forming integrated circuit (IC) die configured for attachment to another die or a package substrate, and stacked IC devices therefrom. At least one IC die having a top semiconductor surface and a bottom surface and at least one through substrate via (TSV) including a tip protruding beyond the bottom surface to a tip length is provided. The tip has an outer dielectric tip liner, and an electrically conductive portion within the outer dielectric tip liner. A compliant layer is applied to the bottom surface of the IC die. The dielectric tip liner is removed from a distal portion of the tip to expose an electrically conductive tip portion. A solder material is deposited on the exposed distal portion of the tip. The solder material is reflowed and coalesced to form a solder bump on the distal portion of the tip. | 04-22-2010 |
| 20100096739 | STACKED SEMICONDUCTOR MODULE - A stacked semiconductor module is made by stacking a second semiconductor device having a second semiconductor chip mounted to the top surface of a second semiconductor substrate above the top surface of a first semiconductor device having a first semiconductor chip mounted to a first semiconductor substrate. The top surface of the first semiconductor substrate is provided with a first connection terminal and the bottom surface of the first semiconductor substrate is provided with an external connection terminal. A region of the bottom surface of the second semiconductor substrate lying opposite to the second semiconductor chip is provided with a second connection terminal. A conductive connecting member connects the first connection terminal to the second connection terminal. | 04-22-2010 |
| 20100096740 | STACKED TYPE CHIP PACKAGE STRUCTURE - A stacked type chip package structure including a backplate, a circuit substrate, a first chip, a second chip, and a conductive film is provided. The backplate comprises a circuit layer. The circuit substrate is disposed on the backplate, and has an upper surface and an opposite lower surface. Besides, the circuit substrate has a receiving hole corresponding to the backplate. The first chip is disposed inside the receiving hole, and the first chip is electrically connected to the circuit substrate through the circuit layer of the backplate. The second chip is disposed above the first chip, and is electrically connected to the circuit substrate. The conductive film is disposed between the first chip and the second chip, wherein the conductive film is electrically connected to a ground of the circuit substrate. | 04-22-2010 |
| 20100096741 | Chip-Stacked Package Structure and Method for Manufacturing the Same - A chip stacked package structure and applications are provided. The chip-stacked package structure includes a main substrate, a baseboard substrate, and a molding compound. The main substrate has a substrate and a first chip. The substrate has a first surface and a second surface opposite to the first surface. The first chip is disposed on the first surface and electrically connected to the substrate via first bumps. The baseboard substrate has a third surface and a fourth surface faced towards the substrate. The baseboard substrate includes a core layer having a plurality of first through holes and a first accommodation space in which the first chip is received. The second chip is disposed on the third surface of the baseboard substrate. The molding compound is used to encapsulate the main substrate, and the baseboard substrate. | 04-22-2010 |
| 20100102426 | Dual face package and method of manufacturing the same - Disclosed herein is a dual face package and a method of manufacturing the same. The dual face package includes a semiconductor substrate including a through-electrode connected to a die pad disposed on one side of the semiconductor substrate, and a lower redistribution layer disposed on another side thereof and connected to the through-electrode, an insulating layer including a post electrode connected to the through-electrode, and an upper redistribution layer disposed on one side thereof and connected to the post electrode, and an adhesive layer disposed on the one side of the semiconductor substrate so as to attach the insulating layer to the semiconductor substrate such that the through-electrode is connected to the post electrode. The dual face package is produced by a simple process and is applicable to a large diameter wafer level package. | 04-29-2010 |
| 20100102427 | SEMICONDUCTOR PACKAGING DEVICE - A semiconductor packaging device is provided. Semiconductor package groups, a side retainer wall, and a filling layer may be located on a base plate. The side retainer wall may be located around the semiconductor package groups. The filling layer may be located between the side retainer wall and the semiconductor package groups. | 04-29-2010 |
| 20100102428 | SEMICONDUCTOR PACKAGE - A semiconductor package that includes a first semiconductor device mounted on a package substrate and includes an inactive surface having a cavity and an active surface opposite to the inactive surface, a second semiconductor device that is disposed on the active surface and electrically connected to the first semiconductor device, and a third semiconductor device that is disposed on the inactive surface in the cavity and electrically connected to the first semiconductor device. The first semiconductor device includes at least one first through electrode electrically connecting the first semiconductor device to the third semiconductor device through the first semiconductor device. | 04-29-2010 |
| 20100109138 | WAFER-LEVEL CHIP-ON-CHIP PACKAGE, PACKAGE ON PACKAGE, AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a multi-chip package in which a plurality of semiconductor chips are mounted on a single package using a chip-on-chip technique reduces warping due to a difference in coefficients of thermal expansion (CTEs) between a printed circuit board (PCB) and a stacked semiconductor chip. A package on package is manufactured by vertically stacking packages to operate a memory semiconductor chip package and a logic semiconductor chip package in a single system. To improve a non-wet defect of solder balls used to connect packages and minimize the mounting height of the package on package, a protection member formed of an epoxy mold compound (EMC) is formed on the memory semiconductor chip package to only partially expose the solder balls, and the exposed portions of the solder balls are connected to vias formed in a rear surface of the logic semiconductor chip package using a solder ball attaching process. | 05-06-2010 |
| 20100109139 | STACK PACKAGE MADE OF CHIP SCALE PACKAGES - A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip scale package face in the opposite direction to those of the lower stacked chip scale package, and the circuit patterns of the upper stacked chip scale package are electrically connected to the those of the lower stacked chip scale package by, for example, connecting boards. Therefore, it is possible to stack not only fan-out type chip scale packages, but to also efficiently stack ordinary area array type chip scale packages. | 05-06-2010 |
| 20100117209 | MULTIPLE CHIPS ON A SEMICONDUCTOR CHIP WITH COOLING MEANS - The present invention is directed to a method of packaging multiple semiconductor chips on a second semiconductor chips with a built-in efficient cooling means. One embodiment is to place two multiple chip stacks on opposing sides of a vapor chamber for transferring heat away from the semiconductor chips. Another embodiment is to construct a vapor chamber with a substrate such that at least one multiple chip stack is embedded inside the vapor chamber. | 05-13-2010 |
| 20100117210 | Semiconductor device - A semiconductor device including: a substrate formed with a concave portion at one surface thereof; and a first semiconductor chip provided in the concave portion of the substrate and is adhered to the substrate by an underfill in the concave portion, wherein the concave portion includes a chip arrangement region in which the first semiconductor chip is arranged, and an adjustment region which protrudes from at least a portion of the periphery of the chip arrangement region when seen in a plan view at a height of at least a portion of a region where the first semiconductor chip is placed in a stacked direction of the substrate, and has different shapes from the chip arrangement region is provided. | 05-13-2010 |
| 20100117211 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit package includes a cover plate disposed on a substrate mounted with an integrated circuit chip thereon. The chip is formed with first solder pads coupled respectively and wiredly to pin terminals on the substrate, and second solder pads coupled respectively and wiredly to pinhole terminals in the cover plate, and includes a main circuit unit, a pin transmission unit interconnecting electrically first ports of a main circuit unit and the first solder pads, a pinhole transmission unit interconnecting electrically second ports of the main circuit unit, and a control unit coupled to the pin and pinhole transmission units, and operable to control operation of the pin and pinhole transmission units such that each first port is coupled to a selected first solder pad through the pin transmission unit and that each second port is coupled to a selected second solder pad through the pinhole transmission unit. | 05-13-2010 |
| 20100117212 | MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING SUCH DEVICES - Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads. | 05-13-2010 |
| 20100123232 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING AN INTERNAL STRUCTURE PROTRUSION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an internal structure substrate having an internal structure substrate cavity; mounting an internal structure die above the internal structure substrate; encapsulating the internal structure die with an internal structure encapsulation to form an internal structure package; forming an internal structure protrusion in the internal structure encapsulation below the internal structure substrate cavity; mounting the internal structure package above a substrate; and encapsulating the internal structure package above the substrate with an encapsulation. | 05-20-2010 |
| 20100123233 | INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF PACKAGE STACKING - A method of manufacturing an integrated circuit package system including: providing a circuit board having an interconnect thereon; mounting a first device offset on the circuit board; and applying a first encapsulant of a first thickness over the first device, the first encapsulant of a second thickness thinner than the first thickness over the remainder of the circuit board with the interconnect exposed, or a second encapsulant of a third thickness over a second device on an opposite surface of the circuit board and differently offset from the first device. | 05-20-2010 |
| 20100123234 | MULTI-CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A multi-chip package includes a carrier, a first chip, a relay circuit substrate, a number of first bonding wires, a number of second bonding wires, a second chip, a number of third bonding wires, and an adhesive layer. The first chip is disposed on the carrier. The relay circuit substrate is disposed on the first chip. The first bonding wires are electrically connected between the first chip and the relay circuit substrate. The second bonding wires are electrically connected between the relay circuit substrate and the carrier. The second chip is disposed on the carrier and is stacked with the first chip. The third bonding wires are electrically connected between the second chip and the carrier. The adhesive layer is adhered between the first chip and the second chip. In addition, a manufacturing method of a multi-chip package is also provided. | 05-20-2010 |
| 20100123235 | PACKAGE ON PACKAGE SUBSTRATE - A package on package substrate is disclosed. The package on package substrate in accordance with an embodiment of the present invention can include a bottom package substrate, on which and an electronic element is mounted and of which an upper surface is formed with a bottom pad part and a solder resist part corresponding to the bottom pad part, and a top package substrate, which is stacked on an upper side of the bottom package substrate by interposing a solder between the top package substrate and the bottom package substrate and of which a lower surface is formed with a top pad part corresponding to the bottom pad part. The solder resist part can include a first solder resist layer, which is formed on the upper surface of the bottom package substrate, corresponding to the bottom pad part, and a second solder resist layer, which is formed on the first solder resist layer such that the bottom pad part is exposed. | 05-20-2010 |
| 20100123236 | SEMICONDUCTOR PACKAGE HAVING ADHESIVE LAYER AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a first substrate comprising a plurality of pads arranged in a first side of the first substrate, a plurality of first semiconductor chips stacked on the first side of the first substrate and each first semiconductor chip comprising a plurality of chip pads arranged in a first side of respective first semiconductor chips, and a sealant arranged on the first substrate, the sealant sealing the first semiconductor chips, wherein at least one of the first semiconductor chips comprises a plurality of redistribution pads arranged in the first side of the at least one semiconductor chip, and a plurality of adhesive layers having portions exposed by the sealant, each adhesive layer is disposed on respective redistribution pads. | 05-20-2010 |
| 20100123237 | Semiconductor package of multi stack type - Provided is a stacked semiconductor package that may include first and second semiconductor packages. The first semiconductor package may include a first package main body and a first lead that includes a first inner lead, a first connection lead, and a first outer lead. The first inner lead may be attached to a bottom part of the first package main body and the first connection lead and the first outer lead may be exposed outside of the first package main body. The second semiconductor package may include a second package main body and a second lead that includes a second inner lead and a second outer lead. The second inner lead may be attached to a bottom part of the second package main body and the second outer lead may be exposed outside of the second package main body. The first and second outer leads may face one another. | 05-20-2010 |
| 20100127373 | Package structure - A package structure includes a first semiconductor package with at least one mount portion recessed from a first surface of the first semiconductor package toward a second surface of the first semiconductor package, the first and second surfaces facing each other. The first semiconductor package at least partially surrounds a second semiconductor package and is spaced apart therefrom via a material layer. | 05-27-2010 |
| 20100133674 | Compact Semiconductor Package with Integrated Bypass Capacitor and Method - A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor dies with the circuit substrate, a first member of the elevation-adaptive interconnection plates has a first flat-top area and a second member of the elevation-adaptive interconnection plates has a second flat-top area in level with the first flat-top area, a bypass capacitor, having two capacitor terminals located at its ends, stacked atop the two interconnection plate members while being bonded thereto via the first flat-top area and the second flat-top area for a reduced interconnection parasitic impedance. | 06-03-2010 |
| 20100133675 | PACKAGE-ON-PACKAGE DEVICE, SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a substrate, a chip, an interposer and a molding compound. The chip is electrically connected to the upper surface of the substrate. The interposer is disposed on the chip, and electrically connected to the upper surface of the substrate. The interposer includes an embedded component and a plurality of electric contacts, wherein the embedded component is located between the upper and lower surfaces of the interposer, and the electric contacts are located on the upper surface of the interposer. The molding compound seals the chip and covers the upper surface of the substrate and the lower surface of the interposer. | 06-03-2010 |
| 20100133676 | A POWER SEMICONDUCTOR ARRANGEMENT AND A SEMICONDUCTOR VALVE PROVIDED THEREWITH - A power semiconductor arrangement including a clamping device including a first clamping element and a second clamping element. A plurality of power semiconductor elements are stacked on each other between the first and second clamping elements of the clamping device. The first clamping element receives a clamping force in an axial direction of the stack of the power semiconductor elements. At least one spring element is arranged between the first clamping element and the power semiconductor elements. The at least one spring element presents at least one support surface with which the at least one spring element bears against at least one corresponding support surface of an adjacent element. The at least one spring element includes a helical spring. A center axis of the at least one spring element coincides with a center of the clamping force, or the at least one spring element includes a plurality of helical springs arranged in parallel with each other, which are arranged symmetrically in relation to a point in which a center of the clamping force is introduced into the first clamping element. | 06-03-2010 |
| 20100133677 | SEMICONDUCTOR CHIP STACKED BODY AND METHOD OF MANUFACTURING THE SAME - A plurality of chip sealing bodies stacked on a wiring substrate with a connection terminal. The chip sealing body includes a semiconductor chip having a semiconductor integrated circuit, a pad and a conductive connecting material, and a resin sealing the semiconductor chip. The chip sealing body is shaped into a cubic form in which a portion of the conductive connecting material except an end portion located on an external device side and all surfaces of semiconductor chip is sealed by the resin and the end portion of the conductive connecting material located on the external device side is exposed from the cubic form. A conductive bonding wire connects the end portions of the conductive connecting materials and the connection terminal respectively. A resin sealing material seals the plurality of chip sealing bodies, the conductive bonding wire, and the wiring substrate. | 06-03-2010 |
| 20100133678 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of semiconductor substrates that are layered; a through electrode penetrating through a predetermined semiconductor substrate of the semiconductor substrates and electrically connected with an external terminal of the semiconductor device; a circuit element provided on the predetermined semiconductor substrate; and an electrostatic discharge protection circuit also provided on the predetermined semiconductor substrate. In the device, wiring resistance between the electrostatic discharge protection circuit and the through electrode is smaller than wiring resistance between the circuit element and the through electrode. | 06-03-2010 |
| 20100140768 | Systems and processes for forming three-dimensional circuits - Provided are systems and processes for forming a three-dimensional circuit on a substrate. A radiation source produces a beam that is directed at a substrate having an isolating layer interposed between circuit layers. The circuit layers communicate with reach other via a seed region exhibiting a crystalline surface. At least one circuit layer has an initial microstructure that exhibits electronic properties unsuitable for forming circuit features therein. After being controllably heat treated, the initial microstructure of the circuit layer having unsuitable properties is transformed into one that exhibits electronic properties suitable for forming circuit feature therein. Also provided are three-dimensional circuit structures optionally formed by the inventive systems and/or processes. | 06-10-2010 |
| 20100140769 | INTEGRATED CIRCUIT PACKAGING SYSTEM USING BOTTOM FLIP CHIP DIE BONDING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate cavity; mounting a bottom flip chip die below the substrate; mounting an internal integrated circuit die above the substrate; filling between the internal integrated circuit die and the substrate and between the bottom flip chip die and the substrate with a substance filling through the substrate cavity; and encapsulating the internal integrated circuit die with an encapsulation. | 06-10-2010 |
| 20100140770 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING ASYMMETRIC ENCAPSULATION STRUCTURES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a first internal integrated circuit structure and a second internal integrated circuit structure over the substrate; connecting the first internal integrated circuit structure and the second internal integrated circuit structure to the substrate with internal interconnects; forming asymmetric encapsulation structures above the first internal integrated circuit structure and the second internal integrated circuit structure; and encapsulating the first internal integrated circuit structure and the internal interconnects with an encapsulation. | 06-10-2010 |
| 20100140771 | Semiconductor Package and Method of Forming Z-Direction Conductive Posts Embedded in Structurally Protective Encapsulant - A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over the base plate of the post carrier and around the conductive posts. A semiconductor die is mounted to a temporary carrier. The post carrier and temporary carrier are pressed together to embed the semiconductor die in the film encapsulant. The semiconductor die is disposed between the conductive posts in the film encapsulant. The temporary carrier and base plate of the post carrier are removed. A first circuit build-up layer is formed over a first side of the film encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. A second circuit build-up layer is formed over a second side of the film encapsulant opposite the first side. The second circuit build-up layer is electrically connected to the conductive posts. | 06-10-2010 |
| 20100140772 | Semiconductor Device and Method of Forming Vertical Interconnect Structure in Substrate for IPD and Baseband Circuit Separated by High-Resistivity Molding Compound - A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of first conductive pillars is formed over the first IPD. A first semiconductor die is mounted over the substrate. An encapsulant is formed around the first conductive pillars and first semiconductor die. A second IPD is formed over the encapsulant. An interconnect structure is formed over the second IPD. The interconnect structure operates as a heat sink. A portion of a back-side of the substrate is removed to expose the first conductive via. A second semiconductor die is mounted to the back-side of the substrate. The second semiconductor die is electrically connected to the first IPD and first semiconductor die through the conductive via. | 06-10-2010 |
| 20100140773 | STACKED CHIP, MICRO-LAYERED LEAD FRAME SEMICONDUCTOR PACKAGE - Semiconductor packages that contain stacked chips on a micro-layered lead frame and methods for making such semiconductor packages are described. The semiconductor packages contain a full array of land pads that has been formed from a lead frame. The packages comprise multiple chips that are stacked vertically and separated by routing leads which are connected to the land pad array. The routing leads can be etched from a metal cladding layer that is provided between each set of stacked chips. Each chip and its routing leads can be encapsulated before the next chip is provided in the package. The semiconductor packages therefore have a high input/output capability with a small package footprint, a flexible routing capability, and a small thickness for multiple chips that are stacked in the package. Other embodiments are also described. | 06-10-2010 |
| 20100140774 | METHOD OF PRODUCING EXTERNAL PADS ON A SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - External electrical connection pads are provided on a semiconductor device. A well is formed in an outer surface for the semiconductor device to at least partially expose an internal electrical connection pad. An electrical connection tab is formed which has an internal branch extending over the internal pad, an external branch extending over a top of the outer surface and extending from one side edge of the well, and a linking branch extending over a sidewall of the wells between the external branch and the internal branch. | 06-10-2010 |
| 20100140775 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided are a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a circuit layer, a metal interconnection layer, and a deep via. The circuit layer is formed on a semiconductor substrate. The metal interconnection layer is formed on the circuit layer. The metal interconnection layer comprises a metal interconnection connected to the circuit layer. The deep via penetrates through the semiconductor substrate and the metal interconnection layer. The deep via comprises a laser-annealed crystalline silicon. | 06-10-2010 |
| 20100140776 | TRIAXIAL THROUGH-CHIP CONNECTON - A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of the annulus trench, etching a via trench into the wafer, making a length of the via trench electrically conductive, thinning a surface of the substrate. | 06-10-2010 |
| 20100140777 | STACKED BALL GRID ARRAY PACKAGE MODULE UTILIZING ONE OR MORE INTERPOSER LAYERS - A multilayer module comprised of stacked IC package layers is disclosed. A plurality of layers preferably having ball grid array I/O are stacked and interconnected using one or more interposer layers for the routing of electronic signals to appropriate locations in the module through angularly depending leads. The stack is further comprised of an interface PCB for the routing of electronics signals to and from the layers in the module and for connection to an external circuit. | 06-10-2010 |
| 20100148335 | SEMICONDUCTOR PACKAGE, METHOD OF MANUFACTURING SAME, SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A highly reliable semiconductor package in which faulty connections do not occur even when an external substrate is curved. The semiconductor package includes a semiconductor chip | 06-17-2010 |
| 20100148336 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING THROUGH SILICON VIAS WITH PARTIAL DEPTH METAL FILL REGIONS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a silicon substrate having a circuitry layer; creating a partial via through the circuitry layer; filling the partial via with a plug having a bottom surface; creating a recess that is angled outward and exposes the bottom surface of the plug; and coating the recess with a recess-insulation-layer while leaving the bottom surface of the plug exposed. | 06-17-2010 |
| 20100148337 | STACKABLE SEMICONDUCTOR PACKAGE AND PROCESS TO MANUFACTURE SAME - In one form a stackable electrical device package has a first plurality of traces, the electrical device bonded to at least some of the first plurality of traces, a second plurality of vertical posts attached to the first plurality of traces, and encapsulation material enclosing the electrical device and sides of the first plurality of traces and the second plurality of vertical posts such that bottoms of the first plurality of traces are exposed on the bottom of the semiconductor package, and tops of the vertical posts are exposed on the top of the semiconductor package. In another form a multiple electrical device package has a semiconductor device in a wafer having a plurality of contacts on an upper surface of the wafer, a first plurality of traces attached to the top of the wafer, a second plurality of vertical posts attached to the first plurality of traces, an electrical device bonded to at least some of the first plurality of traces, and encapsulation material enclosing the electrical device and sides of the first plurality of traces and the second plurality of vertical posts such that tops of the vertical posts are exposed on the top of the semiconductor package. | 06-17-2010 |
| 20100148338 | Three Dimensional Semiconductor Device - A 3D semiconductor device includes a conductive plate defining four sides and four recesses formed in the four sides, respectively. The conductive plate has first and second surfaces opposite to each other. A plurality of conductive leads are located in the recesses, respectively, and the conductive leads have first and second surfaces opposite to each other. A semiconductor die is attached onto the central area of the conductive plate. A plurality of conductive wires electrically connects the semiconductor die to the conductive leads. An encapsulant encloses, as in a capsule, the conductive plate, the conductive leads, the semiconductor die, and the conductive wires in such a manner that the first and second surfaces of the conductive plate and the first and second surfaces of the conductive leads are exposed to the outside. | 06-17-2010 |
| 20100148339 | PROCESS FOR FABRICATING A SEMICONDUCTOR COMPONENT SUPPORT, SUPPORT AND SEMICONDUCTOR DEVICE - An electrical connection support for receiving a semiconductor component includes an electrical connection plate having electrical connection pads. A stand-off structure is provided over the electrical connection pads. The stand-off structure may include a supplementary layer provided on a zone of the electrical connection plate which includes the electrical connection pads of the plate and is outside of a place configured to receive a semiconductor component. The stand-off structure further includes electrical connection vias passing through the supplementary layer. These vias are electrically connected to the electrical connection pads of the plate and have outer faces for making external electrical connection (for example, to another electrical connection support in a stacked structure). | 06-17-2010 |
| 20100148340 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes: (a) half-dicing a semiconductor wafer including plural semiconductor chips, thereby forming dicing grooves in the semiconductor wafer, wherein each semiconductor chip includes a circuit and pads and wherein the semiconductor wafer includes: a first surface on which the circuit and the pads are formed; and a second surface opposite to the first surface, (b) connecting the pads to each other by conductive connectors; (c) sealing the first surface of the semiconductor wafer, the dicing grooves and the conductive connectors with a resin; (d) grinding the second surface of the semiconductor wafer, thereby forming a group of sealed chips; (e) dividing the group of sealed chips into individual sealed chips; (f) mounting and stacking the individual sealed chips on a wiring substrate having connection terminals thereon; and (g) electrically-connecting the conductive connectors and the connection terminals using a conductive member. | 06-17-2010 |
| 20100148341 | Semiconductor device and method for manufacturing the same - A semiconductor device includes: a sensor including a sensor structure on a first side of the sensor and a periphery element surrounding the sensor structure; and a cap covering the sensor structure and having a second side bonded to the first side of the sensor. The cap includes a first wiring layer on the second side of the cap. The first wiring layer steps over the periphery element. The sensor further includes a sensor side connection portion, and the cap further includes a cap side connection portion. The sensor side connection portion is bonded to the cap side connection portion. At least one of the sensor side connection portion and the cap side connection portion provides an eutectic alloy so that the sensor side connection portion and the cap side connection portion are bonded to each other. | 06-17-2010 |
| 20100148342 | STACKED SEMICONDUCTOR MODULE - A stacked semiconductor module is made by stacking a second semiconductor device having a second semiconductor chip mounted to the top surface of a second semiconductor substrate above the top surface of a first semiconductor device having a first semiconductor chip mounted to a first semiconductor substrate. The top surface of the first semiconductor substrate is provided with a first connection terminal and the bottom surface of the first semiconductor substrate is provided with an external connection terminal. A region of the bottom surface of the second semiconductor substrate lying opposite to the second semiconductor chip is provided with a second connection terminal. A conductive connecting member connects the first connection terminal to the second connection terminal. | 06-17-2010 |
| 20100148343 | SIDE STACKING APPARATUS AND METHOD - A module has at least two ICs connected to each other such that they lie in different planes and are arranged as a first stack of ICs, a third IC is connected to at least one of the at least two ICs, wherein the third IC is off plane from both of the at least two ICs. | 06-17-2010 |
| 20100155918 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a stack board with a side having a connect contact next to a connect edge and a top contact next to a top edge perpendicular to the connect edge, and a bottom contact on an opposite side; mounting a circuit assembly having an assembly end next to the connect contact and an edge pad over the stack board; connecting the edge pad with the stack board; and applying an edge encapsulant over the connect contact and over the assembly end with the edge encapsulant extending no more than half the width of the stack board. | 06-24-2010 |
| 20100155919 | High-density multifunctional PoP-type multi-chip package structure - Provided is a high-capacity multifunctional multichip package (MCP) structure in which a multifunctional MCP capable of, for example, high-speed image processing and communications, is mounted on a high-capacity memory package capable of storing various data, e.g., moving images, pictures, or music files. The high-capacity memory package may be efficiently applied to a mass storage of a mobile device. However, an eight-stage-plus chip stacking structure should overcome yield loss during assembly and test processes. To do this, a memory package may be divided into a pair of package to form upper and lower package stacks. To physically connect the pair of packages, molding members may be installed opposite each other and fixed to each other using an adhesive member. Also, to electrically connect the pair of packages, one of the packages may be formed using a flexible PCB substrate capable of bending. The flexible PCB substrate of the one of the packages may be connected to both sides of the other of the packages, and the two packages may be thermally bonded to each other under pressure using solder balls and ball lands. | 06-24-2010 |
| 20100155920 | Stacked semiconductor package, semiconductor package module and method of manufacturing the stacked semiconductor package - Provided are a stacked-type semiconductor package using a stud bump, a semiconductor package module, and a method of fabricating the stacked-type semiconductor package. The stacked-type semiconductor package may include a first semiconductor package and a second semiconductor package stacked on the first semiconductor package. The first semiconductor package may include a first circuit board and at least one conductive member extending upward from the first circuit board. The second semiconductor package may include a second circuit board, and a stud bump being inserted from the second circuit board into the at least one conductive member of the first semiconductor package in order to electrically connect the first semiconductor package and the second semiconductor package. | 06-24-2010 |
| 20100155921 | SEMICONDUCTOR APPARATUS - The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR | 06-24-2010 |
| 20100155922 | Semiconductor Device and Method of Forming Recessed Conductive Vias in Saw Streets - A semiconductor die has an insulating material disposed in a peripheral region around the die. A blind via is formed through the gap. A conductive material is deposited in the blind via to form a conductive via. A conductive layer is formed between the conductive via and contact pad on the semiconductor die. A protective layer is formed over the front side of the semiconductor die. A portion of the insulating material and conductive via is removed from a backside of the semiconductor die opposite the front side of the semiconductor die so that a thickness of the conductive via is less than a thickness of the semiconductor wafer. The insulating material and conductive via are tapered. The wafer is singulated through the gap to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically interconnected through the conductive vias. | 06-24-2010 |
| 20100164083 | PROTECTIVE THIN FILM COATING IN CHIP PACKAGING - A protective thin film coating for device packaging. A dielectric thin film coating is formed over die and package substrate surfaces prior to applying a molding compound. The protective thin film coating may reduce moisture penetration from the bulk molding compound or the interface between the molding compound and the die or substrate surfaces. | 07-01-2010 |
| 20100164084 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - Provided is a semiconductor device capable of removing a power ground grid noise using a small area. The semiconductor device includes a first chip including at least one decoupling capacitor; and a second semiconductor chip stacked over the first semiconductor chip, including internal circuits. | 07-01-2010 |
| 20100164085 | MULTI-DIE BUILDING BLOCK FOR STACKED-DIE PACKAGE - A multi-die building block for a stacked-die package is described. The multi-die building block includes a flex tape having a first surface and a second surface, each surface including a plurality of electrical traces. A first die is coupled, through a first plurality of interconnects, to the plurality of electrical traces of the first surface of the flex tape. A second die is coupled, through a second plurality of interconnects, to the plurality of electrical traces of the second surface of the flex tape. | 07-01-2010 |
| 20100164086 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention is directed to offer a package type semiconductor device that can realize a smaller size device and its manufacturing method as well as a small stacked layer type semiconductor device and its manufacturing method. A device component | 07-01-2010 |
| 20100164087 | Semiconductor device having a stacked chip structure - A semiconductor device is formed by mutually connecting a first semiconductor chip with second and third semiconductor chips arranged side by side, with the active surface of the first chip faced to those of the second and third chip. Both the second and third semiconductor chips have functional elements on their active surfaces. The first semiconductor chip has, in its active surface, a wiring for connecting the second semiconductor chip and the third semiconductor chip, and a terminal for external connection on its surface opposite to its active surface. | 07-01-2010 |
| 20100164088 | SEMICONDUCTOR PACKAGE, MANUFACTURING METHOD THEREOF AND IC CHIP - A package may include a lower unit package and an upper unit package. Each of the unit packages may include a circuit substrate having a lower surface and an upper surface. Wire bonding pads may be provided of the lower surface of the circuit substrate, and chip bonding pads may be provided on the upper surface of the circuit substrate. An IC chip may be provided on the lower surface of the circuit substrate. The IC chip may have an active surface with wire lands and bump lands. Chip bumps may be provided on the bump land. The wire bonding pads of the circuit substrate may be connected to the wire lands of the IC chip using bonding wires. The chip bumps of the upper unit package may be connected to the chip bonding pads of the lower unit package. An IC chip may include a substrate. A conductive layer may be provided on the substrate. The conductive layer may define a bump land for supporting a chip bump and a wire land for connecting to a bonding wire. The bump land and the wire land may be spaced apart from each other on an active surface of the IC chip. | 07-01-2010 |
| 20100171203 | Robust TSV structure - A die includes a seal-ring structure below a substrate. The seal-ring structure is disposed around at least one substrate region. At least one means for substantially preventing ion diffusion into the substrate region. The at least one means is coupled with the seal-ring structure. | 07-08-2010 |
| 20100171204 | THREE-DIMENSIONAL PACKAGE - A three-dimensional package includes a carrier, a first die mounted on a first surface of the carrier, and a second die stacked on the first die. The first die includes first bond pads and second bond pads juxtaposed in separate two rows within a central region of the first die. The package further includes first bond fingers disposed on the first surface along a first side of the carrier, and second bond fingers along a second side opposite to the first side. A first bond wire is bonded to one of the first bond pads and extends to one the first bond fingers. The first bond wire overlies the row of the second bond pads. A second bond wire is bonded to one of the second bond pads and extends to one the second bond fingers. The second bond wire overlies the row of the first bond pads. | 07-08-2010 |
| 20100171205 | Stackable Semiconductor Device Packages - In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width W | 07-08-2010 |
| 20100171206 | Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same - A semiconductor package includes: (1) a substrate including an upper surface and a lower surface opposite to the upper surface; (2) a chip mounted and electrically connected to the upper surface of the substrate; (3) an interposer mounted on the chip and electrically connected to the upper surface of the substrate, the interposer including an upper surface and a lower surface that is opposite to the upper surface and facing the chip, the interposer including a plurality of electrical contacts located on the upper surface of the interposer; and (4) a molding compound sealing the substrate, the interposer, and the chip, and exposing the lower surface of the substrate, the molding compound defining a plurality of holes that enclose and expose respective ones of the electrical contacts. | 07-08-2010 |
| 20100171207 | STACKABLE SEMICONDUCTOR DEVICE PACKAGES - In one embodiment, a manufacturing method includes: (1) applying a first electrically conductive material to an upper surface of a substrate to form first conductive bumps; (2) electrically connecting a semiconductor device to the upper surface of the substrate; (3) applying a molding material to form a molded structure covering the first conductive bumps and the semiconductor device, upper ends of the first conductive bumps being recessed below an upper surface of the molded structure; (4) forming openings adjacent to the upper surface of the molded structure, the openings exposing the upper ends of the first conductive bumps; (5) applying, through the openings, a second electrically conductive material to form second conductive bumps; and (6) forming cutting slits extending through the molded structure and the substrate. | 07-08-2010 |
| 20100171208 | SEMICONDUCTOR DEVICE - A semiconductor device which has a plurality of semiconductor chips stacked on a substrate. The semiconductor device includes semiconductor chip | 07-08-2010 |
| 20100171209 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having stacked semiconductor chips is provided wherein alignment of even thin semiconductor chips of a large warpage is easy and thus high assembling accuracy and high reliability are ensured. Semiconductor chips having hollow through-silicon via electrodes each formed with a tapered portion are melt-joined using solder balls each having a core of a material higher in melting point than solder. When melt-joining the semiconductor chips, the temperature is raised while imparting an urging load to stacked semiconductor chips, thereby correcting warpage of the semiconductor chips. In each chip-to-chip connection thus formed, if the connection is to prevent the occurrence of stress around the electrode due to the urging load, a solder ball having a core of a smaller diameter than in the other connections is used in the connection. | 07-08-2010 |
| 20100171210 | SEMICONDUCTOR DEVICE, STACKED SEMICONDUCTOR DEVICE AND INTERPOSER SUBSTRATE - A semiconductor device has a semiconductor element; an interposer substrate having a wiring pattern electrically connected to the semiconductor element and an insulating substrate formed with the wiring pattern; a connection layer for adhering between the semiconductor element and the interposer substrate; and a solder ball external terminal arranged on the interposer substrate. The insulating substrate is folded in a portion mounted with the external terminal arranged on an outer side to the semiconductor element, and the unfolded and folded portions of the insulating substrate are opposite each other to form a gap therebetween. | 07-08-2010 |
| 20100176501 | Method and Apparatus for Stacked Die Package with Insulated Wire Bonds - A semiconductor package has a substrate with a plurality of contact pads. A first semiconductor die is mounted to the substrate. First bond wires are formed between each of the center-row contact pads of the first semiconductor die and the substrate contact pads. The first bond wires include an electrically insulative coating formed over the shaft that covers a portion of a surface of a bumped end of the first bond wires. An epoxy material is deposited over the first semiconductor die. A second semiconductor die is mounted to the epoxy material. Second bond wires are formed between each of the center-row contact pads of the second semiconductor die and the substrate contact pads. The second bond wires include an electrically insulative coating formed over the shaft of the second bond wires that covers a portion of a surface of a bumped end of the second bond wires. | 07-15-2010 |
| 20100181660 | Multi-Chip Semiconductor Package - Semiconductor packages that contain multiple stacked chips and methods for making such semiconductor packages are described. The semiconductor packages contain a full land pad array and multiple chips that are stacked vertically. Some of the chips are separated by routing leads which are connected to the land pad array. The chips can be directly connected to an inner part of the land pad array and a second and third chip are respectively connected to the middle and outer part of the land pad array through the routing leads that are connected to solder balls. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability. Other embodiments are also described. | 07-22-2010 |
| 20100181661 | SEMICONDUCTOR DEVICE - A semiconductor device includes a chip unit mounted on a wiring board. The chip unit includes of semiconductor chips having electrode pads and an interposer having test pads exposed and electrode pads wired from the test pads. The semiconductor chips and the interposer are stacked in a step-like shape so as to be positioned the interposer in an uppermost level. The electrode pads of the semiconductor chips and the interposer are electrically connected by first connecting members, and the electrode pads of the semiconductor chips or the interposer and the wiring board are electrically connected by second connecting members. | 07-22-2010 |
| 20100187670 | On-Chip Heat Spreader - A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader. | 07-29-2010 |
| 20100187671 | Forming Seal Ring in an Integrated Circuit Die - The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs. | 07-29-2010 |
| 20100193928 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having a through-connection extending between a first main face of the semiconductor chip and a second main face of the semiconductor chip opposite the first main face, encapsulation material at least partially encapsulating the semiconductor chip, and a first metal layer disposed over the encapsulation material and connected with the through-connection. | 08-05-2010 |
| 20100193929 | SEMICONDUCTOR DEVICE - A semiconductor device includes a package board, first connectors, and a first multi-layered structure. The package board has first and second regions. The first connectors are in the first region. The first multi-layered structure includes a first semiconductor chip, a wiring board, and second to fifth connectors. The first semiconductor chip has first and second surfaces. The first surface covers the second region. The wiring board has third and fourth surfaces. The third surface is fixed to the second surface. The second to fourth connectors are in the center regions of the second to fourth surfaces, respectively. The fifth connectors are aligned along opposing two sides of the fourth surface. The second connectors electrically connect to the third connectors. The third connectors electrically connect to the fourth and fifth connectors. The first connectors electrically connect to the fourth and fifth connectors. | 08-05-2010 |
| 20100193930 | MULTI-CHIP SEMICONDUCTOR DEVICES HAVING CONDUCTIVE VIAS AND METHODS OF FORMING THE SAME - A multi-chip device can have a plurality of chips in a stair-step arrangement having respective chip pads thereon. A mold packaging material encapsulates the plurality of chips and at least one conductive via, that is in the mold packaging material and extends from an outer surface of the material, contacts a respective one of the chip pads. A conductive material is in the at least one conductive via. | 08-05-2010 |
| 20100193931 | Package-on-Package Using Through-Hole Via Die on Saw Streets - A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package. | 08-05-2010 |
| 20100200974 | SEMICONDUCTOR PACKAGE STRUCTURE USING THE SAME - A semiconductor package structure using the same is provided. The semiconductor package structure includes a first semiconductor element, a second semiconductor element, a binding wire and a molding compound. The first semiconductor element includes a semiconductor die and a pad. The pad is disposed above the semiconductor die and includes a metal base, a hard metal layer disposed above the metal base and an anti-oxidant metal layer disposed above the hard metal layer. The hardness of the hard metal layer is larger than that of the metal base. The activity of the anti-oxidant metal layer is lower than that of the hard metal layer. The first semiconductor element is disposed above the second semiconductor element. The bonding wire is connected to the pad and the second semiconductor element. The molding compound seals the first semiconductor element and the bonding wire and covers the second semiconductor element. | 08-12-2010 |
| 20100200975 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A first multilayer wiring structure has a first surface and a second surface positioned on an opposite side to the first surface, a first wiring pattern formed on the second surface side and a housing portion penetrating through the first multilayer wiring structure from the first surface to the second surface. An electronic component has an electrode pad. The electronic component is accommodated in the housing portion in a state that an electrode pad formation surface at the side where the electrode pad is formed is positioned on the second surface side of the first multilayer wiring structure. A second multilayer wiring structure has an insulating layer and a second wiring pattern which are stacked on the second surface of the first multilayer wiring structure and the electrode pad formation surface of the electronic component. The second wiring pattern is electrically connected to the first wiring pattern and the electrode pad. | 08-12-2010 |
| 20100200976 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A plurality of semiconductor elements configuring a first element group are stacked in a step-like shape on a wiring board. A plurality of semiconductor elements configuring a second element group are stacked in a step-like shape on the first element group toward a direction opposite to the stepped direction of the first element group. The semiconductor elements are electrically connected to connection pads of the wiring board through metallic wires. Among the plurality of semiconductor elements configuring the second element group, the lowermost semiconductor element has a thickness larger than those of the other semiconductor elements. | 08-12-2010 |
| 20100207262 | PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a package-on-package system includes: providing a package substrate; attaching a semiconductor die to the package substrate; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the package substrate and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings. | 08-19-2010 |
| 20100213591 | Semiconductor package and method of manufacturing the same - A semiconductor package includes a first package and a second package, a connection terminal disposed between the first and second packages and including a first solder ball and a second solder ball that are vertically stacked, a solder passivation layer with which a surface of at least one of the first and second solder balls is coated, and a ring-shaped short prevention part surrounding a coupling portion between the first and second solder balls. | 08-26-2010 |
| 20100213592 | Semiconductor Module, Terminal Strip, Method for Manufacturing Terminal Strip, and Method for Manufacturing Semiconductor Module - To provide a semiconductor module, a terminal strip, a method for manufacturing the terminal strip, and a method for manufacturing the semiconductor module in which loop inductance is decreased. | 08-26-2010 |
| 20100213593 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package includes an upper unit package and a lower unit package. The lower unit package includes a substrate, a semiconductor chip disposed on an upper surface of the substrate, terminal pads arranged on an upper surface of the semiconductor chip, protrusions formed on the terminal pads, a protective layer formed on the substrate and covering the semiconductor chip and the protrusions, and openings formed in the protective layer and exposing the protrusions. The upper unit package includes a substrate, ball lands provided on a lower surface of the substrate, and solder balls formed on the ball lands. The solder balls of the upper unit package are inserted into the openings of the lower unit package to be connected to the protrusions of the lower unit package. | 08-26-2010 |
| 20100213594 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME - A semiconductor device having a structure in which the structure is laminated in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material of liquid state to the back surface of a semiconductor wafer by a spin coating method, this is dried and a solid-like adhesive layer is formed. Then, a semiconductor wafer is divided into each semiconductor chip by making the above-mentioned reforming area into a division origin. By pasting up this semiconductor chip on the main surface of the other semiconductor chip by the adhesive layer of the back surface, a semiconductor device having a structure in which the semiconductor device is laminated in many stages is manufactured. | 08-26-2010 |
| 20100219522 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A first sealing resin seals a side surface of an electronic component and a side surface of a conductive member. A second sealing resin is provided on the first sealing resin, and seals an electrode pad and an electrode pad forming surface of the electronic component and a part of the conductive member. A multilayer wiring structure includes a plurality of stacked insulating layers and a wiring pattern and is provided on a surface of the second sealing resin from which a connecting surface of the electrode pad and a first connecting surface of the conductive member are exposed. The wiring pattern is connected to the connecting surface of the electrode pad and the first connecting surface of the conductive member. | 09-02-2010 |
| 20100219523 | STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM - A stackable integrated circuit package system includes: a substrate having a first side and a second side opposite the first side, the substrate having a cavity provided therein; a first integrated circuit die in the cavity with a first interconnect extending out from the cavity without connection and a second interconnect connected to the first side; a first mold compound to cover the first integrated circuit die, the second interconnect, and a portion of the first interconnect; a second integrated circuit die mounted to the first integrated circuit die with a third interconnect connected to the second side; a second mold compound to cover the second integrated circuit die and the third interconnect; and external interconnects, not encapsulated by the second encapsulant, mounted on the second side. | 09-02-2010 |
| 20100224975 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A DUAL BOARD-ON-CHIP STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a first board-on-chip-structure having a first integrated circuit die mounted over a substrate and the substrate having a substrate cavity; mounting a second board-on-chip-structure over the first board-on-chip-structure, the second board-on-chip-structure having a second integrated circuit die mounted under an interposer and the interposer having an interposer cavity; connecting the first board-on-chip-structure to the second board-on-chip-structure with an internal interconnect; and encapsulating the first board-on-chip-structure, the second board-on-chip-structure, and the internal interconnect with an encapsulation. | 09-09-2010 |
| 20100224976 | METHOD FOR EMBEDDING SILICON DIE INTO A STACKED PACKAGE - Several embodiments of microelectronic configurations with logic components and associated methods of manufacturing are disclosed herein. In one embodiment, the configuration includes a substrate with a recess, a first die carried by the substrate wherein the die substantially covers the recess, and a logic component carried by the die in a location exposed by the recess. The logic component can be substantially coplanar with the substrate. The die is electrically connected to a terminal on a one side of the substrate, and the logic component is electrically connected to a terminal on an opposite side of the substrate. | 09-09-2010 |
| 20100224977 | Semiconductor device and method for fabricating the same - Provided are a semiconductor device and a method for fabricating the same. The semiconductor device may include a substrate including a cell area and a scribe lane area defining the cell area, at least one pad on the cell area, at least one through electrode penetrating the substrate and electrically connected to the at least one pad, and at least one dummy through electrode penetrating the substrate and spaced apart from the at least one through electrode. The semiconductor device may further include at least one conductive pattern on the substrate electrically connecting the at least one through electrode to the at least one dummy through electrode. | 09-09-2010 |
| 20100224978 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLEX TAPE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a device to the substrate; providing interconnects on the substrate; and forming a flexible tape substantially conformal to the device and contacting the interconnects. | 09-09-2010 |
| 20100224979 | STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing of a stacked integrated circuit package system includes: providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; mounting an intermediate integrated circuit package over the base interposer; and mounting a top integrated circuit package over the intermediate integrated circuit package. | 09-09-2010 |
| 20100230794 | Method For Fabricating Semiconductor Components Using Maskless Back Side Alignment To Conductive Vias - A method for fabricating semiconductor components includes the steps of: providing a semiconductor substrate having a circuit side, a back side and conductive vias; removing portions of the substrate from the back side to expose terminal portions of the conductive vias; depositing a polymer layer on the back side encapsulating the terminal portions; and then planarizing the polymer layer and ends of the terminal portions to form self aligned conductors embedded in the polymer layer. Additional back side elements, such as terminal contacts and back side redistribution conductors, can also be formed in electrical contact with the conductive vias. A semiconductor component includes the semiconductor substrate, the conductive vias, and the back side conductors embedded in the polymer layer. A stacked semiconductor component includes a plurality of components having aligned conductive vias in electrical communication with one another. | 09-16-2010 |
| 20100230795 | STACKED MICROELECTRONIC ASSEMBLIES HAVING VIAS EXTENDING THROUGH BOND PADS - A stacked microelectronic assembly is provided which includes first and second stacked microelectronic elements. Each of the first and second microelectronic elements can include a conductive layer extending along a face of such microelectronic element. At least one of the first and second microelectronic elements can include a recess extending from the rear surface towards the front surface, and a conductive via extending from the recess through the bond pad and electrically connected to the bond pad, with a conductive layer connected to the via and extending along a rear face of the microelectronic element towards an edge of the microelectronic element. A plurality of leads can extend from the conductive layers of the first and second microelectronic elements and a plurality of terminals of the assembly can be electrically connected with the leads. | 09-16-2010 |
| 20100230796 | INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM AND METHOD FOR MAKING THEREOF - A method for making an integrated circuit package-in-package system includes: forming a first integrated circuit package including a first device and a first substrate and having a first interface; stacking a second integrated circuit package including a second device and a second substrate and having a second interface above the first integrated circuit package; and fitting the first interface directly on the second interface. | 09-16-2010 |
| 20100237482 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LAYERED PACKAGING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a base package having a base interposer; forming an intermediate package having an intermediate interposer and an intermediate package embedded link trace, the intermediate package embedded link trace being encapsulated in an intermediate package mold compound; forming a cap package having a cap interposer; and connecting the intermediate package to the cap package and the base package using the intermediate package embedded link trace. | 09-23-2010 |
| 20100237483 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERPOSER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting a device over an integrated circuit having a through via; attaching an interposer, having an opening, and the integrated circuit with the device within the opening; and forming an encapsulation at least partially covering the integrated circuit and the interposer facing the integrated circuit. | 09-23-2010 |
| 20100237484 | Semiconductor package - Provided is a semiconductor package including a first package and a second package. The first package includes a first substrate having a first front side and a first back side opposing the first front side. The first package further includes a first semiconductor chip on the first front side and an external connection member on the first semiconductor chip. The external connection member may be configured to electrically connect the first semiconductor chip to an external device. The second package includes a second substrate having a second back side facing the first back side of the first substrate and a second front surface opposing the second back side. The second package includes a second semiconductor chip on the second front side. The semiconductor package further includes an internal connection member between the first back side and the second back side to electrically connect the first package to the second package. | 09-23-2010 |
| 20100237485 | STACK TYPE SEMICONDUCTOR PACKAGE APPARATUS - A semiconductor device includes a first semiconductor package having at least one first semiconductor chip and a first sealing member covering the at least one first semiconductor chip, a second semiconductor package stacked on the first semiconductor package, the second semiconductor package having at least one second semiconductor chip, leads electrically connected to the at least one second semiconductor chip, and a second sealing member covering the at least one second semiconductor chip, and at least one signal connection member disposed in the first sealing member of the first semiconductor package, the at least one signal connection member electrically connecting the at least one first semiconductor chip with the leads of the at least one second semiconductor chip. | 09-23-2010 |
| 20100244216 | Semiconductor Device and Method of Forming No-Flow Underfill Material Around Vertical Interconnect Structure - A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow underfill material is deposited over the first carrier, conductive layer, and solder bump. A semiconductor die or component is compressed into the no-flow underfill material to electrically contact the conductive layer. A surface of the no-flow underfill material and first solder bump is planarized. A first interconnect structure is formed over a first surface of the no-flow underfill material. The first interconnect structure is electrically connected to the solder bump. A second sacrificial carrier is mounted over the first interconnect structure. A second interconnect structure is formed over a second side of the no-flow underfill material. The second interconnect structure is electrically connected to the first solder bump. The semiconductor devices can be stacked and electrically connected through the solder bump. | 09-30-2010 |
| 20100244217 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED CONFIGURATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a first stack layer including a first device over a first substrate, the first device including a through silicon via; configuring a second stack layer over the first stack layer, the second stack layer including an analog device; configuring a third stack layer over the second stack layer; and encapsulating the integrated circuit packaging system. | 09-30-2010 |
| 20100244218 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-STACKED FLIP CHIPS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; depositing a through-conductor on the base substrate; depositing a semiconducting layer on the base substrate and around the through-conductor; forming a metal trace connected to the through-conductor; depositing a dielectric surrounding the metal trace; and removing the base substrate. | 09-30-2010 |
| 20100244219 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an encapsulation surrounding an integrated circuit having an inactive side and an active side exposed; forming a hole through the encapsulation with the hole not exposing the integrated circuit; forming a through conductor in the hole; and mounting a substrate with the integrated circuit surrounded by the encapsulation with the active side facing the substrate. | 09-30-2010 |
| 20100244220 | LAYOUT STRUCTURE AND METHOD OF DIE - A layout structure and layout method are provided. The layout structure includes a first conductive via, a second conductive via, a die and eight pads. The first conductive via and the second conductive via pass through the die. The first conductive via has a first pad and a second pad, and the second conductive via has a third pad and a fourth pad. A fifth pad is conducted to the third pad. A sixth pad is conducted to the second pad. A seventh pad is conducted to the first pad. An eighth pad is conducted to the fourth pad. In a vertical direction of the die, the first pad and the second pad are overlapped, the third pad and the fourth pad are overlapped, the fifth pad and the sixth pad are overlapped, and the eighth pad and the seventh pad are overlapped, partially or totally. | 09-30-2010 |
| 20100252919 | ELECTRONIC DEVICE AND METHOD OF PACKAGING AN ELECTRONIC DEVICE - An electronic device can include a package device structure including a die encapsulated within a packaging material. The package device structure can have a first side and a second side opposite the first side. The electronic device can include a first layer along the first side of the package device structure. The first layer can be capable of causing a first deformation of the package device structure. The electronic device can also include a second layer along the second side of the package device structure. The second layer can be capable of causing a second deformation of the package device structure, the second deformation opposite the first deformation. | 10-07-2010 |
| 20100258927 | Package-on-package interconnect stiffener - Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package. | 10-14-2010 |
| 20100258928 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture an integrated circuit packaging system includes: providing a substrate; attaching a first integrated circuit to the substrate by interconnects only along opposite sides of the first integrated circuit; and attaching a heat spreader to the substrate, the heat spreader extending over the first integrated circuit and between the opposite sides of the first integrated circuit. | 10-14-2010 |
| 20100258929 | STAIRCASE SHAPED STACKED SEMICONDUCTOR PACKAGE - A staircase shaped stacked semiconductor package is presented which includes a substrate, a multiplicity of semiconductor chip modules, a connection member, and conductive members. The substrate has connection pads along an upper surface edge. Each semiconductor chip module includes a first and a second semiconductor chip that oppose each other. The first and second semiconductor chips have respective first and second bonding pads along exposed surfaces. The connection member is placed on an uppermost semiconductor chip module and has first and second terminals electrically connected to the first and second bonding pads via conductive members. The conductive members are also coupled to the connection pads of the substrate. | 10-14-2010 |
| 20100258930 | Stacked semiconductor package and method of manufacturing thereof - Provided is a stacked semiconductor package and a method of manufacturing the same. The stacked semiconductor package may include a first semiconductor package, a second semiconductor package, and at least one electrical connection device electrically connecting the first and second semiconductor packages. The first semiconductor package may include a first re-distribution pattern on a first semiconductor chip and a first sealing member on the first substrate, the first sealing member may include at least one first via to expose the first re-distribution pattern. The second semiconductor package may include a second re-distribution pattern on a second semiconductor chip and a second sealing member on a lower side of the second substrate, the second sealing member may include at least one second via to expose the second re-distribution pattern. An electrical connection device may be between the first and second vias to connect the first and the second re-distribution patterns. | 10-14-2010 |
| 20100258931 | Semiconductor device and method of forming the same - A semiconductor device includes a chip stacked structure. The chip stacked structure may include, but is not limited to, first and second semiconductor chips. The first semiconductor chip has a first thickness. The second semiconductor chip has a second thickness that is thinner than the first thickness. | 10-14-2010 |
| 20100258932 | Supporting substrate before cutting, semiconductor device, and method of forming semiconductor device - A method of forming a semiconductor device may include, but is not limited to, the following processes. A supporting substrate is prepared. The supporting substrate has a chip mounting area, and a plurality of penetrating slits around the chip mounting area. At least a stack of semiconductor chips is formed over the chip mounting area. A first sealing member is formed, which seals the stack of semiconductor chips without the first sealing member filling the plurality of penetrating slits. | 10-14-2010 |
| 20100258933 | Semiconductor device, method of forming the same, and electronic device - A semiconductor device includes a substrate, a stack of semiconductor chips, and a first sealing material. The substrate may include, but is not limited to, a chip mounting area and a higher-level portion. The higher level portion surrounds the chip mounting area. The higher-level portion is higher in level than the chip mounting area. The stack of semiconductor chips is disposed over the chip mounting area. A first sealing material seals the stack of semiconductor chips. The first sealing material is confined by the higher-level portion. | 10-14-2010 |
| 20100276794 | SYSTEM AND METHOD FOR MULTI-CHIP MODULE DIE EXTRACTION AND REPLACEMENT - A system and method are provided in which a first chip in a stacked multi-chip module configuration is affixed via one or more adhesion layers to a first portion of a partitioned interposer unit. Planar partitions of the interposer are physically bonded via multiple solder ābumps,ā which possess high tensile strength but low resistance to horizontal shear force or torque. A second chip is affixed via one or more adhesion layers to the second portion of the partitioned interposer. The chips may thus be separated by horizontally and oppositely shearing or twisting the first and second portions of the partitioned interposer away from one another. | 11-04-2010 |
| 20100276795 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package capable of being efficiently stacked and a method of manufacturing the same is presented. The semiconductor package includes a semiconductor chip, an insulation layer, and a through-electrode. The semiconductor chip has a first surface and a second surface, a circuit section in the semiconductor chip, an internal circuit pattern electrically connected to the circuit section, and a through-hole that passes through the internal circuit pattern and through the first and second surfaces. The insulation layer is on a through-hole of the semiconductor chip and has an opening which exposes the internal circuit pattern which was exposed by the through-hole. The through-electrode is in the through-hole and electrically coupled to the internal circuit pattern which is exposed through the opening of the insulation layer. | 11-04-2010 |
| 20100283140 | PACKAGE ON PACKAGE TO PREVENT CIRCUIT PATTERN LIFT DEFECT AND METHOD OF FABRICATING THE SAME - A package on package includes a lower semiconductor package including a plurality of stacked semiconductor chips, a connection portion including an electrically-conductive lead having a height lower than that of an encapsulation member, and an upper semiconductor package connected to the connection portion of the lower semiconductor package via a solder ball in a fan-in structure. | 11-11-2010 |
| 20100289130 | Method and Apparatus for Vertical Stacking of Integrated Circuit Chips - A method and apparatus for constructing a packaged integrated circuit stack | 11-18-2010 |
| 20100289131 | Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure - A semiconductor device is made by forming first and interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die. | 11-18-2010 |
| 20100295163 | STACKED SEMICONDUCTOR PACKAGE ASSEMBLY - A stacked package assembly includes N (where Nā§2) package bodies stacked together. Each package body is made up of a substrate which comprises a top surface and a bottom surface, and a chip packaged in the substrate. The top surface of the substrate of each package body includes (Nā1) pads, and the bottom surface includes N pads. The Kth pad on the top surface of the substrate of each package body is electrically connected to the (K+1)th pad on the bottom surface thereof. The Kth (K=1, 2, . . . , (Nā1)) pad on the top surface of the substrate of one lower package body corresponds to the Kth pad on the bottom surface of the substrate of another upper package body stacked above the lower package body. | 11-25-2010 |
| 20100301466 | SEMICONDUCTOR DEVICE - The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members). | 12-02-2010 |
| 20100314736 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture an integrated circuit packaging system includes: providing a base substrate; mounting a first base integrated circuit over the base substrate; mounting a second base integrated circuit over the first base integrated circuit; attaching a stacking interconnect to the base substrate and adjacent to the first base integrated circuit; and forming a base encapsulation, having a recess portion from a corner of the base encapsulation and a step portion adjacent to the recess portion, with the step portion over the second base integrated circuit and the recess portion exposing the stacking interconnect. | 12-16-2010 |
| 20100314737 | Intra-Die Routing Using Back Side Redistribution Layer and Associated Method - A semiconductor die includes: a body portion with a plurality of circuit components, a front side including electrical couplings to the plurality of circuit components, a back side having a redistribution layer with a first electrical terminal coupled to the plurality of circuit components by a first through-silicon via, and a second through-silicon via electrically coupled to a third through-silicon via by a trace on the back side redistribution layer. Also, disclosed is a method of coupling circuit components on a die using through-silicon vias and a back side redistribution layer. | 12-16-2010 |
| 20100314738 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A STACK PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a stack board; connecting a device over the stack board; forming a stack encapsulant having a cavity and a pedestal over the device and having a shaped perimeter side from a pedestal surface of the pedestal to the stack board; and attaching a stack adhesive to a base package and the pedestal, the cavity and the shaped perimeter side providing a space for connections to the stack board. | 12-16-2010 |
| 20100314739 | PACKAGE-ON-PACKAGE TECHNOLOGY FOR FAN-OUT WAFER-LEVEL PACKAGING - Methods, systems, and apparatuses for wafer-level package-on-package structures are provided herein. A wafer-level integrated circuit package that includes at least one die is formed. The wafer-level integrated circuit package includes redistribution interconnects that redistribute terminals of the die over an area that is larger than an active-surface of the die. Electrically conductive paths are formed from the redistribution interconnects at a first surface of the wafer-level integrated circuit package to electrically conductive features at a second surface of the wafer-level integrated circuit package. A second integrated circuit package may be mounted to the second surface of the wafer-level integrated circuit package to form a package-on-package structure. Electrical mounting members of the second package may be coupled to the electrically conductive features at the second surface of the wafer-level integrated circuit package to provide electrical connectivity between the packages. | 12-16-2010 |
| 20100314740 | SEMICONDUCTOR PACKAGE, STACK MODULE, CARD, AND ELECTRONIC SYSTEM - A multi-chip package device can include a plurality of integrated circuit device chips stacked on one another inside a multi-chip package including the device. The device can include an electrically isolated multi-chip support structure that is directly connected to first and second electrically active integrated circuit structures via respective first and second adhesive layers located on opposing sides of the electrically isolated multi-chip support structure. | 12-16-2010 |
| 20100320582 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INWARD AND OUTWARD INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base circuit assembly having an integrated circuit device; mounting a pre-formed conductive frame having an outer interconnect and an inner interconnect shorter than the outer interconnect over the base circuit assembly, the inner interconnect over the integrated circuit device and the outer interconnect around the integrated circuit device; applying an encapsulant over the inner interconnect and the outer interconnect; and removing a portion of the pre-formed conductive frame exposing an end of the inner interconnect and an end of the outer interconnect. | 12-23-2010 |
| 20100320583 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A DUAL SUBSTRATE PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a base conductive material on opposite sides of the base substrate; connecting an internal interconnect having a substantially spherical shape on the base substrate; forming a top substrate having a top conductive material on opposite sides of the top substrate with an upper component thereon facing the base substrate; and attaching the top substrate on the internal interconnect. | 12-23-2010 |
| 20100320584 | SEMICONDUCTOR CHIP LAMINATED BODY - A semiconductor chip laminated body includes a wiring board having a connecting terminal; a plurality of semiconductor chips laminated on the wiring board, each of the semiconductor chips having a pad; conductive connecting members having first end parts connected to the pads of the corresponding semiconductor chips and second end parts projecting from side surfaces of the corresponding semiconductor chips; and a conductive member configured to connect the connecting terminal of the wiring board and the second end parts of the conductive connecting members; wherein conductive materials are exposed at the side surfaces of the semiconductor chips; and a gap is provided between the side surfaces of the semiconductor chips and the conductive member. | 12-23-2010 |
| 20100320585 | PACKAGED INTEGRATED CIRCUIT DEVICES WITH THROUGH-BODY CONDUCTIVE VIAS, AND METHODS OF MAKING SAME - A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material. | 12-23-2010 |
| 20100327419 | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same - A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer. | 12-30-2010 |
| 20100327420 | SEMICONDUCTOR DEVICE WITH EMBEDDED INTERCONNECT PAD - A semiconductor device comprising: a lower semiconductor package that comprises a first set of one or more semiconductor dies, an upper semiconductor package that is stacked on the lower semiconductor package, the upper semiconductor package comprises a second set of one or more semiconductor dies, and a first interconnect pad that is embedded in a top side of the lower semiconductor package to couple the upper semiconductor package to the lower semiconductor package. | 12-30-2010 |
| 20110006412 | SEMICONDUCTOR CHIP PACKAGE AND METHOD FOR MANUFACTURING THEREOF AND STACK PACKAGE USING THE SAME - A semiconductor chip package and method for manufacturing thereof and stack package using the same is presented that reduces electrical signal transmission delays and realizes a reduction in thickness is presented. The stack package includes a plurality of semiconductor chip packages coupled to a substrate. Each semiconductor chip package includes a substrate and a device layer attached to the substrate. The device layer has first bonding pads on a first surface and second bonding pads on a second surface opposite to the first surface. The first and second bonding pads are coupled together by through electrodes that pass through the device layer. The stack package also includes conductive materials attached to the second bonding pads such that the conductive materials couple together adjacent semiconductor chip packages and the substrate. | 01-13-2011 |
| 20110006413 | SUBSTRATE FOR SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND STACK PACKAGE USING THE SEMICONDUCTOR PACKAGE - A substrate for a semiconductor package is provided having first and second core layers defining a cavity having an adhesive member and sized and shaped to receive a semiconductor chip. The semiconductor package further having a connection member formed on a bond finger and connected to a via pattern formed through the first and second core layers. A stack package is also provided having multiple substrates. | 01-13-2011 |
| 20110012249 | IC CHIP PACKAGE HAVING IC CHIP WITH OVERHANG AND/OR BGA BLOCKING UNDERFILL MATERIAL FLOW AND RELATED METHODS - An IC chip package, in one embodiment, may include an IC chip including an upper surface including an overhang extending beyond a sidewall of the IC chip, and underfill material about the sidewall and under the overhang. The overhang prevents underfill material from extending over an upper surface of the IC chip. In another embodiment, a ball grid array (BGA) is first mounted to landing pads on a lower of two joined IC chip packages. Since the BGA is formed on the lower IC chip package first, the BGA acts as a dam for the underfill material thereon. The underfill material extends about the respective IC chip and surrounds a bottom portion of a plurality of solder elements of the BGA and at least a portion of respective landing pads thereof. | 01-20-2011 |
| 20110018114 | Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation - A semiconductor device is made by forming a first thermally conductive layer over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer. | 01-27-2011 |
| 20110018115 | POP PRECURSOR WITH INTERPOSER FOR TOP PACKAGE BOND PAD PITCH COMPENSATION - An electronic assembly adapted for forming package on package (PoP) devices includes a package substrate having a molded IC die thereon that defines a mold cap height and substrate contact pads lateral to the molded IC die. An interposer including an interposer substrate has bottom metal land pads and top metal land pads, interposer vias, and an open receptacle region formed through the interposer substrate. The substrate top surface is positioned relative to the interposer so that the molded IC die is within the open receptacle region to align the bottom metal land pads and substrate contact pads. An underfill layer is between the substrate top surface and the bottom side of the interposer substrate. A step height from the mold cap height minus a height of the top metal land pads is generally from 0 to 0.2 mm. | 01-27-2011 |
| 20110024888 | Semiconductor Device and Method of Mounting Die with TSV in Cavity of Substrate for Electrical Interconnect of FI-POP - A semiconductor device has a substrate with a cavity formed through first and second surfaces of the substrate. A conductive TSV is formed through a first semiconductor die, which is mounted in the cavity. The first semiconductor die may extend above the cavity. An encapsulant is deposited over the substrate and a first surface of the first semiconductor die. A portion of the encapsulant is removed from the first surface of the first semiconductor die to expose the conductive TSV. A second semiconductor die is mounted to the first surface of the first semiconductor die. The second semiconductor die is electrically connected to the conductive TSV. An interposer is disposed between the first semiconductor die and second semiconductor die. A third semiconductor die is mounted over a second surface of the first semiconductor die. A heat sink is formed over a surface of the third semiconductor die. | 02-03-2011 |
| 20110024889 | PACKAGE ARCHITECTURE - A packaging architecture for an integrated circuit is provided. The architecture includes a printed circuit board and a package substrate disposed on the printed circuit board. A first integrated circuit is disposed on a first surface of the package substrate. The package substrate is capable of supporting a second integrated circuit. The second integrated circuit is in electrical communication with a plurality of pads disposed on the first surface of the package substrate. Each of the plurality of pads is in electrical communication with the printed circuit board without communicating with the first integrated circuit. | 02-03-2011 |
| 20110024890 | Stackable Package By Using Internal Stacking Modules - A semiconductor package comprises a substrate, a first semiconductor die mounted to the substrate, and a first double side mold (DSM) internal stackable module (ISM) bonded directly to the first semiconductor die through a first adhesive. The first DSM ISM includes a first molding compound, and a second semiconductor die disposed in the first molding compound. The semiconductor package further comprises a first electrical connection coupled between the first semiconductor die and the substrate, and a second electrical connection coupled between the first DSM ISM and the substrate. | 02-03-2011 |
| 20110031598 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device and a method of fabricating the same are disclosed. An interposer used for the semiconductor device includes integrated circuits therein to realize the functions of a decoupling capacitor, an ESD preventing circuit, an impedance matching circuit, and termination. Therefore, it is possible to improve the reliability of the operation of the semiconductor device. | 02-10-2011 |
| 20110031599 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package includes a first semiconductor package having a first semiconductor chip having a first surface and a second surface facing away from the first surface, first bonding pads disposed on the first surface, and through-electrodes electrically connected with the first bonding pads The through-electrodes pass through the first and second surfaces of the first chip and extend from the second surface. A second semiconductor package has a through-holes defined therein into which the through-electrodes are inserted and second bonding pads electrically connected with the through-electrodes. | 02-10-2011 |
| 20110031600 | SEMICONDUCTOR PACKAGE - A semiconductor package comprises a substrate having bond fingers on an upper surface thereof and ball lands on a lower surface thereof; at least two chip modules stacked on the upper surface of the substrate, each of the at least two chip modules including a plurality of semiconductor chips having first connection members and stacked in a manner such that the first connection members of the semiconductor chips are connected to one another, the chip modules being stacked in a zigzag pattern such that connection parts of the chip modules project sideward; and second connection members electrically connecting the connection parts of the respective chip modules to the bond fingers of the substrate. | 02-10-2011 |
| 20110031601 | STACKED SEMICONDUCTOR DEVICE AND METHOD OF FORMING SERIAL PATH THEREOF - A stacked semiconductor device and a method of forming a serial path of the stacked semiconductor device are provided. The stacked semiconductor device includes a plurality of chips each having a first internal circuit for receiving an input signal, performing a designated operation and outputting an output signal. Each of the chips includes a serial bump disposed at the same position on one surface of each of the chips, receiving the input signal and transferring the input signal to the first internal circuit, and a serial through-silicon via (TSV) disposed at a position symmetrical to the serial bump with respect to a center of the chip to penetrate the chip, and receiving and transferring the output signal. Here, the chips are alternately rotated and stacked, so that the serial TSV and the serial bumps of adjacent chips contact each other. According to the stacked semiconductor device and method, a plurality of chips having the same pattern are rotated about the center of the chips and stacked, so that a parallel path and a serial path can be formed. | 02-10-2011 |
| 20110037155 | Semiconductor Device and Method of Forming Dam Material Around Periphery of Die to Reduce Warpage - A semiconductor device has a temporary carrier with a designated area for a first semiconductor die. A dam material is deposited on the carrier around the designated area for a first semiconductor die. The first semiconductor die is mounted to the designated area on the carrier. An encapsulant is deposited over the first semiconductor die and carrier. The dam material is selected to have a CTE that is equal to or less than the CTE of the encapsulant. The carrier is removed to expose the encapsulant and first semiconductor die. A first interconnect structure is formed over the encapsulant. An EMI shielding layer can be formed over the first semiconductor die. A second interconnect structure is formed over a back surface of the first semiconductor die. A conductive pillar is formed between the first and second interconnect structures. A second semiconductor die is mounted to the second interconnect structure. | 02-17-2011 |
| 20110037156 | Variable Feature Interface That Induces A Balanced Stress To Prevent Thin Die Warpage - A packaged semiconductor product includes a packaging substrate coupled to a semiconductor die through an interconnect structure with elements of variable features. The interconnect structure may be bumps or pillars. The variable features of the interconnect structure induce a reverse bend on the semiconductor die that mitigates warpage of the semiconductor die during semiconductor assembly by balancing bending of the packaging substrate during reflow. The variable features can be variable height and/or variable composition. | 02-17-2011 |
| 20110037157 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a component over a side of the substrate; forming an interface module having a module via in any location for connectivity to the substrate; and mounting the entirety of the interface module over a portion of the side of the substrate next to the component. | 02-17-2011 |
| 20110037158 | BALL-GRID-ARRAY PACKAGE, ELECTRONIC SYSTEM AND METHOD OF MANUFACTURE - A multiple-chip-package (MCP) has multiple chip groups and multiple package terminal groups for electrical connections in the MCP. Semiconductor chips of the same chip group are electrically connected to the package terminals of the same package terminal group, while package terminals of different chip groups are electrically connected to the package terminals of different package terminal groups. | 02-17-2011 |
| 20110037159 | Electrically Interconnected Stacked Die Assemblies - In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected. | 02-17-2011 |
| 20110042795 | Three-Dimensional Silicon Interposer for Low Voltage Low Power Systems - Scalable silicon (Si) interposer configurations that support low voltage, low power operations are provided. In one aspect, a Si interposer is provided which includes a plurality of through-silicon vias (TSVs) within a first plane thereof adapted to serve as power, ground and signal interconnections throughout the first plane such that the TSVs that serve as the power and ground interconnections are greater in number and/or size than the TSVs that serve as the signal interconnections; and a plurality of lines within a second plane of the interposer in contact with one or more of the TSVs in the first plane, the second plane being adjacent to the first plane, adapted to serve as power, ground and signal interconnections throughout the second plane such that the lines that serve as the power and the ground interconnections are greater in number and/or size than the lines that serve as the signal interconnections. | 02-24-2011 |
| 20110049694 | Semiconductor Wafer-To-Wafer Bonding For Dissimilar Semiconductor Dies And/Or Wafers - A semiconductor manufacturing process for wafer-to-wafer stacking of a reconstituted wafer with a second wafer creates a stacked (3D) IC. The reconstituted wafer includes dies, die interconnects and mold compound. When stacked, the die interconnects of the reconstituted wafer correspond to die interconnects on the second wafer. Wafer-to-wafer stacking improves throughput of the manufacturing process. The reconstituted wafer may include dies of different sizes than those in the second wafer. Also, the dies of the reconstituted wafer may be singulated from a wafer having a different size than the second wafer. Thus, this wafer-to-wafer manufacturing process may combine dies and/or wafers of dissimilar sizes. | 03-03-2011 |
| 20110049695 | Semiconductor Device and Method of Forming Pre-Molded Semiconductor Die Having Bumps Embedded in Encapsulant - A semiconductor wafer contains a plurality of semiconductor die. A plurality of bumps is formed on the semiconductor wafer. The bumps are electrically connected to contact pads on an active surface of the die. The bumps can also be pillars or stud bumps. A first encapsulant is deposited over the bumps. The semiconductor wafer is singulated to separate the die by cutting channels partially through the wafer and back grinding the wafer down to the channels. A second encapsulant is deposited over the die. A first interconnect structure is formed over a first surface of the second encapsulant. The first interconnect structure is electrically connected to the bumps. A second interconnect structure is formed over a second surface of the second encapsulant. Secondary semiconductor components can be stacked over the second interconnect structure. A third encapsulant is deposited over the stacked secondary components and second interconnect structure. | 03-03-2011 |
| 20110049696 | OFF-CHIP VIAS IN STACKED CHIPS - A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements. | 03-03-2011 |
| 20110062574 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an encapsulation system having a mold chase with a buffer layer attached thereto; forming a base integrated circuit package including: providing a base substrate, connecting an exposed interconnect to the base substrate, a portion of the exposed interconnect having the buffer layer attached thereon, mounting a base component over the base substrate, forming a base encapsulation over the base substrate and the exposed interconnect using the encapsulation system; and releasing the encapsulation system providing the portion of the exposed interconnect exposed from the base encapsulation, the exposed interconnect having characteristics of the buffer layer removed. | 03-17-2011 |
| 20110068453 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATED VIA AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; attaching a buffer interconnect to and over the substrate; forming an encapsulation over the substrate covering the buffer interconnect and the integrated circuit; and forming a via in the encapsulation and to the buffer interconnect. | 03-24-2011 |
| 20110068454 | MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS - Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an āLā shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a āCā shape and include a tiered portion that projects towards the lateral side of the second casing. | 03-24-2011 |
| 20110074002 | STACKING DEVICES AT FINISHED PACKAGE LEVEL - An embodiment is a method and apparatus to stack devices. A first finished package level (FPL) device having a first grounded tested die (GTD) is reduced to nearly size of the first GTD. The first FPL has a first plurality of solder balls. The reduced first FPL device is attached to a first substrate to form a first device assembly. | 03-31-2011 |
| 20110079890 | SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE STRUCTURE INCLUDING THE SEMICONDUCTOR PACKAGE, AND MOBILE PHONE INCLUDING THE SEMICONDUCTOR PACKAGE STRUCTURE - Provided is a semiconductor package. The semiconductor package may include a first semiconductor package having first semiconductor chips sequentially stacked on a substrate. In example embodiments, the first semiconductor chips may have a cascaded arrangement in which first sides and second sides of the semiconductor chips define cascade patterns. The cascaded arrangement may extend in a first direction to define a space between the first sides of the first semiconductor chips and the substrate. The semiconductor package may also include at least one first connection wiring at the second sides of the semiconductor chips, the at least one first connection wiring being configured to electrically connect the substrate with the first semiconductor chips. In addition, the semiconductor package may further include a first filling auxiliary structure adjacent to the first sides of the first semiconductor chips. | 04-07-2011 |
| 20110079891 | INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: forming a stack module including: providing a stack die and encapsulating the stack die with an insulating material having a protruding support and a pad connected to the stack die; mounting the stack module on a package base; connecting the pad to the package base; mounting a top die on the protruding support; connecting the top die to the package base; and encapsulating the top die, the package base, and the stack module with a package encapsulant. | 04-07-2011 |
| 20110084373 | INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: providing a base package including a first integrated circuit coupled to a base substrate by an electrical interconnect formed on one side; and mounting an offset package over the base package, the offset package electrically coupled to the base substrate via a system interconnect. | 04-14-2011 |
| 20110089552 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system including: forming a top package including: providing a through silicon via interposer having a through silicon via; coupling a stacked integrated circuit die to the through silicon via, and testing a top package; forming a base package including: providing a substrate, coupling a base integrated circuit die to the substrate, and testing a base package; and coupling a stacked interconnect between the top package and the base package. | 04-21-2011 |
| 20110089553 | STACK-TYPE SOLID-STATE DRIVE - Provided are a stack-type solid-state drive (SSD) capable of reducing a size thereof by mounting semiconductor chips in a recess region formed in a substrate, and a method of fabricating the stack-type SSD. The stack-type SSD includes a substrate including one or more recess regions; one or more passive electronic elements mounted in the one or more recess regions; one or more control semiconductor chips mounted in the one or more recess regions; one or more non-volatile memory semiconductor chips mounted on a first surface of the substrate so as to overlap the one or more passive electronic elements, the one or more control semiconductor chips, or all the passive electronic elements and the control semiconductor chips; and an external connection terminal located on a side of the substrate. | 04-21-2011 |
| 20110101512 | Semiconductor Package and Method of Mounting Semiconductor Die to Opposite Sides of TSV Substrate - A semiconductor package has a first conductive via formed through a substrate. The substrate with first conductive via is mounted to a first carrier. A first semiconductor die is mounted to a first surface of the substrate. A first encapsulant is deposited over the first die and first carrier. The first carrier is removed. The first die and substrate with the first encapsulant is mounted to a second carrier. A second semiconductor die is mounted to a second surface of the substrate opposite the first surface of the substrate. A second encapsulant is deposited over the second die. The second carrier is removed. A bump is formed over the second surface of the substrate. A conductive layer can be mounted over the first die. A second conductive via can be formed through the first encapsulant and electrically connected to the first conductive via. The semiconductor packages are stackable. | 05-05-2011 |
| 20110108971 | LAMINATE ELECTRONIC DEVICE - A laminate electronic device comprises a first semiconductor chip, the first semiconductor chip defining a first main face and a second main face opposite to the first main face, and having at least one electrode pad on the first main face. The laminate electronic device further comprises a carrier having a first structured metal layer arranged at a first main surface of the carrier. The first structured metal layer is bonded to the electrode pad via a first bond layer of a conductive material, wherein the first bond layer has a thickness of less than 10 Ī¼m. A first insulating layer overlies the first main surface of the carrier and the first semiconductor chip. | 05-12-2011 |
| 20110108972 | Integrated Circuit Die Stacks With Translationally Compatible Vias - An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (āPTVsā) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (āTSVsā) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die. | 05-12-2011 |
| 20110108973 | CHIP PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - The disclosure provides a chip package structure and method for fabricating the same. The chip package structure includes at least one chip having at least one through via. At least one stress buffering structure is disposed in the through via. The stress buffering structure includes a first gasket and a second gasket. A supporting pillar has two terminals respectively connected to the first gasket and the second gasket. The cross-sectional area of the supporting pillar is smaller than areas of the first gasket and the second gasket. A buffering layer is sandwiched between the first gasket and the second gasket, surrounding a sidewall of the supporting pillar. An insulating layer is disposed on the through via, surrounding a sidewall of the stress buffering structure. | 05-12-2011 |
| 20110115064 | Hybrid Package Construction With Wire Bond And Through Silicon Vias - A hybrid interconnect includes a through silicon via and a wire bond. Hybrid interconnects enable better layout of a stacked IC by combining benefits from both interconnect technologies. In one hybrid interconnect, wire bonds couples a second tier die mounted on a first tier die to a redistribution layer in the first tier die. Through silicon vias in the first tier die are coupled to the wire bonds to provide communication. In another hybrid interconnect, a wire bond couples a redistribution layer on a first tier die to a packaging substrate on which the first tier die is mounted. The redistribution layer couples to a second tier die mounted on the first tier die to provide a power supply to the second tier die. Through silicon vias in the first tier die couple to the second tier die to provide communication from the packaging substrate to the second tier die. | 05-19-2011 |
| 20110121442 | PACKAGE STRUCTURE AND PACKAGE PROCESS - A package process includes following steps. A circuit mother board comprising a plurality of circuit boards is disposed on a carrier. Semiconductor devices are provided, wherein each of the semiconductor devices has a top surface and a bottom surface opposite thereto. Each of the semiconductor devices has conductive vias each having a first end surface and a second end surface exposed by the bottom surface of the semiconductor device. The semiconductor devices are connected to the corresponding circuit boards through their conductive vias with their bottom surface facing the circuit mother board. An insulating paste is formed between each of the semiconductor devices and its corresponding circuit board. A protection layer is formed on the circuit mother board to cover the semiconductor devices. Then, the protection layer and the semiconductor devices are thinned to expose the first end surface of each of the conductive vias. | 05-26-2011 |
| 20110127661 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIP CHIP AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming external interconnects having bases of a first thickness and tips of a second thickness extending inwardly directly toward each other; connecting a first circuit device between the tips; attaching a second circuit device to the first circuit device with a combined thickness of the first circuit device and the second circuit device less than the first thickness; and forming an encapsulation of the first thickness between the bases and over the tips. | 06-02-2011 |
| 20110127662 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKABLE PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package base having an inward base side and an outward base side; mounting a device over the inward base side and connected to the outward base side; connecting a silicon interposer having a through silicon via to the device and having an external side facing away from the device; and applying an encapsulant around the device, over the package base, and over the silicon interposer with the external side substantially exposed, the encapsulant having a protrusion over the outward base side. | 06-02-2011 |
| 20110133324 | MULTI-CHIP STACKED PACKAGE AND ITS MOTHER CHIP TO SAVE INTERPOSER - A multi-chip stacked package and its mother chip to save an interposer are revealed. The mother chip is a two-layer structure consisting of a semiconductor layer and an organic layer where a redistribution layer is embedded into the organic layer with a plurality of first terminals and a plurality of second terminals disposed on the redistribution layer and exposed from the organic layer. The mother chip is flip-chip mounted on the substrate. The active surface of the daughter chip is in contact with the organic layer with the bonding pads of the daughter chip bonded to the first terminals. Furthermore, a plurality of electrically connecting components electrically connect the second terminals to the substrate. In the multi-chip stacked package, the interposer can be eliminated with a thinner overall package thickness as well as controlled package warpage. | 06-09-2011 |
| 20110133325 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; mounting a component over the first substrate; mounting a stack substrate over the component, the stack substrate having an inner pad and an outer pad connected to the first substrate; mounting a first exposed interconnect on the outer pad; forming a first encapsulation over the stack substrate, the first exposed interconnect partially exposed and the inner pad partially exposed in a recess of the first encapsulation; and mounting a second exposed interconnect on the inner pad. | 06-09-2011 |
| 20110140257 | Printed Circuit Board having Embedded Dies and Method of Forming Same - A package includes a printed circuit board (PCB) having a first side and a second side and a thickness between the first side and the second side and a stacked die including a top die mounted on a bottom die, the bottom die being at least partially embedded in the PCB. Also a method of forming a package that includes forming an opening in a top surface of the PCB layer, placing a stacked die including a top die stacked on a bottom die into the opening, laminating the PCB layer to form a laminate layer, and forming an electrical connection with the stacked die. | 06-16-2011 |
| 20110140258 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system including: fabricating a base package substrate having component pads and stacking pads; coupling a base integrated circuit die to the component pads; forming a penetrable encapsulation material for enclosing the base integrated circuit die and the component pads on the base package substrate; and coupling stacked interconnects on the stacking pads adjacent to and not contacting the penetrable encapsulation material. | 06-16-2011 |
| 20110140259 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKING INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate; coupling a conductive column lead frame to the base package substrate by: providing a lead frame support, patterning a conductive material on the lead frame support including forming an interconnect securing structure, and coupling the conductive material to the base package substrate; forming a base package body between the base package substrate and the conductive column lead frame; and removing the lead frame support from the conductive column lead frame for exposing the interconnect securing structure from the base package body. | 06-16-2011 |
| 20110147906 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit with an adhesive attached thereto; connecting the integrated circuit and a plated interconnect pad; attaching an embedded interconnect to the plated interconnect pad; and forming an encapsulation, having an encapsulation first side and an encapsulation second side, around the integrated circuit, the embedded interconnect, and the plated interconnect pad with the embedded interconnect exposed from the encapsulation second side and the plated interconnect pad and the adhesive exposed from the encapsulation second side. | 06-23-2011 |
| 20110147907 | ACTIVE PLASTIC BRIDGE CHIPS - A system for proximity communication between semiconductor chips includes a package assembly. The package assembly includes a plurality of bridge circuits made of organic or plastic semiconductor material. A plurality of base chips are assembled to the package assembly. The package assembly positions and aligns the plurality of base chips such that the bridge circuits bridge the base chips and enable proximity communication between the base chips. | 06-23-2011 |
| 20110147908 | Module for Use in a Multi Package Assembly and a Method of Making the Module and the Multi Package Assembly - The module comprises a first substrate and at least one chip mounted on the first substrate. A second substrate is mounted to the first substrate and has an opening therein. The opening is lined with the at least one chip. The second substrate is overmolded and the first substrate is electrically connected to the second substrate by at least one first electrical connector. At least one second electrical connector extends from the second substrate through the overmold and has its exposed ends for electrical connection to an external module. The external module may be mounted to the first module in order to form a package on package assembly. | 06-23-2011 |
| 20110147909 | SEMICONDCUTOR CHIP STACK AND MANUFACTURING METHOD THEREOF - A semiconductor chip stack includes a first chip and a second chip. The first chip includes a first circuit formed in the first chip with a first integration density, and the second chip includes a second circuit in the second chip with a second integration density smaller than the first integration density. The first chip further includes at least a through-silicon via formed therein for electrically connecting the first chip and the second chip. | 06-23-2011 |
| 20110147910 | METHOD FOR STACKING DIE IN THIN, SMALL-OUTLINE PACKAGE - Several embodiments of microelectronic device packaging configurations with lead frames without downsets are disclosed herein. In one embodiment, the configuration includes a pair of microelectronic dies with active surfaces facing one another, and a lead frame positioned between the dies. The lead frame has no downset and extends from between the dies and protrudes out of an encapsulant material. In one embodiment the lead frame is connected to both an upper and a lower die. In other embodiments, the lead frame is connected to a first die by wirebonds and is not connected to a second die. The first and second die may be connected to one another by interconnects such as solder ball interconnects. | 06-23-2011 |
| 20110147911 | STACKABLE CIRCUIT STRUCTURES AND METHODS OF FABRICATION THEREOF - Stackable circuit structures and methods of fabrication are provided employing first level metallization directly on a chips-first layer(s), which includes: a chip(s), each with a pad mask over its upper surface and openings exposing its contact pads; electrically conductive structures; and structural dielectric material surrounding the side surfaces of the chips and the conductive structures. Each chips-first layer further includes a metallization layer on the front surface of the layer, residing at least partially on the pad mask and extending over an edge of the chip. Together, the pad mask and the structural material electrically isolate the metallization layer from the chip. Input/output interconnect structures physically and electrically contact the metallization layer over the front surface and/or the lower surfaces of the electrically conductive structures at the back surface of the chips-first layer, to facilitate input/output connection to chips of the layers in a stack. | 06-23-2011 |
| 20110156230 | MULTI-STACKED SEMICONDUCTOR DICE SCALE PACKAGE STRUCTURE AND METHOD OF MANUFACTURING SAME - A multi-stack semiconductor dice assembly has enhanced board-level reliability and integrated electrical functionalities over a common package foot-print. The multi-stack semiconductor dice assembly includes a bottom die having a stepped upper surface. The stepped upper surface includes a base region and a stepped region, which is raised relative to the base region. The base region includes a plurality of attachment structures that are sized and shaped to receive electrically conductive balls. An upper die is stacked above the bottom die. The upper die includes a plurality of attachment structures that are sized and shaped to receive electrically conductive balls and are arranged to align with the attachment structures of the bottom die. Electrically conductive balls are attached to the attachment structures of the bottom die and the attachment structures of the upper die. | 06-30-2011 |
| 20110156231 | Recessed and embedded die coreless package - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands. | 06-30-2011 |
| 20110156232 | SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR PACKAGE AND SYSTEM HAVING STACK-STRUCTURED SEMICONDUCTOR CHIPS - A module is disclosed. In one embodiment, the module is a memory module including a first multichip package, the first multichip package including a first master chip and a first plurality of slave chips, and a second multichip package, the second multichip package including a second master chip and a second plurality of slave chips. A first through via passes through the first master chip and electrically connects to the first master chip to provide a supply voltage to the first master chip. A second through via passes through the first master chip without being electrically connected to provide a supply voltage to the first master chip. A first set of additional through vias pass through respective ones of the first plurality of slave chips and electrically connect to the respective ones of the first plurality of slave chips, wherein the second through via and first set of additional through vias are aligned to form a first stack of through vias. A third through via passes through the second master chip and electrically connects to the second master chip to provide the supply voltage to the second master chip. A fourth through via passes through the second master chip without being electrically connected to provide a supply voltage to the second master chip. A second set of additional through vias passes through a respective one of the second plurality of slave chips and electrically connects to the respective one of the second plurality of slave chips, wherein the fourth through via and second set of additional through vias are aligned to form a second stack of through vias. A first port is electrically connected to the first and third through vias for providing the supply voltage to the first master chip and the second master chip, and a second port is electrically connected to the first and second stacks of through vias for providing the supply voltage to the first plurality of slave chips and the second plurality of slave chips. | 06-30-2011 |
| 20110156233 | STACK PACKAGE - A stack package includes a first semiconductor chip possessing a first size and one or more second semiconductor chips possessing a second size greater than the first size. The first semiconductor chip has a first surface on which bonding pads are disposed, a second surface which faces away from the first surface, and first through-electrodes which pass through the first surface and the second surface. The one or more second semiconductor chips are stacked on the second surface of the first semiconductor chip and have second through-electrodes which are electrically connected to the first through-electrodes. A molding part abuts one or more side surfaces of the first semiconductor chip such that a total size including the first size and a size of the molding part is equal to or greater than the second size. | 06-30-2011 |
| 20110169154 | MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Microelectronic devices and methods for manufacturing microelectronic devices are described herein. An embodiment of one such method includes attaching a plurality of singulated microelectronic dies to a removable support member with an active side of the individual dies facing toward the support member, depositing a flowable material onto the dies and a portion of the removable support member such that the flowable material covers a back side of the individual dies and is disposed between adjacent dies, and removing the support member from the active sides of the dies. | 07-14-2011 |
| 20110175215 | 3D CHIP STACK HAVING ENCAPSULATED CHIP-IN-CHIP - A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip is formed having second electrical devices. The second chip is then encapsulated within the recess of the first chip. Interconnects are then formed through the first chip into electrical communication with at least one of the second devices on the second chip. A three-dimensional (3D) chip is also provided in which a second chip is embedded within a first chip. | 07-21-2011 |
| 20110175216 | INTEGRATED VOID FILL FOR THROUGH SILICON VIA - A microelectronic assembly and related method of forming a through hole extending through a first wafer and a second wafer are provided. The first and second wafer have confronting faces and metallic features at the faces which are joined together to assemble the first and second wafers. A hole can be etched downwardly through the first wafer until a gap is partially exposed between the confronting faces of the first and second wafers. The hole can have a first wall extending in a vertical direction, and a second wall sloping inwardly from the first wall to an inner opening through which the interfacial gap is exposed. Material of the first or second wafers exposed within the hole can then be sputtered such that at least some of the sputtered material deposits onto at least one of the exposed confronting faces of the first and second wafers and provides a wall between the confronting faces. The method can include resuming etching the hole so as to extend the first wall fully through the first wafer, the wall between the wafers and into the second wafer, such that the wall of the hole extends continuously from the first wafer into the second wafer. An electrically conductive through silicon via can then be formed extending through the first wafer, the wall between the wafers and into the second wafer. | 07-21-2011 |
| 20110186977 | Semiconductor Device and Method of Forming Thin Profile WLCSP with Vertical Interconnect over Package Footprint - A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of a back surface of the second semiconductor die opposite the active surface is removed. Conductive pillars are formed around the second semiconductor die. TSVs can be formed through the first semiconductor die. An interconnect structure is formed over the back surface of the second semiconductor die, encapsulant, and conductive pillars. The interconnect structure is electrically connected to the conductive pillars. A portion of a back surface of the first semiconductor die opposite the active surface is removed. A heat sink or shielding layer can be formed over the back surface of the first semiconductor die. | 08-04-2011 |
| 20110186978 | STACK PACKAGE - A stack package includes a first semiconductor chip first pads and second pads disposed thereon and a second semiconductor chip having third pads and fourth pads electrically connected with the second pads disposed thereon. Capacitors are interposed between the first semiconductor chip and the second semiconductor chip, and include first electrodes electrically connected with the first pads to of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes. | 08-04-2011 |
| 20110193211 | Surface Preparation of Die for Improved Bonding Strength - A surface preparation method for improved adhesion in an electronic package system. The method of improving adhesion in the electronic package system includes depositing a passivation layer on a bonding surface and roughening at least a portion of the passivation layer. A coating material is deposited on the passivation layer. The bonding surface can be part of a semiconductor or package substrate. The roughening process can be performed by a chemical or mechanical process. In another embodiment, an electronic package system includes a bonding surface of a semiconductor or package substrate. A passivation layer is deposited on the bonding surface and a portion of the passivation layer is roughened for improved adhesion. A coating material is deposited on the roughened portion of the passivation layer. | 08-11-2011 |
| 20110193212 | Systems and Methods Providing Arrangements of Vias - A semiconductor chip includes an array of electrical contacts and multiple vias coupling at least one circuit in the semiconductor chip to the array of electrical contacts. A first one of the electrical contacts of the array of electrical contacts is coupled to N vias, and a second one of the electrical contacts of the array of electrical contacts is coupled to M vias. M and N are positive integers of different values. | 08-11-2011 |
| 20110193213 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor chip includes a main substrate supporting a semiconductor chip module, wherein the semiconductor module comprises at least two sub semiconductor chip modules each having a sub substrate in which a first semiconductor chip is embedded and at least two second semiconductor chips are stacked on the sub substrate. | 08-11-2011 |
| 20110193214 | SEMICONDUCTOR PACKAGE HAVING IMPROVED HEAT SPREADING PERFORMANCE - A semiconductor package having a structure in which heat produced in the interior of the package is effectively spread to the outside of the package is provided. The semiconductor package includes one or more semiconductor chips, one or more substrates (PCBs) having the semiconductor chips respectively attached thereto, a plurality of conductive balls such as a plurality of solder balls to provide voltages and signals to the one or more semiconductor chips, and a heat sink positioned to spread heat produced in the interior of the package to the outside and directly connected to at least one of the plurality of solder balls. | 08-11-2011 |
| 20110204504 | Reducing Susceptibility to Electrostatic Discharge Damage during Die-To-Die Bonding for 3-D Packaged Integrated Circuits - Mitigating electrostatic discharge damage when fabricating a 3-D integrated circuit package, wherein in one embodiment when a second tier die is placed in contact with a first tier die, conductive bumps near the perimeter of the second tier die that are electrically coupled to the substrate of the second tier die make contact with corresponding conductive bumps on the first tier die that are electrically coupled to the substrate of first tier die before other signal conductive bumps and power conductive bumps on the second tier and first tier dice make electrical contact. | 08-25-2011 |
| 20110204505 | Semiconductor Device and Method of Forming TMV and TSV in WLCSP Using Same Carrier - A semiconductor device has a semiconductor die mounted over a carrier. An encapsulant is deposited over the semiconductor die and carrier. An insulating layer is formed over the semiconductor die and encapsulant. A plurality of first vias is formed through the insulating layer and semiconductor die while mounted to the carrier. A plurality of second vias is formed through the insulating layer and encapsulant in the same direction as the first vias while the semiconductor die is mounted to the carrier. An electrically conductive material is deposited in the first vias to form conductive TSV and in the second vias to form conductive TMV. A first interconnect structure is formed over the insulating layer and electrically connected to the TSV and TMV. The carrier is removed. A second interconnect structure is formed over the semiconductor die and encapsulant and electrically connected to the TSV and TMV. | 08-25-2011 |
| 20110210436 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; attaching a base barrier on the base substrate adjacent a base perimeter thereof; mounting a stack substrate over the base substrate, the stack substrate having a stack substrate aperture with the stack substrate having an inter-substrate connector thereon; and dispensing a connector underfill through the stack substrate aperture encapsulating the inter-substrate connector, overflow of the connector underfill prevented by the base barrier. | 09-01-2011 |
| 20110215457 | Dummy TSV to Improve Process Uniformity and Heat Dissipation - In a stack of chips which each include active circuit regions, a plurality of through-silicon via (TSV) structures are formed for thermally conducting heat from the multi-chip stack by patterning, etching and filling with thermally conductive material a plurality of TSV openings in the multi-chip stack, including a first larger TSV opening that extends through substantially the entirety of the multi-chip stack without penetrating any active circuit region, and a second smaller TSV opening that extends down to but not through an active circuit region. | 09-08-2011 |
| 20110215458 | Semiconductor Device and Method of Forming Package-on-Package Structure Electrically Interconnected Through TSV in WLCSP - A semiconductor wafer has a plurality of semiconductor die. First and second conductive layers are formed over opposing surfaces of the semiconductor die, respectively. Each semiconductor die constitutes a WLCSP. A TSV is formed through the WLCSP. A semiconductor component is mounted to the WLCSP. The first semiconductor component is electrically connected to the first conductive layer. A first bump is formed over the first conductive layer, and a second bump is formed over the second conductive layer. An encapsulant is deposited over the first bump and first semiconductor component. A second semiconductor component is mounted to the first bump. The second semiconductor component is electrically connected to the first semiconductor component and WLCSP through the first bump and TSV. A third semiconductor component is mounted to the first semiconductor component, and a fourth semiconductor component is mounted to the third semiconductor component. | 09-08-2011 |
| 20110221053 | PRE-PROCESSING TO REDUCE WAFER LEVEL WARPAGE - A method for packaging a stacked integrated circuit (IC) includes pre-processing the stacked IC before releasing the stacked IC from the carrier wafer. Pre-processing reduces wafer warpage and simplifies the packaging process by dicing materials separately. Pre-processing may be performed on the first tier wafer of a stacked IC during manufacturing to partially or completely dice the first tier wafer into first tier dies before release from the carrier wafer. Pre-processing may also be performed by laser cutting the mold compound surrounding the first tier wafer and second tier dies before releasing the stacked IC from the carrier wafer. Openings in the first tier wafer and/or mold compound allows balancing of stresses in the packaging process and reduction of wafer warpage. | 09-15-2011 |
| 20110227209 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes: forming a base package including: fabricating a base package substrate having a component side and a system side, coupling a first integrated circuit die to the component side, and coupling stacking interconnects to the component side to surround the first integrated circuit die; forming a stacked integrated circuit package including: fabricating a stacked package substrate having a chip side, coupling a lower stacked integrated circuit die to the chip side, and attaching on a coupling side, of the stacked package substrate, the stacking interconnects; stacking the stacked integrated circuit package on the base package including the stacking interconnects of the stacked integrated circuit package on the stacking interconnects of the base package; and forming a stacked solder column by reflowing the stacked interconnects. | 09-22-2011 |
| 20110233747 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKING OPTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate having a component side and a system side; coupling a first integrated circuit die on the component side; coupling stacking interconnects on the component side around the first integrated circuit die; forming a package body on the component side, the first integrated circuit die, and the stacking interconnects; forming vertical insertion cavities through the package body and on the stacking interconnects; and forming a trench, in the package body, adjacent to the vertical insertion cavities for reducing a package warping stress. | 09-29-2011 |
| 20110241192 | Wafer-Level Semiconductor Device Packages with Stacking Functionality - Described herein are wafer-level semiconductor device packages with stacking functionality and related stacked package assemblies and methods. In one embodiment, a semiconductor device package includes a set of connecting elements disposed adjacent to a periphery of a set of stacked semiconductor devices. At least one of the connecting elements is wire-bonded to an active surface of an upper one of the stacked semiconductor devices. | 10-06-2011 |
| 20110241193 | Semiconductor Device Packages with Fan-Out and with Connecting Elements for Stacking and Manufacturing Methods Thereof - An embodiment of a semiconductor device package includes: (1) an interconnection unit including a patterned conductive layer; (2) an electrical interconnect extending substantially vertically from the conductive layer; (3) a semiconductor device adjacent to the interconnection unit and electrically connected to the conductive layer; (4) a package body: (a) substantially covering an upper surface of the interconnection unit and the device; and (b) defining an opening adjacent to an upper surface of the package body and exposing an upper surface of the interconnect; and (5) a connecting element electrically connected to the device, substantially filling the opening, and being exposed at an external periphery of the device package. The upper surface of the interconnect defines a first plane above a second plane defined by at least a portion of the upper surface of the interconnection unit, and below a third plane defined by the upper surface of the package body. | 10-06-2011 |
| 20110241194 | Stacked Semiconductor Device Package Assemblies with Reduced Wire Sweep and Manufacturing Methods Thereof - An embodiment of a stacked package assembly includes: (1) a first semiconductor device package including: (a) a semiconductor device including back and lateral surfaces; (b) a package body including an upper surface and substantially covering the back and lateral surfaces of the device; and (c) a first conductive contact adjacent to the upper surface of the body and electrically connected to the device; (2) a second semiconductor device package disposed above the upper surface of the body; (3) a conductive bump adjacent to the first contact and to the second device package; (4) a second conductive contact external to the first and the second device packages; and (5) a conductive wire electrically connecting the first and the second device packages to the second contact, a first end of the wire adjacent to the first contact and at least partially covered by the bump. | 10-06-2011 |
| 20110248396 | BOW-BALANCED 3D CHIP STACKING - A first set of semiconductor substrates includes semiconductor chips having bonding pads arranged in a primary pattern. A second set of semiconductor substrates includes semiconductor chips having bonding pads arranged in a mirror-image pattern. A first semiconductor substrate from the first set is bonded to a second semiconductor substrate from the second set such that each bonding pads is bonded to a mirror-image bonding pad. Additional substrates are bonded sequentially such that the bonded structure includes an even number of semiconductor substrates of which one half have bonding pads of the primary pattern and are bonded to the side of the first semiconductor substrate, while the other half have bonding pads of the mirror-image pattern and are bonded to the side of the second semiconductor substrate. The mirror-image patterns of the bonding pads enable maximal cancellation of wafer bow. | 10-13-2011 |
| 20110254145 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package provides an enhanced data storage capacity along with an improved data processing speed. The stacked semiconductor package includes a substrate having chip selection pads and a connection pad; a semiconductor chip module including a plurality of semiconductor chips including data bonding pads, a chip selection bonding pad, and data redistributions electrically connected with the data bonding pads and a data through electrode passing through the data bonding pad and connected with the data redistribution, the semiconductor chips being stacked so as to expose the chip selection bonding pad; and a conductive wire for connecting electrically the chip selection pad and the chip selection bonding pads. | 10-20-2011 |
| 20110266664 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: applying a conductive material on a support structure; providing a bottom integrated circuit package having a bottom lead extended therefrom; attaching the bottom lead to the conductive material; stacking a top integrated circuit package over the bottom integrated circuit package, the top integrated circuit package having a top lead extending therefrom and the top lead over the bottom lead; attaching a conductive paste at an end portion of the top lead; and forming a stacking joint by flowing the conductive paste and the conductive material, the stacking joint below the top lead as well as below and above the bottom lead. | 11-03-2011 |
| 20110278712 | Semiconductor Device and Method of Forming Perforated Opening in Bottom Substrate of Flipchip POP Assembly to Reduce Bleeding of Underfill Material - A semiconductor device has a flipchip semiconductor die mounted to a first substrate using a plurality of first bumps. An opening or plurality of openings is formed in the first substrate in a location central to placement of the flipchip semiconductor die to the first substrate. A plurality of semiconductor die is mounted to a second substrate. The semiconductor die are electrically connected with bond wires. An encapsulant is over the plurality of semiconductor die and second substrate. The second substrate is mounted to the first substrate with a plurality of second bumps. An underfill material is dispensed through the opening in the first substrate between the flipchip semiconductor die and first substrate. The dispensing of the underfill material is discontinued as the underfill material approaches or reaches a perimeter of the flipchip semiconductor die to reduce bleeding of the underfill material. The underfill material is cured. | 11-17-2011 |
| 20110285005 | PACKAGE SYSTEMS HAVING INTERPOSERS - A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure. | 11-24-2011 |
| 20110285006 | Semiconductor Package and Method for Making the Same - The present invention relates to a semiconductor package and method for making the same. The semiconductor package includes a silicon substrate unit, a bridge chip and at least one active chip. The silicon substrate unit has a cavity and a plurality of vias. The bridge chip is attached to the cavity and has a plurality of non-contact pads. The active chip is disposed above the bridge chip and has a plurality of non-contact pads and a plurality of conducting elements. The conducting elements of the active chip contact the vias of the silicon substrate unit, the non-contact pads of the active chip face but are not in physical contact with the non-contact pads of the bridge chip, so as to provide proximity communication between the active chip and the bridge chip. | 11-24-2011 |
| 20110285007 | Semiconductor Device and Method of Forming Ultra Thin Multi-Die Face-to-Face WLCSP - A semiconductor device has a first semiconductor die stacked over a second semiconductor die which is mounted to a temporary carrier. A plurality of bumps is formed over an active surface of the first semiconductor die around a perimeter of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. A plurality of conductive vias is formed through the encapsulant around the first and second semiconductor die. A portion of the encapsulant and a portion of a back surface of the first and second semiconductor die is removed. An interconnect structure is formed over the encapsulant and the back surface of the first or second semiconductor die. The interconnect structure is electrically connected to the conductive vias. The carrier is removed. A heat sink or shielding layer can be formed over the encapsulant and first semiconductor die. | 11-24-2011 |
| 20110298119 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes: forming a non-inverted internal stacking module including: fabricating an internal stacking module (ISM) substrate having an ISM component side and an ISM coupling side, coupling an internal stacking module integrated circuit to the ISM component side, coupling stacking structures, adjacent to the internal stacking module integrated circuit, on the ISM component side, and molding a stacking module body having a top surface that is coplanar with and exposes the stacking structures; forming a base package substrate under the non-inverted internal stacking module; coupling middle structures between the base package substrate and the ISM coupling side; and forming a base package body on the base package substrate, the middle structures, and the non-inverted internal stacking module including exposing the top surface of the stacking module body to be coplanar with the base package body. | 12-08-2011 |
| 20110304035 | Package On Package Having Improved Thermal Characteristics - Provided is a package on package (POP) having improved thermal and electric signal transmitting characteristics. The POP may include a first semiconductor package, a second semiconductor package larger than the first semiconductor package and mounted on the first semiconductor package, and a heat slug adhered to a bottom of a second substrate of the second semiconductor package and surrounding a side of the first semiconductor package. The heat slug may be a capacitor. | 12-15-2011 |
| 20120007227 | HIGH DENSITY CHIP STACKED PACKAGE, PACKAGE-ON-PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package including a protection layer, a plurality of semiconductor chips stacked on the protection layer, an inner encapsulant disposed on the protection layer to surround side surfaces of the semiconductor chips, and a terminal disposed to be buried in an upper portion of the inner encapsulant. Herein, each of the semiconductor chips includes an active surface, an inactive surface opposite to the active surface, and a chip pad disposed on a portion of the active surface, and an upper surface of the terminal is exposed from an upper surface of the inner encapsulant. | 01-12-2012 |
| 20120018868 | MICROELECTRONIC ELEMENTS HAVING METALLIC PADS OVERLYING VIAS - A microelectronic unit, an interconnection substrate, and a method of fabricating a microelectronic unit are disclosed. A microelectronic unit can include a semiconductor element having a plurality of active semiconductor devices therein, the semiconductor element having a first opening extending from a rear surface partially through the semiconductor element towards a front surface and at least one second opening, and a dielectric region overlying a surface of the semiconductor element in the first opening. The microelectronic unit can include at least one conductive interconnect electrically connected to a respective conductive via and extending away therefrom within the aperture. In a particular embodiment, at least one conductive interconnect can extend within the first opening and at least one second opening, the conductive interconnect being electrically connected with a conductive pad having a top surface exposed at the front surface of the semiconductor element. | 01-26-2012 |
| 20120025364 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device. | 02-02-2012 |
| 20120032318 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. Each layer portion includes a semiconductor chip. The plurality of second terminals are positioned to overlap the plurality of first terminals as viewed in a direction perpendicular to the top surface of the main body. A plurality of pairs of first and second terminals that are electrically connected via the wires include a plurality of pairs of a first terminal and a second terminal that are positioned not to overlap each other. | 02-09-2012 |
| 20120080782 | METHOD OF MANUFACTURING LAYERED CHIP PACKAGE - A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. The first and second terminals are formed by using electrodes of the first and second layer portions. The layered chip package is manufactured by fabricating a layered substructure by stacking two substructures each of which includes an array of a plurality of preliminary layer portions, and then cutting the layered substructure. The layered substructure includes a plurality of preliminary wires that are disposed between two adjacent pre-separation main bodies and are to become the plurality of wires. | 04-05-2012 |
| 20120098114 | Device with mold cap and method thereof - A device including a substrate; at least one semiconductor die on a first side of the substrate; and a mold cap molded on portions of the first side of the substrate and on lateral sides of the at least one semiconductor die. The mold cap is not molded onto a top side of the at least one semiconductor die. | 04-26-2012 |
| 20120153450 | SELF-ORGANIZING NETWORK WITH CHIP PACKAGE HAVING MULTIPLE INTERCONNECTION CONFIGURATIONS - In general, embodiments of the present invention provide a chip package with multiple TSV configurations. Specifically, the chip package typically includes a backend layer (e.g., metal interconnect layer); a substrate coupled to the backend layer; a set (at least one) of backend side interconnects extending (e.g., angularly) from a side surface of the backend layer to a bottom surface of the backend layer; a set of optional vertical TSVs extending from a top surface of the backend layer through the substrate; and a network organizer positioned in the substrate organizer for handling communications made using the set of backend side interconnects and the set of vertical TSVs. A set of connections (e.g., controlled collapse chip connections (C4s) can be positioned adjacent to any of the vias to provide connectively to other hardware elements such as additional chip packages, buses, etc. Among other things, the use of backend side interconnects allows maximum surface area of the chip package to be utilized and provides increased reliability. These advantages are especially realized when used in conjunction with vertical TSVs. | 06-21-2012 |
| 20120199963 | Package-on-Package Using Through-Hole Via Die on Saw Streets - A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package. | 08-09-2012 |
| 20120199964 | ELECTRONIC DEVICE HAVING STACK-TYPE SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure. | 08-09-2012 |
| 20120241935 | PACKAGE-ON-PACKAGE STRUCTURE - A package-on-package structure includes first and second package structures and bumps. The first package structure includes a carrier, a chip configured on the carrier, a heat spreader, and an encapsulant. The chip is electrically connected to the carrier through conductive wires. The heat spreader includes a support portion located on the chip and connection portions located respectively at two opposite sides of the support portion. The heat spreader has a circuit layer thereon, covers the chip and the conductive wires, and electrically connects the carrier through the circuit layer on the connecting portions. The encapsulant encapsulates the chip, the conductive wires, a portion of the heat spreader, and a portion of the carrier. The bumps are configured on the support portion. The second package structure is configured on the first package structure and is electrically connected to the first package structure through the bumps. | 09-27-2012 |
| 20120299173 | Thermally Enhanced Stacked Package and Method - A package-on-package (PoP) device is provided. The device includes a first package with a first chip mounted on a first substrate, a heat spreader stacked on the first package, the heat spreader in thermal contact with the first chip, and a second package stacked on the heat spreader. In an embodiment, the heat spreader is formed using carbon fibers to provide good lateral thermal conductivity. In an embodiment, ends of the heat spreader project beyond a periphery of the first and second packages. | 11-29-2012 |
| 20130075887 | STACKED SEMICONDUCTOR DEVICE - Provided is a stacked semiconductor device ( | 03-28-2013 |
| 20130082372 | Package on Packaging Structure and Methods of Making Same - A package on packaging structure provides for improved thermal conduction and mechanical strength by the introduction of a sold thermal coupler between the first and second packages. The first package has a first substrate and through vias through the first substrate. A first set of conductive elements is aligned with and coupled to the through vias of the first substrate. A solid thermal coupler is coupled to the first set of conductive elements and to a die of the second package. A second set of conductive elements is coupled to the die and a bottom substrate is coupled to the second set of conductive elements. The thermal coupler may be, e.g., an interposer, a heat spreader, or a thermal conductive layer. | 04-04-2013 |
| 20130093073 | HIGH THERMAL PERFORMANCE 3D PACKAGE ON PACKAGE STRUCTURE - A package on package (PoP) structure is disclosed. The PoP structure includes a top package and a bottom package disposed thereunder. The top package includes a first substrate and a first die mounted onto the first substrate. The first substrate has a thermal conductivity which is more than 70 W/(mĆK). The bottom package includes a second substrate and a second die mounted onto the second substrate. An upper surface of the second die is in thermal contact with a lower surface of the first substrate. | 04-18-2013 |
| 20130161808 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - Disclosed herein are a semiconductor package and a method of manufacturing the same. According to a preferred embodiment of the present invention, the semiconductor package includes: a first package having a first semiconductor element mounted on an upper portion thereof and at least one solder ball formed on a lower portion thereof; a second package stacked on the upper portion of the first package; and an interposer formed between the first package and the second package. | 06-27-2013 |
| 20130270685 | PACKAGE-ON-PACKAGE ELECTRONIC DEVICES INCLUDING SEALING LAYERS AND RELATED METHODS OF FORMING THE SAME - A package-on-package (POP) electronic device may include first and second packaging substrates, a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates, and first and second sealing layers between the first and second packaging substrates. The first and second sealing layers may be respective first and second epoxy sealing layers. Moreover, the second epoxy sealing layer may include a solder flux agent, and the first epoxy sealing layer may have a lower concentration of the solder flux agent than the second epoxy sealing layer. | 10-17-2013 |
| 20140021596 | WAFER-LEVEL DEVICE PACKAGING - The present invention relates to a semiconductor device packaged at the wafer level such that an entire packaged device is formed prior to separation of individual devices. The semiconductor device package includes a semiconductor chip having one or more bonding pads associated with the chip and a protective layer bonded over the semiconductor chip. An insulation layer is positioned on at least side edges and a lower surface of the semiconductor chip. Interconnection/bump metallization is positioned adjacent one or more side edges of the semiconductor chip and is electrically connected to at least one bonding pad. A compact image sensor package can be formed that is vertically integrated with a digital signal processor and memory chip along with lenses and a protective cover. | 01-23-2014 |
| 20140027895 | THREE-DIMENSIONAL MOUNTING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THREE-DIMENSIONAL MOUNTING SEMICONDUCTOR DEVICE - A three-dimensional mounting semiconductor device includes a layer structure including a plurality of first substrates with a trench-shaped concavity formed in and a plurality of second substrates with semiconductor elements formed in, which are alternately stacked, wherein an unevenness defined by a size difference between the first substrate and the second substrate is formed on a side surface, and a first through-hole are defined by an inside surface of the trench-shaped concavity and a surface of the second substrate, and a third substrate jointed to the side surface of the layer structure and having an unevenness formed on a surface jointed to the layer structure which are engaged with the unevenness formed on the side surface of the layer structure. | 01-30-2014 |
| 20140042608 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package is provided with a package on package (PoP) configuration, and which may be implemented having a fine pitch. The semiconductor package can include a lower printed circuit board (PCB) having a top surface onto which at least one lower semiconductor chip is attached; an upper printed circuit board (PCB) disposed on the lower printed circuit board (PCB) and having a top surface onto which at least one upper semiconductor chip is attached; and a lower mold layer formed on the top surface of the lower printed circuit board (PCB) so as to be disposed between the lower printed circuit board (PCB) and the upper printed circuit board (PCB). A through via hole, including a first section formed in the lower mold layer and a second section formed on the first section can also be provided. The through via hole extends through the lower mold layer, and a solder layer is formed in the through via hole to electrically connect the upper printed circuit board (PCB) and the lower printed circuit board (PCB). A horizontal cross-sectional area of the first section of the through via hole varies over substantially an entire height of the first section, and a horizontal cross-sectional area of the second section gradually decreases from a top surface thereof toward an inner portion of the lower mold layer. | 02-13-2014 |
| 20140061887 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of semiconductor chips to be mutually bonded via a bonding resin; a sealing resin to seal the plurality of semiconductor chips; and an anchor to be disposed in a first semiconductor chip included by the plurality of semiconductor chips and to seize the bonding resin. | 03-06-2014 |
| 20140145322 | ELECTRONIC COMPONENT PACKAGE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are an electronic component package and a method of manufacturing the same. The electronic component package includes: a substrate; a connection member provided on at least one surface of the substrate; an active element coupled to the substrate by the connection member; and a molding part covering an exposed surface of the active element, wherein the molding part is formed of a first material having a coefficient of thermal expansion of 8 to 15 ppm/Ā° C. and thermal conductivity of 1 to 5 W/mĀ° C. Therefore, warpage may be significantly decreased and heat radiation performance of the active element may be improved, as compared with the case of implementing the molding part using an EMC according to the related art. | 05-29-2014 |
| 20140159222 | CHIP-EMBEDDED PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE USING THE PCB, AND MANUFACTURING METHOD OF THE PCB - A chip-embedded printed circuit board (PCB), a semiconductor package using the PCB, and a manufacturing method of the chip-embedded PCB. The semiconductor package using a chip-embedded printed circuit board (PCB) includes upper and lower semiconductor packages having a package on package (PoP) structure, wherein the lower semiconductor package includes a base substrate including predetermined circuit patterns formed therein; an electronic component electrically connected to the circuit pattern and embedded in the base substrate such that one surface thereof is exposed to an upper surface of the base substrate; and a heat dissipation member installed on an exposed surface of the electronic component to dissipate heat generated from the electronic component to the outside. | 06-12-2014 |
| 20140197529 | METHODS OF FABRICATING PACKAGE STACK STRUCTURE AND METHOD OF MOUNTING PACKAGE STACK STRUCTURE ON SYSTEM BOARD - A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate. | 07-17-2014 |
| 20140231979 | STACKED ASSEMBLY OF A MEMS INTEGRATED DEVICE HAVING A REDUCED THICKNESS - An assembly of a MEMS integrated device envisages: a package having a base substrate with a main surface in a horizontal plane, and a coating set on the base substrate; a first body including semiconductor material and integrating a micromechanical structure, housed within the package on the base substrate; at least one second body including semiconductor material and integrating at least one electronic component, designed to be functionally coupled to the micromechanical structure, the first body and the second body being arranged within the package stacked in a vertical direction transverse to the horizontal plane. In particular, at least one between the first body and the base substrate defines a first recess, in which the second body is housed, at least in part. | 08-21-2014 |
| 20140264810 | Packages with Molding Material Forming Steps - A package includes a first package component having a top surface, a second package component bonded to the top surface of the first package component, and a plurality of electrical connectors at the top surface of the first package component. A molding material is over the first package component and molding the second package component therein. The molding material includes a first portion overlapping the second package component, wherein the first portion includes a first top surface, and a second portion encircling the first portion and molding bottom portions of the plurality of electrical connectors therein. The second portion has a second top surface lower than the first top surface. | 09-18-2014 |
| 20140264811 | Package-On-Package with Cavity in Interposer - A package includes an interposer, which includes a core dielectric material, a through-opening extending from a top surface to a bottom surface of the core dielectric material, a conductive pipe penetrating through the core dielectric material, and a device die in the through-opening. The device die includes electrical connectors. A top package is disposed over the interposer. A first solder region bonds the top package to the conductive pipe, wherein the first solder region extends into a region encircled by the conductive pipe. A package substrate is underlying the interposer. A second solder region bonds the package substrate to the interposer. | 09-18-2014 |
| 20140264812 | SEMICONDUCTOR PACKAGE ASSEMBLY - The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first body having a first device-attach surface and a first bump-attach surface opposite to the first device-attach surface. A second semiconductor package is bonded to the first device-attach surface of the first semiconductor package. The second package includes a second body having a second device-attach surface and a second bump-attach surface opposite to the second device-attach surface. A dynamic random access memory (DRAM) device is mounted on the second device-attach surface. A decoupling capacitor is mounted on the second device-attach surface. Conductive structures are disposed on the second bump-attach surface of the second package, connecting to the first bump-attach surface of the first body of the first semiconductor package. | 09-18-2014 |
| 20140291830 | SEMICONDUCTOR PACKAGES HAVING PACKAGE-ON-PACKAGE STRUCTURES - A semiconductor package includes a lower package with a lower semiconductor chip on a lower package substrate, and an upper package with an upper semiconductor chip on an upper package substrate. The upper semiconductor chip has a plurality of chip pads and the upper package substrate has a plurality of substrate pads. The upper package is stacked on the lower package. The chip pads have a first pitch and the substrate pads have a second pitch greater than the first pitch. The upper package substrate has a plurality of connection lines that electrically connect the substrate pads to the chip pads. | 10-02-2014 |
| 20140312481 | INTEGRATED CIRCUIT PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stacked integrated circuit package and a method for manufacturing the same are provided. | 10-23-2014 |
| 20140319668 | HIGH THERMAL PERFORMANCE 3D PACKAGE ON PACKAGE STRUCTURE - A package on package (PoP) structure is disclosed. The PoP structure comprises a top package and a bottom package disposed thereunder. The top package comprises a first substrate and a first die mounted onto the first substrate. At least one electrically floating pad is disposed on a lower surface of the first substrate. The bottom package comprises a second substrate and a second die mounted onto the second substrate. An upper surface of the second die is in thermal contact with the electrically floating pad. | 10-30-2014 |
| 20140332946 | SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A to semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip. | 11-13-2014 |
| 20140367839 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor package, a second semiconductor package, and a package-connecting member. The first semiconductor package includes a first substrate, a chip stacking portion disposed on the first substrate and including a plurality of first semiconductor chips, and a first sealant for surrounding the chip stacking portion on the first substrate. The second semiconductor package includes a second substrate, at least one second semiconductor chip disposed on the second substrate, and a second sealant for surrounding the second semiconductor chip on the second substrate. The package-connecting member electrically connects the first semiconductor package and the second semiconductor package. The plurality of first semiconductor chips include a first chip including through silicon vias (TSVs) and a second chip electrically connected to the first chip via the TSVs, and the chip stacking portion includes an internal sealant for filling a space between the first chip and the second chip and extending to a side of the second chip. | 12-18-2014 |
| 20140374894 | PACKAGE ON PACKAGE STRUCTRUE AND METHOD FOR MANUFACTURING SAME - A package on package structure includes a connection substrate having a main body and electrically conductive posts, the main body includes a first surface and an opposite second surface, and each electrically conductive post passes through the first and second surfaces, and each end of the two ends of the electrically conductive post protrudes from the main body; a first package device arranged on a side of the first surface of the connection substrate; a package adhesive arranged on a side of the second surface of the connection substrate; and a second package device arranged on a side of the package adhesive furthest away from the first package device. | 12-25-2014 |
| 20150076679 | SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING FACE-TO-FACE SEMICONDUCTOR DICE AND RELATED METHODS - Methods of manufacturing semiconductor device assemblies include attaching a back side of a first semiconductor die to a substrate and structurally and electrically coupling a first end of laterally extending conductive elements to conductive terminals on or in a surface of the substrate. Second ends of the laterally extending conductive elements are structurally and electrically coupled to bond pads on or in an active surface of the first semiconductor die. Conductive structures are structurally and electrically coupled to bond pads of a second semiconductor die. At least some of the conductive structures are aligned with at least some of the bond pads of the first semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. At least some of the conductive structures are structurally and electrically coupled to at least some of the bond pads of the first semiconductor die. | 03-19-2015 |
| 20150091149 | STACK-TYPE SEMICONDUCTOR PACKAGE - According to example embodiments, a stack-type semiconductor package includes a lower semiconductor package, an upper semiconductor package, connection pads, and a metal layer pattern. The lower semiconductor package includes a lower semiconductor chip on a top surface of a lower package substrate, lower lands on the lower package substrate, and an encapsulant on the top surface of the lower package substrate. The encapsulant defines via holes that expose the lower lands. The upper semiconductor package is on the encapsulant. Upper solder balls are connected to a bottom surface of the upper semiconductor package. The connection pads are on the via holes and the encapsulant. The connection pads electrically connect the lower semiconductor package to the upper semiconductor package. The metal layer pattern is between the lower package substrate and the upper semiconductor package. The metal layer pattern surrounds the connection pads and is isolated from the connection pads. | 04-02-2015 |
| 20150091150 | PACKAGE ON PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabricating a POP structure is disclosed. First, a first package is provided, which has: a dielectric layer; a stacked circuit layer embedded in the dielectric layer and exposed from upper and lower surfaces of the dielectric layer; a plurality of conductive posts and a semiconductor chip disposed on the upper surface of the dielectric layer and electrically connected to the stacked circuit layer; and an encapsulant formed on upper surface of the dielectric layer for encapsulating the semiconductor chip and the conductive posts and having a plurality of openings for exposing top ends of the conductive posts. Then, a second package is disposed on the encapsulant and electrically connected to the conductive posts. The formation of the conductive posts facilitates to reduce the depth of the openings of the encapsulant, thereby reducing the fabrication time and increasing the production efficiency and yield. | 04-02-2015 |
| 20150130040 | High Density Microelectronics Packaging - Example packaging of microelectronics and example methods of manufacturing the same are provided herein. The packaging can enable and/or improve the use of the microelectronics in a downhole, high temperature and/or high pressure setting. The microelectronics packaging can include double-sided active components, heat sinks, and/or three-dimensional stacking of dies. | 05-14-2015 |
| 20150130041 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are semiconductor packages and methods of fabricating the same. The method may include, stacking a lower semiconductor chip on a lower package substrate, forming a lower molding layer on the lower package substrate, forming a connecting through-hole and an element through-hole by performing a laser drilling process on the lower molding layer, and stacking an upper package substrate having a bottom surface to which a passive element is bonded on the lower package substrate to insert the passive element into the element through-hole. | 05-14-2015 |
| 20150348951 | SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR ELEMENTS - A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element, wherein the surfaces of each of the plurality of first conductive structures and the plurality of second conductive structures include aluminum; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures. | 12-03-2015 |
| 20150364457 | Wafer Leveled Chip Packaging Structure and Method Thereof - A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias. | 12-17-2015 |
| 20150380391 | PACKAGING SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND CHIP PACKAGING STRUCTURE HAVING SAME - A packaging substrate includes a circuit board, a number of first conductive posts, and a number of second conductive posts. The circuit board includes a first base and a first conductive pattern layer formed on a first surface of the first base. The first conductive posts extend from and are electrically connected to the first conductive pattern layer. The second conductive posts extend from and are electrically connected to the first conductive pattern layer. The height of each of the second conductive posts is larger than that of each of the first conductive posts. A manufacturing method thereof is also provided. | 12-31-2015 |
| 20160005698 | SEMICONDUCTOR PACKAGES HAVING RESIDUAL STRESS LAYERS AND METHODS OF FABRICATING THE SAME - A semiconductor package is provided. The semiconductor includes a lower package and an upper package stacked on the lower package. The lower package includes a package substrate, a semiconductor chip, a mold layer and a residential stress layer. The package substrate has upper and lower surfaces. The semiconductor chip is disposed on the upper surface of the package substrate. The mold layer encapsulates the semiconductor chip. The residual stress layer is disposed on the semiconductor chip. The residual stress layer includes a plastically deformed surface. The residual stress layer has a residual stress to counterbalance warpage of the lower package. | 01-07-2016 |
| 20160013151 | MICROELECTRONIC ASSEMBLIES WITH INTEGRATED CIRCUITS AND INTERPOSERS WITH CAVITIES, AND METHODS OF MANUFACTURE | 01-14-2016 |
| 20160027764 | SEMICONDUCTOR PACKAGE STACK STRUCTURE HAVING INTERPOSER SUBSTRATE - Provided is a semiconductor package stack structure. The semiconductor package stack structure includes a lower semiconductor package, an interposer substrate disposed on the lower semiconductor package and having a horizontal width greater than a horizontal width of the lower semiconductor package, an upper semiconductor package disposed on the interposer substrate, and underfill portions filling a space between the lower semiconductor package and the interposer substrate and surround side surfaces of the lower semiconductor package. | 01-28-2016 |
| 20160035656 | RECONFIGURABLE PoP - A microelectronic package ( | 02-04-2016 |
| 20160035664 | SEMICONDUCTOR PACKAGE ON PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME - A package on package structure may be formed by fabricating or providing a bottom package having a substrate, at least one die on top of the substrate, and bonding pads on the top of the substrate. Next, a frame is formed on the bonding pads and connected to the bonding pads. Next, a package material is molded over the top of the substrate to encapsulate the frame, the die, and the pads or substantially encapsulates these components. Next, a portion of the molded package material is removed to expose at least a portion of the frame. The exposed frame portions are formed such that a desired fan in or fan out configuration is obtained. Next, a non-conductive layer is formed on the exposed frame. Last, a second package having a die or chip is connected to the exposed portion of the frame to form a package on package structure. | 02-04-2016 |
| 20160035711 | STACKED PACKAGE-ON-PACKAGE MEMORY DEVICES - 3D Stacked memory devices with copper pillars electrically connecting the package units are disclosed. A stacked package-on-package memory device includes a base chip package unit having a logic processing chip disposed on a base substrate; and a memory chip stack overlying the base chip unit. The memory chip stack includes a stack of packaged memory units. Each packaged memory unit including a memory chip on an IC substrate. Copper pillars are disposed on the back side of the IC substrate and electrically connected to the base substrate. | 02-04-2016 |
| 20160079213 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package including a first printed circuit board and a second printed circuit board is provided. The first printed circuit board may include a first surface upon which a first semiconductor chip is mounted and a second surface upon which at least one connecting structure is attached. The first printed circuit board may further include at least one thermal via and a heat sink and the at least one thermal via and the heat sink may be disposed under the first semiconductor chip with the heat sink being disposed between the first surface and the second surface. The second printed circuit board may include a third surface upon which a second semiconductor chip is mounted. The second printed circuit board may be disposed under the first printed circuit board with the at least one connecting structure connecting the first printed circuit board to the second printed circuit board. | 03-17-2016 |
| 20160079214 | BVA INTERPOSER - A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds. | 03-17-2016 |
| 20160086901 | Bump-on-Trace Structures with High Assembly Yield - A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace having a trace width measured in a direction perpendicular to a lengthwise direction of the first metal trace. The first package component further includes a second metal trace at the surface of the first package component. The first metal trace and the second metal trace are parallel to each other. A second package component is overlying the first package component, wherein the second package component includes a metal bump. A solder region bonds the metal bump to the first metal trace, wherein the solder region contacts a top surface and sidewalls of the first portion of the first metal trace. A ratio of a volume of the solder region to the trace width is between about 1,100 Ī¼m | 03-24-2016 |
| 20160111396 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A method of fabricating a package-on-package (PoP) type of semiconductor package may include providing a lower package with a lower substrate, a lower semiconductor chip, and a lower mold layer and providing an upper package with an upper substrate, an upper semiconductor chip, and an upper mold layer. A through hole is formed to penetrate the upper package, and the upper package and lower package are electrically connected. A thermal interface material is injected into the through hole to form a first heat transmission part between, and in contact with, the upper package and the lower package. | 04-21-2016 |
| 20160133600 | MICROELECTRONIC ASSEMBLIES WITH INTEGRATED CIRCUITS AND INTERPOSERS WITH CAVITIES, AND METHODS OF MANUFACTURE - Semiconductor integrated circuits ( | 05-12-2016 |
| 20160133613 | SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE HAVING HEAT DISSIPATION - A semiconductor package is provided. The semiconductor package include a lower semiconductor package including a lower package substrate and a lower semiconductor chip mounted thereon, and an upper semiconductor package provided on the lower semiconductor package to include an upper package substrate and an upper semiconductor chip mounted thereon. The upper package substrate include an upper heat-dissipation pattern, the lower semiconductor chip include a first via connected to the upper heat-dissipation pattern through the lower semiconductor chip, and the first via may provide a pathway for dissipating heat generated in the lower semiconductor chip. | 05-12-2016 |
| 20160155722 | Vertical system integration | 06-02-2016 |
| 20160155728 | STACKED PACKAGING USING RECONSTITUTED WAFERS | 06-02-2016 |
| 20160172344 | LOW PROFILE REINFORCED PACKAGE-ON-PACKAGE SEMICONDUCTOR DEVICE | 06-16-2016 |
| 20160181231 | SOLUTION FOR REDUCING POOR CONTACT IN INFO PACKAGES | 06-23-2016 |
| 20160190107 | CHIP PACKAGE-IN-PACKAGE - An electronic package includes an interposer, a die attached to a first side of the interposer, an embedded electronic package attached to a second side of the interposer, an encapsulation compound, a set of vias providing electrical paths from a first side of the electronic package to the interposer through the encapsulation compound, and a redistribution layer electrically redistributing the set of vias to form a set of interconnect-pads. Either the die or the embedded electronic package, or both, are electrically connected to the interposer. | 06-30-2016 |
| 20160197063 | SEMICONDUCTOR PACKAGE WITH PACKAGE-ON-PACKAGE STACKING CAPABILITY AND METHOD OF MANUFACTURING THE SAME | 07-07-2016 |
| 20160379965 | Package Structure and Method for Forming Same - A device comprises a bottom package comprising an interconnect structure, a molding compound layer over the interconnect structure, a semiconductor die in the molding compound layer and a solder layer embedded in the molding compound layer, wherein a top surface of the solder layer is lower than a top surface of the molding compound layer and a top package bonded on the bottom package through a joint structure formed by the solder layer and a bump of the top package. | 12-29-2016 |
| 20190148345 | DUMMY TSV TO IMPROVE PROCESS UNIFORMITY AND HEAT DISSIPATION | 05-16-2019 |
