| Entries |
| Document | Title | Date |
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| 20080197456 | Substrate polishing method, semiconductor device and fabrication method therefor - A substrate polishing method, a semiconductor device and a fabrication method for a semiconductor device are disclosed by which high planarization polishing can be achieved. In the substrate polishing method, two or more different slurries formed from ceria abrasive grains having different BET values from each other are used to carry out two or more stages of chemical-mechanical polishing processing of a polishing object oxide film on a substrate to flatten the polishing object film. | 08-21-2008 |
| 20080217746 | INSULATING FILM - An insulating film for semiconductor devices is obtained by curing, on a substrate, a high molecular compound obtained by polymerizing a cage-type silsesquioxane compound having two or more unsaturated groups as substituents and having a cyclic siloxane structure, wherein the structure of the cage-type silsesquioxane compound is not broken by curing, and the breakage of the cage structure can be detected by observing a peak at approximately 610 cm | 09-11-2008 |
| 20080230875 | DUV LASER ANNEALING AND STABILIZATION OF SiCOH FILMS - A method of fabricating a dielectric film comprising atoms of Si, C, O and H (hereinafter SiCOH) that has improved insulating properties as compared with prior art dielectric films, including prior art SiCOH dielectric films that are not subjected to the inventive deep ultra-violet (DUV) is disclosed. The improved properties include reduced current leakage which is achieved without adversely affecting (increasing) the dielectric constant of the SiCOH dielectric film. In accordance with the present invention, a SiCOH dielectric film exhibiting reduced current leakage and improved reliability is obtained by subjecting an as deposited SiCOH dielectric film to a DUV laser anneal. The DUV laser anneal step of the present invention likely removes the weakly bonded C from the film, thus improving leakage current. | 09-25-2008 |
| 20080237811 | METHOD FOR PRESERVING PROCESSING HISTORY ON A WAFER - A method for capturing process history includes performing at least a first process for forming features on a semiconducting substrate. A first cap is formed over a first region of the semiconducting substrate after performing the first process. At least a second process is performed for forming the features in a second region other than the first region while leaving the first cap in place to thereby prevent the features in the first region covered by the first cap from being exposed to the second process. A first characteristic of a first feature is measured in the first region, and a second characteristic of a second feature in the second region is measured. A wafer includes a first partially completed feature disposed in a first region. A first cap is formed above the first partially completed feature. A second partially completed feature is disposed in a second region of the wafer different than the first region. The second partially completed feature is at a later stage of completion than the first partially completed feature. | 10-02-2008 |
| 20080246124 | PLASMA TREATMENT OF INSULATING MATERIAL - A method is disclosed which includes forming an opening in an insulating material, performing a plasma process to introduce nitrogen into a portion of the insulating material to thereby form a nitrogen-containing region at least on an inner surface of the opening, and, after forming the nitrogen-containing region, performing an etching process through the opening. A device is disclosed which includes an insulating material comprising a nitrogen-enhanced region that is proximate an opening that extends through the insulating material and a conductive structure positioned within the opening. | 10-09-2008 |
| 20080251892 | INSULATING FILM FOR SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention relates to a polymeric compound comprising, as structural units, groups each represented by the following general formula (1); and an insulating film for a semiconductor integrated circuit which comprises the polymeric compound: —R | 10-16-2008 |
| 20080258270 | Mgo-Based Coating for Electrically Insulating Semiconductive Substrates and Production Method Thereof - The present invention relates to a magnesium oxide-based (MgO) inorganic coating intended to electrically insulate semiconductive substrates such as silicon carbide (SiC), and to a method for producing such an insulating coating. The method of the invention comprises the steps of preparing a treatment solution of at least one hydrolysable organomagnesium compound and/or of at least one hydrolysable magnesium salt, capable of forming a homogeneous polymer layer of magnesium oxyhydroxide by hydrolysis/condensation reaction with water; depositing the treatment solution of the hydrolysable organomagnesium compound or of the hydrolysable magnesium salt, onto a surface to form a magnesium oxide-based layer; and densifying the layer formed at a temperature of less than or equal to 1000° C. | 10-23-2008 |
| 20080265380 | METHOD FOR FABRICATING A HIGH-K DIELECTRIC LAYER - One inventive aspect relates to a method for fabricating a high-k dielectric layer. The method comprises depositing onto a substrate a layer of a high-k dielectric material having a first thickness. The high-k dielectric material has a bulk density value and the first thickness is so that the high-k dielectric layer has a density of at least the bulk density value of the high-k dielectric material minus about 10%. The method further comprises thinning the high-k dielectric layer to a second thickness. Another inventive aspect relates to a semiconductor device comprising a high-k dielectric layer as fabricated by the method. | 10-30-2008 |
| 20080265381 | SiCOH DIELECTRIC - A porous composite material useful in semiconductor device manufacturing, in which the diameter (or characteristic dimension) of the pores and the pore size distribution (PSD) is controlled in a nanoscale manner and which exhibits improved cohesive strength (or equivalently, improved fracture toughness or reduced brittleness), and increased resistance to water degradation of properties such as stress-corrosion cracking, Cu ingress, and other critical properties is provided. The porous composite material is fabricating utilizing at least one bifunctional organic porogen as a precursor compound. | 10-30-2008 |
| 20080283972 | Silicon Compounds for Producing Sio2-Containing Insulating Layers on Chips - The present invention relates to a process for producing an SiO | 11-20-2008 |
| 20080283973 | INTEGRATED CIRCUIT INCLUDING A DIELECTRIC LAYER AND METHOD - An integrated circuit including a dielectric layer and a method for producing an integrated circuit. In one embodiment, a dielectric layer is deposited in a process atmosphere. The process atmosphere includes a first starting component at a first point in time, a second starting component at a second point in time and a third starting component at a third point in time. The third starting component includes a halogen. | 11-20-2008 |
| 20080283974 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed herein is a semiconductor device including a gate insulating film formed over a semiconductor substrate, and a gate electrode formed over the gate insulating film, wherein the gate insulating film is so provided as to protrude from both sides of the gate electrode, and the gate electrode includes a wholly silicided layer. | 11-20-2008 |
| 20080290472 | SEMICONDUCTOR INTERLAYER-INSULATING FILM FORMING COMPOSITION, PREPARATION METHOD THEREOF, FILM FORMING METHOD, AND SEMICONDUCTOR DEVICE - Provided is a porous-film-forming composition containing silicon-oxide-based fine particles and a polysiloxane compound obtained by hydrolysis and condensation reactions, in the presence of an acid catalyst, of a hydrolyzable silane compound containing at least one tetrafunctional alkoxysilane compound represented by the following formula (1): | 11-27-2008 |
| 20080290473 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, in which a substrate is disposed in a chamber and a fluorine-containing silicon oxide film is formed on the substrate using a plasma CVD process. The fluorine-containing silicon oxide film is formed such that the release of fluorine from this silicon oxide layer is suppressed. According to this semiconductor device manufacturing method, a stable semiconductor device can be provided such that the device includes a fluorine-containing silicon oxide film (FSG film) at which the release of fluorine is suppressed, and thus peeling does not occur. | 11-27-2008 |
| 20080303119 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a metal oxide on a semiconductor substrate, forming a gate electrode film on the metal oxide, and executing a thermal treatment on the semiconductor substrate provided with the metal oxide and the gate electrode film to crystallize the metal oxide. | 12-11-2008 |
| 20090001524 | GENERATION AND DISTRIBUTION OF A FLUORINE GAS - Molecular fluorine may be generated and distributed on-site at a fabrication facility. A molecular fluorine generator may come in a variety of sizes to fit better the needs of the particular fabrication facility. The generator may service one process tool, a plurality of process tool along a process bay, the entire fabrication facility, or nearly any other configuration within the facility. The process can obviate the need and inherent risks with transporting or handling gas cylinders. The process can be used in conjunction with a cleaning or fabrication operation used in the electronics fabrication industry. | 01-01-2009 |
| 20090008751 | Method for Producing an Area having Reduced Electrical Conductivity Within a Semiconductor Layer and Optoelectronic Semiconductor Element - In a method for producing at least at least one area ( | 01-08-2009 |
| 20090008752 | Ceramic Thin Film On Various Substrates, and Process for Producing Same - The process of Polymer Assisted Chemical Vapor Deposition (PACVD) and the semiconductor, dielectric, passivating or protecting thin films produced by the process are described. A semiconductor thin film of amorphous silicon carbide is obtained through vapor deposition following desublimation of pyrolysis products of polymeric precursors in inert or active atmosphere. PA-CVD allows one or multi-layers compositions, microstructures and thicknesses to be deposited on a wide variety of substrates. The deposited thin film from desublimation is an n-type semiconductor with a low donor concentration in the range of 10 | 01-08-2009 |
| 20090014845 | FILM-FORMING COMPOSITION | 01-15-2009 |
| 20090026587 | GRADIENT DEPOSITION OF LOW-K CVD MATERIALS - A dielectric layer for a semiconductor device having a low overall dielectric constant, good adhesion to the semiconductor substrate, and good resistance to cracking due to thermal cycling. The dielectric layer is made by a process involving continuous variation of dielectric material deposition conditions to provide a dielectric layer having a gradient of dielectric constant. | 01-29-2009 |
| 20090026588 | Plasma processing method for forming a film and an electronic component manufactured by the method - A plasma processing method for forming a film on a substrate using a gas processed by a plasma. The plasma processing method for forming a film includes the steps of forming a CF film on the substrate by using a C | 01-29-2009 |
| 20090039474 | Formation Method of Porous Insulating Film, Manufacturing Apparatus of Semiconductor Device, Manufacturing Method of Semiconductor Device, and Semiconductor Device - In a formation method of a porous insulating film by supplying at least organosiloxane and an inert gas to a reaction chamber and forming an insulating film by a plasma vapor deposition method, a partial pressure of the organosiloxane in the reaction chamber is changed by varying a volume ratio of the organosiloxane and the inert gas to be supplied during deposition. Thus, the dielectric constant of the insulating film in the semiconductor device is reduced while the adhesion of the insulating film with other materials is improved. It is desirable that the organosiloxane be cyclic organosiloxane including at least silicon, oxygen, carbon, and hydrogen, and that the total pressure of the reaction chamber be constant during deposition. | 02-12-2009 |
| 20090039475 | Apparatus and Method for Manufacturing Semiconductor - To provide a semiconductor manufacturing apparatus which is able to improve insulation film. | 02-12-2009 |
| 20090039476 | Apparatus and method for selectively recessing spacers on multi-gate devices - Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed. | 02-12-2009 |
| 20090072356 | High-Heat-Resistant Semiconductor Device - In a wide gap semiconductor device of SiC or the like used at a temperature of 150 degrees centigrade or higher, the insulation characteristic of a wide gap semiconductor element is improved and a high-voltage resistance is achieved. For these purposes, a synthetic high-molecular compound, with which the outer surface of the wide gap semiconductor element is coated, is formed in a three-dimensional steric structure which is formed by linking together organosilicon polymers C with covalent bonds resulting from addition reaction. The organosilicon polymers C have been formed by linking at least one organosilicon polymers A having a crosslinked structure using siloxane (Si—O—Si combination) with at least one organosilicon polymers B having a linear linked structure using siloxane through siloxane bonds. | 03-19-2009 |
| 20090079040 | Semiconductor structure with coincident lattice interlayer - A semiconductor structure consistent with certain implementations has a crystalline substrate oriented with a {111} plane surface that is within 10 degrees of surface normal. An epitaxially grown electrically insulating interlayer overlays the crystalline substrate and establishes a coincident lattice that mates with the surface symmetry of the {111} plane surface. An atomically stable two dimensional crystalline film resides on the epitaxial insulating layer with a coincident lattice match to the insulating interlayer. Methods of fabrication are disclosed. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract. | 03-26-2009 |
| 20090085171 | OXIDE FILM FORMATION METHOD AND IMAGE SENSING APPARATUS - An oxide film formation method comprises steps of: generating a plasma from a gas mixture containing an inert gas and an oxidizing gas whose mixing ratio to the inert gas is higher than 0, and is 0.007 or lower; and forming an oxide film on a surface of a silicon substrate by using the plasma. | 04-02-2009 |
| 20090085172 | Deposition Method, Deposition Apparatus, Computer Readable Medium, and Semiconductor Device - A deposition method includes steps of placing a substrate on a susceptor in a process chamber; supplying to the process chamber a source gas including an organic compound and a plasma gas for facilitating activation of the source gas into plasma; evacuating the process chamber to a reduced pressure; generating plasma of the plasma gas and the source gas in the process chamber to deposit a barrier film including carbon on the substrate; and applying high frequency bias electric power to the susceptor during the plasma generating step. | 04-02-2009 |
| 20090096067 | METHOD OF FABRICATING A METAL OXYNITRIDE THIN FILM THAT INCLUDES A FIRST ANNEALING OF A METAL OXIDE FILM IN A NITROGEN-CONTAINING ATMOSPHERE TO FORM A METAL OXYNITRIDE FILM AND A SECOND ANNEALING OF THE METAL OXYNITRIDE FILM IN AN OXIDIZING ATMOSPHERE - After the surface of the substrate is cleaned, an interface layer or an antidiffusion film is formed. A metal oxide film is built upon the antidiffusion film. Annealing is done in an NH | 04-16-2009 |
| 20090102025 | Semiconductor device and method for manufacturing the same, dry-etching process, method for making electrical connections, and etching apparatus - A method for manufacturing a semiconductor device comprises dry-etching a thin film using a resist mask carrying patterns in which at least one of the width of each pattern and the space between neighboring two patterns ranges from 32 to 130 nm using a halogenated carbon-containing compound gas with the halogen being at least two members selected from the group consisting of F, I and Br. The ratio of at least one of I and Br is not more than 26% of the total amount of the halogen atoms as expressed in terms of the atomic compositional ratio to transfer the patterns onto the thin film. Such etching of a thin film avoids causing damage to the resist mask used. The resulting thin film carrying the transferred patterns is used as a mask for subjecting the underlying material to dry-etching. | 04-23-2009 |
| 20090108413 | Interlayer Insulating Film, Interconnection Structure, and Methods of Manufacturing the Same - This invention provides an interlayer insulating film for a semiconductor device, which has low permittivity, is free from the evolution of gas such as CFx and SiF | 04-30-2009 |
| 20090108414 | WAFER - A wafer has a rare earth oxide layer disposed, typically sprayed, on a substrate. It is useful as a dummy wafer in a plasma etching or deposition system. | 04-30-2009 |
| 20090115029 | Semiconductor substrate and method for manufacturing the same, and method for manufacturing semiconductor device - A semiconductor substrate is irradiated with accelerated hydrogen ions, thereby forming a damaged region including a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated, so that the single crystal semiconductor substrate is separated in the damaged region. A single crystal semiconductor layer which is separated from the single crystal semiconductor substrate is irradiated with a laser beam. The single crystal semiconductor layer is melted by laser beam irradiation, whereby the single crystal semiconductor layer is recrystallized to recover its crystallinity and to planarized a surface of the single crystal semiconductor layer. After the laser beam irradiation, the single crystal semiconductor layer is heated at a temperature at which the single crystal semiconductor layer is not melted, so that the lifetime of the single crystal semiconductor layer is improved | 05-07-2009 |
| 20090115030 | N2 BASED PLASMA TREATMENT FOR ENHANCED SIDEWALL SMOOTHING AND PORE SEALING OF POROUS LOW-K DIELECTRIC FILMS - A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner. | 05-07-2009 |
| 20090127669 | METHOD FOR FORMING INTERLAYER DIELECTRIC FILM, INTERLAYER DIELECTRIC FILM, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS - A method for forming an interlayer dielectric film by a plasma CVD method, including turning off a radio frequency power and purging with an inert gas simultaneously. | 05-21-2009 |
| 20090127670 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME AND MASK PATTERN FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate; and an insulating layer formed on at least a main surface of the semiconductor substrate; wherein a contact hole is formed at the insulating layer so as to expose the main surface of the semiconductor substrate through the insulating layer so that a cross section of the contact hole parallel to the main surface of the semiconductor substrate is shaped rectangularly. | 05-21-2009 |
| 20090146264 | THIN FILM TRANSISTOR ON SODA LIME GLASS WITH BARRIER LAYER - The present invention generally comprises a low cost TFT and a method of manufacturing a TFT. For TFTs, soda lime glass would be an attractive alternative to non-alkali glass, but a soda lime glass substrate will permit sodium to diffuse into the active layer and degrade the performance of the TFT. Substrates comprising a polyimide, because they are flexible, would also be attractive to utilize instead of non-alkali glass substrates, but the plastic substrates permit carbon to diffuse into the active layer. By depositing a silicon rich barrier layer over the soda lime glass substrate or substrate comprising a polyimide, both sodium and carbon diffusion may be reduced. Thus, a lower cost TFT may be produced with a soda lime glass substrate or a substrate comprising a polyimide as compared to a non-alkali glass substrate. | 06-11-2009 |
| 20090146265 | ULTRA LOW k PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION PROCESSES USING A SINGLE BIFUNCTIONAL PRECURSOR CONTAINING BOTH A SiCOH MATRIX FUNCTIONALITY AND ORGANIC POROGEN FUNCTIONALITY - A method for fabricating a SiCOH dielectric material comprising Si, C, O and H atoms from a single organosilicon precursor with a built-in organic porogen is provided. The single organosilicon precursor with a built-in organic porogen is selected from silane (SiH | 06-11-2009 |
| 20090152686 | Film Forming Method for Dielectric Film - The present invention is a film forming method for an SiOCH film, comprising a unit-film-forming step including: a deposition step of depositing an SiOCH film element by using an organic silicon compound as a raw material and by using a plasma CVD method; and a hydrogen plasma processing step of providing a hydrogen plasma process to the deposited SiOCH film element, wherein the unit-film-forming step is repeated several times so as to form an SiOCH film on a substrate. | 06-18-2009 |
| 20090152687 | METHOD OF OPENING PAD IN SEMICONDUCTOR DEVICE - A method of opening a pad in a semiconductor device. A protective film on a pad may be etched with a pad opening pattern as a mask. Dielectric heating may be performed on the pad opened by etching the protective film. Organic material containing C and F groups on the pad may be removed by heating with molecular vibration and/or microwaves, which may substantially prevent and/or minimize corrosion. | 06-18-2009 |
| 20090174040 | SACRIFICIAL PILLAR DIELECTRIC PLATFORM - Briefly, in accordance with one or more embodiments, a dielectric platform is at least partially formed in a semiconductor substrate and extending at least partially below a surface of a semiconductor substrate. The dielectric platform may include structural pillars formed by backfilling a first plurality of cavities etched in the substrate, and a second plurality of cavities formed by etching away sacrificial pillars disposed between the structural pillars. The second plurality of cavities may be capped to hermetically seal the second plurality of cavities to impart the dielectric constant of the material contained therein, for example air, to the characteristic dielectric constant of the dielectric platform. Alternatively, the second plurality of cavities may be backfilled with a material having a lower dielectric constant than the substrate, for example silicon dioxide where the substrate comprises silicon. | 07-09-2009 |
| 20090179306 | ADVANCED LOW k CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES - A carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. In some embodiments, the dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen. The carbon-rich silicon carbide-like dielectric film can be used as a dielectric cap layer in an interconnect structure. The inventive dielectric film is highly robust to UV curing and remains compressively stressed after UV curing. Moreover, the inventive dielectric film has good oxidation resistance and prevents metal diffusion into an interconnect dielectric layer. The present invention also provides an interconnect structure including the inventive dielectric film as a dielectric cap. A method of fabricating the inventive dielectric film is also provided. | 07-16-2009 |
| 20090179307 | INTEGRATED CIRCUIT SYSTEM EMPLOYING FEED-FORWARD CONTROL - An integrated circuit system that includes: providing a substrate and a material layer; measuring a parameter of the material layer; and correlating the thickness of an anti-reflective layer to the measured parameter of the material layer for critical dimension control. | 07-16-2009 |
| 20090189258 | METHOD OF INTEGRATED CIRCUIT FABRICATION - A method for fabricating an integrated circuit including forming a first trench in a rear side of a semiconductor wafer, wherein the first trench has a depth extending partially through a thickness of the semiconductor wafer, coating the rear side with a layer of coating material, including filling the first trench with the coating material, and forming a second trench in a front side of the semiconductor wafer, wherein the second trench is aligned with and has a width less than a width of the first trench, and wherein the second trench has a depth extending at least through a remaining portion of the semiconductor wafer so as to be in communication with the coating material filling the first trench. | 07-30-2009 |
| 20090200646 | One-Dimensional Arrays of Block Copolymer Cylinders and Applications Thereof - Methods for fabricating sublithographic, nanoscale microstructures in one-dimensional arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. | 08-13-2009 |
| 20090206453 | Method for Preparing Modified Porous Silica Films, Modified Porous Silica Films Prepared According to This Method and Semiconductor Devices Fabricated Using the Modified Porous Silica Films - A hydrophobic compound having at least one each of hydrophobic group (an alkyl group having 1 to 6 carbon atoms or a —C | 08-20-2009 |
| 20090224373 | Integrated circuit and method for manufacturing same - When an integrated circuit having an interlayer insulation film built up on top of a wiring layer is subjected to a heat treatment, it is unlikely that a void formed in the interlayer insulation film will rupture in a portion wherein are connected a narrow gap between wirings and a wide open part contiguous therewith. A corner part of a wiring positioned at a portion where a gap and an open part are connected is chamfered, and an end part of the gap is shaped so as to widen toward the open part. Providing the widening end part in the gap thus mitigates any discontinuity in the built up interlayer insulation film between the gap and the open part. As a result, the interlayer insulation film does not readily seal off an end of a void formed in the gap. | 09-10-2009 |
| 20090230515 | INSULATED GATE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A well region in which an insulated gate semiconductor element is formed is a diffusion region, and an impurity concentration of the well region is lower toward its bottom portion. This leads to a problem of increased resistance. Therefore, particularly, an insulated gate semiconductor element having an up-drain structure has a problem of increased on-resistance. A p type well region is formed by stacking two p type impurity regions on one another. The p type impurity regions are allowed to serve as the p type well region by sequentially stacking n type semiconductor layers, on one another, having p type impurities implanted into their surfaces and simultaneously diffusing the impurities by heat treatment. In this way, it is possible to obtain the p type well region in which an impurity concentration sufficient to secure a desired breakdown voltage is maintained approximately uniform up to a desired depth. | 09-17-2009 |
| 20090243048 | METALLIC NANOCRYSTAL ENCAPSULATION - A method of forming a device includes forming protective shells about metallic nanocrystals supported by a substrate. The metallic nanocrystals having protective shells are encapsulated with a layer formed with process parameters that are not compatible with the integrity of unprotected metallic nanocrystals. | 10-01-2009 |
| 20090256243 | LOW K INTERCONNECT DIELECTRIC USING SURFACE TRANSFORMATION - Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement of at least one void formed within the solid structure which lowers an effective dielectric constant of the insulator structure. One aspect is a method of forming a low-k insulator structure. In one embodiment, an insulator material is deposited, and a predetermined arrangement of at least one hole is formed in a surface of the insulator material. The insulator material is annealed such that the low-k dielectric material undergoes a surface transformation to transform the arrangement of at least one hole into predetermined arrangement of at least one empty space below the surface of the insulator material. Other aspects are provided herein. | 10-15-2009 |
| 20090261459 | SEMICONDUCTOR DEVICE HAVING A FLOATING BODY WITH INCREASED SIZE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device with a silicon on insulator substrate having a stacked structure including a silicon substrate, a filled oxide layer, and a silicon layer is provided with a fin pattern formed in the direction of the channel width in a gate forming region of the silicon layer. The fin pattern has a width that is wider at the lower end portion of the fin pattern than the width of the upper end portion. A gate is formed to cover the fin pattern, and junction regions are formed within the silicon layer at both sides of the gate. | 10-22-2009 |
| 20090273061 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR SUBSTRATE - A double-structure silicon on insulator (SOI) substrate with a silicon layer, an insulation film (silicon oxide film), a silicon layer, and an insulation film in this order from the side of the surface. The upper-layer insulation film is formed so as to have a uniform distribution of depth while the lower-layer insulation film is formed so as to have a non-uniform distribution of depth so that a thick portion may be formed in the silicon layer along a predetermined path. The refractive index of Si is 3.5 and the refractive index of SiO | 11-05-2009 |
| 20090294919 | METHOD OF FORMING A FINFET AND STRUCTURE - A method for processing a substrate comprising at least a buried oxide (BOX) layer and a semiconductor material layer is provided. The method includes etching the semiconductor material layer to form a vertical semiconductor material structure overlying the BOX layer, leaving an exposed portion of the BOX layer. The method further includes exposing a top surface of the exposed portion of the BOX layer to an oxide etch resistant species to form a thin oxide etch resistant layer overlying the exposed portion of the BOX layer. | 12-03-2009 |
| 20090294920 | METHOD FOR FORMING DUAL HIGH-K METAL GATE USING PHOTORESIST MASK AND STRUCTURES THEREOF - Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N | 12-03-2009 |
| 20090294921 | SEMICONDUCTOR DEVICE COMPRISING METAL LINES WITH A SELECTIVELY FORMED DIELECTRIC CAP LAYER - A dielectric cap layer of a sophisticated metallization system may be provided in a locally restricted manner so as to enable direct contact of the dielectric material of one metallization layer with a low-k dielectric material of a subsequent metallization layer, which may thus provide enhanced adhesion and overall mechanical integrity. | 12-03-2009 |
| 20090294922 | ORGANIC SILICON OXIDE FINE PARTICLE AND PREPARATION METHOD THEREOF, POROUS FILM-FORMING COMPOSITION, POROUS FILM AND FORMATION METHOD THEREOF, AND SEMICONDUCTOR DEVICE - Provided is an organic silicon oxide fine particle capable of satisfying an expected dielectric constant and mechanical strength and having excellent chemical stability for obtaining a high-performance porous insulating film. More specifically, provided is an organic silicon oxide fine particle comprising a core comprising an inorganic silicon oxide or a first organic silicon oxide containing an organic group having a carbon atom directly attached to a silicon atom and, and a shell on or above an outer circumference of the core, the shell comprising a second organic silicon oxide different from the first organic silicon oxide which the second organic silicon has been formed by hydrolysis and condensation, in the presence of a basic catalyst, of a shell-forming component comprising an organic-group-containing hydrolyzable silane containing an organic group having a carbon atom directly attached to a silicon atom or a mixture of the organic-group-containing hydrolyzable silane and an organic-group-free hydrolyzable silane not having the organic group, wherein a ratio [C]/[Si] is 0 or greater but less than 1 in the core and 1 or greater 1 in the shell wherein [C] represents the number of all the carbon atoms and [Si] represents the number of all the silicon atoms. | 12-03-2009 |
| 20090302433 | METHOD FOR MODIFYING HIGH-K DIELECTRIC THIN FILM AND SEMICONDUCTOR DEVICE - There is provided a method for modifying a high-k dielectric thin film provided on the surface of an object using a metal organic compound material. The method includes a preparation process for providing the object with the high-k dielectric thin film formed on the surface thereof, and a modification process for applying UV rays to the highly dielectric thin film in an inert gas atmosphere while maintaining the object at a predetermined temperature to modify the high-k dielectric thin film. According to the above constitution, the carbon component can be eliminated from the high-k dielectric thin film, and the whole material can be thermally shrunk to improve the density, whereby the occurrence of defects can be prevented and the film density can be improved to enhance the specific permittivity and thus to provide a high level of electric properties. | 12-10-2009 |
| 20090302434 | Preparation of Lanthanide-Containing Precursors and Deposition of Lanthanide-Containing Films - Methods and compositions for depositing rare earth metal-containing layers are described herein. In general, the disclosed methods deposit the precursor compounds comprising rare earth-containing compounds using deposition methods such as chemical vapor deposition or atomic layer deposition. The disclosed precursor compounds include a cyclopentadienyl ligand having at least one aliphatic group as a substituent and an amidine ligand. | 12-10-2009 |
| 20090309195 | Low Dielectric Constant Silicon Coating, Method for the Preparation and Application thereof to Integrated Circuits - The present invention concerns a process for the preparation of a silicone coating of low dielectric constant, comprising the following essential steps:
| 12-17-2009 |
| 20090309196 | SURFACE-HYDROPHOBICIZED FILM, MATERIAL FOR FORMATION OF SURFACE-HYDROPHOBICIZED FILM, WIRING LAYER, SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - A surface-hydrophobicized film is provided which is in contact with an insulating film, and has a higher hydrophobicity than the insulating film at the time of the contact, and which is in contact, on an opposite side of the surface-hydrophobicized film, with wiring, and contains at least one atom selected from the group consisting of sulfur atoms, phosphorus atoms and nitrogen atoms. Semiconductor devices with wiring layers having a low leakage current, a high EM resistance and a high TDDB resistance can be manufactured by using the film. | 12-17-2009 |
| 20090321894 | Multi-functional linear siloxane compound, a siloxane polymer prepared from the compound, and a process for forming a dielectric film by using the polymer - A novel multi-functional linear siloxane compound, a siloxane polymer prepared from the siloxane compound, and a process for forming a dielectric film by using the siloxane polymer. The linear siloxane polymer has enhanced mechanical properties (e.g., modulus), superior thermal stability, a low carbon content and a low hygroscopicity and is prepared by the homopolymerization of the linear siloxane compound or the copolymerization of the linear siloxane compound with another monomer. A dielectric film can be produced by heat-curing a coating solution containing the siloxane polymer which is highly reactive. The siloxane polymer prepared from the siloxane compound not only has satisfactory mechanical properties, thermal stability and crack resistance, but also exhibits a low hygroscopicity and excellent compatibility with pore-forming materials, which leads to a low dielectric constant. Furthermore, the siloxane polymer retains a relatively low carbon content but a high SiO | 12-31-2009 |
| 20100019356 | Semiconductor device and manufacturing method therefor - The present invention relates to a semiconductor device. The semiconductor device includes a fluorocarbon film formed on a substrate and a film containing metal formed on the fluorocarbon film, wherein the content amount of fluorine atom on the fluorocarbon film, which contacts the film containing metal, is in a predetermined range. | 01-28-2010 |
| 20100032813 | IC FORMED WITH DENSIFIED CHEMICAL OXIDE LAYER - A semiconductor device, such as an integrated circuit, has an oxide chemically grown on a silicon surface, and densified by annealing at, e.g., 950° C. for 4 to 5 seconds in an N | 02-11-2010 |
| 20100052114 | CYCLIC SILOXANE COMPOUND, A MATERIAL FOR FORMING SI-CONTAINING FILM, AND ITS USE - The present invention has the objects to provide a novel material for forming Si-containing film, especially a material containing a cyclic siloxane compound suitable to a PECVD equipment for low dielectric constant insulating film, and to provide an Si-containing film using the same, and a semiconductor device containing those films. The present invention relates to a material for forming Si-containing film, containing a cyclic siloxane compound represented by the following general formula (1) | 03-04-2010 |
| 20100052115 | Volatile Precursors for Deposition of C-Linked SiCOH Dielectrics - Disclosed herein are precursors and methods for their use in the manufacture of semiconductor, photovoltaic, TFT-LCD, or flat panel type devices. | 03-04-2010 |
| 20100072581 | COMPOSITION FOR FILM FORMATION, INSULATING FILM, SEMICONDUCTOR DEVICE, AND PROCESS FOR PRODUCING THE SEMICONDUCTOR DEVICE - According to one aspect of the present invention, there is provided a composition for film formation, comprising a compound represented by general formula (I) or a hydrolyzed-dehydrocondensation product thereof: | 03-25-2010 |
| 20100090321 | HIGH-K ETCH STOP LAYER OF REDUCED THICKNESS FOR PATTERNING A DIELECTRIC MATERIAL DURING FABRICATION OF TRANSISTORS - By providing a high-k dielectric etch stop material as an etch stop layer for patterning an interlayer dielectric material, enhanced performance and higher flexibility may be achieved since, for instance, an increased amount of highly stressed dielectric material may be positioned more closely to the respective transistors due to the reduced thickness of the high-k dielectric etch stop material. | 04-15-2010 |
| 20100096733 | PROCESS FOR FABRICATING A SUBSTRATE COMPRISING A DEPOSITED BURIED OXIDE LAYER - A process for fabricating a substrate that includes a buried oxide layer for the production of electronic components or the like. The process includes depositing an oxide layer or a nitride layer on either of a donor or receiver substrate, and bringing the donor and receiver substrates into contact; conducting at least a first heat treatment of the oxide or nitride layer before bonding the substrates, and conducting a second heat treatment of the fabricated substrate of the receiver substrate, the oxide layer and all or part of the donor substrate at a temperature equal to or higher than the temperature applied in the first heat treatment. Substrates that have an oxide or nitride layer deposited thereon wherein the oxide or nitride layer is degassed and has a refractive index smaller than the refractive index of an oxide or nitride layer of the same composition formed by thermal growth. | 04-22-2010 |
| 20100109130 | METHOD OF FORMING AN OXIDE THIN FILM - A thin oxide film is formed by atomic layer deposition (ALD) onto a substrate by exposing the substrate to a first precursor comprising a metal organic alkoxide or amide or heteroleptic derivatives thereof and subsequently exposing the substrate to a second precursor comprising an ALD compatible carboxylic acid or carboxyl acid derivative compound. The sequential exposure to the first and second precursors may be repeated until a sufficient film thickness of an oxide of the metal has been deposited on the substrate. This process allows growth of an oxide thin film or nanostructure, on any suitable substrate. It permits formation of a high-κ dielectric oxide thin film on the substrate with similar dielectric properties to a much thinner SiO | 05-06-2010 |
| 20100123221 | BACKSIDE NITRIDE REMOVAL TO REDUCE STREAK DEFECTS - Exemplary embodiments provide a method for fabricating an integrated circuit (IC) device with reduced streak defects. In one embodiment, the IC device structure can be formed having a first pad oxide-based layer on a front side of a semiconductor substrate and having an oxide-nitride-based structure on a backside of the semiconductor substrate. The IC device structure can be etched to remove a nitride-related material from the backside oxide-nitride-based structure, and further to remove the first pad oxide-based layer from the front side of the semiconductor substrate. On the removed front side of the semiconductor substrate a second pad oxide-based layer can be formed, e.g., for forming an isolation structure for device component or circuitry isolation. | 05-20-2010 |
| 20100123222 | PROCESS FOR FABRICATING A CHARGE STORAGE LAYER OF A MEMORY CELL - A process for fabricating a charge storage layer comprising metal particles of a memory cell, said layer consisting of an organic layer comprising, on the surface, said metal particles, said process comprising the following steps: (a) a step of grafting, onto a metallic, semiconductor or electrically insulating substrate, an organic layer comprising, on the surface, groups capable of complexing at least one metallic element in cationic form; (b) a step of bringing said layer into contact with a solution comprising said metallic element in cationic form, by means of which said metallic element is complexed by said abovementioned groups; and (c) a step of reducing said complexed metallic element to the metallic element in oxidation state 0, by means of which metal particles are obtained. | 05-20-2010 |
| 20100123223 | METHOD OF MANUFACTURING POROUS INSULATING FILM, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group. | 05-20-2010 |
| 20100140754 | FILM-FORMING MATERIAL, SILICON-CONTAINING INSULATING FILM AND METHOD FOR FORMING THE SAME - Disclosed is a silicon-containing film-forming material which contains an organosilane compound represented by the following general formula (1). (In the formula, R1-R4 may be the same or different and represent a hydrogen atom, an alkyl group having 1-4 carbon atoms, a vinyl group or a phenyl group; R5 represents an alkyl group having 1-4 carbon atoms, an acetyl group or a phenyl group; n represents an integer of 1-3; and m represents an integer of 1-2.) | 06-10-2010 |
| 20100140755 | Rare-earth oxides, rare-earth nitrides, rare-earth phosphides and ternary alloys - Fabrication of new forms of rare-earth oxides, rare-earth nitrides and rare-earth phosphides is disclosed. Further, ternary compounds composed of binary (rare-earth oxides, rare-earth nitrides and rare-earth phosphides) mixed with silicon and or germanium to form compound semiconductors. The presented growth techniques and material system can be applied to silicon electronics, opto-electronic, magneto-electronics and magneto-optics devices. | 06-10-2010 |
| 20100148322 | COMPOSITE SUBSTRATE AND METHOD OF FABRICATING THE SAME - The invention specifically relates to methods of fabricating a composite substrate by providing a first insulating layer on a support substrate at a thickness of e | 06-17-2010 |
| 20100155907 | SEMICONDUCTOR DEVICE HAVING AN INORGANIC COATING LAYER APPLIED OVER A JUNCTION TERMINATION EXTENSION - A semiconductor device includes an inorganic coating layer to at least partially cover a junction termination extension. | 06-24-2010 |
| 20100164072 | PLASMA CVD APPARATUS, METHOD FOR FORMING THIN FILM AND SEMICONDUCTOR DEVICE - A plasma CVD apparatus including a reaction chamber including an inlet for supplying a compound including a borazine skeleton, a feeding electrode, arranged within the reaction chamber, for supporting a substrate and being applied with a negative charge, and a plasma generating mechanism, arranged opposite to the feeding electrode via the substrate, for generating a plasma within the reaction chamber. A method forms a thin film wherein a thin film is formed by using a compound including a borazine skeleton as a raw material, and a semiconductor device includes a thin film formed by such a method as an insulating film. The apparatus and method enable to produce a thin film wherein low dielectric constant and high mechanical strength are stably maintained for a long time and insulating characteristics are secured. | 07-01-2010 |
| 20100164073 | ELECTRICAL PASSIVATION OF SILICON-CONTAINING SURFACES USING ORGANIC LAYERS - Electrical structures and devices may be formed and include an organic passivating layer that is chemically bonded to a silicon-containing semiconductor material to improve the electrical properties of electrical devices. In different embodiments, the organic passivating layer may remain within finished devices to reduce dangling bonds, improve carrier lifetimes, decrease surface recombination velocities, increase electronic efficiencies, or the like. In other embodiments, the organic passivating layer may be used as a protective sacrificial layer and reduce contact resistance or reduce resistance of doped regions. The organic passivation layer may be formed without the need for high-temperature processing. | 07-01-2010 |
| 20100171198 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, SEMICONDUCTOR MANUFACTURING APPARATUS AND STORAGE MEDIUM - A method for manufacturing a semiconductor device includes steps of:(a) forming a thin film containing a phenyl group and silicon on a substrate while obtaining a plasma by activating an organic silane gas containing a phenyl group and silicon and nitrogen as not original component but unavoidable impurity and exposing the substrate to the plasma, temperature of the substrate being set at 200° C. or lower; and (b) obtaining a low-permittivity film by supplying energy to the substrate to allow moisture to be released from the thin film. With this method for manufacturing the semiconductor device, it is possible to obtain a silicon-oxide based low-permittivity film containing an organic substance which is not significantly damaged by the release of the organic substance when subjected to a plasma treatment such as an etching treatment, an ashing treatment, and/or the like. | 07-08-2010 |
| 20100181654 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, INSULATING FILM FOR SEMICONDUCTOR DEVICE, AND MANUFACTURING APPARATUS OF THE SAME - An object to provide an insulating film for a semiconductor device, which has characteristics of low permittivity, a low leak current, and high mechanical strength, undergoes small time-dependent change of these characteristics, and has excellent water resistance, and to provide a manufacturing apparatus of the same, and a manufacturing method of the semiconductor device using the insulating film. The production process comprises a film forming step of supplying a mixed gas containing a carrier gas and a raw material gas, which is a gasified material having borazine skeletal molecules, into a chamber, causing the mixed gas to be in a plasma state, applying a bias to the substrate placed in the chamber, and carrying out gas-phase polymerization by using the borazine skeletal molecule as a fundamental unit so as to form the insulating film on the substrate; and a reaction promoting step of, after the film forming step, bringing the bias applied to the substrate to a different magnitude from the bias in the film forming step, supplying the mixed gas while gradually reducing only the raw material gas, which is the gasified material having the borazine skeletal molecules, treating the insulating film with a plasma mainly comprising the carrier gas. | 07-22-2010 |
| 20100200964 | METHOD OF PRODUCING A POROUS DIELECTRIC ELEMENT AND CORRESPONDING DIELECTRIC ELEMENT - A porous dielectric element is produced by forming a first dielectric and a second dielectric. The second dielectric is dispersed in the first dielectric. The second dielectric is then removed from the second dielectric by using a chemical dissolution. The removal of the second dielectric from the first dielectric leaves pores in the first dielectric. The pores, which are filled with air, improve the overall dielectric constant of the resulting dielectric element. | 08-12-2010 |
| 20100213581 | DIELECTRIC FILM WITH LOW COEFFICIENT OF THERMAL EXPANSION (CTE) USING LIQUID CRYSTALLINE RESIN - An embodiment of the present invention is a technique to provide a dielectric film material with controllable coefficient of thermal expansion (CTE). A first compound containing a first liquid crystalline component is formed. The first compound is cast into a first film. The first film is oriented in an magnetic or electromagnetic field in a first direction. The first film is cured at a first temperature. | 08-26-2010 |
| 20100219512 | Method for Forming Porous Insulating Film and Semiconductor Device - A method for forming porous insulating film using cyclic siloxane raw material monomer is provided, which method suppresses detachment of hydrocarbon and is able to form a low-density film. | 09-02-2010 |
| 20100237476 | Low dielectric constant films and manufacturing method thereof, as well as electronic parts using the same - While a fine porous diamond particle film has been known as a high heat resistant and low dielectric constant film and also has high mechanical strength and heat conductivity, and is expected as an insulating film for multi-layered wirings in semiconductor integrated circuit devices, it is insufficient in current-voltage characteristic and has not yet been put into practical use. According to the invention, by treating the fine porous diamond particle film with an aqueous solution of a salt of a metal such as barium and calcium, the carbonate or sulfate of which is insoluble or less soluble, and a hydrophobic agent such as hexamethyl disilazane or trimethyl monochlolo silane, as well as a reinforcing agent containing one of dichlorotetramethyl disiloxane or dimethoxytetramethyl disiloxane, thereby capable of putting the dielectric breakdown voltage and the leak current within a specified range of a practical standard. | 09-23-2010 |
| 20100244204 | FILM FORMING METHOD, FILM FORMING APPARATUS, STORAGE MEDIUM AND SEMICONDUCTOR DEVICE - Provided is a technology capable of obtaining a fluorine-containing carbon film having a good leakage property, coefficient of thermal expansion and mechanical strength. The fluorine-containing carbon film is formed by using active species obtained by activating a C | 09-30-2010 |
| 20100244205 | Glass Frits - Glass frits, conductive inks and articles having conductive inks applied thereto are described. According to one or more embodiments, glass frits with no intentionally added lead comprise TeO | 09-30-2010 |
| 20100283132 | ECR-plasma source and methods for treatment of semiconductor structures - The invention relates to microelectronics, more particularly, to methods of manufacturing solid-state devices and integrated circuits utilizing microwave plasma enhancement under conditions of electron cyclotron resonance (ECR), as well as to use of plasma treatment technology in manufacturing of different semiconductor structures. Also proposed are semiconductor device and integrated circuit and methods for their manufacturing. Technical result consists in improvement of reproducibility parameters of semiconductor structures and devices processed, enhancement of devices parameters, elimination of possibility of defects formation in different regions, and speeding-up of the treatment process. | 11-11-2010 |
| 20100283133 | FILM-FORMING COMPOSITION, INSULATING FILM WITH LOW DIELECTRIC CONSTANT, FORMATION METHOD THEREOF, AND SEMICONDUCTOR DEVICE - In the invention, a silica sol prepared by hydrolyzing and condensing a silane compound represented by the following formula: Si(OR | 11-11-2010 |
| 20100289125 | ENHANCED ELECTROMIGRATION PERFORMANCE OF COPPER LINES IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES BY SURFACE ALLOYING - In sophisticated semiconductor devices, the electromigration performance of copper metal lines at the top interface thereof may be enhanced by forming a copper alloy that is locally restricted to the interface. To this end, an appropriate alloy-forming species, such as aluminum, may be provided on the basis of a non-masked deposition process and may be subsequently removed by a non-masked etch process, wherein the characteristic of the resulting alloy may be adjusted during an intermediate heat treatment. | 11-18-2010 |
| 20100301461 | RELIABLE INTERCONNECTION - Embodiments relate to a method for forming reliable interconnects by the use of a device layer that can serve as a barrier or an etch stop layer, among other applications. The device layer is UV resistant in that its dielectric constant and stress remain stable or relatively stable when subjected to UV curing. | 12-02-2010 |
| 20100301462 | METHOD AND APPARATUS PROVIDING AIR-GAP INSULATION BETWEEN ADJACENT CONDUCTORS USING NANOPARTICLES - A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap. | 12-02-2010 |
| 20100314724 | Selective UV-Ozone Dry Etching of Anti-Stiction Coatings for MEMS Device Fabrication - Organic anti-stiction coatings such as, for example, hydrocarbon and fluorocarbon based self-assembled organosilanes and siloxanes applied either in solvent or via chemical vapor deposition, are selectively etched using a UV-Ozone (UVO) dry etching technique in which the portions of the organic anti-stiction coating to be etched are exposed simultaneously to multiple wavelengths of ultraviolet light that excite and dissociate organic molecules from the anti-stiction coating and generate atomic oxygen from molecular oxygen and ozone so that the organic molecules react with atomic oxygen to form volatile products that are dissipated, resulting in removal of the exposed portions of the anti-stiction coating. A hybrid etching process using heat followed by UVO exposure may be used. A shadow mask (e.g., of glass or quartz), a protective material layer, or other mechanism may be used to selective expose the portions of the anti-stiction coating to be UVO etched. Such selective UVO etching may be used, for example, to expose wafer bond lines prior to wafer-to-wafer bonding in order to increase bond shear and adhesion strength, to expose bond pads in preparation for electrical or other connections, or for general removal of anti-stiction coating materials from metal or other material surfaces. One specific embodiment uses two wavelengths of ultraviolet light, one at around 184.9 nm and the other at around 253.7 nm. | 12-16-2010 |
| 20110001221 | DIELECTRIC LAYER - A dielectric layer is provided. The dielectric layer includes a photo-sensitive polymer or a non-photo-sensitive polymer and an amorphous metal oxide disposed in the photo-sensitive polymer or a non-photo-sensitive polymer. | 01-06-2011 |
| 20110006406 | FABRICATION OF POROGEN RESIDUES FREE AND MECHANICALLY ROBUST LOW-K MATERIALS - A method is provided for producing a porogen-residue-free ultra low-k film with porosity higher than 50% and a high elastic modulus above 5 GPa. The method starts with depositing a SiCOH film using Plasma Enhanced Chemical Vapor Deposition (PE-CVD) or Chemical Vapor Deposition (CVD) onto a substrate and then first Performing an atomic hydrogen treatment at elevated wafer temperature in the range of 200° C. up to 350° C. to remove all the porogens and then performing a UV assisted thermal curing step. | 01-13-2011 |
| 20110018108 | COMPOSITION AND METHOD FOR PRODUCTON THEREOF, POROUS MATERIAL AND METHOD FOR PRODUCTION THEREOF, INTERLAYER INSULATING FILM, SEMICONDUCTOR MATERIAL, SEMICONDUCTOR DEVICE, AND LOW-REFRACTIVE-INDEX SURFACE PROTECTION FILM - Disclosed is a composition comprising a hydrolysate of an alkoxysilane compound, a hydrolysate of a siloxane compound represented by Formula (1), a surfactant, and an element having an electronegativity of 2.5 or less. In Formula (1), R | 01-27-2011 |
| 20110031593 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND SEMICONDUCTOR DEVICE - There are provided a method of manufacturing a semiconductor device, a substrate processing apparatus, and a semiconductor device. The method allows rapid formation of a conductive film, which has a low concentration of impurities permeated from a source owing to its dense structure, and a low resistivity. The method is performed by simultaneously supplying two or more kinds of sources into a processing chamber to form a film on a substrate placed in the processing chamber. The method comprises: performing a first source supply process by supplying at least one kind of source into the processing chamber at a first supply flow rate; and performing a second source supply process by supplying the at least one kind of source into the processing chamber at a second supply flow rate different from the first supply flow rate. | 02-10-2011 |
| 20110042789 | MATERIAL FOR CHEMICAL VAPOR DEPOSITION, SILICON-CONTAINING INSULATING FILM AND METHOD FOR PRODUCTION OF THE SILICON-CONTAINING INSULATING FILM - A chemical vapor deposition material includes an organosilane compound shown by the following general formula (1). | 02-24-2011 |
| 20110079884 | Hydrogen Passivation of Integrated Circuits - An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer. | 04-07-2011 |
| 20110084367 | EPITAXIAL WAFER AND METHOD OF PRODUCING THE SAME - A method of producing an epitaxial wafer, comprising: implanting oxygen ions from a surface of a silicon wafer, thereby forming an ion implanted layer in a surface layer of the silicon wafer; after forming the ion implanted layer, implanting boron ions from the surface of the silicon wafer to the whole area in the ion implanted layer; performing heat treatment of the silicon wafer after implanting boron ions, thereby forming a thinning-stopper layer including a mixture of silicon particles, silicon oxides, and boron, and forming an active layer in the silicon wafer on the surface side of the thinning-stopper layer; and forming an epitaxial layer on the surface of the silicon wafer after the heat treatment. | 04-14-2011 |
| 20110101506 | Stress Memorization Technique Using Silicon Spacer - A structure for memorizing tensile stress in a semiconductor device includes a gate electrode of the semiconductor device; a silicon spacer adjacent to the gate electrode; and a capping layer encapsulating the gate electrode and the silicon spacer, wherein the silicon spacer and capping layer are configured to cause a tensile stress to be memorized in the gate electrode during an annealing process. A method for memorizing tensile stress in a semiconductor device includes forming a silicon spacer adjacent to a gate electrode of the semiconductor device; forming a capping layer over the silicon spacer and the gate electrode; and annealing the semiconductor device, wherein the silicon spacer and capping layer cause a tensile stress to be memorized in the gate electrode during annealing. A disposable silicon spacer is configured to induce a tensile stress in a semiconductor device during a stress memorization technique process. | 05-05-2011 |
| 20110101507 | METHOD AND STRUCTURE FOR REWORKING ANTIREFLECTIVE COATING OVER SEMICONDUCTOR SUBSTRATE - A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer. | 05-05-2011 |
| 20110101508 | RESIST PATTERN THICKENING MATERIAL, SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD THEREOF - A resist pattern thickening material containing a resin, a cyclic compound expressed by the general formula 1, at least one of compounds expressed by the general formulae 2 to 3, respectively, and water: | 05-05-2011 |
| 20110121435 | PHOTOSENSITIVE ADHESIVE COMPOSITION, FILMY ADHESIVE, ADHESIVE SHEET, ADHESIVE PATTERN, SEMICONDUCTOR WAFER WITH ADHESIVE LAYER, SEMICONDUCTOR DEVICE, AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - A photosensitive adhesive composition that comprises (A) a resin with a carboxyl and/or hydroxyl group, (B) a thermosetting resin, (C) a radiation-polymerizable compound and (D) a photoinitiator, wherein the 3% weight reduction temperature of the entire photoinitiator mixture in the composition is 200° C. or greater. | 05-26-2011 |
| 20110127651 | CHAIN SCISSION POLYESTER POLYMERS FOR PHOTORESISTS - Polymers for extreme ultraviolet and 193 nm photoresists are disclosed. The polymers comprise a photoacid generator (PAG) residue, an acid cleavable residue and a diacid joined by ester linkages. The polymers include a photoacid generating diol, a diacid and an acid table diol. | 06-02-2011 |
| 20110147900 | DIELECTRIC LAYER FOR FLASH MEMORY DEVICE AND METHOD FOR MANUFACTURING THEREOF - The present disclosure is related to a dielectric layer comprising a rare-earth aluminate (RE | 06-23-2011 |
| 20110156221 | Method For Producing Ceramic Passivation Layers on Silicon For Solar Cell Manufacture - The invention relates to a method for producing passivation layers on crystalline silicon by a) coating the silicon with a solution containing at least one polysilazane of the general formula (1): —(SiR′R″—NR′″)-n, wherein R′, R″, R′″ are the same or different and stand independently of each other for hydrogen or a possibly substituted alkyl, aryl, vinyl, or (trialkoxysilyl)alkyl group, wherein n is an integer and n is chosen such that the polysilazane has a number average molecular weight of 150 to 150,000 g/mol, b) subsequently removing the solvent by evaporation, whereby polysilazane layers of 50-500 nm thickness remain on the silicon wafer, and c) heating the polysilazane layer at normal pressure to 200-1000° C. in the presence of air or nitrogen, wherein upon tempering the ceramic layers release hydrogen for bulk passivation of the silicon. | 06-30-2011 |
| 20110163424 | Molecular Self-Assembly In Substrate Processing - Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, fluoroalkyl groups, heteroaryl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming. | 07-07-2011 |
| 20110175207 | METHOD FOR PRODUCING METAL OXIDE LAYERS - The invention relates to a method for producing metal oxide layers from oxides of rare earth metals on silicon-containing surfaces, to the device used to carry out the coating method, and to the use of the starting materials used in the method according to the invention for the coating method. | 07-21-2011 |
| 20110186969 | PATTERNED DOPING OF SEMICONDUCTOR SUBSTRATES USING PHOTOSENSITIVE MONOLAYERS - A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate. | 08-04-2011 |
| 20110193202 | METHODS TO ACHIEVE 22 NANOMETER AND BEYOND WITH SINGLE EXPOSURE - Apparatus and methods are disclosed herein for fabricating semiconductor device features with a half-pitch node of 22 nm and beyond using single exposure and single etch (1P1E) photolithography techniques. The method includes exposing in a single exposure a photoresist layer to the exposure source through a photolithography mask where the photolithography mask has on it an island pattern of a material having high percentage transmission. The photoresist layer is developed using a negative tone developer to form a hole pattern in the photoresist layer. The 1P1E does not require the second photo exposure of the double patterning method. Furthermore, the method circumvents the island pattern collapsing issues and the need for strong illumination associated with exiting single 1P1E processes. | 08-11-2011 |
| 20110204490 | FILM FORMING APPARATUS, FILM FORMING METHOD, AND SEMICONDUCTOR DEVICE - According one embodiment, a film forming apparatus includes a stage, a coating section, a vapor supply section, a blower section, and a controller. On the stage, an coating target is placed. The coating section applies a material to a predetermined region on the coating target placed on the stage to form a coating film. The vapor supply section generates solvent vapor capable of dissolving the coating film. The blower section blows the solvent vapor generated by the vapor supply section onto the coating film on the coating target placed on the stage. The controller controls an amount of the solvent vapor to be blown by the blower section so that: the coating film is dissolved; viscosity in a part of the coating film on a surface layer side is lower than that in a part thereof on the coating target side; and the viscosity in the part on the surface layer side and the viscosity of the coating target side take such values that prevent the coating film on the coating target from spreading. | 08-25-2011 |
| 20110204491 | DIELECTRIC LAYER STRUCTURE - A dielectric layer structure includes an interlayer dielectric (ILD) layer covering at least a metal interconnect structure and a single tensile film. The ILD layer further includes a low-k dielectric layer, and the single tensile film is positioned on the low-k dielectric layer for counteracting at least a part of a stress of the low-k dielectric layer. | 08-25-2011 |
| 20110210428 | METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT, SEMICONDUCTOR COMPONENT AND INTERMEDIATE PRODUCT IN THE PRODUCTION THEREOF - Method for producing semiconductor components with a contact structure having a high aspect ratio comprising the following steps: providing an essentially plane semiconductor substrate having a first side and a second side, applying a mask onto at least a first partial area on at least one of the sides of the semiconductor substrate and applying a contact structure onto at least a second partial area, which is different from first partial area, on at least one of the sides of semiconductor substrate. | 09-01-2011 |
| 20110215445 | Methods to Prepare Silicon-Containing Films - Described herein are methods of forming dielectric films comprising silicon, oxide, and optionally nitrogen, carbon, hydrogen, and boron. Also disclosed herein are the methods to form dielectric films or coatings on an object to be processed, such as, for example, a semiconductor wafer. | 09-08-2011 |
| 20110215446 | CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME - A method for fabricating chip package includes providing a semiconductor chip with a bonding pad, comprising an adhesion/barrier layer, connected to a pad through an opening in a passivation layer, next adhering the semiconductor chip to a substrate using a glue material, next bonding a wire to the bonding pad and to the substrate, forming a polymer material on the substrate, covering the semiconductor chip and the wire, next forming a lead-free solder ball on the substrate, and then cutting the substrate and polymer material to form a chip package. | 09-08-2011 |
| 20110241183 | STACKED CHIP PACKAGE WITH REDISTRIBUTION LINES - A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate. | 10-06-2011 |
| 20110254139 | CMP-FIRST DAMASCENE PROCESS SCHEME - An improved metal interconnect is formed with reduced metal voids and dendrites. An embodiment includes forming a mask layer on a dielectric layer, forming openings in the mask and dielectric layers, depositing a planarization layer over the mask layer and filling the openings, planarizing to remove the mask layer, removing the planarization layer from the openings, and filling the openings with metal. The planarization step prior to depositing the metal removes the etch undercut that occurs during formation of the openings and reduces the aspect ratio in the openings, thereby improving metal fill uniformity. | 10-20-2011 |
| 20110254140 | PHOTORESISTS AND METHODS FOR USE THEREOF - New photoresists are provided that comprise preferably as distinct components: a resin, a photoactive component and a phenolic component Preferred photoresists of the invention are can be useful for ion implant lithography protocols. | 10-20-2011 |
| 20110260299 | METHOD FOR VIA PLATING IN ELECTRONIC PACKAGES CONTAINING FLUOROPOLYMER DIELECTRIC LAYERS - A semiconductor printed circuit board assembly (PCBA) and method for making same for use in electronic packages having a core layer of copper-invar-copper (CIC) with a layer of dielectric substrate placed on the core layer. A second layer of dielectric substrate is placed on the lower surface of the core layer of CIC. The layers are laminated together. Blind vias are laser drilled into the layers of dielectric substrate. The partially completed PCBA is subjected to a reactive ion etch (RIE) plasma as a first step to clean blind vias in the PCBA. After the plasma etch, an acidic etchant liquid solution is used on the blind vias. Pre-plating cleaning of blind vias removes a majority of oxides from the blind vias. Seed copper layers are then applied to the PCBA, followed by a layer of copper plating that can be etched to meet the requirements of the PCBA. | 10-27-2011 |
| 20110260300 | Wafer-Bump Structure - A wafer-bump structure includes a wafer-state semiconductor die, a pre-treatment layer, a first ENIG laminate and at least one pillar bump. The wafer-state semiconductor die includes at least one die pad embedded therein and a passivation layer formed on the wafer-state semiconductor die and the die pad. The passivation layer includes an aperture for allowing access to a portion of the die pad. The pre-treatment layer is formed on the un-covered portion of the die pad. The first ENIG laminate is formed on the pre-treatment layer and an annular portion of the passivation layer around the pre-treatment layer. The pillar bump includes a conductive metal layer and a second ENIG laminate. The conductive metal layer is formed on the first ENIG laminate and another annular portion of the passivation layer around the first ENIG laminate. The second ENIG laminate is formed on the conductive metal layer and another annular portion of the passivation layer around the conductive metal layer. | 10-27-2011 |
| 20110266660 | INSULATING FILM FOR SEMICONDUCTOR DEVICE, PROCESS AND APPARATUS FOR PRODUCING INSULATING FILM FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND PROCESS FOR PRODUCING THE SEMICONDUCTOR DEVICE - An object is to provide an insulating film for a semiconductor device which has characteristics of a low permittivity, a low leakage current, and a high mechanical strength, undergoes less change in these characteristics with the elapse of time, and has an excellent water resistance, as well as to provide a process and an apparatus for producing the insulating film for a semiconductor device, a semiconductor device, and a process for producing the semiconductor device. A gas containing a raw material gas which gasified a predetermined alkylborazine compound is supplied in a chamber ( | 11-03-2011 |
| 20110298099 | SILICON DIOXIDE LAYER DEPOSITED WITH BDEAS - A silicon dioxide layer is deposited onto a substrate using a process gas comprising BDEAS and an oxygen-containing gas such as ozone. The silicon dioxide layer can be part of an etch-resistant stack that includes a resist layer. In another version, the silicon dioxide layer is deposited into through holes to form an oxide liner for through-silicon vias. | 12-08-2011 |
| 20110304029 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, WIRING BOARD AND MANUFACTURING METHOD THEREOF, SEMICONDUCTOR PACKAGE, AND ELECTRONIC APPARATUS - A terminal pad is formed on an active surface of an LSI chip, and a composite barrier metal layer is provided over this terminal pad. In the composite barrier metal layer, a plurality of low-elasticity particles composed of a silicone resin is dispersed throughout a metal base phase composed of NiP. The composite barrier metal layer has a thickness of, e.g., 3 μm, and the low-elasticity particles have a diameter of, e.g., 1 μm. A semiconductor device is mounted on a wiring board by bonding a solder bump to the composite barrier metal layer. The low-elasticity particles are thereby allowed to deform according to the applied stress when the semiconductor device is bonded to the wiring board via the solder bump, whereby the stress can be absorbed. | 12-15-2011 |
| 20110316126 | Semiconductor element and method of manufacturing the semiconductor element - A semiconductor element includes a semiconductor layer, an electrode, an adhesion layer, and an insulating layer. The electrode is disposed over the semiconductor layer and has a first upper surface and a second upper surface disposed further away from the semiconductor layer than the first upper surface. The adhesion layer is disposed on the first upper surface of the electrode so that the second upper surface of the electrode is disposed further away from the semiconductor layer than an upper surface of the adhesion layer. The insulating layer covers from the upper surface of the adhesion layer to the semiconductor layer. | 12-29-2011 |
| 20110316127 | SPACER FORMATION FILM, SEMICONDUCTOR WAFER AND SEMICONDUCTOR DEVICE - A spacer formation film is adapted to be used for forming a spacer defining air-gap portions on a side of one surface of a semiconductor wafer and by being cut into a desired shape, the spacer formation film includes: a support base having a sheet-like shape; a spacer formation layer provided on the support base and having a bonding property, the spacer formation layer formed of a material containing an alkali soluble resin, a thermosetting resin and a photo polymerization initiator; and a cutting line along which the spacer formation film is to be cut, wherein the spacer formation layer is provided inside the cutting line so that a peripheral edge thereof is not overlapped to the cutting line. | 12-29-2011 |
| 20120012988 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment, a chip package is provided, which includes: a substrate having a first surface and a second surface; a device region formed in the substrate; a passivation layer formed overlying the first surface of the substrate; at least a polymer planarization layer formed overlying the passivation layer; a package substrate disposed overlying the first surface of the substrate; and a spacer layer disposed between the package substrate and the passivation layer, wherein the spacer layer and the package substrate surround a cavity overlying the substrate, wherein the polymer planar layer does not extends to an outer edge of the spacer layer. | 01-19-2012 |
| 20120012989 | METHOD OF MANUFACTURING SEMICONDUCTOR WAFER BONDING PRODUCT, SEMICONDUCTOR WAFER BONDING PRODUCT AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor wafer bonding product according to the present invention, including: a step of preparing a spacer formation film including a support base and a spacer formation layer; a step of attaching the spacer formation layer of the spacer formation film to a semiconductor wafer; a step of selectively exposing the spacer formation layer with an exposure light via a mask, which is placed at a side of the support base of the spacer formation film, so as to be passed through the support base; a step of removing the support base; a step of developing the spacer formation layer to form a spacer on the semiconductor wafer; and a step of bonding a transparent substrate to a surface of the spacer opposite to the semiconductor wafer. | 01-19-2012 |
| 20120032309 | INK COMPOSITION FOR FORMING LIGHT SHIELDING FILM OF ORGANIC SEMICONDUCTOR DEVICE, METHOD FOR FORMING LIGHT SHIELDING FILM, AND ORGANIC TRANSISTOR DEVICE HAVING LIGHT SHIELDING FILM - There is provided an ink composition for forming a light shielding film in an organic semiconductor device which is capable of stably forming a fine pattern when forming a finely patterned light shielding film by the letterpress reverse printing method or microcontact printing method, which can be baked at a temperature equal to or less than the substrate heatproof temperature, and which is also capable of providing light shielding property and mechanical strength, the ink composition for forming a light shielding film in an organic semiconductor device which is an ink composition for forming a light shielding film in an organic semiconductor device comprising a black pigment; a resin component; a surface energy modifier; a quick-drying organic solvent; a slow-drying organic solvent; and a mold releasing agent, wherein the resin component comprises a solid resin that is in a solid state at 200° C. or less and a liquid resin that is in a liquid state at 10 to 50° C. at a ratio (solid resin/liquid resin) of 0.2 to 0.6. | 02-09-2012 |
| 20120032310 | Production Process For A Semi-Conductor Device And Semi-Conductor Device - A process for producing a semiconductor device comprises the following process steps: provision of a semiconductor substrate ( | 02-09-2012 |
| 20120068314 | CROSSLINKABLE DIELECTRICS AND METHODS OF PREPARATION AND USE THEREOF - The present invention relates to an electronic device comprising at least one dielectric layer, said dielectric layer comprising a crosslinked organic compound based on at least one compound which is radically crosslinkable and a method of making the electronic device. | 03-22-2012 |
| 20120074533 | Structures And Techniques For Atomic Layer Deposition - In one exemplary embodiment, a method includes: forming at least one first monolayer of first material on a surface of a substrate by performing a first plurality of cycles of atomic layer deposition; thereafter, annealing the formed at least one first monolayer of first material under a first inert atmosphere at a first temperature between about 650° C. and about 900° C.; thereafter, forming at least one second monolayer of second material by performing a second plurality of cycles of atomic layer deposition, where the formed at least one second monolayer of second material at least partially overlies the annealed at least one first monolayer of first material; and thereafter, annealing the formed at least one second monolayer of second material under a second inert atmosphere at a second temperature between about 650° C. and about 900° C. | 03-29-2012 |
| 20120074534 | Semiconductor Device and Method of Forming Protective Structure Around Semiconductor Die for Localized Planarization of Insulating Layer - A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die. | 03-29-2012 |
| 20120074535 | LOW DIELECTRIC CONSTANT MATERIAL - The present disclosure provides a dielectric material including a low dielectric constant material and an additive. The additive includes a compound having a Si—X—Si bridge, where X is a number of carbon atoms between 1 and 8. The additive may include terminal Si—CH | 03-29-2012 |
| 20120080777 | TRIPLE OXIDATION ON DSB SUBSTRATE - According to certain embodiments, a semiconductor structure is formed having a gate oxide formed over a semiconductor substrate. The gate oxide is formed as to have three different regions characterized by a different average thickness of gate oxide in each region. A first oxidation process is performed on a semiconductor substrate having both a Si (110) orientation region and a Si (100) orientation region on a surface thereof. Gate oxide is formed at a faster rate on the Si (110) orientation region of the semiconductor substrate relative to the Si (100) orientation region. A portion of the gate oxide is selectively removed and a second oxidation process is performed to form additional gate oxide. A triple oxide semiconductor substrate is recovered with the gate oxide having three different thickness formed thereon. The triple oxide semiconductor substrate is formed using a decreased number of processing acts. | 04-05-2012 |
| 20120080778 | ELECTRONIC DEVICE - A device is prepared using a chemical vapor deposition method and has a patterned thin film on a substrate that is applied using a deposition inhibitor material. The deposition inhibitor material is a hydrophilic polymer that is a neutralized acid having a pKa of 5 or less, wherein at least 90% of the acid groups are neutralized. The deposition inhibitor material can be patterned simultaneously or subsequently to its application to the substrate, to provide selected areas of the substrate effectively not having the deposition inhibitor material. A thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material. | 04-05-2012 |
| 20120086107 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SUBSTRATE PROCESSING APPARATUS AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes loading a substrate, on which a high-k film is formed, into a processing chamber, performing a reforming process by heating the high-k film through irradiation of a microwave on the substrate, and unloading the substrate from the processing chamber. | 04-12-2012 |
| 20120104566 | PASSIVATION LAYER STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a passivation layer structure of a semiconductor device for disposed on a semiconductor substrate is provided, which includes a passivation layer structure disposed on the semiconductor substrate, wherein the passivation layer structure includes a halogen-doped aluminum oxide layer. According to an embodiment of the invention, a method for forming a passivation structure of a semiconductor device is provided. | 05-03-2012 |
| 20120119337 | SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Provided is a substrate processing apparatus capable of suppressing accumulation of reaction products or decomposed matters on an inner wall of a nozzle and suppressing scattering of foreign substances in a process chamber. The substrate processing apparatus includes a process chamber, a heating unit, a source gas supply unit, a source gas nozzle, an exhaust unit, and a control unit configured to control at least the heating unit, the source gas supply unit and the exhaust unit. The source gas nozzle is disposed at a region in the process chamber, in which a first process gas is not decomposed even under a temperature in the process chamber higher than a pyrolysis temperature of the first process gas, and the control unit supplies the first process gas into the process chamber two or more times at different flow velocities to prevent the first process gas from being mixed. | 05-17-2012 |
| 20120126376 | SILICON DIOXIDE FILM AND PROCESS FOR PRODUCTION THEREOF, COMPUTER-READABLE STORAGE MEDIUM, AND PLASMA CVD DEVICE - To produce a silicon dioxide film having concentration of hydrogen atoms below or equal to 9.9×10 | 05-24-2012 |
| 20120161295 | CYCLIC CARBOSILANE DIELECTRIC FILMS - Embodiments of the invention provide dielectric films and low-k dielectric films and methods for making dielectric and low-k dielectric films. Dielectric films are made from carbosilane-containing precursors. In embodiments of the invention, dielectric film precursors comprise attached porogen molecules. In further embodiments, dielectric films have nanometer-dimensioned pores. | 06-28-2012 |
| 20120175751 | DEPOSITION OF GROUP IV METAL-CONTAINING FILMS AT HIGH TEMPERATURE - Disclosed are group IV metal-containing precursors and their use in the deposition of group IV metal-containing films{nitride, oxide and metal) at high process temperature. The use of cyclopentadienyl and imido ligands linked to the metal center secures thermal stability, allowing a large deposition temperature window, and low impurity contamination. The group IV metal (titanium, zirconium, hafnium)-containing fvm depositions may be carried out by thermal and/or plasma-enhanced CVD, ALD, and pulse CVD. | 07-12-2012 |
| 20120187548 | Surface Modification - A method of modifying a fluorinated polymer surface comprising the steps of depositing a first layer on at least a portion of the fluorinated polymer surface, the first layer comprising a first polymer, the first polymer being a substantially perfluorinated aromatic polymer; and depositing a second layer on at least a portion of the first layer, the second layer comprising a second polymer, the second polymer being an aromatic polymer having a lower degree of fluorination than said first polymer, whereby the second layer provides a surface on to which a substance having a lower degree of fluorination than the first polymer, e.g. a non-fluorinated substance is depositable. | 07-26-2012 |
| 20120193766 | SEMICONDUCTOR DEVICE WITH FRONT AND BACK SIDE RESIN LAYERS HAVING DIFFERENT THERMAL EXPANSION COEFFICIENT AND ELASTICITY MODULUS - Disclosed are a semiconductor device wherein warping of a semiconductor chip due to a sudden temperature change can be prevented without increasing the thickness, and a semiconductor device assembly. The semiconductor device comprises a semiconductor chip, a front side resin layer formed on the front surface of the semiconductor chip by using a first resin material, and a back side resin layer formed on the back surface of the semiconductor chip by using a second resin material having a higher thermal expansion coefficient than the first resin material. The back side resin layer is formed thinner than the front side resin layer. | 08-02-2012 |
| 20120193767 | ADVANCED LOW k CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES - A carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. The dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen. The carbon-rich silicon carbide-like dielectric film can be used as a dielectric cap layer in an interconnect structure. | 08-02-2012 |
| 20120205785 | Technique for Etching Monolayer and Multilayer Materials - A process is disclosed for sectioning by etching of monolayers and multilayers using an RIE technique with fluorine-based chemistry. In one embodiment, the process uses Reactive Ion Etching (RIE) alone or in combination with Inductively Coupled Plasma (ICP) using fluorine-based chemistry alone and using sufficient power to provide high ion energy to increase the etching rate and to obtain deeper anisotropic etching. In a second embodiment, a process is provided for sectioning of WSi | 08-16-2012 |
| 20120205786 | METHOD AND STRUCTURE FOR REWORKING ANTIREFLECTIVE COATING OVER SEMICONDUCTOR SUBSTRATE - A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer. | 08-16-2012 |
| 20120211873 | METHOD FOR FORMING A PATTERN AND SEMICONDUCTOR DEVICE - A method for forming a pattern includes: forming a resist film on an object and patterning the formed resist film; forming a spacer film to coat the object and the resist film, and forming a concave portion surrounded by the spacer film; forming a first opening from the concave portion by etching a portion of the spacer film so that the spacer film remains beside a side wall of the resist film while exposing the object under the concave portion and the top surface of the resist film; and forming a second opening by removing the resist film. | 08-23-2012 |
| 20120211874 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFT, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof. | 08-23-2012 |
| 20120217622 | Method for Imparting a Controlled Amount of Stress in Semiconductor Devices for Fabricating Thin Flexible Circuits - Imparting a controlled amount of stress in an assembly comprising a semiconductor circuit on a substrate comprises depositing a tensile stressed metal film stressor layer onto the surface of the circuit. Establishing a fracture region below electrically active regions of the circuit, adhering a foil handle to the assembly and pulling it away from the assembly induces mechanical fracture in the fracture region below the electrically active regions. The mechanical fracture propagates parallel and laterally to the surface of the substrate and below the circuit to produce a thin flexible circuit on a residual substrate. The circuit is under compressive strain that is changed by modifying the stressor layer or residual substrate. Individualized circuits or a circuit may also be defined above the fracture by dividing the circuit into preselected regions with surrounding trenches before fracture. We harvest the circuit(s) by pulling the foil handle away from the assembly. | 08-30-2012 |
| 20120223418 | SOLUTION PROCESSIBLE HARDMASKS FOR HIGH RESOLUTION LITHOGRAPHY - Solution processible hardmasks are described that can be formed from aqueous precursor solutions comprising polyoxometal clusters and anions, such as polyatomic anions. The solution processible metal oxide layers are generally placed under relatively thin etch resist layers to provide desired etch contrast with underlying substrates and/or antireflective properties. In some embodiments, the metal oxide hardmasks can be used along with an additional hardmask and/or antireflective layers. The metal oxide hardmasks can be etched with wet or dry etching. Desirable processing improvements can be obtained with the solution processible hardmasks. | 09-06-2012 |
| 20120228747 | RESIST PATTERN IMPROVING MATERIAL, METHOD FOR FORMING RESIST PATTERN, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - To provide a resist pattern improving material, containing: water; and benzalkonium chloride represented by the following general formula (1): | 09-13-2012 |
| 20120228748 | PASSIVATION LAYER SURFACE TOPOGRAPHY MODIFICATIONS FOR IMPROVED INTEGRITY IN PACKAGED ASSEMBLIES - A structure and method for producing the same is disclosed. The structure includes an organic passivation layer with solids suspended therein. Preferential etch to remove a portion of the organic material and expose portions of such solids creates enhanced surface roughness, which provides a significant advantage with respect to adhesion of that passivation layer to the packaging underfill material. | 09-13-2012 |
| 20120235285 | PROTECTION OF REACTIVE METAL SURFACES OF SEMICONDUCTOR DEVICES DURING SHIPPING BY PROVIDING AN ADDITIONAL PROTECTION LAYER - When forming complex metallization systems on the basis of copper, the very last metallization layer may receive contact regions on the basis of copper, the surface of which may be passivated on the basis of a dedicated protection layer, which may thus allow the patterning of the passivation layer stack prior to shipping the device to a remote manufacturing site. Hence, the protected contact surface may be efficiently re-exposed in the remote manufacturing site on the basis of an efficient non-masked wet chemical etch process. | 09-20-2012 |
| 20120241920 | EDGE BEAD REMOVAL FOR POLYBENZOXAZOLE (PBO) - A method of cleaning polybenzoxazole (PBO) from a semiconductor wafer coated with PBO includes baking a PBO-coated semiconductor wafer, and then exposing the semiconductor wafer with ultraviolet light through a patterned mask to soften selected regions of PBO on the semiconductor wafer. PBO is then dissolved in an edge region of the semiconductor wafer with solvent. After dissolving PBO in the edge region, the semiconductor wafer is chemically developed to dissolve the elected softened regions of PBO on the semiconductor wafer and to dissolve PBO remaining in the edge region of the semiconductor wafer that was left behind after the step of dissolving the PBO in the edge region with the solvent. | 09-27-2012 |
| 20120248582 | Voltage Switchable Dielectric for Die-Level Electrostatic Discharge (ESD) Protection - A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC. | 10-04-2012 |
| 20120248583 | METHOD FOR FORMING GERMANIUM OXIDE FILM AND MATERIAL FOR ELECTRONIC DEVICE - A method for forming a germanium oxide film between a germanium substrate and an insulating film includes producing atomic oxygen on a surface of the insulating film formed on a surface of the germanium substrate by generating a plasma of a processing gas containing oxygen atom-containing gas. The method further includes forming a germanium oxide film by reacting germanium with the atomic oxygen which has reached the germanium substrate after penetrating the insulating film by irradiating the plasma on the surface of the insulating film. | 10-04-2012 |
| 20120256303 | METHOD OF PREPARING A PATTERNED FILM WITH A DEVELOPING SOLVENT - A method of preparing a patterned film on a substrate includes applying a silicone composition onto a substrate to form a film of the silicone composition. A portion of the film is exposed to radiation to produce a partially exposed film having an exposed region and a non-exposed region. The partially exposed film is heated for a sufficient amount of time and at a sufficient temperature to substantially insolubilize the exposed region in a developing solvent that includes a siloxane component. The non-exposed region of the partially exposed film is removed with the developing solvent to reveal a film-free region on the substrate and to form the patterned film including the exposed region that remains on the substrate. The film-free regions is substantially free of residual silicone due to the presence of the siloxane component in the developing solvent. | 10-11-2012 |
| 20120261803 | HIGH-K GATE DIELECTRIC MATERIAL AND METHOD FOR PREPARING THE SAME - The present invention forms Hf | 10-18-2012 |
| 20120273923 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND WAFER - A method of manufacturing semiconductor device and a wafer are provided in accordance with embodiments of the present invention, which relates to semiconductor technology. The method includes: providing a substrate, and forming a gate oxide layer and a polysilicon layer on a first surface of the substrate; etching the polysilicon layer by use of a patterned mask so as to form a polysilicon gate with reentrants; depositing a tensile stress film on a second surface of the substrate before etching the polysilicon layer. The tensile stress film can be deposited on the second surface of the substrate for generating the tensile stress for the wafer. Thus, a polysilicon gate with reentrants can be formed in etching process. In this way, semiconductor devices can have smaller gate-source/drain overlap capacitance and better TDDB parameters, and the performance of the devices can be improved. | 11-01-2012 |
| 20120273924 | ACTINIC-RAY- OR RADIATION-SENSITIVE RESIN COMPOSITION, ACTINIC-RAY- OR RADIATION-SENSITIVE FILM THEREFROM AND METHOD OF FORMING PATTERN USING THE COMPOSITION - Provided are an actinic-ray- or radiation-sensitive resin composition that excels in the sensitivity, roughness characteristics and exposure latitude, and a method of forming a pattern using the same. The composition includes (A) a resin that when acted on by an acid, is decomposed to thereby increase its solubility in an alkali developer, and (B) a compound that when exposed to actinic rays or radiation, is decomposed to thereby generate an acid, the compound being any of compounds of general formula (1-1) below. | 11-01-2012 |
| 20120273925 | PATTERNED DOPING OF SEMICONDUCTOR SUBSTRATES USING PHOTOSENSITIVE MONOLAYERS - A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate. | 11-01-2012 |
| 20120280370 | SEMICONDUCTOR DEVICE DEVOID OF AN INTERFACIAL LAYER AND METHODS OF MANUFACTURE - A method of forming a dielectric stack devoid of an interfacial layer includes subjecting an exposed interfacial layer provided on a semiconductor material to a low pressure thermal anneal process for a predetermined time period at a temperature of about 900° C. to about 1000° C. with an inert gas purge. A semiconductor structure is also disclosed, with a dielectric stack devoid of an interfacial layer. | 11-08-2012 |
| 20120280371 | CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a circuit structure is provided. A metal layer having an upper surface is provided. A surface passivation layer is formed on the metal layer. The surface passivation layer exposes a portion of the upper surface of the metal layer, and a material of the metal layer is different from a material of the surface passivation layer. A covering layer is formed on the surface passivation layer, and the covering layer covers the surface passivation layer. | 11-08-2012 |
| 20120292747 | COMPOUND SEMICONDUCTOR SUBSTRATE - An object is to provide a compound semiconductor substrate and a surface-treatment method thereof, in which, even after the treated substrate is stored for a long period of time, resistance-value defects do not occur. Even when the compound semiconductor substrate is stored for a long period of time and an epitaxial film is then formed thereon, electrical-characteristic defects do not occur. The semiconductor substrate according to the present invention is a compound semiconductor substrate at least one major surface of which is mirror-polished, the mirror-polished surface being covered with an organic substance containing hydrogen (H), carbon (C), and oxygen (O) and alternatively a compound semiconductor substrate at least one major surface of which is mirror-finished, wherein a silicon (Si) peak concentration at an interface between an epitaxial film grown at a growth temperature of 550° C. and the compound semiconductor substrate is 2×10 | 11-22-2012 |
| 20120299161 | CONDUCTIVE VIA STRUCTURE - The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate and having an opening with a first width over the contact pad; a conductive via within the opening; and a conductive pillar having a second width completely covering the conductive via, wherein a ratio of the first width to the second width is from about 0.15 to 0.55. | 11-29-2012 |
| 20120319250 | BACK-SIDE CONTACT FORMATION - In one embodiment, a semiconductor is provided comprising a substrate and a plurality of wiring layers and dielectric layers formed on the substrate, the wiring layers implementing a circuit. The dielectric layers separate adjacent ones of the plurality of wiring layers. A first passivation layer is formed on the plurality of wiring layers. A first contact pad is formed in the layer and connected to the contact pad. A through silicon via (TSV) is formed through the substrate, the plurality of wiring and dielectric layers, and the passivation layer. The TSV is electrically connected to the wire formed on the passivation layer. The TSV is electrically isolated from the wiring layers except for the connection provided by the metal wire formed on the passivation layer. | 12-20-2012 |
| 20120319251 | Solder Ball Protection Structure with Thick Polymer Layer - An integrated circuit structure includes a substrate and a metal pad over the substrate. A post-passivation interconnect (PPI) line is connected to the metal pad, wherein the PPI line includes at least a portion over the metal pad. A PPI pad is connected to the PPI line. A polymer layer is over the PPI line and the PPI pad, wherein the polymer layer has a thickness greater than about 30 μm. An under-bump metallurgy (UBM) extends into an opening in the polymer layer and electrically connected to the PPI pad. | 12-20-2012 |
| 20130001754 | IN-SITU PHOTORESIST STRIP DURING PLASMA ETCHING OF ACTIVE HARD MASK - A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber. | 01-03-2013 |
| 20130009286 | SEMICONDUCTOR CHIP AND FLIP-CHIP PACKAGE COMPRISING THE SAME - A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad. | 01-10-2013 |
| 20130009287 | ACCURATE DEPOSITION OF NANO-OBJECTS ON A SURFACE - The invention notably concerns a method for depositing nano-objects on a surface. The method includes: providing a substrate with surface patterns on one face thereof; providing a transfer layer on said face of the substrate; functionalizing areas on a surface of the transfer layer parallel to said face of the substrate, at locations defined with respect to said surface patterns, such as to exhibit enhanced binding interactions with nano-objects; depositing nano-objects and letting them get captured at the functionalized areas; and thinning down the transfer layer by energetic stimulation to decompose the polymer into evaporating units, until the nano-objects reach the surface of the substrate. The invention also provides a semiconductor device which includes a substrate and nano-objects accurately disposed on the substrate. | 01-10-2013 |
| 20130015562 | ACTINIC-RAY- OR RADIATION-SENSITIVE RESIN COMPOSITION, ACTINIC-RAY- OR RADIATION-SENSITIVE FILM THEREFROM AND METHOD OF FORMING PATTERN USING THE COMPOSITIONAANM Yamamoto; KeiAACI Haibara-gunAACO JPAAGP Yamamoto; Kei Haibara-gun JPAANM Fujita; MitsuhiroAACI Haibara-gunAACO JPAAGP Fujita; Mitsuhiro Haibara-gun JPAANM Matsuda; TomokiAACI Haibara-gunAACO JPAAGP Matsuda; Tomoki Haibara-gun JP - Provided is an actinic-ray- or radiation-sensitive resin composition including (A) a resin that when acted on by an acid, is decomposed to thereby increase its solubility in an alkali developer, (B) an onium salt containing a nitrogen atom in its cation moiety, which onium salt when exposed to actinic rays or radiation, is decomposed to thereby generate an acid, and (C) a compound that when exposed to actinic rays or radiation, generates an acid, the compound being any of compounds of general formulae (1-1) and (1-2) below. | 01-17-2013 |
| 20130020684 | ACTINIC RAY-SENSITIVE OR RADIATION-SENSITIVE RESIN COMPOSITION, AND ACTINIC RAY-SENSITIVE OR RADIATION-SENSITIVE FILM AND PATTERN FORMING METHOD USING THE SAME - The actinic ray-sensitive or radiation-sensitive resin composition according to the present invention includes a resin (A) which contains at least one type of repeating unit which is represented by the general formula (PG1), at least one type of repeating unit which is selected from the repeating units which are represented by the general formula (PG2) and the general formula (PG3), and at least one type of repeating unit which includes a lactone structure, a compound (B) which is a compound which is represented by the general formula (B1) and where the molecular weight of an anion moiety is 200 or less, and a solvent (C). | 01-24-2013 |
| 20130026608 | PROCESS FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE COMPRISING A FUNCTIONALIZED LAYER ON A SUPPORT SUBSTRATE - The invention relates to a process for manufacturing a semiconductor structure comprising a functionalized layer on a support substrate, comprising the following steps: (a) implanting ionic species in a source substrate comprising the said functionalized layer and a sacrificial buffer layer located under the functionalized layer relative to the direction of implantation, to a depth delimiting the thickness of an upper part of the source substrate comprising the functionalized layer and at least part of the buffer layer; (b) bonding the source substrate to the support substrate; (c) fracturing the source substrate and transferring the upper part of the source substrate to the support substrate; (d) removing the buffer layer by selective etching with respect to the functionalized layer. | 01-31-2013 |
| 20130026609 | PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE WITH STRESS RELIEF STRUCTURE - An apparatus configured to be coupled onto a substrate, wherein the apparatus comprises a semiconductor substrate and the semiconductor substrate includes a plurality of trenches defined within a side of the semiconductor substrate. The apparatus further comprises an interconnect layer over portions of the side of the semiconductor substrate, wherein the portions of the side of the semiconductor substrate include the plurality of trenches defined within the side of the semiconductor substrate. Each trench is configured to respectively receive a solder ball to provide an interface between i) the interconnect layer and ii) the substrate to which the apparatus is to be coupled. | 01-31-2013 |
| 20130069207 | METHOD FOR PRODUCING A DEPOSIT AND A DEPOSIT ON A SURFACE OF A SILICON SUBSTRATE - A deposit and a method for producing a deposit on a surface of a silicon substrate. The deposit comprises aluminum oxide, and the method comprises in any order the alternating steps of a) introducing into a reaction space one of water and ozone as a precursor for oxygen, b) introducing into a reaction space the other of water and ozone as a precursor for oxygen, c) introducing into a reaction space a precursor for aluminum and subsequently purging the reaction space;with the provisions that when step a) or step b) precedes step c) then the reaction space is purged before step c), and that the reaction space is not purged between step a) and step b), when step a) precedes step b) or when step b) precedes step a). | 03-21-2013 |
| 20130075872 | Metal Pad Structures in Dies - A die includes a substrate, a metal pad over the substrate, and a passivation layer that has a portion over the metal pad. A dummy pattern is disposed adjacent to the metal pad. The dummy pattern is level with, and is formed of a same material as, the metal pad. The dummy pattern forms at least a partial ring surrounding at least a third of the metal pad. | 03-28-2013 |
| 20130075873 | GLASS COMPOSITION FOR PROTECTING SEMICONDUCTOR JUNCTION, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Provided is a glass composition for protecting a semiconductor junction which contains at least SiO | 03-28-2013 |
| 20130082361 | MANUFACTURING METHOD FOR FLEXIBLE DEVICE AND FLEXIBLE DEVICE MANUFACTURED BY THE SAME - Provided are a method of manufacturing a flexible device and a flexible device manufactured thereby. | 04-04-2013 |
| 20130099363 | Molecular Self-Assembly in Substrate Processing - Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, fluoroalkyl groups, heteroaryl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming. | 04-25-2013 |
| 20130113085 | Atomic Layer Deposition Of Films Using Precursors Containing Hafnium Or Zirconium - Provided are low temperature methods of depositing hafnium or zirconium containing films using a Hf(BH | 05-09-2013 |
| 20130113086 | SELF-LEVELING PLANARIZATION MATERIALS FOR MICROELECTRONIC TOPOGRAPHY - Planarization methods and microelectronic structures formed therefrom are disclosed. The methods and structures use planarization materials comprising fluorinated compounds or acetoacetylated compounds. The materials are self-leveling and achieve planarization over topography without the use of etching, contact planarization, chemical mechanical polishing, or other conventional planarization techniques. | 05-09-2013 |
| 20130127021 | METHODS FOR ADHERING MATERIALS, FOR ENHANCING ADHESION BETWEEN MATERIALS, AND FOR PATTERNING MATERIALS, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES - Methods for adhering materials and methods for enhancing adhesion between materials are disclosed. In some embodiments, a polymer brush material is bonded to a base material, and a developable polymer resist material is applied over the grafted polymer brush material. The resist material is at least partially miscible in the grafted polymer brush material. As such, the resist material at least partially dissolves within the grafted polymer brush material to form an intertwined material of grafted polymer brush macromolecules and resist polymer macromolecules. Adhesion between the developable polymer resist and the base material may be thereby enhanced. Also disclosed are related semiconductor device structures. | 05-23-2013 |
| 20130127022 | ELECTRONIC DEVICE PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode. | 05-23-2013 |
| 20130134561 | BACKSIDE THERMAL PATTERNING OF BURIED OXIDE (BOX) - The dominant source of thermal resistance for silicon photonic devices patterned on SOI wafers is the buried oxide layer. To ensure efficient thermally driven silicon devices there is a need for a large thermal resistance. This is in contrast to temperature sensitive components need to have low thermal resistance in order to reduce their temperature to ensure good performance. Embodiments comprise etching the back of an SOI wafer to expose the buried oxide layer and depositing an additional layer of silicon oxide to increase the local thermal resistance. Thus, embodiments provide the ability to tailor the thermal resistance across the wafer or die depending on the device being fabricated. | 05-30-2013 |
| 20130134562 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR BURIED LAYER - The present disclosure provides a semiconductor device and a method for fabricating a semiconductor buried layer. The method includes: preparing a substrate which includes a first oxide layer; forming a first buried layer region in the surface of the substrate by using a photoresist layer with a first buried layer region pattern as a mask, in which a doping state of the first buried layer region is different from a doping state of other region of the substrate; forming a second oxide layer on the surface of the substrate and the first buried layer region; and forming a second buried layer region in the surface of the substrate through self alignment process by using the second oxide layer as a mask. The method disclosed by the present disclosure reduces the complexity of the buried layer procedures and the cost thereof, as well as the probability of crystal defects. | 05-30-2013 |
| 20130154063 | DRIVING SUBSTRATE, DISPLAY DEVICE, PLANARIZING METHOD, AND METHOD OF MANUFACTURING DRIVING SUBSTRATE - A driving substrate includes: a protective layer including an etching surface; and a film layer including one or more convex portions on a surface thereof, the film layer being in contact with a rear surface of the protective layer, the one or more convex portions each having a surface being flush with the etching surface. | 06-20-2013 |
| 20130168835 | HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF FORMING - A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate. | 07-04-2013 |
| 20130168836 | SOI STRUCTURES HAVING A SACRIFICIAL OXIDE LAYER - Methods for producing silicon on insulator structures with a reduced metal content in the device layer thereof are disclosed. Silicon on insulator structures with a reduced metal content are also disclosed. | 07-04-2013 |
| 20130193564 | SEMICONDUCTOR STRUCTURE AND METHOD AND TOOL FOR FORMING THE SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure includes forming a photoresist layer over a substrate. The photoresist layer includes a first material removable by a removal process. The first material at a guard band portion of the photoresist layer along an edge portion of the photoresist layer is converted to a second material. The second material is not removable by the removal process. Also, the first material at the edge portion of the photoresist layer is not converted to the second material. The guard band portion is farther from a periphery of the substrate than the edge portion. The removal process is performed to remove the first material after the conversion of the guard band portion. | 08-01-2013 |
| 20130207244 | PROCESS FOR FABRICATING A SILICON-ON-INSULATOR STRUCTURE - Embodiments of to invention relate to a process for fabricating a silicon-on-insulator structure comprising the following steps: providing a donor substrate and a support substrate, only one of the substrates being covered with an oxide layer; forming, in the donor substrate, a weak zone; plasma activating the oxide layer; bonding the donor substrate to the support substrate in a partial vacuum; implementing a bond-strengthening anneal at a temperature of 350° C. or less causing the donor substrate to cleave along the weak zone; and carrying out a heat treatment at a temperature above 900° C. A transition from the temperature of the bond-strengthening anneal to the temperature of the heat treatment may be achieved at a ramp rate above 10° C./s. | 08-15-2013 |
| 20130207245 | METHODS FOR MAKING POROUS INSULATING FILMS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME - Low-k porous insulating films with a high modulus of elasticity are made by depositing alkylated cyclic siloxane precursors over a semiconductor substrate by CVD. Plasma enhancement of the CVD is performed either during CVD or in situ on the deposited film. A UV cure of the film is effected under controlled temperature and time conditions, which generates a tight bonding structure between adjacent ring moieties without disrupting the Si—O ring bonding. | 08-15-2013 |
| 20130228901 | MATERIALS AND METHODS FOR STRESS REDUCTION IN SEMICONDUCTOR WAFER PASSIVATION LAYERS - The present invention provides polyimide polymer materials for passivating semiconductor wafers and methods for fabricating thereof. The present invention further provides a device that includes a semiconductor wafer and a passivating layer disposed on the surface of the wafer, wherein the passivating layer comprises such polyimide polymers. | 09-05-2013 |
| 20130234299 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a_semiconductor device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked. The semiconductor device includes a mark and a supporting unit. The mark is opened onto a surface of the stacked body. The supporting unit is provided around the mark. The supporting unit extends in a stacked direction of the stacked body. The supporting unit is in contact with at least a plurality of conductive layers. | 09-12-2013 |
| 20130234300 | SEMICONDUCTOR DEVICE INCLUDING A STRESS BUFFER MATERIAL FORMED ABOVE A LOW-K METALLIZATION SYSTEM - A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer, which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer comprises copper-based buffer regions that cover a significant portion of the overall surface, wherein a thickness of approximately 3-10 μm may also be used. Moreover, the buffer regions may efficiently replace aluminum as a terminal metal active region. | 09-12-2013 |
| 20130292806 | Methods For Manganese Nitride Integration - Described are methods of forming a semiconductor device. Certain methods comprises depositing a film comprising manganese nitride over a dielectric; depositing a copper seed layer over the film; and depositing a copper fill layer over the copper seed layer. Also described are semiconductor devices. Certain semiconductor devices comprise a low-k dielectric layer; a manganese nitride layer overlying the low-k dielectric layer; a seed layer selected from a copper seed layer or electrochemical deposition seed layer overlying the manganese nitride layer; a copper layer overlying the copper seed layer. | 11-07-2013 |
| 20130299952 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less. | 11-14-2013 |
| 20130341768 | SELF REPAIRING PROCESS FOR POROUS DIELECTRIC MATERIALS - The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage. | 12-26-2013 |
| 20130341769 | ALUMINIUM OXIDE-BASED METALLISATION BARRIER - The present invention relates to aluminium oxide-based passivation layers which simultaneously act as diffusion barrier for underlying wafer layers against aluminium and other metals. Furthermore, a process and suitable compositions for the production of these layers are described. | 12-26-2013 |
| 20140027884 | SYSTEM AND METHOD FOR GAS-PHASE SULFUR PASSIVATION OF A SEMICONDUCTOR SURFACE - Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The method includes providing a high-mobility semiconductor surface to a chamber of a reactor and exposing the high-mobility semiconductor surface to a gas-phase sulfur precursor to passivate the high-mobility semiconductor surface. | 01-30-2014 |
| 20140027885 | THREE-DIMENSIONAL INTEGRATED CIRCUIT LAMINATE, AND INTERLAYER FILLER FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT LAMINATE - To provide a three-dimensional integrated circuit laminate filled in with an interlayer filler composition having both high thermal conductivity and low linear expansion property. | 01-30-2014 |
| 20140070376 | Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements - A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall. | 03-13-2014 |
| 20140097523 | METHOD FOR MANUFACTURING BONDED WAFER AND BONDED SOI WAFER - A method for manufacturing a bonded wafer includes: an ion implantation step of using a batch type ion implanter; a bonding step of bonding an ion implanted surface of a bond wafer to a surface of a base wafer directly or through an insulator film; and a delamination step of delaminating the bond wafer at an ion implanted layer, thereby manufacturing a bonded wafer having a thin film on the base wafer, wherein the ion implantation into the bond wafer carried out at the ion implantation step is divided into a plurality of processes, the bond wafer is rotated on its own axis a predetermined rotation angle after each ion implantation, and the next ion implantation is carried out at an arrangement position obtained by the rotation. | 04-10-2014 |
| 20140117510 | Semiconductor Bonding Structure and Process - A system and method for bonding semiconductor devices is provided. An embodiment comprises halting the flow of a eutectic bonding material by providing additional material of one of the reactants in a grid pattern, such that, as the eutectic material flows into the additional material, the additional material will change the composition of the flowing eutectic material and solidify the material, thereby stopping the flow. Other embodiments provide for additional layouts to put the additional material into the path of the flowing eutectic material. | 05-01-2014 |
| 20140124902 | HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF FORMING - A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate. | 05-08-2014 |
| 20140138800 | SMALL PITCH PATTERNS AND FABRICATION METHOD - A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having a first region and a second region on the semiconductor substrate. The method also includes forming a plurality of discrete first sacrificial layers on the first region of the target material layer and a plurality of discrete second sacrificial layers on the second region of the target material layer, and forming first sidewall spacers on both sides of the discrete first sacrificial layers and the discrete second sacrificial layers. Further, the method includes removing the first sacrificial layers and the second sacrificial layers, and forming second sidewall spacers. Further, the method also includes forming discrete repeating patterns in the first region of the target material layer and a continuous pattern in the second region of the target material layer. | 05-22-2014 |
| 20140145312 | SEMICONDUCTOR STRUCTURE WITH RARE EARTH OXIDE - A semiconductor structure with a rare earth oxide is provided. The semiconductor structure comprises: a semiconductor substrate ( | 05-29-2014 |
| 20140151856 | Chip Module, an Insulation Material and a Method for Fabricating a Chip Module - The chip module includes a carrier, a semiconductor chip arranged on or embedded inside the carrier, and an insulation layer that at least partly covers a face of the carrier. The dielectric constant ∈ | 06-05-2014 |
| 20140151857 | METHOD AND SYSTEM FOR BINDING HALIDE-BASED CONTAMINANTS - A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized within the deposition chamber to remove halides, such as chlorine and chlorides, during the deposition process so that contamination of the titanium-based film is minimized. A method for regenerating the halide adsorbing material is also provided. | 06-05-2014 |
| 20140159211 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a dielectric layer located on a substrate, wherein the dielectric layer includes nitrogen atoms, and the concentration of the nitrogen atoms in the dielectric layer is lower than 5% at a location wherein the distance between this location in the dielectric layer to the substrate is less than 20% of the thickness of the dielectric layer. Moreover, the present invention provides a semiconductor process including the following steps: a dielectric layer is formed on a substrate. Two annealing processes are performed in-situly on the dielectric layer, wherein the two annealing processes have different imported gases and different annealing temperatures. | 06-12-2014 |
| 20140167227 | METHOD OF MAKING A SEMICONDUCTOR DEVICE USING MULTIPLE LAYER SETS - A mechanism for forming a semiconductor device is described. The semiconductor device includes a substrate and an inter-layer dielectric (ILD) layer over the substrate. The intermediate semiconductor device further includes a first layer set over the ILD layer and a second layer set over the first layer set. The intermediate semiconductor device further includes a photoresist layer over the second layer set. The method further includes etching the second layer set to form a tapered opening in the second layer set, the tapered opening having sidewalls at an angle with respect to a top surface of the ILD layer ranging from about 85-degrees to about 90-degrees, but less than 90-degrees. The method further includes etching the first layer set to form an opening in the first layer set and etching the ILD layer using the first layer set as a mask to form an opening in the ILD layer. | 06-19-2014 |
| 20140167228 | ETCH PROCESS WITH PRE-ETCH TRANSIENT CONDITIONING - A method for etching features with different aspect ratios in an etch layer is provided. A plurality of cycles is provided wherein each cycle comprises a pre-etch transient conditioning of the etch layer, which provides a transient condition of the etch layer, wherein the transient condition has a duration and etching the etch layer for a duration, wherein the duration of the etching with respect to the duration of the transient condition is controlled to control etch aspect ratio dependence. | 06-19-2014 |
| 20140175617 | OXYGEN-CONTAINING CERAMIC HARD MASKS AND ASSOCIATED WET-CLEANS - A method of forming an oxygen-containing ceramic hard mask film on a semiconductor substrate involves receiving a semiconductor substrate in a plasma-enhanced chemical vapor deposition (PECVD) process chamber and depositing forming by PEVCD on the substrate an oxygen-containing ceramic hard mask film, the film being etch selective to low-k dielectric and copper, resistant to plasma dry-etch and removable by wet-etch. The method may further involve removing the oxygen-containing ceramic hard mask film from the substrate with a wet etch. Corresponding films and apparatus are also provided. | 06-26-2014 |
| 20140183706 | Dielectric Films Comprising Silicon And Methods For Making Same - Described herein are methods of forming dielectric films comprising silicon, such as, but not limited to, silicon oxide, silicon oxycarbide, silicon carbide, and combinations thereof, that exhibit at least one of the following characteristics: low wet etch resistance, a dielectric constant of 6.0 or below, and/or can withstand a high temperature rapid thermal anneal process. Also disclosed herein are the methods to form dielectric films or coatings on an object to be processed, such as, for example, a semiconductor wafer. | 07-03-2014 |
| 20140191375 | METHODS FOR FABRICATING THREE-DIMENSIONAL NANO-SCALE STRUCTURES AND DEVICES - A method of fabricating a 3 dimensional structure, includes: forming a stack of at least 2 layers of photo resist material having different photo resist sensitivities upon a substrate; exposing the stack to beams of electromagnetic radiation or charged particles of different dosages to achieve selective solubility along a height of the stack; and dissolving soluble portions of the stack with a solvent to produce a 3 dimensional structure of desired geometry. | 07-10-2014 |
| 20140203413 | Composite Substrate, Semiconductor Chip Having a Composite Substrate and Method for Producing Composite Substrates and Semiconductor Chips - A composite substrate has a carrier and a utility layer. The utility layer is attached to the carrier by means of a dielectric bonding layer and the carrier contains a radiation conversion material. Other embodiments relate to a semiconductor chip having such a composite substrate, a method for producing a composite substrate and a method for producing a semiconductor chip with a composite substrate. | 07-24-2014 |
| 20140203414 | Method Of Modifying Surfaces - The invention provides a method for chemically modifying a surface of a substrate, preferably a silicon substrate, including the steps of providing a substrate having at least a portion of a surface thereof coated with an organic coating composition including unsaturated moieties forming a surface coating, and introducing a vapour phase reactive intermediate species based on a Group 14 or Group 15 element from the Periodic Table of Elements to the substrate whereupon the reactive intermediate species is able to react with a number of the unsaturated moieties in the coating composition thereby chemically modifying the surface coating. Also disclosed is a surface-modified substrate obtained or obtainable by the method, and uses thereof in the fabrication of MEMS and IC devices. | 07-24-2014 |
| 20140231968 | Conformal Anti-Reflective Coating - In one aspect, a method is disclosed that includes providing a substrate having a topography that comprises a relief and providing an anti-reflective film conformally over the substrate using a molecular layer deposition step. The anti-reflective film may be formed of a compound selected from the group consisting of: (i) an organic compound chemically bound to an inorganic compound, where one of the organic compound and the inorganic compound is bound to the substrate and where the organic compound absorbs light at at least one wavelength selected in the range 150-500 nm, or (ii) a monodisperse organic compound absorbing light at at least one wavelength selected in the range 150-500 nm. The method further includes providing a photoresist layer on the anti-reflective film. | 08-21-2014 |
| 20140239461 | Oxygen Monolayer on a Semiconductor - A Si or Ge semi-conductor substrate includes an oxygen monolayer on a surface thereof. The oxygen monolayer can be fractional or complete. A Si | 08-28-2014 |
| 20140246758 | NITROGEN-CONTAINING OXIDE FILM AND METHOD OF FORMING THE SAME - A method of forming a nitrogen-containing oxide film is disclosed. The method comprises (a) exposing a substrate to a first gas pulse having one of an oxygen-containing gas and a metal-containing gas; (b) exposing the substrate to a second gas pulse having the other of the oxygen-containing gas and the metal-containing gas to form an oxide film over the substrate; and (c) exposing the oxide film to a third gas pulse having a nitrogen-containing plasma to form a nitrogen-containing oxide film, wherein the nitrogen-containing oxide film has a nitrogen concentration between about 0.1 and about 3 atomic percent (at %). | 09-04-2014 |
| 20140246759 | SEMICONDUCTOR DEVICE STRUCTURES COMPRISING A POLYMER BONDED TO A BASE MATERIAL AND METHODS OF FABRICATION - Methods for adhering materials and methods for enhancing adhesion between materials are disclosed. In some embodiments, a polymer brush material is bonded to a base material, and a developable polymer resist material is applied over the grafted polymer brush material. The resist material is at least partially miscible in the grafted polymer brush material. As such, the resist material at least partially dissolves within the grafted polymer brush material to form an intertwined material of grafted polymer brush macromolecules and resist polymer macromolecules. Adhesion between the developable polymer resist and the base material may be thereby enhanced. Also disclosed are related semiconductor device structures. | 09-04-2014 |
| 20140264778 | PRECURSOR COMPOSITION FOR DEPOSITION OF SILICON DIOXIDE FILM AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A precursor composition for forming a silicon dioxide film on a substrate, the precursor composition including at least one precursor compound represented by the following chemical formulas (1), (2), and (3): | 09-18-2014 |
| 20140264779 | Metal Deposition on Substrates - Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate. | 09-18-2014 |
| 20140264780 | ADHESION LAYER TO MINIMIZE DIELECTRIC CONSTANT INCREASE WITH GOOD ADHESION STRENGTH IN A PECVD PROCESS - Embodiments of the present invention provide a film stack and method for depositing an adhesive layer for a low dielectric constant bulk layer without the need for an initiation layer. A film stack for use in a semiconductor device comprises of a dual layer low-K dielectric deposited directly on an underlying layer. The dual low-K dielectric consists of an adhesive layer deposited without a carbon free initiation layer. | 09-18-2014 |
| 20140306324 | SEMICONDUCTOR DEVICE WITH A POLYMER SUBSTRATE AND METHODS OF MANUFACTURING THE SAME - A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure having a first surface and a second surface. A polymer substrate having a high thermal conductivity and a high electrical resistivity is disposed onto the first surface of the semiconductor stack structure. One method includes providing the semiconductor stack structure with the first surface in direct contact with a wafer handle. A next step involves removing the wafer handle to expose the first surface of the semiconductor stack structure. A following step includes disposing a polymer substrate having high thermal conductivity and high electrical resistivity directly onto the first surface of the semiconductor stack structure. | 10-16-2014 |
| 20140312471 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device has a plurality of closely spaced fins each coated at its top and sidewalls with a SiGe layer used for improving charge carrier mobility in a channel portion of the device. The sidewalls of the closely adjacent Fins are selectively thinned so as to prevent an undesired bridging of SiGe material between immediately adjacent ones of the Fins. A method of manufacturing the same comprises: providing a substrate having a plurality of tri-gate transistors, at least two fins of the tri-gate transistors being closely adjacent to each other, where respective top and sidewall surfaces of the fins are coated with a SiGe layer; performing a tilted ion implantation on the SiGe coated fins so as to partially convert the SiGe material into a predetermined etch resistant material (e.g., and oxide of the SiGe); and etching away the non-converted sidewall parts of the SiGe coating layers so as to provide greater spacing between the immediately adjacent sidewalls of the SiGe coated fins. | 10-23-2014 |
| 20140319658 | CHARGE PUMP CAPACITOR ASSEMBLY WITH SILICON ETCHING - Charge pump capacitor assemblies and methods of manufacturing the same. One charge pump capacitor assembly includes a charge pump capacitor and a silicon substrate. The charge pump capacitor includes: a silicon-based charge pump capacitor oxide layer, a first terminal on a first side of the silicon-based charge pump layer, a second terminal on a second side of the silicon-based charge pump capacitor oxide layer opposite the first side, and a field oxide layer mounted adjacent the second terminal. The charge pump capacitor is coupled to the silicon substrate. The silicon substrate is etched to reduce contact between the silicon substrate and the field oxide layer. | 10-30-2014 |
| 20140319659 | RESIST UNDERLAYER COMPOSITION, METHOD OF FORMING PATTERNS AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING THE PATTERNS - A resist underlayer composition, a method of forming patterns, and semiconductor integrated circuit device, the composition including a solvent; and a compound including a moiety represented by the following Chemical Formula 1: | 10-30-2014 |
| 20140319660 | SOLID-STATE ELECTRONIC DEVICE - A solid-state electronic device according to the present invention includes: an oxide layer (possibly containing inevitable impurities) that is formed by heating, in an atmosphere containing oxygen, a precursor layer obtained from a precursor solution as a start material including both a precursor containing bismuth (Bi) and a precursor containing niobium (Nb) as solutes, the oxide layer consisting of the bismuth (Bi) and the niobium (Nb); wherein the oxide layer is formed by heating at a heating temperature from 520° C. to 650° C. | 10-30-2014 |
| 20140327116 | COMPOSITE SUBSTRATE - Disclosed is a composite substrate, which is provided with an inorganic insulating sintered substrate, which has a heat conductivity of 5 W/m·K or more, and a volume resistivity of 1×10 | 11-06-2014 |
| 20140332935 | MgO-Based Coating for Electrically Insulating Semiconductive Substrates and Production Method Thereof - The present invention relates to a magnesium oxide-based (MgO) inorganic coating intended to electrically insulate semiconductive substrates such as silicon carbide (SiC), and to a method for producing such an insulating coating. The method of the invention comprises the steps of preparing a treatment solution of at least one hydrolysable organomagnesium compound and/or of at least one hydrolysable magnesium salt, capable of forming a homogeneous polymer layer of magnesium oxyhydroxide by hydrolysis/condensation reaction with water; depositing the treatment solution of the hydrolysable organomagnesium compound or of the hydrolysable magnesium salt, onto a surface to form a magnesium oxide-based layer; and densifying the layer formed at a temperature of less than or equal to 1000° C. | 11-13-2014 |
| 20140339684 | SYNTHETIC DIAMOND COATED COMPOUND SEMICONDUCTOR SUBSTRATES - A method of fabricating a synthetic diamond coated compound semiconductor substrate, the method comprising: loading a composite substrate into a chemical vapour deposition (CVD) reactor, the composite substrate comprising a single crystal carrier wafer, a layer of single crystal compound semiconductor epitaxially grown on the carrier wafer, and an interface layer disposed on the layer of compound semiconductor, the interface layer forming a growth surface suitable for growth of synthetic diamond material thereon via a CVD technique; and growing a layer of CVD diamond material on the growth surface of the interface layer, wherein during growth of CVD diamond material a temperature difference at the growth surface between an edge and a centre point thereof is maintained to be no more than 80° C., and wherein the carrier wafer has an aspect ratio, defined by a ratio of thickness to width, of no less than 0.25/100. | 11-20-2014 |
| 20140346648 | LOW-K NITRIDE FILM AND METHOD OF MAKING - A low-K nitride film and a method of making are disclosed. Embodiments include forming a nitride film on a substrate by plasma enhanced chemical vapor deposition (PECVD) and periodically fluctuating a production of radicals during the PECVD based, at least in part, on plural cycles of a radiofrequency (RF) induced plasma. | 11-27-2014 |
| 20140346649 | Three dimension structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 11-27-2014 |
| 20140353805 | METHODS OF SEMICONDUCTOR CONTAMINANT REMOVAL USING SUPERCRITICAL FLUID - A process is provided for the removal of contaminants from a semiconductor device, for example, removing contaminants from pores of an ultra-low k film. In one aspect, a method includes: providing a dielectric layer with contaminant-containing pores and exposing the dielectric layer to a supercritical fluid. The supercritical fluid can dissolve and remove the contaminants. In another aspect, an intermediate semiconductor device structure is provided that contains a dielectric layer with contaminant-containing pores and a supercritical fluid within the pores. In another aspect, a semiconductor device structure with a dielectric layer containing uncontaminated pores is provided. | 12-04-2014 |
| 20140353806 | BYPASS DIODE - A bypass diode includes a semiconductor substrate having a first surface and a second surface opposite to each other, a p electrode as a first conductive type electrode and an n electrode as a second conductive type electrode arranged on the first surface, a back surface electrode arranged on the second surface and having a polarity identical to that of the semiconductor substrate, a first oxide layer arranged on the first surface, and a second oxide layer arranged on the second surface. | 12-04-2014 |
| 20140361415 | PHOTORESISTS AND METHODS FOR USE THEREOF - New photoresists are provided that comprise preferably as distinct components: a resin, a photoactive component and a phenolic component Preferred photoresists of the invention are can be useful for ion implant lithography protocols. | 12-11-2014 |
| 20140374886 | METHOD FOR FABRICATING A SUBSTRATE AND SEMICONDUCTOR STRUCTURE - The invention relates to a method for fabricating a substrate, comprising the steps of providing a donor substrate with at least one free surface, performing an ion implantation at a predetermined depth of the donor substrate to form an in-depth predetermined splitting area inside the donor substrate, and is characterized in providing a layer of an adhesive, in particular an adhesive paste, over the at least one free surface of the donor substrate. The invention further relates to a semiconductor structure comprising a semiconductor layer, and a layer of a ceramic-based and/or a graphite-based and/or a metal-based adhesive provided on one main side of the semiconductor layer. | 12-25-2014 |
| 20140374887 | COMPOSITION FOR FORMING PASSIVATION FILM, INCLUDING RESIN HAVING CARBON-CARBON MULTIPLE BOND - There is provided a composition for forming a passivation film that satisfies electric insulation, heat-tolerance, solvent-tolerance, and a dry etch back property at the same time. A composition for forming a passivation film, including: a polymer containing a unit structure of Formula (i): | 12-25-2014 |
| 20150014822 | METHOD OF TESTING A SEMICONDUCTOR ON INSULATOR STRUCTURE AND APPLICATION OF SAID TEST TO THE FABRICATION OF SUCH A STRUCTURE - The invention concerns a method of testing a semiconductor on insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (Q | 01-15-2015 |
| 20150014823 | COMPOSITIONS AND METHODS FOR MAKING SILICON CONTAINING FILMS - Described herein are low temperature processed high quality silicon containing films. Also disclosed are methods of forming silicon containing films at low temperatures. In one aspect, there are provided silicon-containing film having a thickness of about 2 nm to about 200 nm and a density of about 2.2 g/cm | 01-15-2015 |
| 20150035126 | METHODS AND STRUCTURES FOR PROCESSING SEMICONDUCTOR DEVICES - Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at least adjacent a periphery of the carrier substrate, adhesively bonding another substrate to the carrier substrate, and separating the another substrate from the carrier substrate. The silane material includes a compound having a structure of (XO) | 02-05-2015 |
| 20150041963 | Semiconductor Device Having a Surface with Ripples - According to one embodiment of a semiconductor device, the semiconductor device includes a semiconductor substrate having a first surface, an insulation layer having a laterally varying thickness on the first surface, and a metal layer on the first surface. The insulation layer has ripples in its surface facing the metal layer. According to another embodiment of a semiconductor device, the semiconductor device includes a semiconductor substrate having a first surface and including at least one of a laterally varying thickness and an inclined first surface. The first surface of the semiconductor substrate has ripples. | 02-12-2015 |
| 20150048487 | PLASMA POLYMERIZED THIN FILM HAVING HIGH HARDNESS AND LOW DIELECTRIC CONSTANT AND MANUFACTURING METHOD THEREOF - The present invention relates to a plasma polymerized thin film having high hardness and a low dielectric constant and a manufacturing method thereof, and in particular, relates to a plasma polymerized thin film having high hardness and a low dielectric constant for use in semiconductor devices, which has improved mechanical strength properties such as hardness and elastic modulus while having a low dielectric constant, and a manufacturing method thereof. | 02-19-2015 |
| 20150054142 | Wafer Surface Conditioning for Stability in Fab Environment - Hydroxyl moieties are formed on a surface over a semiconductor substrate. The surfaces are silylized to replace the hydroxyl groups with silyl ether groups, the silyl ether groups being of the form: —OSiR | 02-26-2015 |
| 20150069585 | SEMICONDUCTOR DEVICE WITH AN ANGLED PASSIVATION LAYER - A semiconductor device includes a first passivation layer including a first passivation portion and a second passivation portion substantially diametrically opposite the first passivation portion. The semiconductor device includes a first corner of the first passivation portion separated a first distance from a second corner of the second passivation portion. A third corner of the first passivation portion is separated a second distance from a fourth corner of the second passivation portion. The first distance is not equal to the second distance | 03-12-2015 |
| 20150091141 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. The second protective layer reveals the first anti-stress zone and comprises a second surface, a first lateral side, a second lateral side and a first connection side. The second surface comprises a second anti-stress zone. An extension line of the first lateral side intersects with an extension line of the second lateral side to form a first intersection point. A zone formed by connecting the first intersection point and two points of the first connection side is the first anti-stress zone. The third protective layer reveals the second anti-stress zone and comprises a second connection side projected on the first surface to form a projection line parallel to the first connection side. | 04-02-2015 |
| 20150091142 | Layer Deposition on III-V Semiconductors - The present disclosure relates to a method ( | 04-02-2015 |
| 20150108618 | COMPOSITION AND METHOD FOR FORMING A DIELECTRIC LAYER - A porous layer is described. The porous layer comprises a solidified sol-gel inorganic material having a distribution of nanometric voids, wherein at least some of nanometric voids are at least partially coated internally by carbon or a hydrophobic substance containing carbon. | 04-23-2015 |
| 20150108619 | METHOD FOR PATTERNING A SEMICONDUCTOR SUBSTRATE - Embodiments of the present disclosure provide methods for patterning rectangular features with a sequence of lithography, atomic layer deposition (ALD) and etching. Embodiment of the present disclosure includes forming first line clusters along a first direction and second line clusters over the first line clusters in a direction traversing the first direction. The first and second line clusters both include core lines formed from a core material, spacers formed from first and second materials by ALD and etching. After formation of the first and second line clusters, rectangular openings can be formed by selectively etching one or two of the core material, the first material or the second material. | 04-23-2015 |
| 20150115415 | Inkjet Printing on Substrates - Methods, apparatuses and devices relate to inkjet printing a covering layer on at least a first side of a substrate in a peripheral region thereof are discussed. | 04-30-2015 |
| 20150115416 | SILICON-ON-PLASTIC SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME - A semiconductor device that does not produce nonlinearities attributed to a high resistivity silicon handle interfaced with a dielectric region of a buried oxide (BOX) layer is disclosed. The semiconductor device includes a semiconductor stack structure with a first surface and a second surface wherein the second surface is on an opposite side of the semiconductor stack structure from the first surface. At least one device terminal is included in the semiconductor stack structure and at least one electrical contact extends from the second surface and is electrically coupled to the at least one device terminal. The semiconductor stack is protected by a polymer disposed on the first surface of the semiconductor stack. The polymer has high thermal conductivity and high electrical resistivity. | 04-30-2015 |
| 20150115417 | METHODS FOR MANUFACTURING A CHIP ARRANGEMENT, METHODS FOR MANUFACTURING A CHIP PACKAGE, A CHIP PACKAGE AND CHIP ARRANGEMENTS - A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall. | 04-30-2015 |
| 20150123250 | METHODS OF FABRICATING DEFECT-FREE SEMICONDUCTOR STRUCTURES - Methods of facilitating fabrication of defect-free semiconductor structures are provided which include, for instance: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure. | 05-07-2015 |
| 20150145106 | ELECTRONIC DEVICE MANUFACTURE USING LOW-k DIELECTRIC MATERIALS - Materials and methods for manufacturing electronic devices and semiconductor components using low dielectric materials comprising polyimide based aerogels are described. Additional methods for manipulating the properties of the dielectric materials and affecting the overall dielectric property of the system are also provided. | 05-28-2015 |
| 20150344627 | LOW MODULUS NEGATIVE TONE, AQUEOUS DEVELOPABLE PHOTORESIST - Hydrophobic, low modulus, photoimagable, functionalized polyimides have been discovered that can be developed using aqueous solutions. In particular, compositions containing the functionalized polyimides of the current invention can be used in the photolithography step for the passivation layer on a silicon wafer to reduce stress in thin wafers, or as a low modulus hydrophobic solder mask. These materials can serve as protective layers in other applications in which a thin, flexible, and hydrophobic polymer is required. | 12-03-2015 |
| 20160035570 | Method for Masking a Surface Comprising Silicon Oxide - A method for masking a surface, in particular a surface having silicon oxide, aluminum or silicon, includes providing a substrate having a surface to be masked, in particular having a surface having silicon oxide, aluminum or silicon; and producing a defined masking pattern by locally selective forming of colloidal silicon oxide on the surface. The method allows for the creating of an extremely stable masking in a simple and cost-effective manner, in contrast to a plurality of etching media, in particular in contrast to hydrofluoric acid, in order to thus create extremely accurate and defined structures such as by an etching process. | 02-04-2016 |
| 20160041470 | RESIST UNDERLAYER COMPOSITION, METHOD OF FORMING PATTERNS, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING THE PATTERN - Disclosed is a resist underlayer composition including a compound including a moiety represented by the following Chemical Formula 1 and a solvent. | 02-11-2016 |
| 20160118350 | INTERCONNECT ARRANGEMENT WITH STRESS-REDUCING STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor device structure and a method of fabricating the same are provided. The semiconductor structure includes a substrate and an interconnection structure formed over the substrate. The interconnection structure includes a first dielectric layer and a first stress-reducing structure formed in the first dielectric layer. The interconnection structure further includes a first conductive feature formed in the first dielectric layer, and the first conductive feature is surrounded by the first stress-reducing structure. | 04-28-2016 |
| 20160155633 | AZIDE-BASED CROSSLINKING AGENTS | 06-02-2016 |
| 20160167345 | Protective Film Forming Film, Sheet For Forming Protective Film, and Inspection Method | 06-16-2016 |
| 20160181103 | SEMICONDUCTOR DEVICE INCLUDING SMALL PITCH PATTERNS | 06-23-2016 |
| 20160190030 | SELF-LIMITING CHEMICAL VAPOR DEPOSITION AND ATOMIC LAYER DEPOSITION METHODS - Methods for depositing silicon on a semiconductor or metallic surface include cycling dosing of silane and chlorosilane precursors at a temperature between 50° C. and 300° C., and continuing cycling between three and twenty three cycles until the deposition self-limits via termination of surface sites with Si—H groups. Methods of layer formation include depositing a chlorosilane onto a substrate to form a first layer, wherein the substrate is selected from the group consisting of In | 06-30-2016 |
| 20190148144 | ENHANCED SELECTIVE DEPOSITION PROCESS | 05-16-2019 |
| 20220139793 | POWER SEMICONDUCTOR DEVICES WITH IMPROVED OVERCOAT ADHESION AND/OR PROTECTION - A power semiconductor device includes a semiconductor layer structure and a protective overcoating on a bonding surface of the semiconductor layer structure. The bonding surface includes a plurality of adhesion features along an interface with the protective overcoating. The adhesion features protrude from and/or are recessed in the bonding surface, and define an adhesion strength between the bonding surface and the protective overcoating that spatially varies along the interface. Related devices and fabrication methods are also discussed. | 05-05-2022 |
