| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257647000 | Insulating layer recessed into semiconductor surface (e.g., LOCOS oxide) | 17 |
| 20080203542 | ION-ASSISTED OXIDATION METHODS AND THE RESULTING STRUCTURES - Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure. | 08-28-2008 |
| 20080203543 | Semiconductor integrated circuit substrate containing isolation structures - Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths. | 08-28-2008 |
| 20080237812 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes the steps of forming a trench on a semiconductor substrate to define a first and a second element regions; burying a first oxide film in the trench; forming a second oxide film on surfaces of the first and second element regions; performing a first ion doping using a first mask which is exposing a first region containing the first element region and a part of the first oxide; performing a second ion doping using a second mask which is exposing a second region containing the second element region and a part of the first oxide film; and removing the second oxide film formed in the first element region and the second element region by etching, and the first oxide film is selectively thinned using the first or second mask after performing the first or second ion doping. | 10-02-2008 |
| 20080277767 | Semiconductor device including a planarized surface and method thereof - A method of planarizing the surface of a semiconductor substrate to reduce the occurrence of a dishing phenomenon. A patterned etch stop layer defining a trench region is formed on a substrate. The substrate is etched to form a trench region, and a medium material layer and an oxide layer are subsequently formed on the substrate, filling the trench region. Chemical mechanical polishing (CMP) is performed on the oxide layer until the medium material layer is exposed. CMP is then performed until the patterned etch stop layer is exposed and a planarized oxide layer is formed. Because the medium material layer has a higher removal rate during CMP than the oxide layer, occurrences of the dishing phenomenon are reduced. A slurry including an anionic surfactant is used to increase the CMP removal ratio of the medium material layer to the oxide layer. | 11-13-2008 |
| 20090032911 | PATTERNED THIN SOI - A process for treating a structure to prepare it for electronics or optoelectronics applications. The structure includes a bulk substrate, an oxide layer, and a semiconductor layer, and the process includes providing a masking to define on the semiconductor layer a desired pattern, and applying a thermal treatment for removing a controlled thickness of oxide in the regions of the oxide layer corresponding to the desired pattern to assist in preparing the structure. | 02-05-2009 |
| 20090184402 | METHOD OF FABRICATING A SHALLOW TRENCH ISOLATION STRUCTURE INCLUDING FORMING A SECOND LINER COVERING THE CORNER OF THE TRENCH AND FIRST LINER. - A method of fabricating a shallow trench isolation structure is provided. First, a pad oxide layer and a mask layer are formed sequentially on a substrate. Then, the mask layer and the pad oxide layer are patterned and the substrate is etched to form a trench. After that, a first liner is formed in the trench. Thereafter, a portion of the first liner is removed to expose corners of the trench. Then, a second liner is formed over the substrate to cover the corners of the trench and the first liner. The material of the second liner is different from that of the first liner. An insulation layer is further formed over the substrate to fill up the trench. The insulation layer, the second liner, the mask layer and the pad oxide layer outside the trench are eventually removed. | 07-23-2009 |
| 20090243050 | Isolation Structure in Memory Device and Method for Fabricating the Same - A method for fabricating an isolation structure in a memory device includes forming a first trench in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. The method also includes oxidating the surface of the first and second trenches to form a sidewall oxide layer; depositing a tetraethylorthosilicate(TEOS) layer on the sidewall oxide layer; forming a silicon nitride layer and a silicon oxide layer on the TEOS layer; selectively removing portions of the silicon nitride and silicon oxide layers on the second trench to expose a portion of the underlying TEOS layer; coating a flowable insulation layer that fills the first and second trenches; and curing the flowable insulation layer. | 10-01-2009 |
| 20090283873 | METHOD FOR FORMING SELF-ALIGNMENT INSULATION STRUCTURE - A method for forming a self-align insulation of a passing gate is disclosed. First, a substrate is provided. A deep trench filled with silicon material and a shallow trench isolation adjacent to the deep trench are formed in the substrate. A patterned pad oxide and a patterned hard mask are sequentially formed on the substrate. The patterned pad oxide and the patterned hard mask together define the opening of the deep trench. Then, an oxidation step is carried out to form a first oxide layer serving as the insulation of a passing gate on the top surface of the silicon material of the deep trench. Later, a first Si layer is formed to cover the first oxide layer. Afterwards, the hard mask is removed. | 11-19-2009 |
| 20090294927 | SEMICONDUCTOR-DEVICE ISOLATION STRUCTURE AND MANUFACTURING METHOD THEREBY - A manufacturing method for a semiconductor-device isolation structure comprises providing a substrate with at least one shallow trench isolation structure, performing a salicide process that forms a recess on the surface of the shallow trench isolation structure, forming a cap film covering the substrate and filling the recess, performing an etching process to remove the cap film outside the recess, and forming a contact etch stop layer covering the substrate and filling the recess. Due to the filling recess with the cap film first, the contact etch stop layer covering the substrate and filling the recess does not have seams or voids. | 12-03-2009 |
| 20100006985 | FORMATION OF SOI BY OXIDATION OF SILICON WITH ENGINEERED POROSITY GRADIENT - A method is provided for making a silicon-on-insulator substrate. Such method can include epitaxially growing a highly p-type doped silicon-containing layer onto a major surface of an underlying semiconductor region of a substrate. Subsequently, a non-highly p-type doped silicon-containing layer may be epitaxially grown onto a major surface of the p-type highly-doped epitaxial layer to cover the highly p-type doped epitaxial layer. The overlying non-highly p-type doped epitaxial layer can have a dopant concentration substantially lower than the dopant concentration of the highly p-type doped epitaxial layer. The substrate can then be processed to form a buried oxide layer selectively by oxidizing at least portions of the highly p-type doped epitaxial layer covered by the non-highly p-type doped epitaxial layer, the buried oxide layer separating the overlying monocrystalline semiconductor layer from the underlying semiconductor region. Such processing can be performed while simultaneously annealing the non-highly p-type doped epitaxial layer. | 01-14-2010 |
| 20100164075 | TRENCH FORMING METHOD AND STRUCTURE - An electrical structure and method of forming. The method includes providing a semiconductor structure comprising a semiconductor substrate, a buried oxide layer (BOX) formed over the semiconductor substrate, and a silicon on insulator layer (SOI) formed over and in contact with the BOX layer. The SOI layer comprises shallow trench isolation (STI) structures formed between electrical devices. A first photoresist layer is formed over the STI structures and the electrical devices. Portions of said first photoresist layer, portions of the STI structures, and portions of the BOX layer are removed resulting in formed trenches. Ion implants are formed within portions of the semiconductor substrate. Remaining portions of the first photoresist layer are removed. A dielectric layer is formed over the electrical devices and within the trenches. A second photoresist layer is formed over the dielectric layer. Portions of the second photoresist layer are removed. | 07-01-2010 |
| 20110156222 | Silicon Wafer and Manufacturing Method Thereof - Silicon wafers, are manufactured with which a desired strength and electric resistance of a semiconductor device can be obtained. A non-oxidizing heat treatment for oxygen out-diffusion is performed wherein the desired amount of oxygen is discharged from the surface layer of the silicon substrate. By this heat treatment for oxygen out-diffusion, a surface layer having a low oxygen content is formed on the silicon substrate, the heat treatment of the silicon substrate being performed through an oxide film. | 06-30-2011 |
| 20110180912 | PATTERNED THIN SOI - A semiconductor structure for electronics or optoelectronics that includes successively a bulk substrate, an oxide layer and a semiconductor layer, wherein the oxide layer comprises regions of different thicknesses which are selectively controlled. | 07-28-2011 |
| 20120223420 | SEMICONDUCTOR BODY WITH A BURIED MATERIAL LAYER - One aspect includes a semiconductor arrangement with a semiconductor body having a first surface. A buried material layer is in the semiconductor body, the buried material layer being arranged distant to the first surface. A monocrystalline semiconductor material is arranged between the material layer and the first surface, and a monocrystalline semiconductor material adjoins the material layer in a lateral direction of the semiconductor body. | 09-06-2012 |
| 20140291817 | SEMICONDUCTOR DEVICE INCLUDING POROUS LOW-K DIELECTRIC LAYER AND FABRICATION METHOD - Semiconductor devices including porous low-k dielectric layers and fabrication methods are provided. A dielectric layer is formed on a substrate by introducing and polymerizing a main reaction gas on a surface of the substrate. The main reaction gas has a chemical structure including a ring-shaped group, silicon, carbon, and hydrogen, and the ring-shaped group includes at least carbon and hydrogen. A porous low-k dielectric layer is then formed from the dielectric layer by curing the dielectric layer with UV light. | 10-02-2014 |
| 20140306325 | COMPENSATION FOR A CHARGE IN A SILICON SUBSTRATE - A silicon device includes an active silicon layer, a buried oxide (BOX) layer beneath the active silicon layer and a high-resistivity silicon layer beneath the BOX layer. The device also includes a harmonic suppression layer at a boundary of the BOX layer and the high-resistivity silicon layer. | 10-16-2014 |
| 20150014824 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - The present invention relates to a method for fabricating a substrate for a semiconductor device comprising an interface region between a first layer and a second layer having different electrical properties and an exposed surface, wherein at least the second layer includes defects and/or dislocations, the method comprising the steps of: a) removing material at one or more locations of the defects and/or dislocations, thereby forming pits, wherein the pits intersect the interface region, and b) passivating the pits. The invention also relates to a corresponding semiconductor device structure. | 01-15-2015 |
