| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257578000 | With enlarged emitter area (e.g., power device) | 15 |
| 20090079031 | METHOD AND DEVICE WITH IMPROVED BASE ACCESS RESISTANCE FOR NPN BIPOLAR TRANSISTOR - A configuration composed of multiple short emitters still share common DTI regions and a single big piece of base poly. This allows for base current to flow in 4 directions (e.g., 2 dimensions) as opposed to only two. This significantly reduces the base resistance of the transistor that is crucial for better NPN transistor RF performance and high frequency noise performance. | 03-26-2009 |
| 20090127660 | STRUCTURE AND METHOD FOR FORMING A GUARD RING TO PROTECT A CONTROL DEVICE IN A POWER SEMICONDUCTOR IC - Provided is a power semiconductor device including a guard ring region to protect control devices. The power semiconductor device includes a semiconductor body layer extending over a semiconductor substrate of a first conductivity type. The semiconductor body layer has a second conductivity type opposite the first conductivity type. A well of the first conductivity type extends in the semiconductor body layer and is configured to be electrically insulated from the semiconductor substrate. At least one control device is formed in the well, where the control device comprises at least one of PN junction. A guard ring region of the first conductivity type is laterally spaced from but surrounds the well. The guard ring region together with the semiconductor substrate and the semiconductor body layer form a parasitic bipolar transistor, and the guard ring region functions as a collector of the parasitic bipolar transistor. | 05-21-2009 |
| 20090302423 | ESD protection circuit and semiconductor device - An electrostatic discharge protection circuit has a bipolar transistor which includes a first diffusion layer of a first conductive type connected with a first power supply and functioning as a base; a second diffusion layer of a second conductive type connected with a second power supply and functioning as a collector; and a third diffusion layer of the second conductive type connected with an input/output pad and functioning as an emitter. An area of a first region of the third diffusion layer which is opposite to the first diffusion layer is larger than an area of a second region of the second diffusion layer which is opposite to the first diffusion layer. | 12-10-2009 |
| 20100155895 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a P type silicon substrate; a deep N well in the P type silicon substrate; a P grade region in the deep N well; a P | 06-24-2010 |
| 20170236923 | BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME | 08-17-2017 |
| 257579000 | With separate emitter areas connected in parallel | 7 |
| 20080203535 | SEMICONDUCTOR DEVICE - A semiconductor device relating to the present invention comprises a base layer of an N-type impurity region. In the base layer, trenches are provided. In the each trench, a gate insulating film and a gate electrode are formed. A body layer of a P-type impurity region is formed in contact with the trenches, and in parallel adjacent to the base layer. On the main surface of the body layer, an emitter layer of an N-type impurity region is provided. On the main surface of the body layer, a contact layer of a P-type impurity region is provided spaced from the trenches. The emitter layer and the contact layer are exposed in different regions on the main surface of the body layer. A buried layer of a P-type impurity region is formed spaced from the trenches in closer to the base layer than to the contact layer in the body layer. | 08-28-2008 |
| 20080224266 | LATERAL BIPOLAR TRANSISTOR - A lateral bipolar transistor is described, including a semiconductor substrate, a gate structure on the substrate, an emitter and a collector of a first conductivity type in the substrate, and a base of a second conductivity type in the substrate. The gate structure has a structure enclosing one or more closed areas. The emitter and the collector respectively includes a plurality of electrically connected unit emitters and a plurality of electrically connected unit collectors defined by the gate structure, which are arranged laterally intermixing with each other and separated by the substrate under the gate structure. The base includes a part under the gate structure. | 09-18-2008 |
| 20090020852 | SEMICONDUCTOR DEVICE - An emitter layer is provided in stripes in a direction orthogonal to an effective gate trench region connected to a gate electrode and a dummy trench region isolated from the gate electrode. A width of the emitter layer is determined to satisfy a predetermined relational expression so as not to cause latch-up in an underlying P base layer. In the predetermined relational expression, an upper limit value of the width W of the emitter layer is (3500/Rspb)·Wso·exp(decimation ratio), where Rspb is a sheet resistance of the P base layer immediately below the emitter layer, Wso is an interval between the trenches, and the decimation ratio is a ratio of the number of the effective gate trench region to the total number of the trench regions. Variations in saturation current in a trench IGBT can be suppressed, and a tolerance of an Reverse Bias Safe Operation Area can be improved. | 01-22-2009 |
| 20090315146 | Compact dual direction BJT clamps - In a dual direction BJT clamp, multiple emitter and base fingers are alternatingly connected to ground and pad and share a common sub-collector. | 12-24-2009 |
| 20120223415 | IGBT Power Semiconductor Package Having a Conductive Clip - According to one disclosed embodiment, a power semiconductor package includes an insulated-gate bipolar transistor (IGBT) residing on a package substrate, where the IGBT includes a plurality of solderable front metal (SFM) coated emitter segments situated atop the IGBT and connected to an emitter of the IGBT. The power semiconductor package also includes a conductive clip coupling the plurality of SFM coated emitter segments to an emitter pad on the package substrate. Additionally, the power semiconductor package includes a gate pad on the package substrate coupled to a gate of the IGBT, a collector pad on the package substrate situated under the IGBT and coupled to a collector of the IGBT, and an emitter terminal, a collector terminal and a gate terminal of the package substrate that are routed to the emitter pad, collector pad, and gate pad, respectively. | 09-06-2012 |
| 20160133731 | LATERAL BIPOLAR JUNCTION TRANSISTORS HAVING HIGH CURRENT-DRIVING CAPABILITY - A bipolar junction transistor includes a common base region, a plurality of emitter regions disposed in the common base region and arrayed to be spaced apart from each other in a first diagonal direction, and a plurality of collector regions disposed in the common base region and arrayed to be spaced apart from each other in the first diagonal direction. The plurality of emitter regions and the plurality of collector regions are alternately arrayed in a second diagonal direction. | 05-12-2016 |
| 257580000 | With current ballasting means (e.g., emitter ballasting resistors or base current ballasting means) | 1 |
| 20090140388 | INTEGRATED CIRCUIT INCLUDING AN EMITTER STRUCTURE AND METHOD FOR PRODUCING THE SAME - A semiconductor emitter structure for emitting charge carriers of a first conductivity type in a base volume of a second conductivity type material neighbored to the emitter structure in a vertical direction, includes multiple emitter volumes of first conductivity tape material having a predetermined lateral dimension in a lateral direction perpendicular to the vertical direction. The emitter volumes are, in the lateral direction, neighbored by semiconductor volumes of second conductivity type material, wherein the predetermined lateral dimension is such that space charges created by second conductivity type carriers laterally diffusing into the emitter volumes from the semiconductor volumes limit a maximum density of first conductivity type carriers within the emitter volumes by more than 20% as compared to emitter volumes of the same lateral dimension not neighbored by semiconductor volumes of the second conductivity type material. | 06-04-2009 |
| 257582000 | With current ballasting means (e.g., emitter ballasting resistors or base current ballasting resistors) | 1 |
| 20140361406 | SEMICONDUCTOR DEVICE AND RADIO COMMUNICATION DEVICE - A radio communication device includes a power amplifier having a semiconductor device formed with a plurality of unit transistors. Base electrodes of the unit transistors are connected with each other by a base line, and an input capacitor is connected to the base line such that the input capacitor is commonly and electrically connected to the base electrodes of a plurality of the unit transistors. | 12-11-2014 |
| 257584000 | With housing or contact (i.e., electrode) means | 2 |
| 20100025820 | SEMICONDUCTOR DEVICE - In a first region at a first main surface of an n type semiconductor substrate, a p base layer, an n source layer, a gate electrode and an emitter electrode are formed, and a collector electrode is formed at a second main surface, constituting an IGBT. A p layer constituting a guard ring is formed in a second region qualified as an outer circumferential junction region, extending to a predetermined depth from the surface. In the second region are also formed an AlSi layer and a semi-insulating silicon nitride film, as well as an over coat film. An n layer is formed at the surface of a third region. In addition, an AlSi layer qualified as a stepped portion is formed in the third region, spaced apart from an AlSi layer located at the outermost circumferential side. Thus, a semiconductor device directed to stabilizing the main breakdown voltage characteristics is obtained. | 02-04-2010 |
| 20150123246 | Bipolar Junction Transistor Formed on Fin Structures - A Bipolar Junction Transistor (BJT) includes an elongated collector line, an elongated emitter line parallel to the collector line, and an elongated base line parallel to the collector line and positioned between the collector line and the base line. The emitter line, the base line, and the collector line are formed over fin structures. | 05-07-2015 |
