| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257272000 | Junction field effect transistor in integrated circuit | 61 |
| 20080230812 | Isolated junction field-effect transistor - Various integrated circuit devices, in particular a junction field-effect transistor (JFET), are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described. | 09-25-2008 |
| 20080272408 | ACTIVE AREA JUNCTION ISOLATION STRUCTURE AND JUNCTION ISOLATED TRANSISTORS INCLUDING IGFET, JFET AND MOS TRANSISTORS AND METHOD FOR MAKING - Integrated active area isolation structure for transistor to replace larger and more expensive Shallow Trench Isolation or field oxide to isolate transistors. Multiple well implant is formed with PN junctions between wells and with surface contacts to substrate and wells so bias voltages applied to reverse bias PN junctions to isolate active areas. Insulating layer is formed on top surface of substrate and interconnect channels are etched in insulating layer which do not go down to the semiconductor substrate. Contact openings for surface contacts to wells and substrate are etched in insulating layer down to semiconductor layer. Doped silicon or metal is formed in contact openings for surface contacts and to form interconnects in channels. Silicide may be formed on top of polycrystalline silicon contacts and interconnect lines to lower resistivity. Any JFET or MOS transistor may be integrated into the resulting junction isolated active area. | 11-06-2008 |
| 20090026506 | SEMICONDUCTOR DEVICE - In the semiconductor device, a gate region is formed in a mesh pattern having first polygonal shapes and second polygonal shapes the area of which is smaller than that of the first polygonal shapes, and drain regions and source regions are disposed within the first polygonal shapes and the second polygonal shapes, respectively. With this configuration, the forward transfer admittance gm can be increased as compared with a structure in which gate regions are disposed in a stripe pattern. Furthermore, compared with a case in which a gate region is disposed in a grid pattern, deterioration in forward transfer characteristics (amplification characteristics) due to an increase in input capacitance Ciss can be minimized while a predetermined withstand voltage is maintained. | 01-29-2009 |
| 20090039398 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An n type impurity region is continuously formed on the bottom portion of a channel region below a source region, a gate region and a drain region. The n type impurity region has an impurity concentration higher than the channel region and a back gate region, and is less influenced by the diffusion of p type impurities from the gate region and the back gate region. Moreover, by continuously forming the impurity region from a portion below the source region to a portion below the drain region, the resistance value of a current path in the impurity region is substantially uniformed. Therefore, the IDSS is stabilized, the forward transfer admittance gm and the voltage gain Gv are improved, and the noise voltage Vno is decreased. Furthermore, the IDSS variation within a single wafer is suppressed. | 02-12-2009 |
| 20090278177 | SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING - Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described. | 11-12-2009 |
| 20100032729 | INTEGRATION OF HIGH VOLTAGE JFET IN LINEAR BIPOLAR CMOS PROCESS - A dual channel JFET which can be integrated in an IC without adding process steps is disclosed. Pinch-off voltage is determined by lateral width of a first, vertical, channel near the source contact. Maximum drain voltage is determined by drain to gate separation and length of a second, horizontal, channel under the gate. Pinch-off voltage and maximum drain potential are dependent on lateral dimensions of the drain and gate wells and may be independently optimized. A method of fabricating the dual channel JFET is also disclosed. | 02-11-2010 |
| 20100065894 | Semiconductor Device Having a Field Effect Source/Drain Region - A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device. | 03-18-2010 |
| 20100090260 | Integrated circuit layout pattern for cross-coupled circuits | 04-15-2010 |
| 20100123171 | Multi-level Lateral Floating Coupled Capacitor Transistor Structures - A semiconductor device includes a source region, a drain region, a gate region, and a drift region. The drift region further includes an active drift region and inactive floating charge control (FCC) regions. The active drift region conducts current between the source region and the drain region when voltage is applied to the gate region. The inactive FCC regions, which field-shape the active drift region to improve breakdown voltage, are vertically stacked in the drift region and are separated by the active drift region. Vertically stacking the inactive FCC regions reduce on-resistance while maintaining higher breakdown voltages. | 05-20-2010 |
| 20100148225 | LOW POWER MEMORY DEVICE WITH JFET DEVICE STRUCTURES - There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory cells having a memory element and a JFET access device electrically coupled to the memory element. The memory cells may be isolated using diffusion based isolation. | 06-17-2010 |
| 20100155789 | LOW NOISE JFET - A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise. | 06-24-2010 |
| 20100207174 | SEMINCONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - The invention provides a method for forming a semiconductor structure. A plurality of first type well regions is formed in the first type substrate. A plurality of second type well regions and a plurality of second type bar doped regions are formed in the first type substrate by a doping process using a mask. The second type bar doped regions are diffused to form a second type continuous region by annealing. The second type continuous region is adjoined with the first type well regions. A second type dopant concentration of the second type continuous region is smaller than a second type dopant concentration of the second type bar doped regions. A second type source/drain region is formed in the second type well region. | 08-19-2010 |
| 20100252867 | MFMS-FET, Ferroelectric Memory Device, And Methods Of Manufacturing The Same - Disclosed herein are a metal-ferroelectric-metal-substrate (MFMS) field-effect transistor (FET), an MFMS-ferroelectric memory device, and method of manufacturing the same. The MFMS-FET and the ferroelectric memory device in accordance with the present invention include: a substrate including source and drain regions, and a channel region formed therebetween; a buffer layer formed on the top of the channel region of the substrate; a ferroelectric layer formed on the buffer layer; and a gate electrode formed on the ferroelectric layer, wherein the buffer layer is formed of a conductive material. | 10-07-2010 |
| 20110042726 | High-voltage transistor device with integrated resistor - A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 02-24-2011 |
| 20110068377 | HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR WITH SPIRAL FIELD PLATE - In one embodiment, a junction field effect transistor having a substrate, wherein formed on the substrate is a graded n-doped region having a high doping concentration in an inner region and a low doping concentration in an outer region, with a p-doped buried region adjacent to the graded n-doped region near the outer region, and a spiral resistor connected to the graded n-doped region at its inner region and at its outer region. An ohmic contact at the inner region provides the drain, an ohmic contact at the outer region provides the source, and an ohmic contact at the substrate provides the gate. | 03-24-2011 |
| 20110101424 | JUNCTION FIELD EFFECT TRANSISTOR - A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, and in which a dopant profile at a side of the drain facing the channel is modified so as to provide a region of reduced doping compared to a body region of the drain. The region of reduced doping and the body region can be defined by the same mask and doping step, but the mask is shaped to provide a lesser amount and thus less depth of doping for the region of reduced doping. | 05-05-2011 |
| 20110147808 | ASYMMETRIC JUNCTION FIELD EFFECT TRANSISTOR - A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch. | 06-23-2011 |
| 20110193142 | Structure and Method for Post Oxidation Silicon Trench Bottom Shaping - A method of fabricating an LFCC device includes forming a first trench in a substrate that extends vertically from an upper surface to a depth within the substrate, the first trench having first sidewalls, a first bottom, and a pattern formed on the first sidewalls near the first bottom of the trench, and forming an oxide layer on the first sidewalls and first bottom of the first trench that leaves a second trench located within the first trench and is separated from the first trench by the oxide layer. The second trench has second sidewalls that are substantially vertical without showing the pattern and a second bottom that is substantially flat. The pattern compensates for the difference in oxidation rates between the bottom of the first trench and the first sidewalls. The LFCC structure includes a first trench with the pattern. | 08-11-2011 |
| 20110220973 | JUNCTION-FIELD-EFFECT-TRANSISTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A junction-field-effect-transistor (JFET) device includes a substrate of a first-type impurity, a first well region of a second-type impurity in the substrate, a pair of second well regions of the first-type impurity separated from each other in the first well region, a third well region of the first-type impurity between the pair of second well regions, a first diffused region of the second-type impurity between the third well region and one of the second well regions, and a second diffused region of the second-type impurity between the third well region and the other one of the second well regions. | 09-15-2011 |
| 20110227135 | SCHOTTKY DIODES - Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact, the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device. | 09-22-2011 |
| 20110254059 | STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES - A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures. | 10-20-2011 |
| 20110316055 | SUBSTRATE PROVIDED WITH A SEMI-CONDUCTING AREA ASSOCIATED WITH TWO COUNTER-ELECTRODES AND DEVICE COMPRISING ONE SUCH SUBSTRATE - A support substrate comprises first and second counter-electrodes arranged in the same plane at the level of a surface of the support substrate. An electrically insulating area separates the first and second counter-electrodes. A semi-conducting area with first and second portions is separated from the support substrate by an electrically insulating material. The electrically insulating material is different from the material forming the support substrate. The first portion of the semi-conducting area is facing the first counter-electrode. The second portion of the semi-conducting area is facing the second counter-electrode. | 12-29-2011 |
| 20120146105 | High-voltage transistor device with integrated resistor - A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 06-14-2012 |
| 20120205725 | Method of Fabricating a Semiconductor Device with a Strain Inducing Material - Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating. | 08-16-2012 |
| 20120286334 | Semiconductor Device and Method of Making Same - Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the plurality of terminals is connectable to a predetermined voltage by activating the gate line. | 11-15-2012 |
| 20120319177 | JUNCTION FIELD EFFECT TRANSISTOR, INTEGRATED CIRCUIT FOR SWITCHING POWER SUPPLY, AND SWITCHING POWER SUPPLY - A switching power supply has a start-up circuit that includes a field effect transistor (JFET), which has a gate region (a p-type well region) formed in a surface layer of a p-type substrate and a drift region (a first n-type well region). A plurality of source regions (second n-type well regions) are formed circumferentially around the drift region. A drain region (a third n-type well region) is formed centrally of the source region. The drain region and the source regions can be formed at the same time. A metal wiring of the source electrode wiring connected to source regions is divided into at least two groups to form at least two junction field effect transistors. | 12-20-2012 |
| 20130015508 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEAANM Jang; Wen-YuehAACI Hsinchu CityAACO TWAAGP Jang; Wen-Yueh Hsinchu City TW - A semiconductor device and a method for fabricating the same are described. The semiconductor device includes a well of a first conductive type, first doped regions of a second conductive type, gates of the second conductive type, second doped regions of the first conductive type, and isolation structures. The well is disposed in a substrate. The first doped regions are disposed in the well. The first doped regions are arranged in parallel and extend along a first direction. The gates are disposed on the substrate. The gates are arranged in parallel and extend along a second direction different from the first direction. One of the first doped regions is electrically connected to one of the gates. Each of the second doped regions is disposed in the first doped regions between two adjacent gates. Each of the isolation structures is disposed in the substrate between two adjacent first doped regions. | 01-17-2013 |
| 20130020615 | Borderless Contacts in Semiconductor Devices - A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity. | 01-24-2013 |
| 20130032862 | High Voltage Resistor with High Voltage Junction Termination - Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a substrate that includes a doped well disposed therein. The doped well and the substrate have opposite doping polarities. The high voltage semiconductor device includes an insulating device disposed over the doped well. The high voltage semiconductor device includes an elongate resistor disposed over the insulating device. A non-distal portion of the resistor is coupled to the doped well. The high voltage semiconductor device includes a high-voltage junction termination (HVJT) device disposed adjacent to the resistor. | 02-07-2013 |
| 20130032863 | INTEGRATED GATE CONTROLLED HIGH VOLTAGE DIVIDER - An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider. | 02-07-2013 |
| 20130056801 | JUNCTION FIELD EFFECT TRANSISTOR AND ANALOG CIRCUIT - A junction field effect transistor comprising: a semiconductor substrate having a first conductivity type; a channel region having a second conductivity type different from the first conductivity type, and being formed in a surface of the semiconductor substrate; a first buried region having the second conductivity type, being formed within the channel region, and having an impurity concentration higher than the channel region; a first gate region having the first conductivity type, and being formed in a surface of the channel region; and first drain/source region and a second drain/source region both having the second conductivity type, which are formed each on an opposite side of the first gate region in the surface of the channel region, in which the first buried region is not formed below the second drain/source region, but is formed below the first drain/source region. | 03-07-2013 |
| 20130105866 | SEMICONDUCTOR DEVICE | 05-02-2013 |
| 20130193491 | Field Controlled Diode with Positively Biased Gate - An integrated circuit containing a field controlled diode which includes a p-type channel region between an upper gate and a lower n-type depletion gate, a p-type anode in a p-type anode well abutting the channel region, and an n-type cathode in a p-type anode well abutting the channel region opposite from the anode well. An n-type lower gate link connects the lower gate to the surface of the substrate. A surface control element is located at the surface of the channel region between the cathode and the upper gate. A process of forming the integrated circuit containing the field controlled diode is described. | 08-01-2013 |
| 20130248947 | METHODS AND APPARATUS RELATED TO A DIODE DEVICE INCLUDING A JFET PORTION - In one general aspect, an apparatus can include an anode terminal, and a cathode terminal. The apparatus can include a junction field-effect transistor (JFET) portion having a channel disposed within a semiconductor substrate and defining a first portion of an electrical path between the anode terminal and the cathode terminal. The apparatus can also include a diode portion formed within the semiconductor substrate and defining a second portion of the electrical path between the anode terminal and the cathode terminal. The diode portion can be serially coupled to the channel of the JFET device. | 09-26-2013 |
| 20140061731 | Tunable Schottky Diode - A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region. | 03-06-2014 |
| 20140197467 | HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE - A JFET structure includes a first JFET having a first terminal and a second JFET neighboring with the first JFET. Both JFETs commonly share the first terminal and the first terminal is between the gate of each JFET. The JFET also provides at least one tuning knob to adjust the pinch-off voltage and a tuning knob to adjust the breakdown voltage of the JFET structure. Moreover, the JFET has a buried layer as another tuning knob to adjust the pinch-off voltage of the JFET structure. | 07-17-2014 |
| 20150380398 | FORMING JFET AND LDMOS TRANSISTOR IN MONOLITHIC POWER INTEGRATED CIRCUIT USING DEEP DIFFUSION REGIONS - A power integrated circuit includes a junction field effect transistor (JFET) device formed in a first portion of a semiconductor layer with a gate region being formed using a first body region, and a double-diffused metal-oxide-semiconductor (LDMOS) transistor formed in a second portion of the semiconductor layer with a channel being formed in a second body region. The power integrated circuit includes a first deep diffusion region formed under the first body region and in electrical contact with the first body region where the first deep diffusion region together with the firs body region establish a pinch off voltage of the JFET device; and a second deep diffusion region formed under the second body region and in electrical contact with the second body region where the second deep diffusion region forms a reduced surface field (RESURF) structure in the LDMOS transistor. | 12-31-2015 |
| 20160043236 | HIGH VOLTAGE DEPLETION MODE N-CHANNEL JFET - An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer. | 02-11-2016 |
| 20160064376 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a substrate; a nitride semiconductor layer formed on the substrate; a transistor formed on the nitride semiconductor layer, and including a source electrode, a gate electrode, and a drain electrode disposed in this order; and a diode formed on the nitride semiconductor layer, and including an anode electrode and a cathode electrode disposed in this order. The semiconductor apparatus has a transistor/diode pair in which the source electrode, the gate electrode, the drain electrode, the anode electrode, and the cathode electrode are sequentially disposed in this order, and the drain electrode of the transistor and the anode electrode of the diode are connected by a drain/anode common electrode wiring and serve as a common electrode. | 03-03-2016 |
| 20160071837 | POWER SEMICONDUCTOR DEVICES - A power semiconductor device includes a diode part disposed in a first region of a substrate, a junction field effect transistor (JFET) part disposed in a second region adjacent to the first region of the substrate, an anode terminal disposed on the first region of the substrate, and a cathode terminal disposed on the second region of the substrate. The diode part includes a p-type body region disposed inside the substrate and electrically connected with the anode terminal, an n-type well disposed on one side of the p-type body region and having a first impurity concentration, and a first n-type semiconductor region disposed below the p-type body region and having a second impurity concentration which is lower than the first impurity concentration. | 03-10-2016 |
| 20160133704 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first conductive type first main electrode region, a first conductive type drift region which makes contact with the first main electrode region, a first conductive type second main electrode region which makes contact with the drift region, a second conductive type well region which is provided in a part of a surface layer portion of the drift region and to which a reference potential is applied, and a first conductive type potential extracting region which is provided in a surface layer portion of the well region and to which the reference potential is applied. The well region serves as a base region which controls a current flowing between the potential extracting region and the drift region. Thus, it is possible to provide a novel semiconductor device which is high in reliability while the increase of the chip size can be suppressed. | 05-12-2016 |
| 20160254258 | FIELD EFFECT TRANSISTOR WITH INTEGRATED ZENER DIODE | 09-01-2016 |
| 257273000 | With bipolar device | 7 |
| 20080237657 | Signaling circuit and method for integrated circuit devices and systems - An integrated circuit device can include at least one bipolar junction transistor (BJT) having a first base electrode comprising a semiconductor material doped to a first conductivity type formed on and in contact with a surface of the semiconductor substrate, and separated from an emitter electrode by a separation space. A first base region can be formed in the substrate below the emitter electrode and include a first portion of the substrate doped to the first conductivity type. A second base region can be formed in the substrate below the separation space and can include a second portion of the substrate doped to the first conductivity type. | 10-02-2008 |
| 20080308849 | SEMICONDUCTOR APPARATUS AND COMPLIMENTARY MIS LOGIC CIRCUIT - A configuration is adopted comprising an NchMOS transistor | 12-18-2008 |
| 20090057728 | DYNAMIC RANDOM ACCESS MEMORY HAVING JUNCTION FIELD EFFECT TRANSISTOR CELL ACCESS DEVICE - A dynamic random access memory (DRAM) device can include a plurality of memory cells. Each memory cell can include a charge storing structure and an access device comprising an enhancement mode junction field effect transistor (JFET). The DRAM device can further include a plurality of sense amplifiers that each generates an output value in response to a signal received at respective sense amplifier inputs, and a plurality of bit lines, each bit line coupling a plurality of memory cells to at least one input of at least one of the sense amplifiers. A method can fabricate such DRAM devices. | 03-05-2009 |
| 20100019291 | JFET Devices with PIN Gate Stacks and Methods of Making the Same - Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET. | 01-28-2010 |
| 20130087836 | SEMICONDUCTOR DEVICE - A channel region having a first conductivity type is disposed in a surface portion of a semiconductor substrate. A gate region having a second conductivity type is disposed in a surface portion of the channel region. A first semiconductor region having the second conductivity type is disposed under the channel region. Source/drain regions having the first conductivity type are disposed in parts of the surface portion of the channel region on both sides of the gate region in a channel length direction. Second semiconductor regions each having a high impurity concentration and the second conductivity type are disposed in parts of the semiconductor substrate on both sides of the channel region in a channel width direction. | 04-11-2013 |
| 20140138749 | INTEGRATED CIRCUIT (IC) STRUCTURE - One or more techniques or systems for forming an integrated circuit (IC) or associated IC structure are provided herein. In some embodiments, the IC includes a junction gate field effect transistor (JFET) and a lateral vertical bipolar junction transistor (LVBJT). For example, the JFET and the LVBJT are formed in a same region, such as a substrate. In some embodiments, the JFET and the LVBJT are at least one of adjacent or share one or more features. In this manner, a reliable IC is provided, thus enabling power amplification, for example. | 05-22-2014 |
| 20140361350 | THIN-FILM HYBRID COMPLEMENTARY CIRCUITS - Complementary circuits based on junction (or heterojunction) field effect transistor devices and bipolar junction (or heterojunction) transistor devices comprised of thin crystalline semiconductor-on-insulator substrates are provided which are compatible with low-cost and/or flexible substrates. Only one substrate doping type (i.e., n-type or p-type) is required for providing the complementary circuits and thus the number of masks (typically three or four) remains the same as that required for either n-channel or p-channel devices in the TFT level. | 12-11-2014 |
| 257274000 | Complementary junction field effect transistors | 2 |
| 20080217663 | Enhanced Transistor Performance by Non-Conformal Stressed Layers - NFET and PFET devices with separately strained channel regions, and methods of their fabrication is disclosed. A stressing layer overlays the device in a manner that the stressing layer is non-conformal with respect the gate. The non-conformality of the stressing layer increases the amount of stress that is imparted onto the channel of the device, in comparison to stressing layers which are conformal. The method for overlaying in a non-conformal manner includes non-conformal deposition techniques, as well as, conformal depositions where subsequently the layer is turned into a non-conformal one by etching. | 09-11-2008 |
| 20090200582 | SEMICONDUCTOR DEVICE WITH AN IMPROVED OPERATING PROPERTY - The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region are made different from each other. With this, it enables to increase the drive current of both the n-channel transistor and p-channel transistor without changing the dimensions of the active region and the element isolation region. | 08-13-2009 |
| 257275000 | Microwave integrated circuit (e.g., microstrip type) | 8 |
| 20090250730 | MICROWAVE SEMICONDUCTOR DEVICE USING COMPOUND SEMICONDUCTOR AND METHOD FOR MANUFACTURING THE SAME - An undoped AlGaN layer | 10-08-2009 |
| 20120074470 | MICROWAVE SEMICONDUCTOR DEVICE USING COMPOUND SEMICONDUCTOR AND METHOD FOR MANUFACTURING THE SAME - An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode | 03-29-2012 |
| 20140339609 | TRANSISTOR PERFORMANCE USING A TWO-STEP DAMAGE ANNEAL - A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation. | 11-20-2014 |
| 257276000 | With contact or heat sink extending through hole in semiconductor substrate, or with electrode suspended over substrate (e.g., air bridge) | 3 |
| 20080210989 | SEMICONDUCTOR DEVICE - A semiconductor device includes a p-type semiconductor layer made of a compound semiconductor provided on a substrate, a compound semiconductor layer provided on the p-type semiconductor layer, active regions that are provided on the compound semiconductor layer and are adjacent to each other across an isolation region, a connecting portion that is connected to the p-type semiconductor layer in the isolation region located between the active regions or a region adjacent to another region between the active regions, and FETs respectively provided in the active regions adjacent to each other, a source electrode of at least one of the FETs being connected to a potential of the connecting portion in a region other than the active regions. | 09-04-2008 |
| 20080277697 | SEMICONDUCTOR DEVICE FOR HIGH FREQUENCY - A semiconductor device for high frequency includes a channel region fabricated on a compound semiconductor substrate, a gate electrode fabricated on the channel region, a source electrode and a drain electrode alternately fabricated on the channel region by sandwiching the gate electrode, a bonding pad to be connected to an external circuit, and an air-bridge having one end connected to the source electrode or the drain electrode above and outside the channel region, and the other end connected to the bonding pad. | 11-13-2008 |
| 20080277698 | FIELD EFFECT TRANSISTOR - A field effect transistor includes a channel region fabricated on a compound semiconductor substrate,
| 11-13-2008 |
| 257277000 | With capacitive or inductive elements | 2 |
| 20080230813 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR | 09-25-2008 |
| 20110049581 | SEMICONDUCTOR STRUCTURE AND METHOD - A method for forming a structure on a surface of a semiconductor. The method includes: forming the material as a lower layer of the structure using a first deposition process to provide the lower layer with a first etch rate to a predetermined etchant; forming the upper layer of the structure with the material on the lower using a second deposition process to provide the upper layer with a second etch rate to the predetermined etchant higher than the first etch rate; and applying the predetermined etchant to upper layer to selectively remove the upper while leaving the lower layer. | 03-03-2011 |
| 257278000 | With devices vertically spaced in different layers of semiconductor material (e.g., "3-dimensional" integrated circuit) | 2 |
| 20080203445 | Three-Dimensional Cascaded Power Distribution in a Semiconductor Device - An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers. | 08-28-2008 |
| 20100148226 | JFET DEVICE STRUCTURES AND METHODS FOR FABRICATING THE SAME - In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source. | 06-17-2010 |
