| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257206000 | Particular layout of complementary FETs with regard to each other | 37 |
| 20080210981 | Integrated Circuit Having Gates and Active Regions Forming a Regular Grating - A semiconductor device includes a plurality of repeatable circuit cells connectable to one or more conductors providing at least electrical connection to the circuit cells and/or electrical connection between one or more circuit elements in the cells. Each of the circuit cells are configured having gates and active regions forming a grating, wherein, for a given active layer in the device, a width of each active region is substantially the same relative to one another, a spacing between any two adjacent active regions is substantially the same, a width of each gate is substantially the same relative to one another, and a spacing between any two adjacent gates is substantially the same. | 09-04-2008 |
| 20090166681 | MOS Transistor and Semiconductor Device - According to one embodiment of the present invention, a MOS transistor includes a semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region. A gate structure is arranged above the channel regions. A source wiring structure is arranged above the source region and is connected to the source region. A drain wiring structure is arranged above the drain region and is connected to the drain region. The width of the source wiring structure is larger than the width of the drain wiring structure, and the height of the source wiring structure is smaller than the height of the drain wiring structure, or vice versa. | 07-02-2009 |
| 20090302354 | High Density Stable Static Random Access Memory - A memory circuit includes a plurality of bit line structures, a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells is selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures, and each of the cells in turn includes a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor. The at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of the bit line structures, and the at least first p-type field effect transistor is formed with a relatively thin buried oxide layer | 12-10-2009 |
| 20100006897 | Semiconductor Device Layout Having Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors - A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to pattern conductive features within a gate electrode level above the portion of the substrate. The gate electrode level layout includes rectangular-shaped layout features placed to extend in only a first parallel direction. Some of the rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some of the rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the restricted layout region of the semiconductor device. | 01-14-2010 |
| 20100006898 | Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors - A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to include rectangular-shaped layout features placed to extend in only a first parallel direction. Some of the rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some of the rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A total number of the PMOS transistor devices and the NMOS transistor devices in the restricted layout region of the semiconductor device is greater than or equal to eight. Additionally, the restricted layout region corresponds to an entire gate electrode level of a cell layout. | 01-14-2010 |
| 20100006899 | Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors - A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features within the gate electrode level region extend over the p-type diffusion regions to form respective PMOS transistor devices. Also, some of the conductive features within the gate electrode level region extend over the n-type diffusion regions to form respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region. | 01-14-2010 |
| 20100006900 | Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors - A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Each of the conductive features within the gate electrode level region has a width less than a wavelength of light used in a photolithography process to fabricate the conductive features. Conductive features within the gate electrode level region form respective PMOS transistor devices and respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region. | 01-14-2010 |
| 20100025731 | Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors - A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. The cell also includes a number of interconnect levels formed above the gate electrode level. | 02-04-2010 |
| 20100025732 | Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors - A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. A width of the conductive features in the gate electrode level is less than a wavelength of light used in a photolithography process for their fabrication. | 02-04-2010 |
| 20100025733 | Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors - A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level region. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. A width of the conductive features within a five wavelength photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication. | 02-04-2010 |
| 20100032721 | Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors - A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent are fabricated from respective originating layout features separated from each other by an end-to-end spacing of substantially equal and minimum size across the gate electrode level region. A width of the conductive features within a 5 wavelength photolithographic interaction radius is less than a 193 nanometer wavelength of light used in a photolithography process for their fabrication. Some conductive features extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region. | 02-11-2010 |
| 20100032722 | Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors - A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features within the gate electrode level region extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the gate electrode level region is greater than or equal to eight. | 02-11-2010 |
| 20100032723 | Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors - A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a substantially equal and minimum size across the gate electrode level region. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. Some of the conductive features extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the gate electrode level region is greater than or equal to eight. | 02-11-2010 |
| 20100032724 | Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors - A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. A width size of the conductive features within a five wavelength photolithographic interaction radius within the gate electrode level is less than a wavelength of light of 193 nanometers. Some of the conductive features form respective PMOS and/or NMOS transistor devices. The cell includes an equal number of PMOS and NMOS transistor devices. The cell also includes a number of interconnect levels formed above the gate electrode level. | 02-11-2010 |
| 20100044755 | SEMICONDUCTOR DEVICE - A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch. | 02-25-2010 |
| 20100059794 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. | 03-11-2010 |
| 20100084689 | SEMICONDUCTOR DEVICE - A semiconductor device in accordance with an exemplary aspect of the present invention includes: an even number of transistor pairs; connection nodes connecting the n-type transistors and the p-type transistors of the transistor pairs; and inter-gate wiring lines connected to the connection nodes, each inter-gate wiring line connecting a gate of the p-type transistor of one of the transistor pairs disposed in the subsequent stage of one of the transistor pairs for which each connection node is provided, wherein the n-type transistor of a first transistor pair is disposed in a p-well region different from both a p-well region in which the n-type transistor of a second transistor pair disposed in two stages preceding of the first transistor pair is disposed and a p-well region in which the n-type transistor of a third transistor pair disposed in two stages subsequent of the first transistor pair is disposed. | 04-08-2010 |
| 20100096671 | Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors - A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level. | 04-22-2010 |
| 20100117120 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first well region | 05-13-2010 |
| 20100133589 | ANALOG CIRCUIT CELL ARRAY AND ANALOG INTEGRATED CIRCUIT - An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein the first gate electrode and the second gate electrode are connected together for use, and the first source region and the second source region are connected together for use. | 06-03-2010 |
| 20100155783 | Standard Cell Architecture and Methods with Variable Design Rules - Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed. | 06-24-2010 |
| 20110049575 | Semiconductor integrated circuit - Disclosed herein is a semiconductor integrated circuit, wherein a desired circuit is formed by combining and laying out a plurality of standard cells and connecting the cells together, of which the cell length, i.e., the gap between a pair of opposed sides, is standardized, the plurality of standard cells forming the desired circuit include complementary in-phase driven standard cells, each of which includes a plurality of complementary transistor pairs that are complementary in conductivity type to each other and have their gate electrodes connected together, and N (≧2) pairs of all the complementary transistor pairs are driven in phase, and the size of the standardized cell length of the complementary in-phase driven standard cell is defined as an M-fold cell length which is M (N≧M≧2) times the basic cell length which is appropriate to the single complementary transistor pair. | 03-03-2011 |
| 20110073916 | GATE ARRAY - A gate array of a semiconductor substrate on which plural unit cells are arranged in parallel, the unit cells having the same pattern that includes a source potential region VDD, a PMOS, an NMOS and a ground potential region GND. Metal wiring lines being formed, with an insulating layer between, on the unit cells, with contacts that make electrical connection between the metal wiring lines and the unit cell transistors. The gate wiring of a transistor in a non-used unit cell is used in place of a metal wiring line. By doing so, the area of metal wiring lines in a gate array is reduced and the array wiring efficiency is increased. | 03-31-2011 |
| 20110316053 | MOS transistor structure with easy access to all nodes - A transistor device structured such that the bulk, gate, drain, and source are all accessible from all four edges of the device and such that current distribution is uniform over the device is provided. The transistor is created with a four-metal CMOS process. A bulk connection can be made with Metal | 12-29-2011 |
| 20120001231 | Electrical Fuse - An electrical fuse comprises first, second, and third thick oxide NMOS transistors and a thin oxide NMOS transistor. The first thick oxide NMOS transistor has a gate connected to a first input signal, and the thin oxide NMOS transistor has a drain connected to the source of the first thick oxide NMOS transistor and a gate shorted to its source. The second thick oxide transistor has a gate connected to a power up signal, a drain connected to the source of the thin oxide NMOS transistor, and a source connected to a reference voltage. The third thick oxide transistor has a gate connected to the second input signal, a drain connected to a high voltage, and a source connected to the drain of the thin oxide NMOS transistor. The first input signal and the second input signal are complementary. | 01-05-2012 |
| 20120012896 | Integrated Circuit Cell Architecture Configurable for Memory or Logic Elements - An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other. | 01-19-2012 |
| 20120205721 | Design Structure for High Density Stable Static Random Access Memory - A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit includes a plurality of bit line structures, a plurality of word line structures intersecting said plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding bit line structure under control of a corresponding word line structure, each of said cells comprising a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor, wherein said at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of said bit line structures, and said at least first p-type field effect transistor is formed with a relatively thin buried oxide layer. | 08-16-2012 |
| 20130313615 | INTEGRATED CIRCUIT LAYOUT HAVING MIXED TRACK STANDARD CELL - An integrated circuit layout having a mixed track standard cell configuration that having a mixed track standard cell configuration that includes first well regions of a predetermined height and second well regions of a predetermined height, the first and second well regions are arranged within a substrate, first conductors and second conductors arranged and extending across regions of corresponding first and second well regions, and a plurality of standard cells in multiple rows. The standard cells include a first substantially equal to standard cell having a first cell height substantially equal to I(X+Y)+X or Y, wherein X is one half the predetermined height of the first well region, Y is one half the predetermined height of the second well region, and I is a positive integer. | 11-28-2013 |
| 20140291730 | Semiconductor Chip Including Digital Logic Circuit Including Linear-Shaped Conductive Structures Having Electrical Connection Areas Located Within Inner Region Between Transistors of Different Type and Associated Methods - A first linear-shaped conductive structure (LCS) forms a gate electrode (GE) of a first transistor of a first transistor type. A second LCS forms a GE of a first transistor of a second transistor type. A third LCS forms a GE of a fourth transistor of the first transistor type. A fourth LCS forms a GE of a fourth transistor of the second transistor type. Transistors of the first transistor type are collectively separated from transistors of the second transistor type by an inner region. Each of the first, second, third, and fourth LCS's has a respective electrical connection area. At least two of the electrical connection areas of the first, second, third, and fourth LCS's are located within the inner region. The first and fourth transistors of the first transistor type and the first and fourth transistors of the second transistor type form part of a cross-coupled transistor configuration. | 10-02-2014 |
| 20140291731 | Semiconductor Chip Including Region Including Linear-Shaped Conductive Structures Forming Gate Electrodes and Having Electrical Connection Areas Arranged Relative to Inner Region Between Transistors of Different Types and Associated Methods - A first linear-shaped conductive structure (LCS) forms gate electrodes (GE's) of a first transistor of a first transistor type and a first transistor of a second transistor type. A second LCS forms a GE of a second transistor of the first transistor type. A third LCS forms a GE of a second transistor of the second transistor type. A fourth LCS forms a GE of a third transistor of the first transistor type. A fifth LCS forms a GE of a third transistor of the second transistor type. A sixth LCS forms a GE of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. Transistors of the first transistor type are collectively separated from transistors of the second transistor type by an inner region. The second, third, fourth, and fifth LCS's have respective electrical connection areas arranged relative to the inner region. | 10-02-2014 |
| 20150014748 | SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAMMABLE LOGIC DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode. | 01-15-2015 |
| 20150069470 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device includes a plurality of basic cells that each have a first transistor pair including two p-channel transistors of a first-type and a second transistor pair including two p-channel transistors of a second-type. The second-type transistors are configured to consume less power and operate more slowly than the first-type transistors. The basic cell further includes a third transistor pair of two n-channel transistors of a third-type. The third transistor pair is disposed between the first and second transistor pairs. Gate electrodes are separately provided for each transistor in the first, second, and third transistor pairs. The basic cell thus formed can be used to fabricate various circuit elements by making wiring connections between various transistor pairs and/or basic cells. | 03-12-2015 |
| 20150076564 | MULTI-THRESHOLD CIRCUITRY BASED ON SILICON-ON-INSULATOR TECHNOLOGY - Multiple threshold voltage circuitry based on silicon-on-insulator (SOI) technology is disclosed which utilizes N-wells and/or P-wells underneath the insulator in SOI FETs. The well under a FET is biased to influence the threshold voltage of the FET. A PFET and an NFET share a common buried P-well or N-well. Various types of logic can be fabricated in silicon-on-insulator (SOI) technology using multiple threshold voltage FETs. Embodiments provide circuits including the advantageous properties of both low-leakage transistors and high-speed transistors. | 03-19-2015 |
| 20150084097 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a substrate on which a plurality of logic cells are provided, and a plurality of active portions provided on the substrate and extending in a first direction. Contacts and gate structures extend in a second direction intersecting the first direction and are alternately arranged. A common conductive line extends along a boundary region of the plurality of logic cells in the first direction. At least one of the contacts is electrically connected to the common conductive line through a via therebetween, and each of the contacts intersects a plurality of the active portions. End portions of the contacts are aligned with each other along the first direction. | 03-26-2015 |
| 20160079381 | Semiconductor Chip Including Integrated Circuit Including At Least Five Gate Level Conductive Structures Having Particular Spatial and Electrical Relationship and Method for Manufacturing the Same - A semiconductor chip region includes a first conductive structure (CS) that forms a gate electrode (GE) of a first transistor of a first transistor type (TT) and a GE of a first transistor of a second TT, a second CS that forms a GE of a second transistor of the first TT, a third CS that forms a GE of a second transistor of the second TT, a fourth CS that forms a GE of a third transistor of the first TT, and a fifth CS that forms a GE of a third transistor of the second TT. Diffusion terminals of the first and second transistors of the first TT are electrically connected. Diffusion terminals of the first and second transistors of the second TT are electrically connected. Diffusion terminals of the second and third transistors of both the first TT and second TT are electrically connected. | 03-17-2016 |
| 20160379991 | Semiconductor Chip and Method for Manufacturing the Same - A first transistor has a gate electrode formed by a substantially linear portion of a first conductive structure. A second transistor has a gate electrode formed by a substantially linear portion of a second conductive structure. A third transistor has a gate electrode formed by a substantially linear portion of a third conductive structure. A fourth transistor has a gate electrode formed by a substantially linear portion of a fourth conductive structure. The substantially linear portions of the first, second, third, and fourth conductive structures extend in a first direction and are positioned in accordance with a gate pitch. Gate electrodes of the first and second transistors have a first size as measured in the first direction. Gate electrodes of the third and fourth transistors have a second size as measured in the first direction. The first size is at least two times the second size. | 12-29-2016 |
| 20190148407 | SEMICONDUCTOR DEVICE INCLUDING STANDARD CELLS | 05-16-2019 |
