| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257119000 | Bidirectional rectifier with control electrode (gate) (e.g., Triac) | 74 |
| 20080277687 | High power density switch module with improved thermal management and packaging - A semiconductor power device, e.g., an Insulated Gate Bi-polar Transistor (IGBT) or a Metal-Oxide Field Effect Transistor (MOSFET) may be constructed in a reusable and repairable cost-effective sealed shell. The switch may be provided with direct-pressure-contact caps which may perform as electrical conductors for a semiconductor die of the switch and also as thermal heat-sink contacts for the device. The switch may be provided with internal self-powered gate driving control and PHM incorporated in sealed shell. Embodiments of the switch may be constructed with no external gating/PHM connection pin penetrations through the shell. | 11-13-2008 |
| 20090179222 | SILICON CONTROLLED RECTIFIER - A silicon controlled rectifier structure of polygonal layouts is provided. The polygonal first conductive type doped region is located in the middle of the polygonal second conductive type well. The first conductive type well shaped as a polygonal ring surrounds the second conductive type well and the second conductive type doped region is located within the first conductive type well and shaped as a polygonal ring concentric to the first conductive type well. | 07-16-2009 |
| 20090267110 | INTEGRATED LOW LEAKAGE SCHOTTKY DIODE - An integrated low leakage Schottky diode has a Schottky barrier junction proximate one side of an MOS gate with one end of a drift region on an opposite side of the gate. Below the Schottky metal and the gate oxide is a RESURF structure of an N− layer over a P− layer which also forms the drift region that ends at the diode's cathode in one embodiment of the present invention. The N− and P− layers have an upward concave shape under the gate. The gate electrode and the Schottky metal are connected to the diode's anode. A P− layer lies between the RESURF structure and an NISO region which has an electrical connection to the anode. A P+ layer under the Schottky metal is in contact with the P− layer through a P well. | 10-29-2009 |
| 20110210372 | HIGH-VOLTAGE VERTICAL POWER COMPONENT - A high-voltage vertical power component including a lightly-doped semiconductor substrate of a first conductivity type and, on the side of an upper surface, an upper semiconductor layer of the second conductivity type which does not extend all the way to the component periphery, wherein the component periphery includes, on the lower surface side, a ring-shaped diffused region of the second conductivity type extending across from one third to half of the component thickness; and on the upper surface side, an insulated ring-shaped groove crossing the substrate to penetrate into an upper portion of ring-shaped region. | 09-01-2011 |
| 20110241067 | Gate Controlled Atomic Switch - The invention relates to a method for producing a switch element. The invention is characterized in that the switch element comprises three electrodes that are located in an electrolyte, two of which (source electrode and drain electrode) are interconnected by a bridge consisting of one or more atoms that can be reversibly opened and closed. The opening and closing of said contact between the source and drain electrodes can be controlled by the potential that is applied to the third electrode (gate electrode). The switch element is produced by the repeated application of potential cycles between the gate electrode and the source or drain electrode. The potential is increased and reduced during the potential cycles until the conductance between the source and drain electrode can be switched back and forth between two conductances, as a result of said change in potential in the gate electrode, as a reproducible function of the voltage of the gate electrode. | 10-06-2011 |
| 20110284921 | HF-CONTROLLED BIDIRECTIONAL SWITCH - A bidirectional switch controllable by a voltage between its gate and rear electrode and including an N-type semiconductor substrate surrounded with a P-type well; on the front surface side, a P-type well in which is formed a first N-type region; on the rear surface side, a P-type layer in which is formed a second N-type region. The well is doped to less than 10 | 11-24-2011 |
| 20110284922 | DEVICES WITH ADJUSTABLE DUAL-POLARITY TRIGGER-AND HOLDING-VOTAGE/CURRENT FOR HIGH LEVEL OF ELECTROSTATIC DISCHARGE PROTECTION IN SUB-MICRON MIXED SIGNAL CMOS/BICMOS INTEGRATED - Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P | 11-24-2011 |
| 20120056238 | BIDIRECTIONAL SILICON-CONTROLLED RECTIFIER - A bidirectional silicon-controlled rectifier, wherein the conventional field oxide layer, which separates an anode structure from a cathode structure, is replaced by a field oxide layer having floating gates, a virtual gate or a virtual active region. Thus, the present invention can reduce or escape from the bird's beak effect of a field oxide layer, which results in crystalline defects, a concentrated current and a higher magnetic field and then causes abnormal operation of a rectifier. Thereby, the present invention can also reduce signal loss. | 03-08-2012 |
| 20120146089 | FOUR-QUADRANT TRIAC - A vertical four-quadrant triac wherein the gate region, arranged on the side of a front surface, includes a U-shaped region of a first conductivity type, the base of the U lying against one side of the structure, the main front surface region of the second conductivity type extending in front of the gate region and being surrounded with portions of the main front surface region of the first conductivity type. | 06-14-2012 |
| 20120286321 | High-Performance Device for Protection from Electrostatic Discharge - The semiconductor device for protection from electrostatic discharges comprises several modules (MDi) for protection from electrostatic discharges comprising triggerable elements (TRi) coupled with triggering means, the said modules being connected between two terminals by the intermediary of a resistive network (R). A common semiconductor layer contacts all of the modules, each triggerable element (TRi) having at least one gate (GHi), and the triggering means comprise a single triggering circuit (TC) common to all of the triggerable elements and whose output is connected to the gates of all of the triggerable elements. | 11-15-2012 |
| 20130009204 | BIDIRECTIONAL DUAL-SCR CIRCUIT FOR ESD PROTECTION - An ESD protection circuit includes a pad of an IC, circuitry coupled to the pad for buffering data, an RC power clamp on the IC, and first and second silicon controlled rectifier (SCR) circuits. The RC power clamp is coupled between a positive power supply terminal and a ground terminal. The first SCR circuit is coupled between the pad and the positive power supply terminal. The first SCR circuit has a first trigger input coupled to the RC power clamp circuit. The second SCR circuit is coupled between the pad and the ground terminal. The second SCR circuit has a second trigger input coupled to the RC power clamp circuit. At least one of the SCR circuits includes a gated diode configured to selectively provide a short or relatively conductive electrical path between the pad and one of the positive power supply terminal and the ground terminal. | 01-10-2013 |
| 20130105855 | GATE AMPLIFICATION TRIAC | 05-02-2013 |
| 20130228822 | VERTICAL POWER COMPONENT - A vertical power component including a silicon substrate of a first conductivity type and, on the side of a lower surface supporting a single electrode, a well of the second conductivity type, in which the component periphery includes, on the lower surface side, a peripheral trench at least partially filled with a passivation and, between the well and the trench, a porous silicon insulating ring. | 09-05-2013 |
| 20130320396 | MUTUAL BALLASTING MULTI-FINGER BIDIRECTIONAL ESD DEVICE - An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node. | 12-05-2013 |
| 20140034995 | ACTIVE EDGE STRUCTURES PROVIDING UNIFORM CURRENT FLOW IN INSULATED GATE TURN-OFF THYRISTORS - An insulated gate turn-off thyristor, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The thyristor is formed of a matrix of cells. Due to the discontinuity along the edge cells, a relatively large number of holes are injected into the n− epi layer and drift into the edge p-well, normally creating a higher current along the edge and lowering the breakover voltage of the thyristor. To counter this effect, the dopant concentration of the n+ region(s) near the edge is reduced to reduce the NPN transistor beta and current along the edge, thus increasing the breakover voltage. Alternatively, a deep trench may circumscribe the edge cells to provide isolation from the injected holes. | 02-06-2014 |
| 20140097464 | Electronic Device for Protection against Electrostatic Discharges, with a Concentric Structure - The component incorporates, in topological terms, a scalable number of triac structures in a concentric annular arrangement. The component can be used with an electronic device to protect against electrostatic discharges. For example, the components can be used to protect the input/output pad, the first power supply terminal, and the second power supply terminal of an integrated circuit against electrostatic discharges. | 04-10-2014 |
| 20140131764 | STRUCTURES AND TECHNIQUES FOR USING SEMICONDUCTOR BODY TO CONSTRUCT SCR, DIAC, OR TRIAC - Switch devices, such as Silicon Controlled Rectifier (SCR), DIAC, or TRIAC, on a semiconductor body are disclosed. P/N junctions can be built on a semiconductor body, such as polysilicon or active region body on an insulated substrate, with a first implant in one end and a second implant in the other end. The first and second implant regions are separated with a space. A silicide block layer can cover the space and overlap into both implant regions to construct P/N junctions in the interface. | 05-15-2014 |
| 20140217461 | BIDIRECTIONAL DUAL-SCR CIRTCUIT FOR ESD PROTECTION - An ESD protection circuit includes at least a first and a second silicon controlled rectifier (SCR) circuits. The first SCR circuit is coupled between the pad and the positive power supply terminal. The second SCR circuit is coupled between the pad and the ground terminal. At least one of the SCR circuits is configured to selectively provide a short or relatively conductive electrical path between the pad and one of the positive power supply terminal and the ground terminal. | 08-07-2014 |
| 20140299912 | SILICON-CONTROLLED-RECTIFIER WITH ADJUSTABLE HOLDING VOLTAGE - In a silicon-controlled-rectifier (SCR) with adjustable holding voltage, an epitaxial layer is formed on a heavily doped semiconductor layer. A first N-well having a first P-heavily doped area is formed in the epitaxial layer. A first P-well is formed in the epitaxial layer. Besides, a first N-heavily doped area is formed in the first P-well. At least one deep isolation trench is formed in the epitaxial layer, having a depth greater than the depth of the first N-type well and located between the first P-heavily doped area and the first N-heavily doped area. A distance between the deep isolation trench and the heavily doped semiconductor layer is larger than zero. | 10-09-2014 |
| 20140332842 | PACKAGED OVERVOLTAGE PROTECTION CIRCUIT FOR TRIGGERING THYRISTORS - In a first embodiment, an ultra-fast breakover diode has a turn on time T | 11-13-2014 |
| 20150108537 | HIGH-VOLTAGE VERTICAL POWER COMPONENT - A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well. | 04-23-2015 |
| 20160027774 | BIDIRECTIONAL SWITCH - A bidirectional switch formed in a substrate includes first and second main vertical thyristors in antiparallel connection. A third auxiliary vertical thyristor has a rear surface layer in common with the rear surface layer of the first thyristor. A peripheral region surrounds the thyristors and connects the rear surface layer to a layer of the same conductivity type of the third thyristor located on the other side of the substrate. A metallization connects the rear surfaces of the first and second thyristors. An insulating structure is located between the rear surface layer of the third thyristor and the metallization. The insulating structure extends under the periphery of the first thyristor. The insulating structure includes a region made of an insulating material and a complementary region made of a semiconductor material. | 01-28-2016 |
| 20160027907 | BIDIRECTIONAL SWITCH - A bidirectional switch is formed in a semiconductor substrate of a first conductivity type. The switch includes first and second thyristors connected in antiparallel extending vertically between front and rear surfaces of the substrate. A vertical peripheral wall of the second conductivity type connects the front surface to the rear surface and surrounds the thyristors. On the front surface, in a ring-shaped region of the substrate separating the vertical peripheral wall from the thyristors, a first region of the first conductivity type is provided having a doping level greater than the substrate and having the shape of a ring-shaped band portion partially surrounding the first thyristor and stopping at the level of the adjacent region between the first and second thyristors. | 01-28-2016 |
| 20160118485 | HIGH-VOLTAGE VERTICAL POWER COMPONENT - A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well. | 04-28-2016 |
| 257120000 | Six or more semiconductor layers of alternating conductivity types (e.g., npnpnpn structure) | 5 |
| 20110220960 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention improves the performance of a semiconductor device formed with a triac. A thyristor is formed between a back surface electrode and an electrode by p-type semiconductor regions, an n-type substrate region, p-type semiconductor regions and an n-type semiconductor region. A thyristor is formed therebetween by the p-type semiconductor regions, the n-type substrate region, the p-type semiconductor regions and an n-type semiconductor region. The two thyristors are opposite in the direction of currents flowing between the back surface electrode and the electrode. The p-type semiconductor region of a high impurity concentration is formed so as to be internally included in the p-type semiconductor region of a low impurity concentration. The p-type semiconductor region of a low impurity concentration is interposed between the p-type semiconductor region of a high impurity concentration and the n-type substrate region. | 09-15-2011 |
| 20120199874 | APPARATUS AND METHOD FOR TRANSIENT ELECTRICAL OVERSTRESS PROTECTION - An apparatus and method for high voltage transient electrical overstress protection are disclosed. In one embodiment, the apparatus includes an internal circuit electrically connected between a first node and a second node; and a protection circuit electrically connected between the first node and the second node. The protection circuit is configured to protect the internal circuit from transient electrical overstress events while maintaining a relatively high holding voltage upon activation. The holes—or electrons—enhanced conduction protection circuit includes a bi-directional bipolar device having an emitter/collector, a base, and a collector/emitter; a first bipolar transistor having an emitter electrically coupled to the first node, a base electrically coupled to the emitter/collector of the bipolar device, and a collector electrically coupled to the base of the bipolar transistor; and a second bipolar transistor having an emitter electrically coupled to the second node, a base electrically coupled to the collector/emitter of the bipolar device, and a collector electrically coupled to the base of the bipolar transistor. | 08-09-2012 |
| 20130270605 | APPARATUS AND METHOD FOR TRANSIENT ELECTRICAL OVERSTRESS PROTECTION - An apparatus and method for high voltage transient electrical overstress protection are disclosed. In one embodiment, the apparatus includes an internal circuit electrically connected between a first node and a second node; and a protection circuit electrically connected between the first node and the second node. The protection circuit is configured to protect the internal circuit from transient electrical overstress events while maintaining a relatively high holding voltage upon activation. The holes- or electrons-enhanced conduction protection circuit includes a bi-directional bipolar device having an emitter/collector, a base, and a collector/emitter; a first bipolar transistor having an emitter electrically coupled to the first node, a base electrically coupled to the emitter/collector of the bipolar device, and a collector electrically coupled to the base of the bipolar transistor; and a second bipolar transistor having an emitter electrically coupled to the second node, a base electrically coupled to the collector/emitter of the bipolar device, and a collector electrically coupled to the base of the bipolar transistor. | 10-17-2013 |
| 20140175507 | SEMICONDUCTOR DEVICE - Between a back surface electrode and an electrode, a first thyristor is formed of fifth and seventh semiconductor regions, a substrate region, first and second semiconductor regions and a third semiconductor region, and a second thyristor is formed of the second and first semiconductor regions, the substrate region, the seventh and fifth semiconductor regions and a sixth semiconductor region. Depths from the surface of the semiconductor substrate to bottom surfaces of the third and fourth semiconductor regions are 20 μm or more. The second semiconductor region with a high impurity concentration is enclosed by the first semiconductor region with a low impurity concentration, and a difference between a depth from the surface of the semiconductor substrate to the bottom of the second semiconductor region and a depth from the surface of the semiconductor substrate to the bottom of the first semiconductor region is less than 10 μm. | 06-26-2014 |
| 20160204239 | INSULATED GATE POWER DEVICE USING A MOSFET FOR TURNING OFF | 07-14-2016 |
| 257121000 | With diode or transistor in reverse path | 13 |
| 20110012170 | SEMICONDUCTOR DEVICE USED IN STEP-UP DC-DC CONVERTER, AND STEP-UP DC-DC CONVERTER - A power supply device is disclosed that is able to satisfy the power requirements of a device in service and has high efficiency. | 01-20-2011 |
| 20110127573 | BI-DIRECTIONAL TRANSISTOR WITH BY-PASS PATH AND METHOD THEREFOR - In one embodiment, a transistor is formed to have a first current flow path to selectively conduct current in both directions through the transistor and to have a second current flow path to selectively conduct current in one direction. | 06-02-2011 |
| 20120080717 | BI-DIRECTIONAL BACK-TO-BACK STACKED SCR FOR HIGH-VOLTAGE PIN ESD PROTECTION, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode of a first of the back-to-back stacked SCR is connected to an input. An anode of a second of the back-to-back stacked SCR is connected to ground. Cathodes of the first and second of the back-to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively and deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes. | 04-05-2012 |
| 20130161687 | BI-DIRECTIONAL BACK-TO-BACK STACKED SCR FOR HIGH-VOLTAGE PIN ESD PROTECTION, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode of a first of the back-to-back stacked SCR is connected to an input. An anode of a second of the back-to-back stacked SCR is connected to ground. Cathodes of the first and second of the back-to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively and deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes. | 06-27-2013 |
| 20130248923 | BI-DIRECTIONAL SWITCH USING SERIES CONNECTED N-TYPE MOS DEVICES IN PARALLEL WITH SERIES CONNECTED P-TYPE MOS DEVICES - A bi-directional switch circuit includes a pair of N-type MOS devices connected in series with a common source terminal, and a pair of P-type MOS devices connected in series with a common source terminal. The series connected N-type devices are connected in parallel with the series connected P-type devices in a configuration that includes a first input/output (I/O) point of the switch circuit being connected to a drain of a first one of the N-type devices and a drain of a first one of the P-type devices. The parallel configuration also includes a second I/O point of the switch circuit being connected to a drain of a second one of the N-type devices and a drain of a second one of the P-type devices. | 09-26-2013 |
| 20130328103 | METHOD AND APPARATUS FOR PROTECTION AND HIGH VOLTAGE ISOLATION OF LOW VOLTAGE COMMUNICATION INTERFACE TERMINALS - A high voltage isolation protection device for low voltage communication interface systems in mixed-signal high voltage electronic circuit is disclosed. According to one aspect, the protection device includes a semiconductor structure configured to provide isolation between low voltage terminals and protection from transient events. The protection device includes a thyristor having an anode, a cathode, and a gate, and a thyristor cathode-gate control region that is built into the protection device. The protection device is configured to provide multiple built-in path-up to power-high terminals and path-down to power-low terminals at different voltage levels. The protection device also includes independently built-in discharge paths to the common substrate that is connected to a different power-low voltage reference. The conduction paths may be built into a single structure with dual isolation regions. As a result, the protection device enables superior robustness and compact protection solutions for smart power applications. | 12-12-2013 |
| 20140054641 | INTEGRATING A TRENCH-GATED THYRISTOR WITH A TRENCH-GATED RECTIFIER - An integrated trench-MOS-controlled-thyristor plus trench gated diode combination, in which the trenches are preferably formed at the same time. A backside polarity reversal process permits a backside p+ region in the thyristor areas, and only a backside n+ region in the diode areas (for an n-type device). This is particularly advantageous in motor control circuits and the like, where the antiparallel diode permits the thyristor to be dropped into existing power MOSFET circuit designs. In power conversion circuits, the antiparallel diode can conveniently serve as a freewheeling diode. | 02-27-2014 |
| 20140084331 | HETEROJUNCTION COMPOUND SEMICONDUCTOR PROTECTION CLAMPS AND METHODS OF FORMING THE SAME - A protection clamp is provided between a first terminal and a second terminal, and includes a multi-gate high electron mobility transistor (HEMT), a current limiting circuit, and a forward trigger control circuit. The multi-gate HEMT includes a drain/source, a source/drain, a first depletion-mode (D-mode) gate, a second D-mode gate, and an enhancement-mode (E-mode) gate disposed between the first and second D-mode gates. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward trigger control and the current limiting circuits are coupled between the E-mode gate and the first and second terminals, respectively. The forward trigger control circuit provides an activation voltage to the E-mode gate when a voltage of the first terminal exceeds a voltage of the second terminal by a forward trigger voltage. | 03-27-2014 |
| 20140239343 | BI-DIRECTIONAL SILICON CONTROLLED RECTIFIER STRUCTURE - Bi-directional silicon controlled rectifier device structures and design structures, as well as fabrication methods for bi-directional silicon controlled rectifier device structures. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. An anode of a first silicon controlled rectifier is formed in the first well. A cathode of a second silicon controlled rectifier is formed in the first well. The anode of the first silicon controlled rectifier has the first conductivity type. The cathode of the second silicon controlled rectifier has a second conductivity type opposite to the first conductivity type. | 08-28-2014 |
| 20140264431 | ENHANCEMENT-MODE III-NITRIDE DEVICES - A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact. | 09-18-2014 |
| 20140332843 | JUNCTION-ISOLATED BLOCKING VOLTAGE STRUCTURES WITH INTEGRATED PROTECTION STRUCTURES - Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well. | 11-13-2014 |
| 20140374790 | Structure of a Trench MOS Rectifier and Method of Forming the Same - A structure of trench MOS rectifier and a method of forming the same are disclosed including a plurality of trenches formed in the n− drift epitaxial layer, a plurality of MOS structure formed on the substrate either in discrete islands or in rows. Asides the MOS gates there are source regions formed under the mesas. A top metal served as an anode is then formed on the resulted front surface connecting the MOS gates and the adjacent source regions. | 12-25-2014 |
| 20160111530 | Structure of a Trench MOS Rectifier and Method of Forming the Same - A structure of trench MOS rectifier and a method of forming the same are disclosed including a plurality of trenches formed in the n− drift epitaxial layer, a plurality of MOS structure formed on the substrate either in discrete islands or in rows. Asides the MOS gates there are source regions formed under the mesas. A top metal served as an anode is then formed on the resulted front surface connecting the MOS gates and the adjacent source regions. | 04-21-2016 |
| 257122000 | Lateral | 2 |
| 20120153347 | ESD clamp with auto biasing under high injection conditions - In a dual direction ESD protection circuit formed from multiple base-emitter fingers that include a SiGe base region, and a common sub-collector region, the I-V characteristics are adjusted by including P+ regions to define SCR structures that are operable to sink positive and negative ESD pulses, and adjusting the layout and distances between regions and the number of regions. | 06-21-2012 |
| 20140034996 | ESD CLAMP WITH AUTO BIASING UNDER HIGH INJECTION CONDITIONS - In a dual direction ESD protection circuit formed from multiple base-emitter fingers that include a SiGe base region, and a common sub-collector region, the I-V characteristics are adjusted by including P+ regions to define SCR structures that are operable to sink positive and negative ESD pulses, and adjusting the layout and distances between regions and the number of regions. | 02-06-2014 |
| 257124000 | Combined with field effect transistor structure | 21 |
| 20090159925 | BIDIRECTIONAL ELECTRONIC SWITCH - A main semiconductor region grown on a substrate has formed on its surface a pair of main electrodes spaced from each other, a gate electrode between the main electrodes, and a pair of diode-forming electrodes spaced farther away from the gate electrode than are the main electrodes. Making ohmic contact with the main semiconductor region, the pair of main electrodes serve both as drain or source of a HEMT switch and as cathodes of a pair of Schottky diodes integrated with the HEMT switch. Both gate electrode and diode-forming electrodes are in Schottky contact with the main semiconductor region. | 06-25-2009 |
| 20090267111 | MOSFET with Integrated Field Effect Rectifier - A modified MOSFET structure comprises an integrated field effect rectifier connected between the source and drain of the MOSFET to shunt current during switching of the MOSFET. The integrated FER provides faster switching of the MOSFET due to the absence of injected carriers during switching while also decreasing the level of EMI relative to discrete solutions. The integrated structure of the MOSFET and FER can be fabricated using N-, multi-epitaxial and supertrench technologies, including 0.25 μm technology. Self-aligned processing can be used. | 10-29-2009 |
| 20100001314 | Bidirectional switch having control gate embedded in semiconductor substrate and semiconductor device - A bidirectional switch includes a first switch and a second switch. The switch includes a well region of a first-conductivity-type formed on a semiconductor substrate, and serving as drains of the first switch and the second switch, a gate electrode of the first switch provided in a first trench formed in the well region through a first gate insulating film, a gate electrode of the second switch formed in a second trench formed in the well region so as to be spaced apart from the first trench with a second gate insulating film, a source region of the first switch formed on a side wall of the first trench, and on a surface of the well region via a first channel region of a second-conductivity-type, and a source region of the second switch formed on a side wall of the second trench, and on a surface of the well region via a second channel region of the second-conductivity-type. The well region is formed in a region between the first trench and the second trench. | 01-07-2010 |
| 20100044748 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An ESD protection device includes a p-well with first protrudent portions, an N-well with second protrudent portions, a P-well/N-well boundary, a PMOS transistor disposed in the N-well, an NMOS transistor disposed in the P-well, first P+ diffusion regions in the first protrudent portions, first N+ diffusion regions in the second protrudent portions, second P+ diffusion regions disposed between the PMOS transistor and the second protrudent portions, second N+ diffusion regions disposed between the NMOS transistor and the first protrudent portions, third P+ diffusion regions disposed between the NMOS transistor, the boundary, and two adjacent second P+ diffusion regions, and third N+ diffusion regions disposed between the PMOS transistor, the boundary, and two adjacent second N+ diffusion regions, wherein the first and second protrudent portions are interlacedly arranged at the boundary. | 02-25-2010 |
| 20100044749 | BIDIRECTIONAL SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR DEVICE INCORPORATING THE SAME - A semiconductor device and a method of fabrication thereof includes a bidirectional device having a high breakdown voltage and a decreased ON voltage. An n-type extended drain region is formed in the bottom surface of each trench. A p-type offset region is formed in each split semiconductor region. First and second n-source regions are formed in the surface of the p-type offset region. This reduces the in-plane distance between the first and second n-source regions to thereby increase the density of cells. The breakdown voltage is maintained along the trenches. This increases the resistance to high voltages. Channels are formed in the sidewalls of the trenches by making the voltage across each gate electrode higher than the voltage across each of the first and second n-source electrodes. Thus, a bidirectional LMOSFET through which current flows in both directions is achieved. The LMOSFET has a high breakdown voltage and a decreased ON voltage. | 02-25-2010 |
| 20110049561 | Solid-State Pinch Off Thyristor Circuits - Provided is a semiconductor bistable switching device that includes a thyristor portion including an anode layer, a drift layer, a gate layer and a cathode layer, the gate layer operable to receive a gate trigger current that, when the anode layer is positively biased relative to the cathode layer, causes the thyristor portion to latch into a conducting mode between the anode and the cathode. The device also includes a transistor portion formed on the thyristor portion, the transistor portion including a source, a drain and a transistor gate, the drain coupled to the cathode of the thyristor portion. | 03-03-2011 |
| 20120012891 | VOLTAGE-CONTROLLED BIDIRECTIONAL SWITCH - A voltage-controlled vertical bi-directional monolithic switch, referenced with respect to the rear surface of the switch, formed from a lightly-doped N-type semiconductor substrate, in which the control structure includes, on the front surface side, a first P-type well in which is formed an N-type region, and a second P-type well in which is formed a MOS transistor, the first P-type well and the gate of the MOS transistor being connected to a control terminal, said N-type region being connected to a main terminal of the MOS transistor, and the second main terminal of the MOS transistor being connected to the rear surface voltage of the switch. | 01-19-2012 |
| 20120068220 | REVERSE CONDUCTING-INSULATED GATE BIPOLAR TRANSISTOR - According to one embodiment, in a reverse conducting-insulated gate bipolar transistor, the buffer layer is provided on the backside of the second base layer, has a higher impurity concentration in comparison with the second base layer. The first collector layer is in contact with a portion of the backside of the buffer layer, has a higher impurity concentration in comparison with the second base layer. The second collector layer is in contact with a portion of the backside of the buffer layer, is provided so as to surround the first collector layer, has a higher impurity concentration in comparison with the first base layer. The third collector layer is in contact with a portion of the backside of the buffer layer, is provided so as to surround the second collector layer, has a higher impurity concentration in comparison with the second collector layer. | 03-22-2012 |
| 20120211798 | ADJUSTABLE FIELD EFFECT RECTIFIER - An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference. | 08-23-2012 |
| 20120305984 | SCR/MOS CLAMP FOR ESD PROTECTION OF INTEGRATED CIRCUITS - An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad. | 12-06-2012 |
| 20130049065 | BI-DIRECTIONAL SWITCH WITH Q1 AND Q4 CONTROL - A vertical bidirectional switch of the type having its control referenced to the rear surface, including on its rear surface a first main electrode and on its front surface a second main electrode and a gate electrode, this switch being controllable by a positive voltage between its gate and its first electrode, wherein the gate electrode is arranged on the front surface of a via crossing the chip in which the switch is formed. | 02-28-2013 |
| 20130113017 | ELECTRONIC DEVICE FOR PROTECTING FROM ELECTROSTATIC DISCHARGE - A protection device includes a triac and triggering units. Each triggering unit is formed by a MOS transistor configured to operate at least temporarily in a hybrid operating mode and a field-effect diode. The field-effect diode has a controlled gate that is connected to the gate of the MOS transistor. | 05-09-2013 |
| 20130207157 | REVERSE-CONDUCTING POWER SEMICONDUCTOR DEVICE - An exemplary reverse-conducting power semiconductor device with a wafer having a first main side and a second main side parallel to the first main side. The device includes a plurality of diode cells and a plurality of IGCT cells, each IGCT cell including between the first and second main side: a first anode electrode, a first anode layer of a first conductivity type on the first anode electrode, a buffer layer of a second conductivity type on the first anode layer, a drift layer of the second conductivity type on the buffer layer, a base layer of the first conductivity type on the drift layer, a first cathode layer of a second conductivity type on the base layer, and a cathode electrode on the first cathode layer. A mixed part includes the second anode layers of the diode cells alternating with the first cathode layers of the IGCT cells. | 08-15-2013 |
| 20130264607 | Reverse Conducting Insulated Gate Bipolar Transistor - A semiconductor includes a drift zone of a first conductivity type arranged between a first side and a second side of a semiconductor body. The semiconductor device further includes a first region of the first conductivity type and a second region of a second conductivity type subsequently arranged along a first direction parallel to the second side. The semiconductor device further includes an electrode at the second side adjoining the first and second regions. The semiconductor device further includes a third region of the second conductivity type arranged between the drift zone and the first region. The third region is spaced apart from the second region and from the second side. | 10-10-2013 |
| 20140054642 | ESD PROTECTION DEVICE WITH IMPROVED BIPOLAR GAIN USING CUTOUT IN THE BODY WELL - An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor. | 02-27-2014 |
| 20140138735 | JUNCTION-ISOLATED BLOCKING VOLTAGE DEVICES WITH INTEGRATED PROTECTION STRUCTURES AND METHODS OF FORMING THE SAME - Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well. | 05-22-2014 |
| 20140197448 | Bidirectional Semiconductor Device for Protection against Electrostatic Discharges - An integrated circuit is produced on a bulk semiconductor substrate in a given CMOS technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate thyristors coupled in parallel and head-to-tail. Each thyristor has a pair of electrode regions. The two thyristors respectively have two separate gates and a common semiconductor gate region. The product of the current gains of the two transistors of each thyristor is greater than 1. Each electrode region of at least one of the thyristors has a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the thyristor an intrinsic triggering voltage less than the breakdown voltage of a transistor to be protected, and produced in the CMOS technology. | 07-17-2014 |
| 20150115313 | Semiconductor Device Package - In an embodiment, a semiconductor device package includes a bidirectional switch circuit. The bidirectional switch circuit includes a first semiconductor transistor mounted on a first die pad, a second semiconductor transistor mounted on a second die pad, the second die pad being separate from the first die pad, and a conductive connector extending between a source electrode of the first transistor and a source electrode of the second transistor. | 04-30-2015 |
| 20150371985 | POSITIVE STRIKE SCR, NEGATIVE STRIKE SCR, AND A BIDIRECTIONAL ESD STRUCTURE THAT UTILIZES THE POSITIVE STRIKE SCR AND THE NEGATIVE STRIKE SCR - A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled rectifier has a breakdown voltage with a higher magnitude than the first silicon controlled rectifier in the first direction, and a breakdown voltage with a lower magnitude than the first silicon controlled rectifier in the second direction. A bidirectional electrostatic discharge (ESD) structure utilizes both the first silicon controlled rectifier and the second silicon controlled rectifier to provide bidirectional protection. | 12-24-2015 |
| 20160172471 | REVERSE CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR | 06-16-2016 |
| 257125000 | Controllable emitter shunting | 1 |
| 20160181409 | Bidirectional Power Switching with Bipolar Conduction and with Two Control Terminals Gated by Two Merged Transistors | 06-23-2016 |
| 257126000 | With means to separate a device into sections having different conductive polarity | 4 |
| 257127000 | Guard ring or groove | 4 |
| 20090014753 | POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A power semiconductor device of the present invention has an active region and an electric field reduction region and includes: an emitter region of a first conductivity type; a base region of a second conductivity type in contact with the emitter region; an electrical strength providing region of the first conductivity type in contact with the base region; a collector region of the second conductivity type in contact with the electrical strength providing region; and a collector electrode in contact with the collector region; wherein the collector region is disposed on both a active region and a electric field reduction region each containing a dopant of the second conductivity type, and the collector region disposed on the electric field reduction region includes a region having a lower density of carriers of the second conductivity type than the collector region disposed on the active region. | 01-15-2009 |
| 20090261378 | DEVICES WITH ADJUSTABLE DUAL-POLARITY TRIGGER - AND HOLDING-VOLTAGE/CURRENT FOR HIGH LEVEL OF ELECTROSTATIC DISCHARGE PROTECTION IN SUB-MICRON MIXED SIGNAL CMOS/BICMOS INTEGRATED - Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P | 10-22-2009 |
| 20100032710 | Deep Diffused Thin Photodiodes - This invention comprises photodiodes, optionally organized in the form of an array, including p+ deep diffused regions or p+ and n+ deep diffused regions. More specifically, the invention permits one to fabricate thin 4 inch and 6 inch wafer using the physical support provided by a n+ deep diffused layer and/or p+ deep diffused layer. Consequently, the present invention delivers high device performances, such as low crosstalk, low radiation damage, high speed, low leakage dark current, and high speed, using a thin active layer. | 02-11-2010 |
| 20180026122 | B-TRAN Geometry and Structure That Provides Both High Gain and High Current Density | 01-25-2018 |
| 257129000 | With means to increase reverse breakdown voltage | 1 |
| 20140217462 | VERTICAL POWER COMPONENT - A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring. | 08-07-2014 |
| 257130000 | Switching speed enhancement means | 4 |
| 20090078962 | Adjustable Field Effect Rectifier - An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference. | 03-26-2009 |
| 20100213503 | BIODIRECTIONAL SWITCH - A bidirectional switch includes a plurality of unit cells | 08-26-2010 |
| 20110278642 | POWER SEMICONDUCTOR STRUCTURE WITH FIELD EFFECT RECTIFIER AND FABRICATION METHOD THEREOF - A power semiconductor structure with a field effect rectifier having a drain region, a body region, a source region, a gate channel, and a current channel is provided. The body region is substantially located above the drain region. The source region is located in the body region. The gate channel is located in the body region and adjacent to a gate structure. The current channel is located in the body region and is extended from the source region downward to the drain region. The current channel is adjacent to a conductive structure coupled to the source region. | 11-17-2011 |
| 20140197449 | SEMICONDUCTOR RECTIFIER DEVICE - Provided is a semiconductor rectifier device. The semiconductor rectifier device may include a substrate doped with a first conductive type, a second electrode provided on a bottom surface of the substrate, an active region and a field region defined on the substrate, a gate provided in the active region, a gate insulating film provided between the gate and the substrate, body regions provided on the substrate adjacent to first and second sides of the gate, facing each other, and doped with a second conductive type dopant different from the first conductive type, and a second conductive type plug region formed on the substrate adjacent to third and fourth sides of the gate, connecting the first and second sides. | 07-17-2014 |
