Entries |
Document | Title | Date |
20080197360 | Diode Having Reduced On-resistance and Associated Method of Manufacture - A diode structure having a reduced on-resistance in the forward-biased condition includes semiconductor layers, preferably of silicon carbide. The anode and cathode of the device are located on the same side of the bottom semiconductor layer, providing lateral conduction across the diode body. The anode is positioned on a semiconductor mesa, and the sides of the mesa are covered with a nonconductive spacer extending from the anode to the bottom layer. An ohmic contact, preferably a metal silicide, covers the surface of the bottom layer between the spacer material and the cathode. The conductive path extends from anode to cathode through the body of the mesa and across the bottom semiconductor layer, including the ohmic contact. The method of forming the diode includes reacting layers of silicon and metal on the appropriate regions of the diode to form an ohmic contact of metal silicide. | 08-21-2008 |
20080197361 | INSULATED GATE SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An insulated gate silicon carbide semiconductor device is provided having small on-resistance in a structure obtained by combining the SIT and MOSFET structures having normally-off operation. The device includes an n | 08-21-2008 |
20080203397 | Switching Device - A high voltage diamond based switching device capable of sustaining high currents in the on state with a relatively low impedance and a relatively low optical switching flux, and capable of being switched off in the presence of the high voltage being switched. The device includes a diamond body having a Schottky barrier contact, held in reverse bias by the applied voltage to be switched, to an essentially intrinsic diamond layer or portion in the diamond body, a second metal contact, and an optical source or other illuminating or irradiating device such that when the depletion region formed by the Schottky contact to the intrinsic diamond layer is exposed to its radiation charge carriers are generated. Cain in the total number of charge carriers then occurs as a result of these charge carriers accelerating under the field within the intrinsic diamond layer and generating further carriers by assisted avalanche breakdown. | 08-28-2008 |
20080203398 | Silicon carbide self-aligned epitaxial MOSFET and method of manufacturing thereof - A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer. | 08-28-2008 |
20080203399 | POLARIZATION DOPED TRANSISTOR CHANNELS IN SIC HETEROPOLYTYPES - Heteropolytype SiC heterojunctions display an abrupt change in polarization leading to 2 dimensional electron or hole gases at the lattice matched interface, depending on the direction of polarization. These channels carry a large amount of electric current which can be modulated with a gate electrode, giving rise to transistor operation in the lateral geometry without the need for n or p type doping. Furthermore, some of these structures display high turn-on voltages which may have applications in terahertz sources and exotic diodes in the transverse geometry. | 08-28-2008 |
20080203400 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H | 08-28-2008 |
20080203401 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED THEREFROM - A method for producing a semiconductor device includes forming a first hetero-semiconductor layer as a hetero-junction to a surface of a silicon carbide epitaxial layer. This layer is composed of polycrystalline silicon having a band gap different from that of the silicon carbide epitaxial layer. An etching stopper layer composed of a material having a different etching rate from that of the polycrystalline silicon is formed on the surface of the first hetero-semiconductor layer. A second hetero-semiconductor layer composed of polycrystalline silicon is formed so that the second hetero-semiconductor layer contacts the surface of the first hetero-semiconductor layer and the etching stopper layer. The etching stopper layer is removed, the first hetero-semiconductor layer is thermally oxidized, and the thermally oxidized portion is then removed. | 08-28-2008 |
20080203402 | SiC semiconductor device and method for manufacturing the same - A SiC semiconductor device includes: a SiC substrate having a main surface; a channel region on the substrate; first and second impurity regions on upstream and downstream sides of the channel region, respectively; a gate on the channel region through a gate insulating film. The channel region for flowing current between the first and second impurity regions is controlled by a voltage applied to the gate. An interface between the channel region and the gate insulating film has a hydrogen concentration equal to or greater than 2.6×10 | 08-28-2008 |
20080210950 | Diamond-like carbon electronic devices and methods of manufacture - Materials, devices, and methods for enhancing performance of electronic devices such as solar cells, fuels cells, LEDs, thermoelectric conversion devices, and other electronic devices are disclosed and described. A diamond-like carbon electronic device can include a conductive diamond-like carbon cathode having specified carbon, hydrogen and sp | 09-04-2008 |
20080217626 | DIAMOND SEMICONDUCTOR ELEMENT AND PROCESS FOR PRODUCING THE SAME - An integrated optical waveguide has a first optical waveguide, a second optical waveguide, and a groove. The second optical waveguide is coupled to the first optical waveguide and has a refractive index that is different from the first optical waveguide. The groove is disposed so as to traverse an optical path of the first optical waveguide and is separated from an interface between the first optical waveguide and the second optical waveguide by a predetermined spacing. The spacing from the interface and the width of the groove are determined such that reflection at a boundary between the first optical waveguide and the second optical waveguide is weakened. A semiconductor board may be disposed at a boundary between the first optical waveguide and the second optical waveguide. In this case, the width of the groove and the thickness of the semiconductor board are determined such that light reflected off an interface between the first optical waveguide and the groove is weakened by light reflected from an interface between the groove and the semiconductor board, and by light reflected from an interface between the semiconductor board and the second optical waveguide. | 09-11-2008 |
20080217627 | SiC-PN Power Diode - An integrated vertical SiC—PN power diode has a highly doped SiC semiconductor body of a first conductivity type, a low-doped drift zone of the first conductivity type, arranged above the semiconductor body on the emitter side, an emitter zone of a second conductivity type, applied to the drift zone, and at least one thin intermediate layer of the first conductivity type. The intermediate layer is arranged inside the drift zone, has a higher doping concentration than the drift zone, and divides the drift zone into at least one first anode-side drift zone layer and at least one second cathode-side drift zone layer. There is also disclosed a circuit configuration with such SiC—PN power diodes. | 09-11-2008 |
20080224149 | Silicon Carbide Semiconductor Device and Manufacturing Method Thereof - The present invention provides a silicon carbide semiconductor device comprising a semiconductor substrate comprising silicon carbide, which contains a first conductivity type impurity diffused therein in a high concentration, a semiconductor layer formed over the semiconductor substrate and containing the first conductivity type impurity diffused therein in a low concentration, a plurality of well regions formed on a front surface side of a cell forming area set to the semiconductor layer and in which a second conductivity type impurity corresponding to a type opposite to the first conductivity type impurity is diffused, source layers formed on the front surface side lying within the well regions and each containing the first conductivity type impurity diffused therein in a high concentration, an outer peripheral insulating film thick in thickness, which is formed over the semiconductor layer in an outer peripheral area that surrounds the cell forming area, a gate oxide film formed over the front surface of the semiconductor layer in the cell forming area, and a gate electrode layer formed so as to extend from above the gate oxide film to above the outer peripheral insulating film, wherein each of steplike portions adjacent to the outer peripheral insulating film and thicker than the gate oxide film in thickness is provided at an edge portion of the gate oxide film. | 09-18-2008 |
20080224150 | Silicon carbide semiconductor device - The SiC semiconductor device includes a substrate of a first conduction type made of silicon carbide, a drift layer of the first conduction type made of silicon carbide, the drift layer being less doped than the substrate, a cell portion constituted by a part of the substrate and a part of the drift layer, a circumferential portion constituted by another part of the substrate and another part of the drift layer, the circumferential portion being formed so as to surround the cell portion, and a RESURF layer of a second conduction type formed in a surface portion of the drift layer so as to be located in the circumferential portion. The RESURF layer is constituted by first and second RESURF layers having different impurity concentrations, the second RESURF layer being in contact with an outer circumference of the first RESURF layer and extending to a circumference of the cell portion. | 09-18-2008 |
20080230787 | Silicon carbide semiconductor device, and method of manufacturing the same - The silicon carbide semiconductor device includes a trench formed from a surface of a drift layer of a first conductivity type formed on a substrate of the first conductivity type, and a deep layer of a second conductivity type located at a position in the drift layer beneath the bottom portion of the trench. The deep layer is formed at a certain distance from base regions of the second conductivity type formed on the drift layer so as to have a width wider than the width of the bottom portion of the trench, and surround both the corner portions of the bottom portion of the trench. | 09-25-2008 |
20080237608 | Molybdenum barrier metal for SiC Schottky diode and process of manufacture - A method for fabricating a diode is disclosed. In one embodiment, the method includes forming a Schottky contact on an epitaxial layer of silicon carbide (SiC) and annealing the Schottky contact at a temperature in the range of 300° C. to 700° C. The Schottky contact is formed of a layer of molybdenum. | 10-02-2008 |
20080237609 | Low Micropipe 100 mm Silicon Carbide Wafer - A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 100 mm and a micropipe density of less than about 25 cm | 10-02-2008 |
20080237610 | COMPOUND SEMICONDUCTOR DEVICE INCLUDING AIN LAYER OF CONTROLLED SKEWNESS - A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive. | 10-02-2008 |
20080246041 | METHOD OF FABRICATING SOI nMOSFET AND THE STRUCTURE THEREOF - A method of fabricating a silicon-on-insulator (SOI) N-channel metal oxide semiconductor field effect transistor (nMOSFET), where the transistor has a structure incorporating a gate disposed above a body of the SOI substrate. The body comprises of a first surface and a second surface. The second surface interfaces between the body and the insulator of the SOI. Between the first surface and second surface is defined a channel region separating a source region and a drain region. Each of the source region and drain region includes a third surface under which is embedded crystalline silicon-carbon (Si:C), which extends from the second surface to the third surface. | 10-09-2008 |
20080251793 | JUNCTION BARRIER SCHOTTKY RECTIFIERS HAVING EPITAXIALLY GROWN P+-N JUNCTIONS AND METHODS OF MAKING - A junction barrier Schottky (JBS) rectifier device and a method of making the device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p | 10-16-2008 |
20080258152 | SiC semiconductor device having outer periphery structure - A SiC semiconductor device includes: a SiC substrate; a SiC drift layer on the substrate having an impurity concentration lower than the substrate; a semiconductor element in a cell region of the drift layer; an outer periphery structure including a RESURF layer in a surface portion of the drift layer and surrounding the cell region; and an electric field relaxation layer in another surface portion of the drift layer so that the electric field relaxation layer is separated from the RESURF layer. The electric field relaxation layer is disposed on an inside of the RESURF layer so that the electric field relaxation layer is disposed in the cell region. The electric field relaxation layer has a ring shape. | 10-23-2008 |
20080258153 | Silcon carbide semiconductor device having schottky barrier diode and method for manufacturing the same - An SiC semiconductor device is provided, which comprises: a substrate made of silicon carbide and having a principal surface; a drift layer made of silicon carbide and disposed on the principal surface; an insulating layer disposed on the drift layer and including an opening; a Schottky electrode contacting with the drift layer through the opening; a termination structure disposed around an outer periphery of the opening; and second conductivity type layers disposed in a surface part of the drift layer, contacting the Schottky electrode, surrounded by the termination structure, and separated from one another. The second conductivity type layers include a center member and ring members. Each ring member surrounds the center member and is arranged substantially in a point symmetric manner with respect to the center member. | 10-23-2008 |
20080265260 | Power Device - A power device having a transistor structure is formed by using a wide band gap semiconductor. A current path | 10-30-2008 |
20080265261 | PROCESS FOR TRANSFERRING A LAYER OF STRAINED SEMICONDUCTOR MATERIAL - Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer. | 10-30-2008 |
20080277668 | SIS semiconductor having junction barrier schottky device - A semiconductor device having a junction barrier Schottky diode includes: a SiC substrate; a drift layer on the substrate; an insulation film on the drift layer having an opening in a cell region; a Schottky barrier diode having a Schottky electrode contacting the drift layer through the opening of the insulation film and an ohmic electrode on the substrate; a terminal structure having a RESURF layer surrounding the cell region; and multiple second conductive type layers on an inner side of the RESURF layer. The second conductive type layers and the drift layer provide a PN diode. The Schottky electrode includes a first Schottky electrode contacting the second conductive type layers with ohmic contact and a second Schottky electrode contacting the drift layer with Schottky contact. | 11-13-2008 |
20080277669 | SiC semiconductor having junction barrier Schottky device - A semiconductor device having a JBS diode includes: a SiC substrate; a drift layer on the substrate; an insulation film on the drift layer having an opening in a cell region; a Schottky barrier diode having a Schottky electrode contacting the drift layer through the opening and an ohmic electrode on the substrate; a terminal structure having a RESURF layer in the drift layer surrounding the cell region; and multiple second conductive type layers in the drift layer on an inner side of the RESURF layer contacting the Schottky electrode. The second conductive type layers are separated from each other. The second conductive type layers and the drift layer provide a PN diode. Each second conductive type layer has a depth larger than the RESURF layer. | 11-13-2008 |
20080277670 | SiC crystal and semiconductor device - The present invention discloses a SiC crystal, comprising: acceptor impurities that are in a concentration greater than 5×10 | 11-13-2008 |
20080283845 | Silicon carbide semiconductor device having high channel mobility and method for manufacturing the same - A silicon carbide semiconductor device having a MOS structure includes: a substrate; a channel area in the substrate; a first impurity area; a second impurity area; a gate insulating film on the channel area; and a gate on the gate insulating film. The channel area provides an electric current path. The channel area and the gate insulating film have an interface therebetween. The interface includes a dangling bond, which is terminated by a hydrogen atom or a hydroxyl. The interface has a hydrogen concentration equal to or larger than 2.6×10 | 11-20-2008 |
20080290348 | Semiconductor device - In the present invention, a vertical MOSFET is formed by growing epitaxial Si on a SiC substrate and forming a Si oxide layer on the Si. In particular, a semiconductor device according to the present invention includes a SiC substrate, and an epitaxial Si layer formed on a surface of the SiC substrate, and a Si oxide layer formed on the epitaxial Si layer, and a gate electrode formed on the Si oxide layer, and a source region formed in the epitaxial Si layer, and a drain electrode connected to the SiC substrate. | 11-27-2008 |
20080296586 | COMPOSITE WAFERS HAVING BULK-QUALITY SEMICONDUCTOR LAYERS AND METHOD OF MANUFACTURING THEREOF - Method for producing composite wafers with thin high-quality semiconductor films atomically attached to synthetic diamond wafers is disclosed. Synthetic diamond substrates are created by depositing synthetic diamond onto a nucleating layer deposited on bulk semiconductor wafer which has been prepared to allow separation of the thin semiconductor film from the remaining bulk semiconductor wafer. The remaining semiconductor wafer is available for reuse. The synthetic diamond substrate serves as heat spreader and a mechanical substrate. | 12-04-2008 |
20080296587 | Silicon carbide semiconductor device having junction barrier schottky diode - A silicon carbide semiconductor device includes a substrate; a drift layer having a first conductivity type; an insulating layer; a Schottky electrode; an ohmic electrode; a resurf layer; and second conductivity type layers. The drift layer and the second conductivity type layers provide multiple PN diodes. Each second conductivity type layer has a radial width with respect to a center of a contact region between the Schottky electrode and the drift layer. A radial width of one of the second conductivity type layers is smaller than that of another one of the second conductivity type layers, which is disposed closer to the center of the contact region than the one of the second conductivity type layers. | 12-04-2008 |
20080303036 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED THEREOF - Methods of manufacturing a semiconductor device including a semiconductor substrate and a hetero semiconductor region including a semiconductor material having a band gap different from that of the semiconductor substrate and contacting a portion of a first surface of the semiconductor substrate are taught herein, as are the resulting devices. The method comprises depositing a first insulating film on exposed portions of the first surface of the semiconductor substrate and on exposed surfaces of the hetero semiconductor material and forming a second insulating film between the first insulating film and facing surfaces of the semiconductor substrate and the hetero semiconductor region by performing a thermal treatment in an oxidizing atmosphere. | 12-11-2008 |
20080315211 | SIC semiconductor device with BPSG insulation film and method for manufacturing the same - A SiC device includes: a substrate; a drift layer; a base region; a source region; a channel layer connecting the drift layer and the source region; a gate oxide film on the channel layer and the source region; a gate electrode on the gate oxide film; an interlayer insulation film with a contact hole having a barrier layer and a BPSG insulation film on the gate electrode; a source electrode having upper and lower wiring electrodes on the interlayer insulation film and in the contact hole for connecting the base region and the source region; and a drain electrode on the substrate. The barrier layer prevents a Ni component in the lower wiring electrode from being diffused into the BPSG insulation film. | 12-25-2008 |
20090001382 | Schottky barrier diode and method for making the same - A schottky diode includes a SiC substrate which has a first surface and a second surface facing away from the first surface, a semiconductor layer which is formed on the first surface of the SiC substrate, a schottky electrode which is in contact with the semiconductor layer, and an ohmic electrode which is in contact with the second surface of the SiC substrate. The first surface of the SiC substrate is a (000-1) C surface, upon which the semiconductor layer is formed. | 01-01-2009 |
20090001383 | Doped Diamond LED Devices and Associated Methods - LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode. | 01-01-2009 |
20090001384 | Group III Nitride semiconductor HFET and method for producing the same - Provided is an HFET exhibiting reduced buffer leakage current. The HFET of the present invention includes an SiC substrate, an AlN layer, a graded AlGaN layer, a GaN layer, an AlGaN layer (Al compositional proportion: 20%), a source electrode, a gate electrode, and a drain electrode, wherein the AlN layer, the graded AlGaN layer, the GaN layer, and the AlGaN (Al: 20%) layer are successively stacked on the substrate, and the electrodes are formed on the AlGaN (Al: 20%) layer so as to be separated from one another. In the graded AlGaN layer, the Al compositional proportion gradually decreases from 30% (at the side facing the AlN layer) to 5% (at the side facing the GaN layer). Provision of the graded AlGaN layer reduces strain between the AlN layer and the GaN layer. Therefore, the HFET exhibits reduced buffer leakage current. | 01-01-2009 |
20090008649 | Silicon carbide semiconductor device and method of manufacturing the same - A silicon carbide semiconductor device includes a substrate having one of a first conductivity type and a second conductivity type, a drift layer having the first conductivity type, a plurality of base regions having the second conductivity type, a plurality of source regions having the first conductivity type, a surface channel layer having the first conductivity type, a plurality of body layers having the second conductivity type, a gate insulation layer, a gate electrode, a first electrode, a second electrode, and a plurality of second conductivity-type regions. The first electrode is electrically coupled with the source regions and the body layers. The second conductivity-type regions are disposed at portions of the drift layer located under the body layers so as to be connected with the base regions respectively. | 01-08-2009 |
20090008650 | FIELD-EFFECT TRANSISTOR AND THYRISTOR - A decrease in breakdown voltage can be prevented as much as possible. A field-effect transistor includes: a drain region made of SiC; a drift layer which is formed on the drain region and is made of n-type SiC; a source region which is formed on the surface of the drift layer and is made of n-type SiC; a channel region which is formed on the surface of the drift layer located on a side of the source region and is made of SiC; an insulating gate which is formed on the channel region; and a p-type base region interposed between the bottom portion of the source region and the drift region, and containing two kinds of p-type impurities. | 01-08-2009 |
20090008651 | Silicon carbide semiconductor device having junction barrier schottky diode - A silicon carbide semiconductor device includes a drift layer having first conductive type on a substrate, a cell region in the drift layer, a schottky electrode on the drift layer and multiple second conductive type layers in the cell region. The second conductive type layers are separated from each other and contact the schottky electrode. A size and an impurity concentration of the second conductive type layers and a size and an impurity concentration of a portion of the drift layer sandwiched between the second conductive type layers are determined so that a charge quantity of the second conductive type layers is equal to a charge quantity of the portion. Hereby, the pressure-proof JBS and low resistivity second conductive type layers arranged on a surface of the drift layer to provide a PN diode, can be obtained. | 01-08-2009 |
20090014730 | SILICON CARBIDE TRANSISTORS AND METHODS FOR FABRICATING THE SAME - An exemplary method for forming an insulator layer over a silicon carbide substrate includes providing a silicon carbide substrate and anodizing the silicon carbide substrate in a liquid ambient at a temperature of not more than 200° C. to form a silicon dioxide layer thereon. Also provided are silicon carbide transistors and methods for fabricating the same. | 01-15-2009 |
20090020764 | GRAPHENE-BASED TRANSISTOR - A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafter removed to provide an opening over the channel of the transistor. Threshold voltage adjustment implantation may be performed to form a threshold voltage implant region directly beneath the channel, which comprises the graphene layer. A gate dielectric is deposited over a channel portion of the graphene layer. After an optional spacer formation, a gate conductor is formed by deposition and planarization. The resulting graphene-based field effect transistor has a high carrier mobility due to the graphene layer in the channel, low contact resistance to the source and drain region, and optimized threshold voltage and leakage due to the threshold voltage implant region. | 01-22-2009 |
20090020765 | Semiconductor Device and Method for Manufacturing Same - A semiconductor device includes a first conductive type SiC semiconductor substrate; a second conductive type well formed on the SiC semiconductor substrate; a first impurity diffusion layer formed by introducing a first conductive type impurity so as to be partly overlapped with the well in a region surrounding the well; a second impurity diffusion layer formed by introducing the first conductive type impurity in a region spaced apart for a predetermined distance from the impurity diffusion layer in the well; and a gate electrode opposed to a channel region between the first and the second impurity diffusion layers with gate insulating film sandwiched therebetween. | 01-22-2009 |
20090020766 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device less prone to cause a reaction between a metal material for interconnection and an electrode or the like connected to a semiconductor region during the high-temperature operation thereof and less prone to be strained during the high-temperature operation thereof. The power semiconductor device can be an SiC power device or the like in which a first metal layer containing at least one selected from the group consisting of Pt, Ti, Mo, W and Ta is formed on a source electrode formed on the semiconductor region, such as a source region or the like. A second metal layer containing at least one selected from the group consisting of Mo, W and Cu is formed on the first metal layer. A third metal layer containing at least one selected from the group consisting of Pt, Mo and W is formed on the second metal layer. | 01-22-2009 |
20090026466 | QUASI SINGLE CRYSTAL NITRIDE SEMICONDUCTOR LAYER GROWN OVER POLYCRYSTALLINE SiC SUBSTRATE - A compound semiconductor device is manufactured by using a polycrystalline SiC substrate, the compound semiconductor device having a buffer layer being formed on the substrate and having a high thermal conductivity of SiC and aligned orientations of crystal axes. The method for manufacturing the compound semiconductor device includes: forming a mask pattern on a polycrystalline SiC substrate, the mask pattern having an opening of a stripe shape defined by opposing parallel sides or a hexagonal shape having an apex angle of 120 degrees and exposing the surface of the polycrystalline SiC substrate in the opening; growing a nitride semiconductor buffer layer, starting growing on the polycrystalline SiC substrate exposed in the opening of the mask pattern, burying the mask pattern, and having a flat surface; and growing a GaN series compound semiconductor layer on the nitride semiconductor buffer layer. | 01-29-2009 |
20090032821 | SEMICONDUCTOR DEVICE AND ELECTRICAL CIRCUIT DEVICE USING THEREOF - A UMOSFET is capable of reducing a threshold voltage and producing a large saturation current. A typical UMOSFET according to the present invention includes: an N | 02-05-2009 |
20090039357 | STACKED NON-VOLATILE MEMORY WITH SILICON CARBIDE-BASED AMORPHOUS SILICON THIN FILM TRANSISTORS - A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer. | 02-12-2009 |
20090039358 | SiC Crystal Semiconductor Device - A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers by high temperature annealing and a SiC semiconductor device fabricated by the method. The method for improving the quality of a SiC layer by eliminating or reducing some carrier trapping centers includes the steps of: (a) carrying out ion implantation of carbon atom interstitials (C), silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer (A) of the starting SiC crystal layer (E) to introduce excess carbon interstitials into the implanted surface layer, and (b) heating the layer for making the carbon interstitials (C) to diffuse out from the implanted surface layer (A) into a bulk layer (E) and for making the electrically active point defects in the bulk layer inactive. After the above steps, the surface layer (A) can be etched or mechanically removed. The SiC semiconductor device is fabricated by the method. | 02-12-2009 |
20090045411 | Forming Embedded Dielectric Layers Adjacent to Sidewalls of Shallow Trench Isolation Regions - A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate; an insulating region extending from substantially a top surface of the semiconductor substrate into the semiconductor substrate; an embedded dielectric spacer adjacent the insulating region, wherein a bottom of the embedded dielectric spacer adjoins the semiconductor substrate; and a semiconductor material adjoining a top edge and extending on a sidewall of the embedded dielectric spacer. | 02-19-2009 |
20090045412 | Method for production of silicon carbide layer, gallium nitride semiconductor device and silicon substrate - A method for producing a silicon carbide layer on a surface of a silicon substrate includes the step of irradiating the surface of the silicon substrate heated in a high vacuum at a temperature in a range of from 500° C. to 1050° C. with a hydrocarbon-based gas as well as an electron beam to form a cubic silicon carbide layer on the silicon substrate surface. | 02-19-2009 |
20090045413 | Silicon Carbide Bipolar Semiconductor Device - In a SiC bipolar semiconductor device with a mesa structure having a SiC drift layer of a first conductive type and a SiC carrier injection layer of a second conductive type that are SiC epitaxial layers grown from a surface of a SiC single crystal substrate, the formation of stacking faults and the expansion of the area thereof are prevented and thereby the increase in forward voltage is prevented. Further, a characteristic of withstand voltage in a reverse biasing is improved. An forward-operation degradation preventing layer is formed on a mesa wall or on a mesa wall and a mesa periphery to separate spatially the surface of the mesa wall from a pn-junction interface. In one embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide low resistance layer of a second conductive type that is equipotential during the application of a reverse voltage. In another embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide conductive layer of a second conductive type, and a metal layer that is equipotential during the application of a reverse voltage is formed on a surface of the silicon carbide conductive layer. In still another embodiment, the forward-operation degradation preventing layer is composed of a high resistance amorphous layer. | 02-19-2009 |
20090045414 | SILICON CARBIDE SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING THE SAME, AND SILICON CARBIDE DEVICE - A silicon carbide semiconductor element and a manufacturing method thereof are disclosed in which a low contact resistance is attained between an electrode film and a wiring conductor element, and the wiring conductor element is hardly detached from the electrode film. In the method, a nickel film and a nickel oxide film are laminated in this order on a surface of an n-type silicon carbide substrate or an n-type silicon carbide region of a silicon carbide substrate, followed by a heat treatment under a non-oxidizing condition. The heat treatment transforms a portion of the nickel film into a nickel silicide film. Then, the nickel oxide film is removed with hydrochloric acid solution, and subsequently, a nickel aluminum film and an aluminum film are laminated in this order on a surface of the nickel silicide film. | 02-19-2009 |
20090050897 | Substrate, method of polishing the same, and polishing apparatus - A polishing method and a polishing apparatus capable of polishing a surface of a substrate made of SiC or diamond extremely smoothly and efficiently without causing subsurface damage are provided. A polishing platen | 02-26-2009 |
20090050898 | Silicon carbide semiconductor device and method for producing the same - A silicon carbide semiconductor device ( | 02-26-2009 |
20090050899 | High-output diamond semiconductor element - The present invention relates to a high-output diamond semiconductor element, including a Schottky electrode as a cathode, a diamond P | 02-26-2009 |
20090050900 | FIELD-EFFECT TRANSISTOR - At least two drain ohmic contacts are arranged to intersect with an active area. A source ohmic contact is arranged between the drain ohmic contacts. A drain coupling portion on an element separating area couples ends of the drain ohmic contacts on the same side thereof. A gate power supply wiring on the element separating area couples gate fingers at the end thereof on the opposite side of the arrangement side of the drain coupling portion. A gate edge coupling portion couples two gate fingers adjacent to each other, sandwiching the source ohmic contact at the end thereof on the arrangement side of the drain coupling portion. The gate edge coupling portion does not intersect with the drain ohmic contact and the drain coupling portion. | 02-26-2009 |
20090050901 | GLASS-CERAMIC-BASED SEMICONDUCTOR-ON-INSULATOR STRUCTURES AND METHOD FOR MAKING THE SAME - The present invention relates to a semiconductor-on-insulator structure including a semiconductor component comprised of substantially single-crystal semiconductor material layer and a single-crystal semiconductor material with an enhanced oxygen content layer; an oxide glass material layer; and a glass-ceramic layer. | 02-26-2009 |
20090050902 | SEMICONDUCTOR DEVICE HAVING SILICON CARBIDE AND CONDUCTIVE PATHWAY INTERFACE - The present invention provides semiconductor device formed by an in situ plasma reducing process to reduce oxides or other contaminants, using a compound of nitrogen and hydrogen, typically ammonia, at relatively low temperatures prior to depositing a subsequent layer thereon. The adhesion characteristics of the layers are improved and oxygen presence is reduced compared to the typical physical sputter cleaning process of an oxide layer. This process may be particularly useful for the complex requirements of a dual damascene structure, especially with copper applications. | 02-26-2009 |
20090057685 | BIPOLAR DEVICE AND FABRICATION METHOD THEREOF - In a mesa type bipolar transistor or a thyristor, since carriers injected from an emitter layer or an anode layer to a base layer or a gate layer diffuse laterally and are recombined, reduction in the size and improvement for the switching frequency is difficult. | 03-05-2009 |
20090057686 | SEMICONDUCTOR DEVICE AND ELECTRIC POWER CONVERTER, DRIVE INVERTER, GENERAL-PURPOSE INVERTER AND SUPER-POWER HIGH-FREQUENCY COMMUNICATION EQUIPMENT USING THE SEMICONDUCTOR DEVICE - In a semiconductor device that uses a silicon carbide semiconductor substrate having p type, n type impurity semiconductor regions formed by ion implantation, the electrical characteristics of the end semiconductor device can be improved by decreasing the roughness of the silicon carbide semiconductor substrate surface. The semiconductor device of this invention is a Schottky barrier diode or a p-n type diode comprising at least one of a p type semiconductor region and n type semiconductor region selectively formed in a silicon carbide semiconductor region having an outermost surface layer surface that is a (000-1) surface or a surface inclined at an angle to the (000-1) surface, and a metal electrode formed on the outermost surface layer surface, that controls a direction in which electric current flows in a direction perpendicular to the outermost surface layer surface from application of a voltage to the metal electrode. | 03-05-2009 |
20090065788 | Semiconductor substrate with islands of diamond and resulting devices - Disclosed is a method of forming a substrate having islands of diamond (or other material, such as diamond-like carbon), as well as integrated circuit devices formed from such a substrate. A diamond island can form part of the thermal solution for an integrated circuit formed on the substrate, and the diamond island can also provide part of a stress engineering solution to improve performance of the integrated circuit. Other embodiments are described and claimed. | 03-12-2009 |
20090072241 | GRID-UMOSFET WITH ELECTRIC FIELD SHIELDING OF GATE OXIDE - A trench metal oxide semiconductor field effect transistor or UMOSFET, includes a buried region that extends beneath the trench and beyond a corner of the trench. The buried region is tied to a source potential of the UMOSFET, and splits the potential realized across the structure. This effectively shields the electric field from the corners of the trench to reduce gate oxide stress, and resultantly improves device performance and reliability. | 03-19-2009 |
20090072242 | Insulated Gate Bipolar Conduction Transistors (IBCTS) and Related Methods of Fabrication - Insulated gate bipolar conduction transistors (IBCTs) are provided. The IBCT includes a drift layer having a first conductivity type. An emitter well region is provided in the drift layer and has a second conductivity type opposite the first conductivity type. A well region is provided in the drift layer and has the second conductivity type. The well region is spaced apart from the emitter well region. A space between the emitter well region and the well region defines a JFET region of the IBCT. An emitter region is provided in the well region and has the first conductivity type and a buried channel layer is provided on the emitter well region, the well region and the JFET region and has the first conductivity type. Related methods of fabrication are also provided. | 03-19-2009 |
20090072243 | Compound semiconductor device and method for fabricating compound semiconductor - In the present invention, a technology for causing arbitrary polarity, crystal face and crystal orientation to exist mixedly in a plane on the surface of a SiC substrate, and for forming a SiC layer or a group III-nitride or group II-oxide layer on the surface, is provided. A first SiC substrate | 03-19-2009 |
20090072244 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE, AND SILICON CARBIDE SEMICONDUCTOR DEVICE - The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carbide with an insulating film and provide the semiconductor device. The method for the fabrication of a silicon carbide semiconductor device includes the steps of performing thermal oxidation on the (000-1) plane of a silicon carbide semiconductor in a gas containing at least oxygen and moisture, thereby forming an insulating film in such a manner as to contact the (000-1) plane of the silicon carbide semiconductor, removing part of the insulating film, thereby forming an opening part therein, depositing contact metal on at least part of the opening part, and performing a heat treatment, thereby forming a reaction layer of the contact metal and silicon carbide, wherein the heat treatment is implemented in a mixed gas of an inert gas and hydrogen. | 03-19-2009 |
20090078942 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an SiC substrate, a first SiC layer of first conductivity provided on the substrate, a second SiC layer of second conductivity provided on the first SiC layer, first and second SiC regions provided in the second SiC layer, facing each other and having the same depth, a third SiC region extending through the first SiC region and reaching the first SiC layer, a gate insulator formed on the first and second SiC regions and the second SiC layer interposed therebetween, a gate electrode formed on the gate insulator, a first contact of first conductivity formed on the second SiC region, a second contact of second conductivity formed on the second SiC region, reaching the second SiC layer through the second SiC region, and a top electrode formed on the first and second contacts, and a bottom electrode formed on a back surface of the substrate. | 03-26-2009 |
20090078943 | NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A nitride semiconductor device mainly made of a nitride semiconductor material having excellent heat dissipation characteristics and great crystallinity and a method for manufacturing thereof are provided. The method for manufacturing the nitride semiconductor includes vapor-depositing a diamond layer on a silicon substrate, bonding an SOI substrate on a surface of the diamond layer, thinning the SOI substrate, epitaxially growing an GaN layer on the thinned SOI substrate, removing the silicon substrate, and bonding, on a rear-surface of the diamond layer, a material having a thermal conductivity greater than a thermal conductivity of the silicon substrate. The SOI substrate has an outermost surface layer and a silicon oxide layer. In the thinning, the SOI substrate is thinned by selectively removed through the silicon oxide layer, so that only the outermost surface layer is left. | 03-26-2009 |
20090085044 | SILICON CARBIDE SEMICONDUCTOR SUBSTRATE AND SILICON CARBIDE SEMICONDUCTOR DEVICE BY USING THEREOF - A manufacturing method is provided for a silicon carbide semiconductor substrate adapted for reduced basal plane dislocations in a silicon carbide epitaxial layer. Between a silicon carbide epitaxial layer for device fabrication (i.e., a drift layer) and a base substrate formed of a silicon carbide single-crystal wafer, a highly efficient dislocation conversion layer through which any basal plane dislocations in the silicon carbide single-crystal wafer are converted into threading edge dislocations very efficiently when the dislocations propagate into the layer epitaxially grown is provided by epitaxial growth. Assigning to the dislocation conversion layer a donor concentration lower than that of the drift layer, therefore, allows the above conversion of a larger number of basal plane dislocations than the case where the drift layer exists alone (without the dislocation conversion layer). | 04-02-2009 |
20090090918 | TRANSPARENT NANOCRYSTALLINE DIAMOND CONTACTS TO WIDE BANDGAP SEMICONDUCTOR DEVICES - A heterojunction between thin films of NCD and 4H—SiC was developed. Undoped and B-doped NCDs were deposited on both n− and p− SiC epilayers. I-V measurements on p+ NCD/n− SiC indicated Schottky rectifying behavior with a turn-on voltage of around 0.2 V. The current increased over eight orders of magnitude with an ideality factor of 1.17 at 30° C. Ideal energy-band diagrams suggested a possible conduction mechanism for electron transport from the SiC conduction band to either the valence band or acceptor level of the NCD film. | 04-09-2009 |
20090090919 | Semiconductor device and method of producing the same - A semiconductor device includes a silicon carbide substrate having a channel region formed on a surface thereof; a silicon layer formed on the channel region; a gate insulation film formed on the silicon layer; and a gate electrode formed on the gate insulation film. A method of producing a semiconductor device includes the steps of: forming a silicon layer on a surface of a silicon carbide substrate; forming a gate insulation film on the silicon layer to form a laminated structure of the silicon layer and the gate insulation film; and forming a gate electrode on the gate insulation film. | 04-09-2009 |
20090090920 | Silicon carbide semiconductor device - A silicon carbide semiconductor device is disclosed. The silicon carbide semiconductor device includes a substrate; a drift layer having a first conductivity type and located on a first surface of the substrate; and a vertical type semiconductor element. The vertical type semiconductor element includes: an impurity layer having a second conductivity type, and located in a surface portion of the drift layer; and a first conductivity type region located in the drift layer, spaced away from the impurity layer, located closer to the substrate than the impurity layer, and having an impurity concentration higher than the drift layer. | 04-09-2009 |
20090101918 | SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a semiconductor layer | 04-23-2009 |
20090108266 | Friction Control in Apparatus Having Wide Bandgap Semiconductors - Apparatus comprising, in use, a wide bandgap semiconductor, a conductor which is moveable relative to the semiconductor and means for applying a potential across the junction between a conductor and semiconductor to control the friction generated by the relative movement between the semiconductor and the conductor. A method of controlling friction between a wide bandgap semiconductor and conductor which are moveable relative to each other comprising applying a potential across the junction between the semiconductor and the conductor. | 04-30-2009 |
20090114923 | SEMICONDUCTOR DEVICE - A semiconductor device includes a peripheral voltage withstanding structure, which includes an n | 05-07-2009 |
20090114924 | LIGHTLY DOPED SILICON CARBIDE WAFER AND USE THEREOF IN HIGH POWER DEVICES - A method for manufacturing a silicon carbide single crystal. A silicon carbide single crystal is grown. The crystal has a boron concentration less than 5×10 | 05-07-2009 |
20090121235 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A transistor of a semiconductor device includes a substrate, a gate over the substrate, a source/drain region formed in the substrate to have a channel region therebetween, and an epitaxial layer formed below the channel region to have a different lattice constant from the substrate. The epitaxial layer having a different lattice constant with a substrate material is formed below the channel region to apply a stress to the channel region. Thus, the mobility of carriers of the transistor increases. | 05-14-2009 |
20090127565 | P-n junctions on mosaic diamond substrates - The present invention provides methods of making and using semiconductive single crystal diamond bodies, including semiconductive diamond bodies made by such methods. In one aspect, a method of making a semiconductive single crystal diamond layer may include placing a plurality of diamond segments in close proximity under high pressure in association with a molten catalyst and a carbon source, where the diamond segments are arranged in a single crystal orientation. The plurality of diamond segments are then maintained under high pressure in the molten catalyst until the plurality of diamond segments have joined together with diamond to diamond bonds to form a substantially single crystal diamond body. Following creation of the single crystal diamond body, a homoepitaxial single crystal diamond layer may be deposited on the single crystal diamond body. A dopant may be introduced into the homoepitaxial single crystal diamond layer to form a semiconductive single crystal diamond layer. | 05-21-2009 |
20090127566 | Method of Selectively Forming Atomically Flat Plane on Diamond Surface, Diamond Substrate Produced by The Method, and Semiconductor Device Using The Same | 05-21-2009 |
20090134402 | SILICON CARBIDE MOS FIELD-EFFECT TRANSISTOR AND PROCESS FOR PRODUCING THE SAME - In the SiC vertical MOSFET having a low-concentration p-type deposition film provided therein with a channel region and a base region resulting from reverse-implantation to n-type through ion implantation, dielectric breakdown of gate oxide film used to occur at the time of off, thereby preventing a further blocking voltage enhancement. This problem has been resolved by interposing of a low-concentration n-type deposition film between a low-concentration p-type deposition film and a high-concentration gate layer and selectively forming of a base region resulting from reverse-implantation to n-type through ion implantation in the low-concentration p-type deposition film so that the thickness of deposition film between the high-concentration gate layer and each of channel region and gate oxide layer is increased. | 05-28-2009 |
20090134403 | DIAMOND ULTRAVIOLET SENSOR - In a conventional ultraviolet sensing device using a diamond semiconductor in a light-receiving unit, an Au-based electrode material is used for both a rectifier electrode and an ohmic electrode. However, the Au-based electrode material has fatal defects, such as poor adhesion to diamond, low mechanical strength, and furthermore poor thermal stability. | 05-28-2009 |
20090134404 | SILICON CARBIDE SEMICONDUCTOR DEVICE - On a major surface of an n-type silicon carbide inclined substrate ( | 05-28-2009 |
20090134405 | SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE - A semiconductor substrate includes a silicon carbide substrate having a first impurity concentration, a first silicon carbide layer formed on the silicon carbide substrate and having a second impurity concentration, and a second silicon carbide layer of a first conductivity type formed on the first silicon carbide layer and having a third impurity concentration, wherein the second impurity concentration is higher than either the first impurity concentration or the third impurity concentration. | 05-28-2009 |
20090140263 | METHOD FOR DIAMOND SURFACE TREATMENT AND DEVICE USING DIAMOND THIN FILM - A method for surface treatment of diamond comprising exposing the surface of diamond to UV light containing wavelengths of 172 nm to 184.9 nm and 253.7 nm at an integrated exposure of 10 to 5,000 J/cm | 06-04-2009 |
20090140264 | SEMICONDUCTOR DEVICE - A hetero semiconductor corner region, which is a current-concentration relief region that keeps a reverse bias current from concentrating on the convex corner, is arranged in a hetero semiconductor region. Thereby, a current concentration on the convex corner can be prevented. As a result, an interrupting performance can be improved at the time of interruption, and at the same time, the generation of the hot spot where in a specific portion is prevented at the time of conduction to suppress deterioration in a specific portion, thereby ensuring a long-term reliability. Further, when the semiconductor chip is used in an L load circuit or the like, for example, at the time of conduction or during a transient response time to the interrupted state, in an index such as a short resistant load amount and an avalanche resistant amount, which are indexes of a breakdown tolerance when overcurrent or overvoltage occurs, the current concentration on a specific portion can be prevented, and thus, these breakdown tolerances can also be improved. | 06-04-2009 |
20090146154 | Transistor with A-Face Conductive Channel and Trench Protecting Well Region - A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner. | 06-11-2009 |
20090152566 | Junction field-effect transistor - A junction field-effect transistor comprises an n-type semiconductor layer having a channel region, a buffer layer formed on the channel region and a p | 06-18-2009 |
20090159896 | SILICON CARBIDE MOSFET DEVICES AND METHODS OF MAKING - A method of making a silicon carbide MOSFET is disclosed. The method includes providing a semiconductor device structure, wherein the device structure comprises a silicon carbide semiconductor device layer, an ion implanted well region of a first conductivity type formed in the semiconductor device layer, an ion implanted source region of a second conductivity type formed into the ion implanted well region; providing a mask layer over the semiconductor device layer, the mask layer exposing a portion of the ion implanted source region, then etching through the portion of the ion implanted source region to form a dimple; then implanting ions through the dimple to form a high dopant concentration first conductivity type ion implanted contact region, wherein the ion implanted contact region is deeper than the ion implanted well region; then removing the contact region mask layer and annealing implanted ions. | 06-25-2009 |
20090159897 | METHOD FOR TREATING SEMICONDUCTOR PROCESSING COMPONENTS AND COMPONENTS FORMED THEREBY - A semiconductor processing component has an outer surface portion comprised of silicon carbide, the outer surface portion having a skin impurity level and a bulk impurity level. The skin impurity level is average impurity level from 0 nm to 100 nm of depth into the outer surface portion, the bulk impurity level is measured at a depth of at least 3 microns into the outer surface portion, and the skin impurity level is not greater than 80% of the bulk impurity level | 06-25-2009 |
20090159898 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device is provided in which the contact resistance of the interface between an electrode and the semiconductor substrate is reduced. The semiconductor device includes a 4H polytype SiC substrate, and an electrode formed on a surface of the substrate. A 3C polytype layer, which extends obliquely relative to the surface of the substrate and whose end portion at the substrate surface is in contact with the electrode, is formed at the surface of the substrate. The 3C polytype layer has a lower bandgap than 4H polytype. Hence, electrons present in the 4H polytype region pass through the 3C polytype layer and reach the electrode. More precisely, the width of the passageway of the electrons is determined by the thickness of the 3C polytype layer. Consequently, with this semiconductor device, in which the passageway of the electrons is narrow, the electrons are able to reach the electrode at a speed close to the theoretical value, by the quantum wire effect. In this way, the contact resistance can be reduced in the semiconductor device. | 06-25-2009 |
20090173949 | SILICON CARBIDE MOS FIELD EFFECT TRANSISTOR WITH BUILT-IN SCHOTTKY DIODE AND METHOD FOR MANUFACTURING SUCH TRANSISTOR - This invention has a cell incorporating a built-in Schottky diode region disposed in at least part of an elementary cell that constitutes an SiC vertical MOSFET provided in a low-density p-type deposit film with a channel region and a base region inverted to an n-type by ion implantation. This built-in Schottky diode region has built therein a Schottky diode of low on-resistance that is formed of a second deficient pan disposed in a high-density gate layer, a second n-type base layer penetrating a low-density p-type deposit layer formed thereon, reaching an n-type drift layer of the second deficient part and attaining its own formation in consequence of inversion of the p-type deposit layer into an n-type by the ion implantation of an n-type impurity from the surface, and a source electrode connected in the manner of forming a Schottky barrier to the surface-exposed part of the second n-type base layer. | 07-09-2009 |
20090173950 | CONTROLLING DIAMOND FILM SURFACES AND LAYERING - A method comprising: providing at least one first diamond film comprising polycrystalline diamond, e.g., nanocrystalline or ultrananocrystalline diamond, disposed on a substrate, wherein the first diamond film comprises a surface comprising diamond asperities and having a first diamond film thickness, removing asperities from the first diamond film to form a second diamond film having a second diamond film thickness, wherein the second thickness is either substantially the same as the first thickness, or the second thickness is about 100 nm or less thinner than the first diamond film thickness, optionally patterning the second diamond film to expose substrate regions and, optionally, depositing semiconductor material on the exposed substrate regions, and depositing a solid layer on the second diamond film to form a first layered structure. Applications include for example dielectric isolation in the semiconductor industry, as well as surface acoustic wave devices, scanning probe microscope, and atomic force microscope devices. | 07-09-2009 |
20090173951 | COMPOUND SEMICONDUCTOR DEVICE USING SiC SUBSTRATE AND ITS MANUFACTURE - A compound semiconductor device includes: a conductive SiC substrate; an AlN buffer layer formed on said conductive SiC substrate and containing Cl; a compound semiconductor buffer layer formed on said AlN layer which contains Cl, said compound semiconductor buffer layer not containing Cl; and a device constituent layer or layers formed above said compound semiconductor buffer layer not containing Cl. | 07-09-2009 |
20090184327 | METHOD FOR PRODUCING SILICON CARBIDE SINGLE CRYSTAL - A method for the production of an SiC single crystal includes the steps of growing a first SiC single crystal in a first direction of growth on a first seed crystal formed of an SiC single crystal, disposing the first SiC single crystal grown on the first seed crystal in a direction parallel or oblique to the first direction of growth and cutting the disposed first SiC single crystal in a direction of a major axis in a cross section perpendicular to the first direction of growth to obtain a second seed crystal, using the second seed crystal to grow thereon in a second direction of growth a second SiC single crystal to a thickness greater than a length of the major axis in the cross section, disposing the second SiC single crystal grown on the second seed crystal in a direction parallel or oblique to the second direction of growth and cutting the disposed second SiC single crystal in a direction of a major axis in a cross section perpendicular to the second direction of growth to obtain a third seed crystal, using the third seed crystal to grow thereon a third SiC single crystal, and cutting the third SiC single crystal grown on the third seed crystal in such a manner as to expose a {0001} crystal face, thereby obtaining an SiC single crystal. The method enables the crystal to be enlarged efficiently without impairing crystallinity. | 07-23-2009 |
20090184328 | ELECTRICAL SWITCHING DEVICE AND METHOD OF EMBEDDING CATALYTIC MATERIAL IN A DIAMOND SUBSTRATE - An electrical switching device ( | 07-23-2009 |
20090194772 | Method For Fabricating Silicon Carbide Vertical MOSFET Devices - A method of forming a vertical MOSFET device includes forming a first trench within a semiconductor layer of a first polarity, the first trench generally defining a well region of a second polarity opposite the first polarity; growing a first epitaxial well layer of the second polarity over the original semiconductor layer; growing a second epitaxial source contact layer of the first polarity over the well layer; forming a second trench through the source contact layer and at least a portion of the well layer; growing a third epitaxial layer of the second polarity over the source contact layer; and planarizing at least the first and second epitaxial layers so as to expose an upper surface of the original semiconductor layer, wherein a top surface of the third epitaxial layer is substantially coplanar with a top surface of the source contact layer prior to ohmic contact formation. | 08-06-2009 |
20090194773 | GALLIUM NITRIDE MATERIAL DEVICES INCLUDING DIAMOND REGIONS AND METHODS ASSOCIATED WITH THE SAME - Gallium nitride material structures are provided, as well as devices and methods associated with such structures. The structures include a diamond region which may facilitate conduction and removal of heat generated within the gallium nitride material during device operation. The structures described herein may form the basis of a number of semiconductor devices and, in particular, transistors (e.g., FETs). | 08-06-2009 |
20090200559 | Silicon carbide semiconductor device including deep layer - A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench penetrating the source region and the base region to the drift layer, a channel layer located in the trench, a gate insulating layer located on the channel layer, a gate electrode located on the gate insulating layer, a source electrode electrically coupled with the source region and the base region, a drain electrode located on a second surface of the substrate, and a deep layer. The deep layer is located under the base region, extends to a depth deeper than the trench and is formed along an approximately normal direction to a sidewall of the trench. | 08-13-2009 |
20090206347 | Semiconductor Device - A unipolar semiconductor device having a drift layer ( | 08-20-2009 |
20090212301 | Double Guard Ring Edge Termination for Silicon Carbide Devices and Methods of Fabricating Silicon Carbide Devices Incorporating Same - Edge termination structures for semiconductor devices are provided including a plurality of spaced apart concentric floating guard rings in a semiconductor layer that at least partially surround a semiconductor junction. The spaced apart concentric floating guard rings have a highly doped portion and a lightly doped portion. Related methods of fabricating devices are also provided herein. | 08-27-2009 |
20090218579 | SUBSTRATE HEATING APPARATUS, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE - In a substrate heating apparatus, thermoelectrons generated by a filament ( | 09-03-2009 |
20090230404 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR | 09-17-2009 |
20090230405 | Diode having Schottky junction and PN junction and method for manufacturing the same - A manufacturing method of a diode includes: forming a P type semiconductor film on a N type semiconductor layer with a crystal growth method; forming a first metallic film on the P type semiconductor film so that the first metallic film contacts the P type semiconductor film with an ohmic contact; forming a mask having an opening on the first metallic film; etching a part of the first metallic film and a part of the P type semiconductor film via the opening so that a part of the N type semiconductor layer is exposed; and forming a second metallic film on the part of the N type semiconductor layer so that the second metallic film contacts the N type semiconductor layer with a Schottky contact. | 09-17-2009 |
20090230406 | HOMOEPITAXIAL GROWTH OF SIC ON LOW OFF-AXIS SIC WAFERS - A wafer including a SiC substrate having a surface that is inclined relative to a (0001) basal plane at an angle higher than 0.1 degree but less than 1 degree, a SiC homoepitaxial device layer, and a SiC homoepitaxial boundary layer having a thickness up to 1 μm arranged between the substrate and the device layer. The boundary layer has been grown on the substrate under an atmosphere of lower supersaturation than when forming the device layer and at a C/Si ratio above 1. | 09-17-2009 |
20090236608 | Method for Producing Graphitic Patterns on Silicon Carbide - In a method of making a vertical graphitic path on a silicon carbide crystal having a horizontal surface, a portion of the silicon carbide crystal is removed from the horizontal surface so as to define a vertical surface that is transverse to the horizontal surface of the silicon carbide crystal. The vertical surface is annealed so as to generate a thin-film graphitic layer on the vertical surface. In another method of making graphitic layers, a material that inhibits formation of a graphitic layer when the silicon carbide crystal is annealed is applied to a surface of a silicon carbide crystal so as to define at least one opening that exposes a portion of the surface of the silicon carbide crystal. The portion of the silicon carbide crystal is annealed so as to generate a thin-film graphitic layer in the portion of the silicon carbide crystal. | 09-24-2009 |
20090236609 | Method and Apparatus for Producing Graphene Oxide Layers on an Insulating Substrate - In a method of making a functionalized graphitic structure, a portion of a multi-layered graphene surface extending from a silicon carbide substrate is exposed to an acidic environment so as to separate graphene layers in a portion of the multi-layered graphene surface. The portion of the multi-layered graphene surface is exposed to a functionalizing material that binds to carbon atoms in the graphene sheets so that the functionalizing material remains between the graphene sheets, thereby generating a functionalized graphitic structure. The functionalized graphitic structure is dried in an inert environment. | 09-24-2009 |
20090236610 | Method for Manufacturing a Semiconductor Structure, and a Corresponding Semiconductor Structure - A method for manufacturing a semiconductor structure is provided which includes the following operations: supplying a crystalline semiconductor substrate, providing a porous region adjacent to a surface of the semiconductor substrate, introducing a dopant into the porous region from the surface, and thermally recrystallizing the porous region into a crystalline doping region of the semiconductor substrate whose doping type and/or doping concentration and/or doping distribution are/is different from those or that of the semiconductor substrate. A corresponding semiconductor structure is likewise provided. | 09-24-2009 |
20090236611 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME - A silicon carbide semiconductor device provided as a semiconductor chip includes a substrate, a drift layer on the substrate, an insulation film on the drift layer, a semiconductor element formed in a cell region of the drift layer, a surface electrode formed on the drift layer and electrically coupled to the semiconductor element through an opening of the insulation film, and a passivation film formed above the drift layer around the periphery of the cell region to cover an outer edge of the surface electrode. The passivation film has an opening through which the surface electrode is exposed outside. A surface of the passivation film is made uneven to increase a length from an inner edge of the opening of the passivation film to a chip edge measured along the surface of the passivation film. | 09-24-2009 |
20090236612 | SILICON CARBIDE MOS SEMICONDUCTOR DEVICE - A silicon carbide MOS semiconductor device is disclosed which suppresses degradation of efficiency percentage yield with respect to a breakdown voltage even when a surface region with a high impurity concentration is formed by ion implantation with such a high dose as required for attaining a good ohmic contact. The device has a silicon carbide semiconductor substrate, a voltage blocking layer of a first conductivity type formed on the substrate, a body region of a second conductivity type formed on the voltage blocking layer, a body contact region of the second conductivity type formed in a surface region of the body region by selective ion implantation, a surface of the body contact region having such a high impurity concentration as to impart an ohmic contact, a source contact region of the first conductivity type formed in a surface region of the body region by selective ion implantation, a surface of the source contact region having such a high impurity concentration as to impart an ohmic contact, and a source extension region with an impurity concentration lower than that in the source contact region under the source contact region at a region deeper than a tail part of a bottom region of the source contact region by selective ion implantation, the source extension region having an impurity concentration less than 3×10 | 09-24-2009 |
20090242899 | Epitaxial Growth on Low Degree Off-Axis SiC Substrates and Semiconductor Devices Made Thereby - A method of epitaxially growing a SiC layer on a single crystal SiC substrate is described. The method includes heating a single-crystal SiC substrate to a first temperature of at least 1400° C. in a chamber, introducing a carrier gas, a silicon containing gas and carbon containing gas into the chamber; and epitaxially growing a layer of SiC on a surface of the SiC substrate. The SiC substrate is heated to the first temperature at a rate of at least | 10-01-2009 |
20090242900 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention discloses a memory device and method thereof. The memory device comprises a substrate, an insulator layer, a first conducting layer, a CaCu | 10-01-2009 |
20090242901 | SiC MOSFETS AND SELF-ALIGNED FABRICATION METHODS THEREOF - The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided. | 10-01-2009 |
20090250705 | SILICON CARBIDE SEMICONDUCTOR DEVICE COMPRISING SILICON CARBIDE LAYER AND METHOD OF MANUFACTURING THE SAME - A p base ohmic contact of a silicon carbide semiconductor device consists of a p++ layer formed by high-concentration ion implantation and a metal electrode. Since the high-concentration ion implantation performed at the room temperature significantly degrades the crystal of the p++ layer to cause a process failure, a method for implantation at high temperatures is used. In terms of switching loss and the like of devices, it is desirable that the resistivity of the p base ohmic contact should be lower. In well-known techniques, nothing is mentioned on a detailed relation among the ion implantation temperature, the ohmic contact resistivity and the process failure. Then, in the ion implantation step, the temperature of a silicon carbide wafer is maintained in a range from 175° C. to 300° C., more preferably in a range from 175° C. to 200° C. The resistivity of the p base ohmic contact using a p++ region formed by ion implantation at a temperature in a range from 175° C. to 300° C. becomes lower than that in a case where the p++ region is formed by ion implantation at a temperature over 300° C. Further, this can avoid any process failure. | 10-08-2009 |
20090256160 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device is provided. A gate structure is formed on a substrate. A first dopant implantation and a first strain atom implantation are performed. Thereafter, spacers are formed on sidewalls of the gate structure. A second dopant implantation and a second strain atom implantation are performed. A solid-phase epitaxy annealing process is performed to form source and drain regions made of a semiconductor compound solid-phase epitaxial layer beside the gate structure. | 10-15-2009 |
20090256161 | POWER CONVERSION APPARATUS - In the case where a chip is made of wide band gap semiconductor, a power conversion apparatus is obtained in which a component having a low heat resistant temperature is prevented from receiving thermal damage by heat generated at the chip. In a configuration including: a chip portion ( | 10-15-2009 |
20090256162 | Method for Producing Semi-Insulating Resistivity in High Purity Silicon Carbide Crystals - A method is disclosed for producing high quality semi-insulating silicon carbide crystals in the absence of relevant amounts of deep level trapping elements. The invention includes the steps of heating a silicon carbide crystal having a first concentration of point defects to a temperature that thermodynamically increases the number of point defects and resulting states in the crystal, and then cooling the heated crystal at a sufficiently rapid rate to maintain an increased concentration of point defects in the cooled crystal. | 10-15-2009 |
20090261347 | DIAMOND SEMICONDUCTOR ELEMENT AND PROCESS FOR PRODUCING THE SAME - In a conventional diamond semiconductor element, because of high density of crystal defects, it is impossible to reflect the natural physical properties peculiar to a diamond, such as high thermal conductivity, high breakdown field strength, high-frequency characteristics and the like, in the transistor characteristics. By slightly shifting surface orientation of a diamond substrate in a [001] direction, a significant reduction in crystal defects peculiar to a diamond is possible. The equivalent effects are also provided by shifting surface orientation of a single-crystal diamond thin-film or channel slightly from a [001] direction. It is possible to obtain a significantly high transconductance gm as compared with that in a transistor produced using conventional surface orientation. | 10-22-2009 |
20090261348 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In a semiconductor device using a SiC substrate, a Junction Termination Edge (JTE) layer is hardly affected by fixed charge so that a stable dielectric strength is obtained. A semiconductor device according to a first aspect of the present invention includes a SiC epi-layer having n type conductivity, an impurity region in a surface of the SiC epi-layer and having p type conductivity, and JTE layers adjacent to the impurity region, having p type conductivity, and having a lower impurity concentration than the impurity region. The JTE layers are spaced by a distance from an upper surface of the SiC epi-layer, and SiC regions having n type conductivity are present on the JTE layers. | 10-22-2009 |
20090261349 | SEMICONDUCTOR DEVICE WITH STRAINED CHANNEL AND METHOD OF FABRICATING THE SAME - A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern. | 10-22-2009 |
20090261350 | Silicon carbide semiconductor device including deep layer - A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench sandwiched by each of the base region to the drift layer, a channel layer located in the trench, a gate insulating layer located on the channel layer, a gate electrode located on the gate insulating layer, a source electrode electrically coupled with the source region and the base region, a drain electrode located on a second surface of the substrate, and a deep layer located under the base region and extending to a depth deeper than the trench. The deep layer is formed into a lattice pattern. | 10-22-2009 |
20090261351 | Silicon Carbide Devices Having Smooth Channels - Power devices are provided including a p-type conductivity well region and a buried p | 10-22-2009 |
20090267081 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATION THEREOF - A semiconductor device includes a substrate formed of a single crystal. a silicon carbide layer disposed on a surface of the single crystal substrate and an intermediate layer disposed on a surface of the silicon carbide layer and formed of a Group III nitride semiconductor, wherein the silicon carbide layer is formed of a cubic crystal stoichiometrically containing silicon copiously and the surface thereof has a (3×3) reconstruction structure. The semiconductor device is fabricated by a method including a first step of blowing a hydrocarbon gas on the surface of the substrate, thereby inducing adsorption of hydrocarbon thereon, a second step of heating the substrate having adsorbed the hydrocarbon to a temperature exceeding a temperature used for the adsorption of the hydrocarbon while irradiating the surface of the substrate with electrons and consequently giving rise to a silicon carbide layer formed of a cubic crystal stoichiometrically containing silicon copiously and provided with a surface having a (3×3) reconstruction structure and a third step of supplying a gaseous raw material containing nitrogen and a gaseous raw material containing a Group III element to the surface of the silicon carbide layer and consequently giving rise to the intermediate layer formed of the Group III nitride semiconductor. | 10-29-2009 |
20090267082 | Semiconductor device and manufacturing method of the same - A semiconductor device includes: a semiconductor element having a first surface and a second surface; a first electrode disposed on the first surface of the element; a second electrode disposed on the second surface of the element; and an insulation film covers a part of the first electrode, the first surface of the element and a part of a sidewall of the element. The above semiconductor device has small dimensions and a high breakdown voltage. | 10-29-2009 |
20090272982 | TRENCH GATE TYPE SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A method of producing a trench gate type MOSFET is provided in which each intersection trench is formed as a two-stage trench structure. A gate trench is backfilled with a mask material and the mask material is then patterned to form a mask used for forming each intersection trench. The intersection trench intersecting the gate trench is provided so as to be deeper than the gate trench. A Schottky electrode is provided in the bottom of each intersection trench | 11-05-2009 |
20090272983 | Silicon carbide semiconductor device and method for manufacturing the same - A silicon carbide semiconductor device includes: a semiconductor substrate having a silicon carbide substrate, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; a trench penetrating the second and the third semiconductor layers to reach the first semiconductor layer; a channel layer on a sidewall and a bottom of the trench; an oxide film on the channel layer; a gate electrode on the oxide film; a first electrode connecting to the third semiconductor layer; and a second electrode connecting to the silicon carbide substrate. A position of a boundary between the first semiconductor layer and the second semiconductor layer is disposed lower than an utmost lowest position of the oxide film. | 11-05-2009 |
20090272984 | Silicon Carbide on Diamond Substrates and Related Devices and Methods - A high power, wide-bandgap device is disclosed that exhibits reduced junction temperature and higher power density during operation and improved reliability at a rated power density. The device includes a diamond substrate for providing a heat sink with a thermal conductivity greater than silicon carbide, a single crystal silicon carbide layer on the diamond substrate for providing a supporting crystal lattice match for wide-bandgap material structures that is better than the crystal lattice match of diamond, and a Group III nitride heterostructure on the single crystal silicon carbide layer for providing device characteristics. | 11-05-2009 |
20090278137 | SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING - Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described. | 11-12-2009 |
20090289262 | JUNCTION BARRIER SCHOTTKY DIODES WITH CURRENT SURGE CAPABILITY - An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing. | 11-26-2009 |
20090289263 | System and Method for Emitter Layer Shaping - Embodiments of an LED disclosed has an emitter layer shaped to a controlled depth or height relative to a substrate of the LED to maximize the light output of the LED and to achieve a desired intensity distribution. In some embodiments, the exit face of the LED may be selected to conserve radiance. In some embodiments, shaping the entire LED, including the substrate and sidewalls, or shaping the substrate alone can extract 100% or approximately 100% of the light generated at the emitter layers from the emitter layers. In some embodiments, the total efficiency is at least 90% or above. In some embodiments, the emitter layer can be shaped by etching, mechanical shaping, or a combination of various shaping methods. In some embodiments, only a portion of the emitter layer is shaped to form the tiny emitters. The unshaped portion forms a continuous electrical connection for the LED. | 11-26-2009 |
20090289264 | Silicon carbide semiconductor device and method of manufacturing the same - An SiC semiconductor device includes a substrate, a drift layer disposed on a first surface of the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a trench penetrating the source region and the base region to the drift layer, a gate insulating layer disposed on a surface of the trench, a gate electrode disposed on a surface of the gate insulating layer, a first electrode electrically coupled with the source region and the base region, a second electrode disposed on the second surface of the substrate, and a second conductivity-type layer disposed at a portion of the base region located under the source region. The second conductivity-type layer has the second conductivity type and has an impurity concentration higher than the base region. | 11-26-2009 |
20090294776 | Highly Oxygen-Sensitive Silicon Layer and Method for Obtaining Same - Silicon layer highly sensitive to oxygen and method for obtaining said layer. | 12-03-2009 |
20090294777 | METHOD FOR FORMING A GROUP III NITRIDE MATERIAL ON A SILICON SUBSTRATE - Semiconductor process technology and devices are provided, including a method for forming a high quality group III nitride layer on a silicon substrate and to a device obtainable therefrom. According to the method, a pre-dosing step is applied to a silicon substrate, wherein the substrate is exposed to at least 0.01 μmol/cm | 12-03-2009 |
20090302326 | SILICON CARBIDE SINGLE CRYSTAL WAFER AND PRODUCING METHOD THEREOF - A silicon carbide single crystal wafer wherein a substrate is cut out at an OFF angle from a (0001) c plane of an α-type silicon carbide single crystal of less than 2° and in an OFF direction in which a deviation from a (11-20) direction is less than 10°, the number of substantially triangular lamination defects exposed from a surface of a wafer which is epitaxial grown on the substrate is less than 4/cm | 12-10-2009 |
20090302327 | RUGGED SEMICONDUCTOR DEVICE ARCHITECTURE - A wide bandgap silicon carbide device has an avalanche control structure formed in an epitaxial layer of a first conductivity type above a substrate that is connected to a first electrode of the device. A first region of a second conductivity type is in the upper surface of the epitaxial layer with a connection to a second electrode of the device. A second region of the first conductivity type lies below the first region and has a dopant concentration greater than the dopant concentration in the epitaxial layer. | 12-10-2009 |
20090302328 | Silicon carbide semiconductor substrate and method of manufacturing the same - A buffer layer configured of the same conductive semiconductor layers of two or more layers as a drift layer is installed by epitaxial growth between a first semiconductor layer configuring the drift layer that is a layer in which components of the semiconductor device are made and a base substrate including a silicon carbide single crystal wafer. A step of donor concentration is provided at an interface between the drift layer and the buffer layer, an interface between the semiconductor layers configuring the buffer layer, and an interface between the buffer layer and the base substrate and the donor concentration of the drift layer side is lower than that of the base substrate side, thereby making it possible to convert most basal plane dislocations into threading edge dislocations as compared to the drift layer having one layer or the buffer layer configured of one layer. | 12-10-2009 |
20090315039 | Trench MOS type silicon carbide semiconductor device - A trench MOS type SiC semiconductor device includes a first conductivity semiconductor substrate, a first conductivity drift layer on the substrate, a second conductivity base layer on the drift layer, a first conductivity source layer on the base layer, a stripe shaped trench reaching from the surface of the source layer to the drift layer and having a gate electrode via a gate oxide film, a second conductivity layer on the bottom of the trench, and a second conductivity type region thereon on across-the-width side walls of at least one end of the trench, electrically coupling the second conductivity layer with the base layer. The device allows a low on-resistance without newly forming an electrode connected to the second conductivity layer even in the case of a device in which the second conductivity layer has to be grounded. | 12-24-2009 |
20090315040 | WIDE BANDGAP DEVICE IN PARALLEL WITH A DEVICE THAT HAS A LOWER AVALANCHE BREAKDOWN VOLTAGE AND A HIGHER FORWARD VOLTAGE DROP THAN THE WIDE BANDGAP DEVICE - A method and device for protecting wide bandgap devices from failing during suppression of voltage transients. An improvement in avalanche capability is achieved by placing one or more diodes, or a PNP transistor, across the blocking junction of the wide bandgap device. | 12-24-2009 |
20090321746 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A low on-resistance silicon carbide semiconductor device is provided that includes an ohmic electrode of low contact resistance and high adhesion strength formed on a lower surface of silicon carbide. | 12-31-2009 |
20090321747 | MULTILAYERED SEMICONDUCTOR WAFER AND PROCESS FOR MANUFACTURING THE SAME - The invention relates to a process for manufacturing a multilayered semiconductor wafer comprising a handle wafer ( | 12-31-2009 |
20100001290 | BIPOLAR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor crystal includes a recombination-inhibiting semiconductor layer ( | 01-07-2010 |
20100001291 | ELECTRONIC DEVICE AND MANUFACTURING THEREOF - An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane. | 01-07-2010 |
20100001292 | High Efficiency Indirect Transition Semiconductor Ultraviolet Light Emitting Device - Provided is a light emitting device formed of an indirect transition semiconductor configured from a semiconductor material having high exciton binding energy, wherein an active layer of the indirect transition semiconductor or an active region by a pn junction is formed, the light emitting device has an electrode for injecting current into the active layer or the active region, and the internal quantum efficiency is 10% or more. | 01-07-2010 |
20100001293 | SEMICONDUCTOR DEVICES HAVING GALLIUM NITRIDE EPILAYERS ON DIAMOND SUBSTRATES - Methods for integrating wide-gap semiconductors with synthetic diamond substrates are disclosed. Diamond substrates are created by depositing synthetic diamond onto a nucleating layer deposited or formed on a layered structure including at least one layer of gallium nitride, aluminum nitride, silicon carbide, or zinc oxide. The resulting structure is a low stress process compatible with wide-gap semiconductor films, and may be processed into optical or high-power electronic devices. The diamond substrates serve as heat sinks or mechanical substrates. | 01-07-2010 |
20100006858 | Semiconductor-on-diamond devices and associated methods - Semiconductor devices and methods for making such devices are provided. One such method may include forming an epitaxial layer of single crystal SiC on a single crystal Si growth substrate, forming an epitaxial diamond layer on the layer of SiC, forming a Si layer on the diamond layer, bonding a SiO | 01-14-2010 |
20100006859 | Method of Manufacturing Substrates Having Improved Carrier Lifetimes - This invention relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a chlorosilane gas, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C. but less than 2000° C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr. This invention also relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a non-chlorinated silicon-containing gas, hydrogen chloride, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C. but less than 2000° C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr. | 01-14-2010 |
20100006860 | METHOD FOR IMPROVING INVERSION LAYER MOBILITY IN A SILICON CARBIDE MOSFET - A method of manufacturing a semiconductor device based on a SiC substrate ( | 01-14-2010 |
20100006861 | Silicon carbide semiconductor device and manufacturing method of the same - A SiC semiconductor device includes: a substrate; a drift layer on a first side of the substrate; a trench in the drift layer; a base region contacting a sidewall of the trench; a source region in an upper portion of the base region; a gate electrode in the trench via a gate insulation film; a source electrode on the source region; and a drain electrode on a second side of the substrate. The source region has multi-layered structure including a first layer and a second layer. The first layer as an upper layer contacts the source electrode with ohmic contact. The second layer as a lower layer has an impurity concentration, which is lower than an impurity concentration of the first layer. | 01-14-2010 |
20100012949 | SUBSTRATE, IN PARTICULAR MADE OF SILICON CARBIDE, COATED WITH A THIN STOICHIOMETRIC FILM OF SILICON NITRIDE, FOR MAKING ELECTRONIC COMPONENTS, AND METHOD FOR OBTAINING SUCH A FILM - Substrate, in particular in silicon carbide, covered by a thin film of stoichiometric silicon nitride, for the manufacture of electronic components and method for obtaining said film. | 01-21-2010 |
20100012950 | CRACKSTOP STRUCTURES AND METHODS OF MAKING SAME - An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a set of wiring levels stacked from a first wiring level to a last wiring level; and a respective void in each wiring level of two or more wiring levels of the set wiring levels, each respective void extending in a continuous ring parallel and proximate to a perimeter of the integrated circuit chip, a void of a higher wiring level stacked directly over but not contacting a void of a lower wiring level, the respective voids forming a crack stop. | 01-21-2010 |
20100012951 | Silicon carbide semiconductor device and method for producing the same - In an SiC vertical MOSFET comprising a channel region and an n-type inverted electron guide path formed through ion implantation in a low-concentration p-type deposition film, the width of the channel region may be partly narrowed owing to implantation mask positioning failure, and the withstand voltage of the device may lower, and therefore, the device could hardly satisfy both low on-resistance and high withstand voltage. In the invention, second inverted layers ( | 01-21-2010 |
20100012952 | Nitride-Based Transistors Having Laterally Grown Active Region and Methods of Fabricating Same - High electron mobility transistors and/or methods of fabricating high electron mobility transistors that include a first Group III-nitride layer having vertically grown regions, laterally grown regions and a coalescence region are provided. A Group III-nitride channel layer is provided on the first Group III-nitride layer and a Group III-nitride barrier layer is provided on the Group III-nitride channel layer. A drain contact, a source contact and a gate contact are provided on the barrier layer. The gate contact is disposed on a portion of the barrier layer on a laterally grown region of the first Group III-nitride layer and at least a portion of one of the source contact and/or the drain contact is disposed on a portion of the barrier layer on a vertically grown region of the first Group III-nitride layer. | 01-21-2010 |
20100019249 | JFET Devices with Increased Barrier Height and Methods of Making Same - Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET. | 01-28-2010 |
20100019250 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device and a method of forming thereof has a base body has a field stopping layer, a drift layer, a current spreading layer, a body region, and a source contact region layered in the order on a substrate. A trench that reaches the field stopping layer or the substrate is provided. A gate electrode is provided in the upper half section in the trench. In a section deeper than the position of the gate electrode in the trench, an insulator is buried that has a normal value of insulation breakdown electric field strength equal to or greater than the value of the insulation breakdown electric field strength of the semiconductor material of the base body. This inhibits short circuit between a gate and a drain due to insulation breakdown of an insulator film at the bottom of the trench to realize a high breakdown voltage in a semiconductor device using a semiconductor material such as SiC. The sidewall surfaces of the trench located below the gate electrode is inclined to form a trapezoidal profile. | 01-28-2010 |
20100025695 | ANNEALING METHOD FOR SEMICONDUCTOR DEVICE WITH SILICON CARBIDE SUBSTRATE AND SEMICONDUCTOR DEVICE - In an atmosphere in which a silicon carbide (SiC) substrate implanted with impurities is annealed to activate the impurities, by setting a partial pressure of H | 02-04-2010 |
20100025696 | Process for Producing a Silicon Carbide Substrate for Microelectric Applications - The process according to the present invention is adapted to produce a silicon carbide substrate for microelectronic applications; it comprises the following steps:
| 02-04-2010 |
20100032685 | MESA TERMINATION STRUCTURES FOR POWER SEMICONDUCTOR DEVICES AND METHODS OF FORMING POWER SEMICONDUCTOR DEVICES WITH MESA TERMINATION STRUCTURES - An electronic device includes a drift layer having a first conductivity type, a buffer layer having a second conductivity type, opposite the first conductivity type, on the drift layer and forming a P—N junction with the drift layer, and a junction termination extension region having the second conductivity type in the drift layer adjacent the P—N junction. The buffer layer includes a step portion that extends over a buried portion of the junction termination extension. Related methods are also disclosed. | 02-11-2010 |
20100032686 | Bipolar Semiconductor Device, Method for Producing the Same, and Method for Controlling Zener Voltage - Bipolar semiconductor devices have a Zener voltage controlled very precisely in a wide range of Zener voltages (for example, from 10 to 500 V). A bipolar semiconductor device has a mesa structure and includes a silicon carbide single crystal substrate of a first conductivity type, a silicon carbide conductive layer of a first conductivity type, a highly doped layer of a second conductivity type and a silicon carbide conductive layer of a second conductivity type which substrate and conductive layers are laminated in the order named. | 02-11-2010 |
20100038653 | DIAMOND ELECTRONIC DEVICES AND METHODS FOR THEIR MANUFACTURE - The present invention relates to a diamond electronic device comprising a functional interface between two solid materials, wherein the interface is formed by a planar first surface of a first layer of single crystal diamond and a second layer formed on the first surface of the first diamond layer, the second layer being solid, non-metallic and selected from diamond, a polar material and a dielectric material, and wherein the planar first surface of the first layer of single crystal diamond has an Rq of less than 10 nm and has at least one of the following characteristics: (a) the first surface is an etched surface; (b) a density of dislocations in the first diamond layer breaking the first surface is less than 400 cm | 02-18-2010 |
20100044720 | SEMICONDUCTOR DEVICE WITH A REDUCED BAND GAP AND PROCESS - The application relates to a semiconductor device made of silicon with regionally reduced band gap and a process for the production of same. One embodiment provides a semiconductor device including a body zone, a drain zone and a source zone. A gate extends between the source zone and the drain zone. A reduced band gap region is provided in a region of the body zone, made of at least ternary compound semiconductor material. | 02-25-2010 |
20100044721 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer | 02-25-2010 |
20100051963 | POWER TRANSISTOR - A power transistor. One embodiment provides a power transistor having a first terminal, a second terminal and a control terminal. A support layer is formed of a first material having a first bandgap. An active region is formed of a second material having a second bandgap wider than the first bandgap, and is disposed on the support layer. The active region is arranged to form part of a current path between the first and second terminal in a forward mode of operation. The active region includes at least one pn-junction. | 03-04-2010 |
20100051964 | METHOD FOR PREPARING A SEMICONDUCTOR ULTRANANOCRYSTALLINE DIAMOND FILM AND A SEMICONDUCTOR ULTRANANOCRYSTALLINE DIAMOND FILM PREPARED THEREFROM - A method for preparing a semiconductor ultrananocrystalline diamond (UNCD) film includes doping an UNCD film with an ion source at a dose not less than 10 | 03-04-2010 |
20100059762 | HEAT REMOVAL FACILITATED WITH DIAMOND-LIKE CARBON LAYER IN SOI STRUCTURES - Described are Silicon-on-Insulator devices containing a diamond-like carbon layer, methods of making the Silicon-on-Insulator devices, and methods of using the Silicon-on-Insulator devices. | 03-11-2010 |
20100059763 | LUMINOUS ELEMENT HAVING A PLURALITY OF CELLS - Disclosed is a light emitting element comprising a first array having a plurality of vertical light emitting cells connected in series on a single substrate; and a second array that has another plurality of vertical light emitting cells connected in series on the single substrate and is connected to the first array in reverse parallel. In the light emitting element, each of the vertical light emitting cells in the first and second arrays has a first electrode pad on a bottom surface thereof and a second electrode pad on a top surface thereof, and a connection portion is provided to electrically connect the first electrode pad of the vertical light emitting cell in the first array to the first electrode pad of the vertical light emitting cell in the second array. | 03-11-2010 |
20100059764 | STRUCTURE AND METHOD TO FORM MULTILAYER EMBEDDED STRESSORS - A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions. | 03-11-2010 |
20100065857 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A silicon carbide semiconductor device having excellent performance characteristics and a method of manufacturing the same are obtained. A coating film made of Si is formed on an initial growth layer on a 4H—SiC substrate, and an extended terrace surface is formed in a region covered with the coating film. Next, the coating film is removed, and a new growth layer is epitaxially grown on the initial growth layer. A 3C—SiC portion made of 3C—SiC crystals having a polytype stable at a low temperature is grown on the extended terrace surface of the initial growth layer. A channel region of a MOSFET or the like is provided in the 3C—SiC portion having a narrow band gap. As a result, the channel mobility is improved because of a reduction in an interface state, and a silicon carbide semiconductor device having excellent performance characteristics is obtained. | 03-18-2010 |
20100072484 | HETEROEPITAXIAL GALLIUM NITRIDE-BASED DEVICE FORMED ON AN OFF-CUT SUBSTRATE - Embodiments include but are not limited to apparatuses and systems including a heteroepitaxial gallium nitride-based device formed on an off-cut substrate, and methods for making the same. Other embodiments may be described and claimed. | 03-25-2010 |
20100072485 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING METHOD - One atomic layer of Si atoms 3 is grown on an Si-terminated SiC surface 1 | 03-25-2010 |
20100078650 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate made of silicon carbide and having a surface, a normal vector for the surface having an off angle with respect to a <0001> direction or a <000-1> direction, a semiconductor layer of a first conductivity type formed on the semiconductor substrate, a first semiconductor region of a second conductivity type formed in a surface region of the semiconductor layer, a source region of a first conductivity type formed in a surface region of the first semiconductor region, a second semiconductor region of a second conductivity type formed in the surface region of the semiconductor layer, contacting the first semiconductor region, and having a bottom surface lower than a bottom surface of the first semiconductor region, wherein at least one end of the bottom surface of the second semiconductor region is perpendicular to an off angle direction. | 04-01-2010 |
20100078651 | ELECTRONIC FIELD EFFECT DEVICES AND METHODS FOR THEIR MANUFACTURE - Electronic field effect devices, and methods of manufacture of these electronic field effect devices are disclosed. In particular, there is disclosed an electronic field effect device which has improved electrical properties due to the formation of a highly mobile two-dimensional charge-carrier gas in a simple structure formed from diamond in combination with polar materials. | 04-01-2010 |
20100078652 | DIAMOND ELECTRONIC DEVICES INCLUDING A SURFACE AND METHODS FOR THEIR MANUFACTURE - The present invention relates to a diamond electronic device comprising a functional surface formed by a planar surface of a single crystal diamond, the planar surface of the single crystal diamond having an Rq of less than 10 nm and at least one of the following characteristics: (a) the surface has not been mechanically processed since formation by synthesis; (b) the surface is an etched surface; (c) a density of dislocations in the diamond breaking the surface is less than 400 cm″2 measured over an area greater than 0.014 cm2; (d) the surface has an Rq less than 1 nm; (e) the surface has regions with a layer of charge carriers immediately below it, such that the regions of the surface are normally termed conductive, such as a hydrogen terminated {100} diamond surface region; (f) the surface has regions with no layer of charge carriers immediately below it, such that these regions of the surface are normally termed insulating, such as an oxygen terminated {100} diamond surface; and (g) the surface has one or more regions of metallization providing electrical contact to the diamond surface beneath these regions. | 04-01-2010 |
20100078653 | TRANSISTOR HAVING A HIGH-K METAL GATE STACK AND A COMPRESSIVELY STRESSED CHANNEL - In a manufacturing flow for adapting the band gap of the semiconductor material with respect to the work function of a metal-containing gate electrode material, a strain-inducing material may be deposited to provide an additional strain component in the channel region. For instance, a layer stack with silicon/carbon, silicon and silicon/germanium may be used for providing the desired threshold voltage for a metal gate while also providing compressive strain in the channel region. | 04-01-2010 |
20100078654 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a first transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the semiconductor substrate under the first gate insulating film, and first epitaxial crystal layers formed on both sides of the first channel region in the semiconductor substrate, the first epitaxial crystal layers comprising a first crystal; and a second transistor comprising a second gate electrode formed on the semiconductor substrate via a second gate insulating film, a second channel region formed in the semiconductor substrate under the second gate insulating film, second epitaxial crystal layers formed on both sides of the second channel region in the semiconductor substrate, and third epitaxial crystal layers formed on the second epitaxial crystal layers, the second epitaxial crystal layers comprising a second crystal, the third epitaxial crystal layers comprising the first crystal, the second transistor having a conductivity type different from that of the first transistor. | 04-01-2010 |
20100084663 | Silicon Carbide Zener Diode - A silicon carbide Zener diode is a bipolar semiconductor device that has a mesa structure and includes a silicon carbide single crystal substrate of a first conductivity type, formed thereon, a silicon carbide conductive layer of a first conductivity type, and a silicon carbide conductive layer of a second conductivity type formed on the silicon carbide conductive layer of a first conductivity type, wherein a depletion layer that is formed under reverse bias at a junction between the silicon carbide conductive layer of a first conductivity type and the silicon carbide conductive layer of a second conductivity type does not reach a mesa corner formed in the silicon carbide conductive layer of a first conductivity type. | 04-08-2010 |
20100090226 | DIAMOND UV-RAY SENSOR - Au base electrode materials have fatal disadvantages, such as inferior adhesion to diamond, low mechanical strength, and low thermal stability. | 04-15-2010 |
20100090227 | METHOD FOR THE FORMATION OF A GATE OXIDE ON A SIC SUBSTRATE AND SIC SUBSTRATES AND DEVICES PREPARED THEREBY - Methods are provided for improving inversion layer mobility and providing low defect density in a semiconductor device based upon a silicon carbide (SiC) substrate. More specifically, embodiments of the present method provide for the formation of a gate oxide on a silicon carbide substrate comprising oxidizing the substrate with a gaseous mixture comprising oxygen at a temperature of at least about 1300° C. Semiconductor devices, such as MOSFETS, based upon a substrate treated according to the present method are expected to have inversion layer mobilities of at least about 12 cm | 04-15-2010 |
20100090228 | BORON ALUMINUM NITRIDE DIAMOND HETEROSTRUCTURE - A heterostructure having a heterojunction comprising: a diamond layer; and a boron aluminum nitride (B | 04-15-2010 |
20100102331 | OHMIC ELECTRODE FOR SIC SEMICONDUCTOR, METHOD OF MANUFACTURING OHMIC ELECTRODE FOR SIC SEMICONDUCTOR, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An ohmic electrode for SiC semiconductor that contains Si and Ni or an ohmic electrode for SiC semiconductor that further contains Au or Pt in addition to Si and Ni is provided. In addition, a method of manufacturing the ohmic electrode for SiC semiconductor, a semiconductor device including the ohmic electrode for SiC semiconductor, and a method of manufacturing the semiconductor device are provided. | 04-29-2010 |
20100102332 | METHOD OF FORMING AN OHMIC CONTACT ON A P-TYPE 4H-SIC SUBSTRATE - A method of forming an Ohmic contact on a P-type 4H—SiC and an Ohmic contact formed by the same are provided. A method of forming an Ohmic contact on a P-type 4H—SiC substrate including a deposition step of successively depositing a 1 to 60 nm thick first Al layer, Ti layer, and second Al layer on a P-type 4H—SiC substrate and an alloying step of forming an alloy layer between the SiC substrate and the Ti layer through the first Al layer by heat treatment in a nonoxidizing atmosphere. An Ohmic contact on a P-type 4H—SiC substrate formed by this method is also provided. | 04-29-2010 |
20100117097 | SILICON CARBIDE SEMICONDUCTOR DEVICE - The present invention relates to a semiconductor device ( | 05-13-2010 |
20100117098 | SCHOTTKY ELECTRODE FOR DIAMOND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a Schottky electrode in a diamond semiconductor, which has a good adhesion properties to diamonds, has a contacting surface which does not become peeled due to an irregularity in an external mechanical pressure, does not cause a reduction in yield in a diode forming process and does not cause deterioration in current-voltage characteristics, and a method of manufacturing the Schottky electrode. | 05-13-2010 |
20100123140 | SiC SUBSTRATES, SEMICONDUCTOR DEVICES BASED UPON THE SAME AND METHODS FOR THEIR MANUFACTURE - The present invention generally relates to a method for improving inversion layer mobility and providing low defect density in a semiconductor device based upon a silicon carbide (SiC) substrate. More specifically, the present invention provides a method for the manufacture of a semiconductor device based upon a silicon carbide substrate and comprising an oxide layer comprising incorporating at least one additive into the atomic structure of the oxide layer. Semiconductor devices, such as MOSFETS, based upon a substrate treated according to the present method are expected to have inversion layer mobilities of at least about 60 cm | 05-20-2010 |
20100127277 | SEMICONDUCTOR MODULE - A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced. | 05-27-2010 |
20100127278 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot α+cot β) (where α and β are variables that satisfy the relations 0.5≦α,β,≦45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property. | 05-27-2010 |
20100133549 | Semiconductor Devices with Current Shifting Regions and Related Methods - A semiconductor device may include a semiconductor buffer layer having a first conductivity type and a semiconductor mesa having the first conductivity type on a surface of the buffer layer. In addition, a current shifting region having a second conductivity type may be provided adjacent a corner between the semiconductor mesa and the semiconductor buffer layer, and the first and second conductivity types may be different conductivity types. Related methods are also discussed. | 06-03-2010 |
20100133550 | STABLE POWER DEVICES ON LOW-ANGLE OFF-CUT SILICON CARBIDE CRYSTALS - A silicon carbide-based power device includes a silicon carbide drift layer having a planar surface that forms an off-axis angle with a < | 06-03-2010 |
20100140628 | Insulated gate bipolar transistors including current suppressing layers - An insulated gate bipolar transistor (IGBT) includes a first conductivity type substrate and a second conductivity type drift layer on the substrate. The second conductivity type is opposite the first conductivity type. The IGBT further includes a current suppressing layer on the drift layer. The current suppressing layer has the second conductivity type and has a doping concentration that is larger than a doping concentration of the drift layer. A first conductivity type well region is in the current suppressing layer. The well region has a junction depth that is less than a thickness of the current suppressing layer, and the current suppressing layer extends laterally beneath the well region. A second conductivity type emitter region is in the well region. | 06-10-2010 |
20100148186 | VERTICAL JUNCTION FIELD EFFECT TRANSISTORS HAVING SLOPED SIDEWALLS AND METHODS OF MAKING - Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation. | 06-17-2010 |
20100148187 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a transistor including a gate electrode formed on a semiconductor substrate of a predetermined crystal via a gate insulating film and a source-drain region formed in the semiconductor substrate so as to have a convex portion in a direction of a gate width and in which an epitaxial crystal having a lattice constant different from that of the predetermined crystal is embedded, and a contact plug formed on the source-drain region other than the convex portion. | 06-17-2010 |
20100155742 | LIGHT-EMITTING DIODE AND LIGHT-EMITTING DIODE LAMP - The present invention provides a light-emitting diode ( | 06-24-2010 |
20100155743 | SiC SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACTS, INTEGRATED CIRCUIT AND MANUFACTURING METHOD - One aspect includes a semiconductor device with self-aligned contacts, integrated circuit and manufacturing method. One embodiment provides gate control structures. Each of the gate control structures is configured to control the conductivity of a channel region within a silicon carbide substrate by field effect. A contact hole is self-aligned to opposing sidewalls of adjacent gate control structures by intermediate spacers. | 06-24-2010 |
20100176403 | SILICON CARBIDE SUBSTRATE, EPITAXIAL WAFER AND MANUFACTURING METHOD OF SILICON CARBIDE SUBSTRATE - An SiC substrate includes the steps of preparing a base substrate having a main surface and made of SiC, washing the main surface using a first alkaline solution, and washing the main surface using a second alkaline solution after the step of washing with the first alkaline solution. The SiC substrate has the main surface, and an average of residues on the main surface are equal to or larger than 0.2 and smaller than 200 in number. | 07-15-2010 |
20100187543 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND THE SILICON CARBIDE SEMICONDUCTOR DEVICE - Silicon carbide semiconductor device includes trench, in which connecting trench section is connected to straight trench section. Straight trench section includes first straight trench and second straight trench extending in parallel to each other. Connecting trench section includes first connecting trench perpendicular to straight trench section, second connecting trench that connects first straight trench and first connecting trench to each other, and third connecting trench that connects second straight trench and first connecting trench to each other. Second connecting trench extends at 30 degrees of angle with the extension of first straight trench. Third connecting trench extends at 30 degrees of angle with the extension of second straight trench. A manufacturing method according to the invention for manufacturing a silicon carbide semiconductor device facilitates preventing defects from being causes in a silicon carbide semiconductor device during the manufacture thereof. | 07-29-2010 |
20100187544 | FABRICATING A GALLIUM NITRIDE LAYER WITH DIAMOND LAYERS - In one aspect, a method includes fabricating a gallium nitride (GaN) layer with a first diamond layer having a first thermal conductivity and a second diamond layer having a second thermal conductivity greater than the first thermal conductivity. The fabricating includes using a microwave plasma chemical vapor deposition (CVD) process to deposit the second diamond layer onto the first diamond layer. | 07-29-2010 |
20100193799 | Semiconductor device and method of manufacturing semiconductor device - The semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type made of SiC having an Si surface; a gate trench dug down from the surface of the semiconductor layer; a gate insulating film formed on a bottom surface and a side surface of the gate trench so that the ratio of the thickness of a portion located on the bottom surface to the thickness of a portion located on the side surface is 0.3 to 1.0; and a gate electrode embedded in the gate trench through the gate insulating film. | 08-05-2010 |
20100193800 | SEMICONDUCTOR DEVICE - A semiconductor device is fabricated on an off-cut semiconductor substrate | 08-05-2010 |
20100193801 | SOLDER MATERIAL, METHOD FOR MANUFACTURING THE SAME, JOINED BODY, METHOD FOR MANUFACTURING THE SAME, POWER SEMICONDUCTOR MODULE, AND METHOD FOR MANUFACTURING THE SAME - A zinc based solder material | 08-05-2010 |
20100200866 | SiC single crystal substrate, SiC single crystal epitaxial wafer, and SiC semiconductor device - A direction of a dislocation line of a threading dislocation is aligned, and an angle between the direction of the dislocation line of the threading dislocation and a [0001]-orientation c-axis is equal to or smaller than 22.5 degrees. The threading dislocation having the dislocation line along with the [0001]-orientation c-axis is perpendicular to a direction of a dislocation line of a basal plane dislocation. Accordingly, the dislocation does not provide an extended dislocation on the c-face, so that a stacking fault is not generated. Thus, when an electric device is formed in a SiC single crystal substrate having the direction of the dislocation line of the threading dislocation, which is the [0001]-orientation c-axis, a SiC semiconductor device is obtained such that device characteristics are excellent without deterioration, and a manufacturing yield ration is improved. | 08-12-2010 |
20100207125 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present invention includes: a silicon carbide substrate ( | 08-19-2010 |
20100207126 | MOS-Driver Compatible JFET Structure with Enhanced Gate Source Characteristics - A MOSFET driver compatible JFET device is disclosed. The JFET device can include a gate contact, a drain contact, and a source contact. The JFET device can further include a first gate region of semiconductor material adjacent the gate contact and a second region of semiconductor material adjacent the first gate region. The first gate region and the second gate region can form a first p-n junction between the first gate region and the second gate region. The JFET device can further include a channel region of semiconductor material adjacent the source contact. The channel region and the second gate region can form a second p-n junction between the second gate region and the channel region. | 08-19-2010 |
20100213469 | ILLUMINATION DEVICE - An illumination device having a plurality of light emitting diodes is provided. The light emitting diode may include a plurality of semiconductor layers at least one of which has a light emitting surface which may include a rough surface pattern having a pre-determined pattern. The pre-determined pattern may include one or more impurity regions with each region having a recess for guiding current across the light emitting surface and maximizing the emission of light (i.e. light intensity) of the illumination device. Each recess may include a lower internal portion having a bottom contact point located on a bottom surface and an upper internal portion integrally connected to the lower internal portion by a plurality of center contact points. The gaps created between the center and bottom contact points in adjacent recesses may act as spark gaps allowing for the current to flow through the entire light emitting surface. | 08-26-2010 |
20100213470 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - At least part of a semiconductor layer or a semiconductor substrate includes a semiconductor region having a large energy gap. The semiconductor region having a large energy gap is preferably formed from silicon carbide and is provided in a position at least overlapping with a gate electrode provided with an insulating layer between the semiconductor region and the gate electrode. By making a structure in which the semiconductor region is included in a channel formation region, a dielectric breakdown voltage is improved. | 08-26-2010 |
20100219417 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device and a method of manufacturing the same, to appropriately determine an impurity concentration distribution of a field relieving region and reduce an ON-resistance. The semiconductor device includes a substrate, a first drift layer, a second drift layer, a first well region, a second well region, a current control region, and a field relieving region. The first well region is disposed continuously from an end portion adjacent to the vicinity of outer peripheral portion of the second drift layer to a portion of the first drift layer below the vicinity of outer peripheral portion. The field relieving region is so disposed in the first drift layer as to be adjacent to the first well region. | 09-02-2010 |
20100219418 | DIAMOND LED DEVICES AND ASSOCIATED METHODS - LED devices incorporating diamond materials and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode. | 09-02-2010 |
20100224884 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A channel layer ( | 09-09-2010 |
20100224885 | SEMICONDUCTOR DEVICE - A semiconductor device having a junction FET having improved characteristics is provided. The semiconductor device has a junction FET as a main transistor and has a MISFET as a transistor for control. The junction FET has a first gate electrode, a first source electrode, and a first drain electrode. The MISFET has a second gate electrode, a second source electrode, and a second drain electrode. The MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET. The second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting. The first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting. | 09-09-2010 |
20100224886 | P-CHANNEL SILICON CARBIDE MOSFET - A second trench in each source electrode portion (Schottky diode portion) is formed to have a depth equal to or larger than the depth of a first trench in each gate electrode portion. The distance between the first and second trenches is set to be not longer than 10 μm. A source electrode is formed in the second trench and a Schottky junction is formed in the bottom portion of the second trench. In this manner, it is possible to provide a wide band gap semiconductor device which is small-sized, which has low on-resistance and low loss characteristic, in which electric field concentration into a gate insulating film is relaxed to suppress reduction of a withstand voltage, and which has high avalanche breakdown tolerance at turn-off time. | 09-09-2010 |
20100237356 | BIDIRECTIONAL SILICON CARBIDE TRANSIENT VOLTAGE SUPPRESSION DEVICES - An electronic device includes a silicon carbide layer having a first conductivity type and having a first surface and a second surface opposite the first surface, and first and second silicon carbide Zener diodes on the silicon carbide layer. Each of the first and second silicon carbide Zener diodes may include a first heavily doped silicon carbide region having a second conductivity type opposite the first conductivity type on the silicon carbide layer, and an ohmic contact on the first heavily doped silicon carbide region. | 09-23-2010 |
20100244047 | Methods of Forming Semiconductor Devices Including Epitaxial Layers and Related Structures - A method of forming a semiconductor device may include forming a terminal region of a first conductivity type within a semiconductor layer of the first conductivity type. A well region of a second conductivity type may be formed within the semiconductor layer wherein the well region is adjacent at least portions of the terminal region within the semiconductor layer, a depth of the well region into the semiconductor layer may be greater than a depth of the terminal region into the semiconductor layer, and the first and second conductivity types may be different. An epitaxial semiconductor layer may be formed on the semiconductor layer, and a terminal contact region of the first conductivity type may be formed in the epitaxial semiconductor layer with the terminal contact region providing electrical contact with the terminal region. In addition, an ohmic contact may be formed on the terminal contact region. Related structures are also discussed. | 09-30-2010 |
20100244048 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present invention comprises a silicon carbide semiconductor substrate ( | 09-30-2010 |
20100244049 | Silicon carbide semiconductor device with schottky barrier diode and method of manufacturing the same - A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements. | 09-30-2010 |
20100244050 | SEMICONDUCTOR DEVICE - A semiconductor device which is capable of operating at an operation frequency “f”, includes a substrate, a first element unit and a second element unit. The substrate has a thermal diffusion coefficient “D”. The first element unit is formed on the substrate. The first element includes a first active element. The second element unit is adjacent to the first element unit on the substrate. The second element includes a second active element. The second active element acts on a different timing from the first active element. Moreover, a distance of between a first gravity center of the first element unit and a second gravity center of the second element unit is equal to or less than twice of a thermal diffusion length (D/πf) | 09-30-2010 |
20100244051 | Semiconductor Device and Manufacturing Method Thereof - An object is to realize an integrated circuit included in a semiconductor device which has multiple functions, or to increase the size of an integrated circuit even when the integrated circuit is formed using a silicon carbide substrate. The integrated circuit includes a first transistor including an island-shaped silicon carbide layer provided over a substrate with a first insulating layer interposed therebetween, a first gate insulating layer provided over the silicon carbide layer, and a first conductive layer provided over the first gate insulating layer and overlapped with the silicon carbide layer; and a second transistor including an island-shaped single crystal silicon layer provided over the substrate with a second insulating layer interposed therebetween, a second gate insulating layer provided over the single crystal silicon layer, and a second conductive layer provided over the second gate insulating layer and overlapped with the single crystal silicon layer. | 09-30-2010 |
20100244052 | HIGH OUTPUT GROUP III NITRIDE LIGHT EMITTING DIODES - A light emitting diode is disclosed that includes a silicon carbide substrate and a light emitting structure formed from the Group III nitride material system on the substrate. The diode has an area greater than 100,000 square microns and has a radiant flux at 20 milliamps current of at least 29 milliwatts at its dominant wavelength between 390 and 540 nanometers. | 09-30-2010 |
20100252837 | METHOD FOR PRODUCING SINGLE CRYSTAL SiC SUBSTRATE AND SINGLE CRYSTAL SiC SUBSTRATE PRODUCED BY THE SAME - A single crystal SiC substrate is produced with low cost in which a polycrystalline SiC substrate with relatively low cost is used as a base material substrate where the single crystal SiC substrate has less strain, good crystallinity and large size. The method including a P-type ion introduction step for implanting P-type ions from a side of a surface Si layer | 10-07-2010 |
20100252838 | Semiconductor device and method of manufacturing the same - A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten. | 10-07-2010 |
20100258815 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An objective is to provide a manufacturing method of a silicon carbide semiconductor device in which an electric field applied to a gate oxide film can be relaxed and thereby reliability can be ensured, and by the manufacturing method increase of the manufacturing cost can also be prevented as much as possible. Well regions, channel regions, and gate electrodes are formed so that, given that extending lengths, with respect to the inner sides of source regions, of each of the well regions, the channel regions, and the gate electrodes are Lwell, Lch, and Lg, respectively, a relationship of Lch10-14-2010 | |
20100258816 | Silicon carbide semiconductor device and manufacturing method therefor - With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle θ of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 μm/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate. | 10-14-2010 |
20100258817 | Silicon carbide semiconductor device and manufacturing method therefor - With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle θ of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 μm/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate. | 10-14-2010 |
20100264426 | DIAMOND CAPACITOR BATTERY - In one embodiment, a charge storage device can include: a first node having a plurality of n-type diamond layers connected together; and a second node having a plurality of p-type diamond layers connected together, the plurality of p-type diamond layers being interleaved with the plurality of n-type diamond layers, where each of the plurality of diamond layers is formed using chemical vapor deposition (CVD). | 10-21-2010 |
20100264427 | Bipolar Junction Transistor Guard Ring Structures and Method of Fabricating Thereof - Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer. | 10-21-2010 |
20100270561 | Method for manufacturing a cubic silicon carbide single crystal thin film and semiconductor device based on the cubic silicon carbide single crystal thin film - A cubic silicon carbide single crystal thin film is manufactured by a method. A sacrificial layer is formed on a surface of a substrate. A cubic semiconductor layer is formed on the sacrificial layer, the cubic semiconductor layer having at least a surface of cubic crystal structure. A cubic silicon carbide single crystal layer is formed on the cubic semiconductor layer. The sacrificial layer is etched away to release a multilayer structure of the cubic semiconductor layer and the 3C—SiC layer from the substrate. A cubic silicon carbide single crystal thin film of a multilayer structure includes an Al | 10-28-2010 |
20100270562 | Semiconductor wafer, semiconductor thin film, and method for manufacturing semiconductor thin film devices - A method for manufacturing a semiconductor thin film device includes: forming a buffer layer on an Si (111) substrate and a single crystal semiconductor layer on the buffer layer; forming an island including the semiconductor layer, buffer layer, and a portion of the substrate; forming a coating layer on the island; etching the substrate along its Si (111) plane to release the island from the substrate, the coating layer serving as a mask; and bonding the released island to another substrate, a released surface of the released island contacting the another substrate. A semiconductor device includes a single crystal semiconductor layer other than Si, which has a semiconductor device formed on a front surface of an Si (111) layer lying in a (111) plane. The layer is bonded to another substrate with a back surface contacting the another substrate or a bonding layer formed on the another substrate. | 10-28-2010 |
20100276701 | LOW THERMAL RESISTANCE AND ROBUST CHIP-SCALE-PACKAGE (CSP), STRUCTURE AND METHOD - A chip scale package (CSP) semiconductor device can include a semiconductor layer, circuitry on an active surface of the semiconductor layer, and a diamond layer on a back side of the semiconductor layer. The diamond layer can provide an efficient heat sink for the semiconductor layer, with a thermal conductivity which can be more than three times greater than the thermal conductivity of copper. Further, a hardness of the diamond layer (up to about 10 times stronger than silicon) can provide effective protection against damage to the exposed semiconductor layer, for example during manufacturing, handling, and use of the CSP device. Thus a thin protective diamond layer can be used, which can result in a very thin CSP package design. | 11-04-2010 |
20100276702 | Doped Diamond LED Devices and Associated Methods - LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode. | 11-04-2010 |
20100276703 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A MOS type SiC semiconductor device having high reliability and a longer lifespan against TDDB of a gate oxide film is disclosed. The semiconductor device includes a MOS (metal-oxide-semiconductor) structure having a silicon carbide (SiC) substrate, a polycrystalline Si gate electrode, a gate oxide film interposed between the SiC substrate and the polycrystalline Si gate electrode and formed by thermally oxidizing a surface of the SiC substrate, and an ohmic contact electrically contacted with the SiC substrate. The semiconductor device further includes a polycrystalline Si thermally-oxidized film formed by oxidizing a surface of the polycrystalline Si gate electrode. The gate oxide film has a thickness of 20 nm or less, preferably 15 nm or less. | 11-04-2010 |
20100283061 | HIGH TEMPERATURE GATE DRIVERS FOR WIDE BANDGAP SEMICONDUCTOR POWER JFETS AND INTEGRATED CIRCUITS INCLUDING THE SAME - Gate drivers for wide bandgap (e.g., >2 eV) semiconductor junction field effect transistors (JFETs) capable of operating in high ambient temperature environments are described. The wide bandgap (WBG) semiconductor devices include silicon carbide (SiC) and gallium nitride (GaN) devices. The driver can be a non-inverting gate driver which has an input, an output, a first reference line for receiving a first supply voltage, a second reference line for receiving a second supply voltage, a ground terminal, and six Junction Field-Effect Transistors (JFETs) wherein the first JFET and the second JFET form a first inverting buffer, the third JFET and the fourth JFET form a second inverting buffer, and the fifth JFET and the sixth JFET form a totem pole which can be used to drive a high temperature power SiC JFET. An inverting gate driver is also described. | 11-11-2010 |
20100289030 | DIAMOND SEMICONDUCTOR ELEMENT AND PROCESS FOR PRODUCING THE SAME - In a conventional diamond semiconductor element, because of high density of crystal defects, it is impossible to reflect the natural physical properties peculiar to a diamond, such as high thermal conductivity, high breakdown field strength, high-frequency characteristics and the like, in the transistor characteristics. By slightly shifting surface orientation of a diamond substrate in a [001] direction, a significant reduction in crystal defects peculiar to a diamond is possible. The equivalent effects are also provided by shifting surface orientation of a single-crystal diamond thin-film or channel slightly from a [001] direction. It is possible to obtain a significantly high transconductance gm as compared with that in a transistor produced using conventional surface orientation. | 11-18-2010 |
20100289031 | DIAMOND SEMICONDUCTOR DEVICE - The diamond semiconductor device is a diamond semiconductor device where a pair of electrodes are fixed on a diamond substrate, and wherein at least one interface to the electrode on the surface of the diamond substrate has a hydrogen termination and at least the surface of the substrate between the pair of two electrodes is controlled to have a larger electric resistivity value than inside the substrate. Accordingly, a diamond semiconductor device can be realized, capable of attaining the device work stability, especially the device work stability in severe environments such as high temperature with exhibiting the function of the hydrogen termination thereof to the utmost extent. | 11-18-2010 |
20100289032 | DIFFUSED JUNCTION TERMINATION STRUCTURES FOR SILICON CARBIDE DEVICES AND METHODS OF FABRICATING SILICON CARBIDE DEVICES INCORPORATING SAME - An electronic device includes a silicon carbide layer having a first conductivity type and a main junction adjacent a surface of the silicon carbide layer, and a junction termination region at the surface of the silicon carbide layer adjacent the main junction. Charge in the junction termination region decreases with lateral distance from the main junction, and a maximum charge in the junction termination region may be less than about 2×10 | 11-18-2010 |
20100289033 | SINGLE-CRYSTAL SILICON CARBIDE INGOT, AND SUBSTRATE AND EPITAXIAL WAFER OBTAINED THEREFROM - The present invention provides a single-crystal silicon carbide ingot capable of providing a good-quality substrate low in dislocation defects, and a substrate and epitaxial wafer obtained therefrom. | 11-18-2010 |
20100295058 | TUNNELING FIELD EFFECT TRANSISTOR SWITCH DEVICE - A tunneling field effect transistor (TFET) device includes a semiconductor substrate having a layer of relatively intermediate bandgap semiconductor material, a layer of relatively low bandgap semiconductor material overlying the layer of relatively intermediate bandgap semiconductor material, and a layer of relatively high bandgap semiconductor material overlying the layer of relatively low bandgap semiconductor material. The TFET device includes a source region, a drain region, and a channel region defined in the semiconductor substrate. The TFET device also has a gate structure overlying at least a portion of the channel region. The source region is highly doped with an impurity dopant having a first conductivity type, and the drain region is highly doped with an impurity dopant having a second conductivity type. The layer of relatively low bandgap semiconductor material promotes tunneling at a first junction between the source region and the channel region, and the layer of relatively high bandgap semiconductor material inhibits tunneling at a second junction between the source region and the channel region. | 11-25-2010 |
20100295059 | SIC SINGLE-CRYSTAL SUBSTRATE AND METHOD OF PRODUCING SIC SINGLE-CRYSTAL SUBSTRATE - The invention provides a high-quality SiC single-crystal substrate, a seed crystal for producing the high-quality SiC single-crystal substrate, and a method of producing the high-quality SiC single-crystal substrate, which enable improvement of device yield and stability. Provided is an SiC single-crystal substrate wherein, when the SiC single-crystal substrate is divided into 5-mm square regions, such regions in which dislocation pairs or dislocation rows having intervals between their dislocation end positions of 5 μm or less are present among the dislocations that have ends at the substrate surface account for 50% or less of all such regions within the substrate surface and the dislocation density in the substrate of dislocations other than the dislocation pairs or dislocation is 8,000/cm | 11-25-2010 |
20100295060 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device | 11-25-2010 |
20100295061 | RECRYSTALLIZATION OF SEMICONDUCTOR WATERS IN A THIN FILM CAPSULE AND RELATED PROCESSES - An original wafer, typically silicon, has the form of a desired end PV wafer. The original may be made by rapid solidification or CVD. It has small grains. It is encapsulated in a clean thin film, which contains and protects the silicon when recrystallized to create a larger grain structure. The capsule can be made by heating a wafer in the presence of oxygen, or steam, resulting in silicon dioxide on the outer surface, typically 1-2 microns. Further heating creates a molten zone in space, through which the wafer travels, resulting in recrystallization with a larger grain size. The capsule contains the molten material during recrystallization, and protects against impurities. Recrystallization may be in air. Thermal transfer through backing plates minimizes stresses and defects. After recrystallization, the capsule is removed. | 11-25-2010 |
20100295062 | SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes: a semiconductor layer including silicon carbide, which has been formed on a substrate; a semiconductor region | 11-25-2010 |
20100301350 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Recesses are formed in a pMOS region | 12-02-2010 |
20100301351 | HIGH VOLTAGE SWITCHING DEVICES AND PROCESS FOR FORMING SAME - The present invention relates to various switching device structures including Schottky diode, P—N diode, and P—I—N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm | 12-02-2010 |
20100308340 | SEMICONDUCTOR DEVICE HAVING A BURIED CHANNEL - Provided is a device that includes a semiconductor body having a surface. Source and drain regions with effective dopant populations of a first polarity can be disposed adjacent to the surface and spaced apart from one another. A channel region with an effective dopant population of the first polarity can extend between the source and drain regions while being spaced apart from the surface. A gate region with an effective dopant population of a second polarity and first effective dopant density can extend between the source and drain regions and be disposed between the channel region and the surface. A gate contact region can be disposed between the source and drain regions and adjacent to the surface. The gate contact region can have an effective dopant population of the second polarity and a second effective dopant density greater than the first effective dopant density. | 12-09-2010 |
20100308341 | SEMICONDUCTOR MEMORY DEVICE - A switching resistance RAM that is highly integrated as well as reduced in a read-out time is realized. There is formed an NPN type bipolar transistor BT composed of a collector layer made of an N-well | 12-09-2010 |
20100308342 | ELECTRICAL SWITCHING DEVICE AND METHOD OF EMBEDDING CATALYTIC MATERIAL IN A DIAMOND SUBSTRATE - An electrical device according to one embodiment includes a substrate including at least one diamond layer; at least one first electrode in contact with said substrate, wherein at least one said first electrode includes at least one electrically conductive protrusion extending into said substrate; and at least one second electrode in contact with said substrate and spaced from the or each said first electrode. | 12-09-2010 |
20100308343 | SILICON CARBIDE SEMICONDUCTOR DEVICE - According to the embodiment, a semiconductor device includes an SiC substrate of a first or second conductivity type. An SiC layer of the first conductivity type is formed on a front surface of the substrate, a first SiC region of the second conductivity type is formed on the SiC layer, a second SiC region of the first conductivity type is formed within a surface of the first SiC region, a gate dielectric is continuously formed on the SiC layer, the second SiC region, and the surface of the first SiC region interposed between the SiC layer and the second SiC region, a gate electrode is formed on the gate dielectric, a first electrode is embedded in a trench selectively formed in a part where the first SiC region adjoins the second SiC region, and a second electrode is formed on a back surface of the substrate. | 12-09-2010 |
20100308344 | METHOD FOR GROWING P-TYPE SIC SEMICONDUCTOR SINGLE CRYSTAL AND P-TYPE SIC SEMICONDUCTOR SINGLE CRYSTAL - In a method for growing a p-type SiC semiconductor single crystal on a SiC single crystal substrate, using a first solution in which C is dissolved in a melt of Si, a second solution is prepared by adding Al and N to the first solution such that an amount of Al added is larger than that of N added, and the p-type SiC semiconductor single crystal is grown on the SiC single crystal substrate from the second solution. A p-type SiC semiconductor single crystal is provided which is grown by the method as described above, and which contains 1×10 | 12-09-2010 |
20100314626 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A silicon carbide semiconductor device having excellent performance characteristics and a method of manufacturing the same are obtained. An extended terrace surface is formed at a surface of an initial growth layer on a 4H—SiC substrate by annealing with the initial growth layer covered with an Si film, and then a new growth layer is epitaxially grown on the initial growth layer. A 3C—SiC portion having a polytype stable at a low temperature is grown on the extended terrace surface, and a 4H—SiC portion is grown on the other region. A trench is formed by selectively removing the 3C—SiC portion with the 4H—SiC portion remaining, and a gate electrode of a UMOSFET is formed in the trench. A channel region of the UMOSFET can be controlled to have a low-order surface, and a silicon carbide semiconductor device having high channel mobility and excellent performance characteristics is obtained. | 12-16-2010 |
20100314627 | DIAMOND GaN DEVICES AND ASSOCIATED METHODS - Semiconductor devices and methods of making thereof are provided. In one aspect, for example, a method for making a semiconductor device can include polishing a working surface of a diamond layer to a substantially flat surface, depositing a buffer layer on the working surface of the diamond layer, and depositing a semiconductor layer on the buffer layer. In one specific aspect, the c-axis of the buffer layer is oriented perpendicular to the working surface of the diamond layer. | 12-16-2010 |
20100314628 | PROCESS FOR TRANSFERRING A LAYER OF STRAINED SEMICONDUCTOR MATERIAL - Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer. | 12-16-2010 |
20100314629 | SILICON CARBIDE SEMICONDUCTOR DEVICE - In order to obtain a silicon carbide semiconductor device that ensures both stability of withstand voltage and reliability in high-temperature operations in its termination end-portion provided for electric-field relaxation in the perimeter of a cell portion driven as a semiconductor element, the termination end-portion is provided with an inorganic protection film having high heat resistance that is formed on an exposed surface of a well region as a first region formed on a side of the cell portion, and an organic protection film having a high electrical insulation capability with a little influence by electric charges that is formed on a surface of an electric-field relaxation region formed in contact relation to an outer lateral surface of the well region and apart from the cell portion, and on an exposed surface of the silicon carbide layer. | 12-16-2010 |
20100320476 | VERTICAL JUNCTION FIELD EFFECT TRANSISTORS AND DIODES HAVING GRADED DOPED REGIONS AND METHODS OF MAKING - Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications. | 12-23-2010 |
20100320477 | PROCESS FOR PRODUCING SILICON CARBIDE CRYSTALS HAVING INCREASED MINORITY CARRIER LIFETIMES - A process is described for producing silicon carbide crystals having increased minority carrier lifetimes. The process includes the steps of heating and slowly cooling a silicon carbide crystal having a first concentration of minority carrier recombination centers such that the resultant concentration of minority carrier recombination centers is lower than the first concentration. | 12-23-2010 |
20110001143 | Composition Comprising Silicon Carbide - A method of depositing a ceramic film, particularly a silicon carbide film, on a substrate is disclosed in which the residual stress, residual stress gradient, and resistivity are controlled. Also disclosed are substrates having a deposited film with these controlled properties and devices, particularly MEMS and NEMS devices, having substrates with films having these properties. | 01-06-2011 |
20110001144 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w | 01-06-2011 |
20110006309 | EPITAXIAL SiC SINGLE CRYSTAL SUBSTRATE AND METHOD OF MANUFACTURE OF EXPITAXIAL SiC SINGLE CRYSTAL SUBSTRATE - An epitaxial SiC single crystal substrate including a SiC single crystal wafer whose main surface is a c-plane or a surface that inclines a c-plane with an angle of inclination that is more than 0 degree but less than 10 degrees, and SiC epitaxial film that is formed on the main surface of the SiC single crystal wafer, wherein the dislocation array density of threading edge dislocation arrays that are formed in the SiC epitaxial film is 10 arrays/cm | 01-13-2011 |
20110006310 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device comprises a semiconductor substrate made of silicon carbide, a gate insulating film formed on the semiconductor substrate, and a gate electrode formed on the gate insulating film. The junction surface of the semiconductor surface joined with the gate insulating film is macroscopically parallel to a nonpolar face and microscopically comprised of the nonpolar face and a polar face. In the polar face, either a Si face or a C face is dominant. A semiconductor device comprises a semiconductor substrate comprised of silicon carbide and a gate electrode formed on the semiconductor substrate. The junction surface of the semiconductor surface joined with the electrode is macroscopically parallel to a nonpolar face and microscopically comprised of the nonpolar face and a polar face. In the polar face, either a Si face or a C face is dominant. The present invention is a semiconductor device having a silicon carbide substrate, and the electrical characteristics and the stability of the interface between the electrode and the silicon carbide or between the oxide film (insulating film) and the silicon carbide in the nonpolar face of a silicon carbide epitaxial layer can be improved. | 01-13-2011 |
20110012129 | High-Gain Wide Bandgap Darlington Transistors and Related Methods of Fabrication - A packaged power electronic device includes a wide bandgap bipolar driver transistor having a base, a collector, and an emitter terminal, and a wide bandgap bipolar output transistor having a base, a collector, and an emitter terminal. The collector terminal of the output transistor is coupled to the collector terminal of the driver transistor, and the base terminal of the output transistor is coupled to the emitter terminal of the driver transistor to provide a Darlington pair. An area of the output transistor is at least 3 times greater than an area of the driver transistor in plan view. For example, an area ratio of the output transistor to the driver transistor may be between about 3:1 to about 5:1. Related devices and methods of fabrication are also discussed. | 01-20-2011 |
20110012130 | High Breakdown Voltage Wide Band-Gap MOS-Gated Bipolar Junction Transistors with Avalanche Capability - High power wide band-gap MOSFET-gated bipolar junction transistors (“MGT”) are provided that include a first wide band-gap bipolar junction transistor (“BJT”) having a first collector, a first emitter and a first base, a wide band-gap MOSFET having a source region that is configured to provide a current to the base of the first wide band-gap BJT and a second wide band-gap BJT having a second collector that is electrically connected to the first collector, a second emitter that is electrically connected to the first emitter, and a second base that is electrically connected to the first base. | 01-20-2011 |
20110012131 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE - An object is to provide a novel manufacturing method of a semiconductor substrate containing silicon carbide, and another object is to provide a semiconductor device using silicon carbide. A semiconductor substrate is manufactured through the steps of: adding ions to a silicon carbide substrate to form an embrittlement region in the silicon carbide substrate; bonding the silicon carbide substrate to a base substrate with insulating layers interposed therebetween; heating the silicon carbide substrate and separating the silicon carbide substrate at the embrittlement region to form a silicon carbide layer over the base substrate with the insulating layers interposed between therebetween; and performing heat treatment on the silicon carbide layer at a temperature of 1000° C. to 1300° C. to reduce defects of the silicon carbide layer. A semiconductor device is manufactured using the semiconductor substrate formed as described above. | 01-20-2011 |
20110012132 | Semiconductor Device - Provided is a semiconductor device which has improved withstand voltage and can be manufactured by simpler manufacturing process. The semiconductor device according to the present invention includes: a SiC-containing n-type epitaxial layer | 01-20-2011 |
20110012133 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A silicon carbide MOSFET that exhibits a high source-to-drain withstand voltage and that involves a smaller difference between gate-to-drain capacitance achieved in an activated state and gate-to-drain capacitance achieved in a deactivated state. A silicon carbide drift layer of a first conductivity type is provided on a silicon carbide substrate of a first conductivity type; a pair of base regions are provided in a surface layer portion of the silicon carbide drift layer and exhibit a second conductivity type; a pair of source regions are provided in interiors of surface layer portions of the pair of base regions and exhibit a first conductivity type; and semi-insulating regions are provided between the silicon carbide substrate and the pair of base regions. | 01-20-2011 |
20110018004 | SEMICONDUCTOR DEVICE WITH LARGE BLOCKING VOLTAGE AND MANUFACTURING METHOD THEREOF - There is no effective method for fabricating a semiconductor power device containing UMOSFET possessing large channel mobility and whose threshold voltage can be lowered with no loss in blocking voltage. A semiconductor device with large blocking voltage is provided utilizing silicon carbide trench MOSFET possessing both narrow regions where the p body concentration is low, and wide regions where the p body concentration is high. | 01-27-2011 |
20110018005 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device of the present invention includes a semiconductor layer composed of SiC, a metal layer directly bonded to one face of the semiconductor layer, and a high carbon concentration layer formed on a surface layer portion at one side of the semiconductor layer and containing more highly concentrated carbon than a surface layer portion of the other side. Further, a manufacturing method of a semiconductor device of the present invention includes the steps of forming, on a surface layer portion at one face side of a semiconductor layer composed of SiC, a high carbon concentration layer containing more highly concentrated carbon than a surface layer portion at the other face side by heat treatment and directly bonding metal to the high carbon concentration layer. | 01-27-2011 |
20110024765 | SILICON CARBIDE SEMICONDUCTOR STRUCTURES, DEVICES AND METHODS FOR MAKING THE SAME - There are provided semiconductor structures and devices comprising silicon carbide (SiC) and methods for making the same. The structures and devices comprise a base or shielding layer, channel and surface layer, all desirably formed via ion implantation. As a result, the structures and devices provided herein are hard, “normally off” devices, i.e., exhibiting threshold voltages of greater than about 3 volts. | 02-03-2011 |
20110024766 | ONE HUNDRED MILLIMETER SINGLE CRYSTAL SILICON CARBIDE WAFER - A method is disclosed for producing a high quality bulk single crystal of silicon carbide in a seeded growth system by reducing the separation between a silicon carbide seed crystal and a seed holder until the conductive heat transfer between the seed crystal and the seed holder dominates the radiative heat transfer between the seed crystal and the seed holder over substantially the entire seed crystal surface that is adjacent the seed holder. | 02-03-2011 |
20110024767 | Semiconductor Substrates, Devices and Associated Methods - Semiconductor substrates and devices having improved performance and cooling, as well as associated methods, are provided. In one aspect, for example, a semiconductor device can include a matrix layer and a plurality of single crystal semiconductor tiles disposed in the matrix layer. The plurality of semiconductor tiles are positioned such that an exposed surface of each of substantially all of the plurality of diamond tiles aligns along a common plane to form a substrate surface. In one aspect, a semiconductor layer is disposed on the substrate surface. In another aspect, the semiconductor layer is a doped diamond layer. In yet another aspect, the semiconductor tiles are doped. In a further aspect, the exposed surface of each of the plurality of semiconductor tiles has a common crystallographic orientation. | 02-03-2011 |
20110024768 | SiC AVALANCHE PHOTODIODE WITH IMPROVED EDGE TERMINATION - An avalanche photodiode semiconductor device ( | 02-03-2011 |
20110024769 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot α+cot β) (where α and β are variables that satisfy the relations 0.5≦α, β≦45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property. | 02-03-2011 |
20110031502 | LIGHT EMITTING DIODES INCLUDING INTEGRATED BACKSIDE REFLECTOR AND DIE ATTACH - Light emitting diodes include a silicon carbide substrate having first and second opposing faces, a diode region on the first face, anode and cathode contacts on the diode region opposite the silicon carbide substrate and a hybrid reflector on the silicon carbide substrate opposite the diode region. The hybrid reflector includes a transparent layer having an index of refraction that is lower than the silicon carbide substrate, and a reflective layer on the transparent layer, opposite the substrate. A die attach layer may be provided on the hybrid reflector, opposite the silicon carbide substrate. A barrier layer may be provided between the hybrid reflector and the die attach layer. | 02-10-2011 |
20110031503 | DEVICE WITH STRESSED CHANNEL - An FET device is disclosed which contains a source and a drain that are each provided with an extension. The source and the drain, and their extensions, are composed of epitaxial materials containing Ge or C. The epitaxial materials and the Si substrate have differing lattice constants, consequently the source and the drain and their extensions are imparting a state of stress onto the channel. For a PFET device the epitaxial material may be SiGe, or Ge, and the channel may be in a compressive state of stress. For an NFET device the epitaxial material may be SiC and the channel may be in a tensile state of stress. A method for fabricating an FET device is also disclosed. One may form a first recession in the Si substrate to a first depth on opposing sides of the gate. The first recession is filled epitaxially with a first epitaxial material. Then, a second recession may be formed in the Si substrate to a second depth, which is greater than the first depth. Next, one may fill the second recession with a second epitaxial material, which is the same kind of material as the first epitaxial material. The epitaxial materials are selected to have a different lattice constant than the Si substrate, and consequently a state of stress is being imparted onto the channel. | 02-10-2011 |
20110031504 | Apparatus and method for increasing thermal conductivity of a substrate - An apparatus and method is disclosed for increasing the thermal conductivity in a substrate of a non-wide bandgap material comprising the steps of directing a thermal energy beam onto the substrate in the presence of a first doping gas for converting a region of the substrate into a wide bandgap material to enhance the thermal conductivity of the substrate for cooling the non-wide bandgap material. In one example, the invention is incorporated into a carbon rich layer formed within the wide bandgap material. In another example, the invention is incorporated into a carbon rich layer formed within the wide bandgap material having basal planes disposed to extend generally outwardly relative to an external surface of the substrate to enhance the cooling of the substrate. | 02-10-2011 |
20110031505 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A silicon carbide semiconductor device having an active layer with reduced defect density which is formed on a substrate made of silicon carbide, and a method of manufacturing the same are provided. A semiconductor device includes a substrate made of silicon carbide and having an off angle of not less than 50° and not more than 65° with respect to a plane orientation; a buffer layer, and an epitaxial layer, a p-type layer and an n | 02-10-2011 |
20110031506 | SEMICONDUCTOR DEVICE - A MOSFET capable of achieving decrease in the number of steps in a manufacturing process and improvement in integration includes an SiC wafer composed of silicon carbide and a source contact electrode arranged in contact with the SiC wafer and containing titanium, aluminum, silicon, and carbon as well as a remaining inevitable impurity. The SiC wafer includes an n | 02-10-2011 |
20110031507 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A MOSFET representing a semiconductor device capable of achieving decrease in the number of steps in a manufacturing process and improvement in integration by including an electrode that can be in contact with any of a p-type SiC region and an n-type SiC region with contact resistance being sufficiently suppressed includes an n | 02-10-2011 |
20110037076 | DIAMOND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention is contemplated for providing a diamond semiconductor device where an impurity-doped diamond semiconductor is buried in a selected area, and a method of manufacturing the same. | 02-17-2011 |
20110042685 | SUBSTRATES AND METHODS OF FABRICATING EPITAXIAL SILICON CARBIDE STRUCTURES WITH SEQUENTIAL EMPHASIS - Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, and methods to form silicon carbide structures, including epitaxial layers, by supplying sources of silicon and carbon with sequential emphasis. In at least some embodiments, a method of forming an epitaxial layer of silicon carbide can include depositing a layer on a substrate in the presence of a silicon source, and purging gaseous materials subsequent to depositing the layer. Further, the method can include converting the layer into a sub-layer of silicon carbide in the presence of a carbon source, and purging other gaseous materials subsequent to converting the layer. The presence of the silicon source can be independent of the presence of the carbon source. In some embodiments, dopants, such as n-type dopants, can be introduced during the formation of the epitaxial layer of silicon carbide. | 02-24-2011 |
20110042686 | SUBSTRATES AND METHODS OF FABRICATING DOPED EPITAXIAL SILICON CARBIDE STRUCTURES WITH SEQUENTIAL EMPHASIS - Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, and methods to form silicon carbide structures, including doped epitaxial layers (e.g., P-doped silicon carbide epitaxial layers), by supplying sources of silicon and carbon with sequential emphasis. In some embodiments, a method of forming an epitaxial layer of silicon carbide can include depositing a layer in the presence of a silicon source, and purging gaseous materials subsequent to depositing the layer. Further, the method can include converting the layer into a sub-layer of silicon carbide in the presence of a carbon source and a dopant, and purging other gaseous materials. In some embodiments, the presence of the silicon source can be independent of the presence of the carbon source and/or the dopant. | 02-24-2011 |
20110042687 | GRAPHENE GROWTH ON A CARBON-CONTAINING SEMICONDUCTOR LAYER - A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm. | 02-24-2011 |
20110049530 | TRANSISTORS WITH A GATE INSULATION LAYER HAVING A CHANNEL DEPLETING INTERFACIAL CHARGE AND RELATED FABRICATION METHODS - A metal-insulator-semiconductor field-effect transistor (MISFET) includes a SiC layer with source and drain regions of a first conductivity type spaced apart therein. A first gate insulation layer is on the SiC layer and has a net charge along an interface with the SiC layer that is the same polarity as majority carriers of the source region. A gate contact is on the first gate insulation layer over a channel region of the SiC layer between the source and drain regions. The net charge along the interface between the first gate insulation layer and the SiC layer may deplete majority carriers from an adjacent portion of the channel region between the source and drain regions in the SiC layer, which may increase the threshold voltage of the MISFET and/or increase the electron mobility therein. | 03-03-2011 |
20110049531 | POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - Provided is a power semiconductor device including: an insulating substrate; a circuit pattern formed on an upper surface of the insulating substrate; a power semiconductor formed on the circuit pattern; a plurality of metal socket electrode terminals formed perpendicularly to the circuit pattern or the power semiconductor so as to be in conduction with external terminals; an integral resin sleeve in which a plurality of sleeve parts are integrated, the plurality of sleeve parts being fitted with the plurality of metal socket electrode terminals from above the plurality of metal socket electrode terminals and having openings at both ends thereof; and a molding resin covering the insulating substrate, the circuit pattern, the power semiconductor, the electrode terminals, and the integral resin sleeve. | 03-03-2011 |
20110049532 | SILICON CARBIDE DUAL-MESA STATIC INDUCTION TRANSISTOR - A dual-mesa static induction transistor (SIT) structure includes a silicon carbide substrate having a layer arrangement formed thereon. Laterally spaced ion implanted gate regions are defined in the layer arrangement. Source regions are defined in the layer arrangement. Each of the source regions can include a channel mesa having a source mesa disposed thereon. The source mesa includes sidewalls relative to a principal plane of the substrate defining a horizontal dimension thereof. The channel mesa includes slanted sidewalls relative to the source mesa and the principal plane of the substrate. Also disclosed is a method of fabricating a dual-mesa SiC transistor device. The method includes implanting ions at a normal relative to a principal plane of the substrate to form gate junctions in upper portions of the substrate and lateral portions of the slanted channel mesas. | 03-03-2011 |
20110049533 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region. | 03-03-2011 |
20110049534 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device and a method of manufacturing the same, a first insulation layer is removed from a cell area of a substrate and a first active pattern is formed on the first area by a laser-induced epitaxial growth (LEG) process. Residuals of the first insulation layer are passively formed into a first device isolation pattern on the first area. The first insulation layer is removed from the second area of the substrate and a semiconductor layer is formed on the second area of the substrate by a SEG process. The semiconductor layer on the second area is patterned into a second active pattern including a recessed portion and a second insulation pattern in the recessed portion is formed into a second device isolation pattern on the second area. Accordingly, grain defects in the LEG process and lattice defects in the SEG process are mitigated or eliminated. | 03-03-2011 |
20110049535 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a first stacked body including a first radiator plate, a first insulating layer, a first conductive layer and a first semiconductor element in this order; a second stacked body including a second radiator plate, a second insulating layer, a second conductive layer and a second semiconductor element in this order and configured to be made of a semiconductor material different from that of the first semiconductor element; and a connecting part configured to electrically connect the first conductive layer and the second conductive layer, wherein the first stacked body and the second stacked body are thermally insulated. | 03-03-2011 |
20110057202 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to the embodiments, a semiconductor device using SiC and having a high breakdown voltage, a low on-resistance, and excellent reliability is provided. The semiconductor device includes a silicon carbide substrate having first and second main surfaces; a first silicon carbide layer of a first conductive type provided on the first main surface of the silicon carbide substrate; first silicon carbide regions of a second conductive type formed on a surface of the first silicon carbide layer; second silicon carbide regions of the first conductive type formed on respective surfaces of the first silicon carbide regions; third silicon carbide regions of the second conductive type formed on the respective surfaces of the first silicon carbide regions; a fourth silicon carbide region of the second conductive type formed between the facing first silicon carbide regions with the first silicon carbide layer therebetween; a gate insulating film formed continuously on surfaces of the first silicon carbide regions, the first silicon carbide layer, and the fourth silicon carbide region; a gate electrode formed on the gate insulating film; an interlayer insulating film which covers the gate electrode; a first electrode which is electrically connected to the second silicon carbide regions and the third silicon carbide regions; and a second electrode formed on the second main surface of the silicon carbide substrate. | 03-10-2011 |
20110062450 | Silicon carbide semiconductor device - A silicon carbide semiconductor device comprising a region of germanium and a region of crystalline or polycrystalline silicon carbide. The germanium region and the silicon carbide region are configured to form a germanium/silicon carbide heterojunction. | 03-17-2011 |
20110068350 | Diamond semiconductor devices and associated methods - Semiconductor devices and methods for making such devices are provided. One such method may include forming a transparent diamond layer having a SiC layer coupled thereto, where the SiC layer has a crystal structure that is substantially epitaxially matched to the transparent diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer, and coupling a diamond substrate to at least one of the plurality of semiconductor layers such that the diamond support is oriented parallel to the transparent diamond layer. In one aspect such a method may further include electrically coupling at least one of a p-type electrode or an n-type electrode to at least one of the plurality of semiconductor layers. | 03-24-2011 |
20110068351 | Method of Forming Three Dimensional Features on Light Emitting Diodes for Improved Light Extraction - A method is disclosed for obtaining a high-resolution lenticular pattern on the surface of a light emitting diode. The method comprises imprinting a patterned sacrificial layer of etchable material that is positioned on a semiconductor surface that is in turn adjacent a light emitting active region, and thereafter etching the imprinted sacrificial layer and the underlying semiconductor to transfer an imprinted pattern into the semiconductor layer adjacent the light emitting active region. | 03-24-2011 |
20110068352 | DIAMOND SEMICONDUCTOR ELEMENT AND PROCESS FOR PRODUCING THE SAME - An integrated optical waveguide has a first optical waveguide, a second optical waveguide, and a groove. The second optical waveguide is coupled to the first optical waveguide and has a refractive index that is different from the first optical waveguide. The groove is disposed so as to traverse an optical path of the first optical waveguide and is separated from an interface between the first optical waveguide and the second optical waveguide by a predetermined spacing. The spacing from the interface and the width of the groove are determined such that reflection at a boundary between the first optical waveguide and the second optical waveguide is weakened. A semiconductor board may be disposed at a boundary between the first optical waveguide and the second optical waveguide. In this case, the width of the groove and the thickness of the semiconductor board are determined such that light reflected off an interface between the first optical waveguide and the groove is weakened by light reflected from an interface between the groove and the semiconductor board, and by light reflected from an interface between the semiconductor board and the second optical waveguide. | 03-24-2011 |
20110068353 | SEMICONDUCTOR DEVICE - A semiconductor device (A | 03-24-2011 |
20110073872 | HIGH BRIGHTNESS LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A high brightness light emitting diode includes a carrier substrate and an epitaxial multi-layer formed thereon. The carrier substrate includes a metal material and a medium, and a coefficient of thermal expansion (CTE) of the medium is less than a CTE of the metal material. | 03-31-2011 |
20110073873 | COMPOUND SEMICONDUCTOR DEVICE USING SIC SUBSTRATE AND ITS MANUFACTURE - A compound semiconductor device includes: a conductive SiC substrate; an AlN buffer layer formed on said conductive SiC substrate and containing Cl; a compound semiconductor buffer layer formed on said AlN layer which contains Cl, said compound semiconductor buffer layer not containing Cl; and a device constituent layer or layers formed above said compound semiconductor buffer layer not containing Cl. | 03-31-2011 |
20110073874 | METHOD OF REDUCING MEMORY EFFECTS IN SEMICONDUCTOR EPITAXY - A method of reducing memory effects during an epitaxial growth process is provided in which a gas mixture comprising hydrogen gas and a halogen-containing gas is used to flush the CVD reaction chamber between growth steps. | 03-31-2011 |
20110079791 | BETAVOLTAIC CELL - High aspect ratio micromachined structures in semiconductors are used to improve power density in Betavoltaic cells by providing large surface areas in a small volume. A radioactive beta-emitting material may be placed within gaps between the structures to provide fuel for a cell. The pillars may be formed of SiC. In one embodiment, SiC pillars are formed of n-type SiC. P type dopant, such as boron is obtained by annealing a borosilicate glass boron source formed on the SiC. The glass is then removed. In further embodiments, a dopant may be implanted, coated by glass, and then annealed. The doping results in shallow planar junctions in SiC. | 04-07-2011 |
20110079792 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - Provided are a semiconductor device and a method of fabricating the semiconductor device, the semiconductor device including: a source trace, a drain trace, and a gate trace placed on a substrate; a transistor which is placed on the drain trace and includes a source pad and a gate pad; insulating films placed between the drain and source traces and between the drain and gate traces on the substrate so as to cover sidewall surfaces of the transistor; a source spray electrode which is placed on the insulating film between the source and drain traces and connects the source pad of the transistor and the source trace; and a gate spray electrode placed on the insulating film between the gate and drain traces and connects the gate pad of the transistor and the gate trace. | 04-07-2011 |
20110079793 | SEMICONDUCTOR SUBSTRATE AND ITS MANUFACTURING METHOD - A semiconductor substrate includes: a substrate having a single crystal silicon on at least one surface thereof; a buffer layer that is provided on the single crystal silicon and has at least one cobalt silicide layer primarily containing cobalt silicide; and a silicon carbide single crystal film provided on the buffer layer. | 04-07-2011 |
20110079794 | METHOD FOR MANUFACTURING ELECTRONIC DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICES - A method manufactures a vertical power MOS transistor on a semiconductor substrate comprising a first superficial semiconductor layer of a first conductivity type, comprising: forming trench regions in the first semiconductor layer, filling in said trench regions with a second semiconductor layer of a second conductivity type, to form semiconductor portions of the second conductivity type contained in the first semiconductor layer, carrying out an ion implantation of a first dopant type in the semiconductor portions for forming respective implanted body regions of said second conductivity type, carrying out an ion implantation of a second dopant type in one of the implanted body regions for forming an implanted source region of the first conductivity type inside one of the body regions, carrying out an activation thermal process of the first and second dopant types with low thermal budget suitable to complete said formation of the body and source regions. | 04-07-2011 |
20110079795 | SEMICONDUCTOR LIGHT EMITTING DEVICE, ILLUMINATION MODULE, ILLUMINATION APPARATUS, METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting device ( | 04-07-2011 |
20110084284 | Transistors with Semiconductor Interconnection Layers and Semiconductor Channel Layers of Different Semiconductor Materials - A transistor may include a semiconductor drift layer of a first semiconductor material and a semiconductor channel layer on the semiconductor drift layer. The semiconductor channel layer may include a second semiconductor material different than the first semiconductor material. A semiconductor interconnection layer may be electrically coupled between the semiconductor drift layer and the semiconductor channel layer, and the semiconductor interconnection layer may include a third semiconductor material different than the first and second semiconductor materials. In addition, a control electrode may be provided on the semiconductor channel layer. | 04-14-2011 |
20110084285 | BASE MATERIAL FOR GROWING SINGLE CRYSTAL DIAMOND AND METHOD FOR PRODUCING SINGLE CRYSTAL DIAMOND SUBSTRATE - The present invention is a base material for growing a single crystal diamond comprising: at least a single crystal SiC substrate; and an iridium film or a rhodium film heteroepitaxially grown on a side of the single crystal SiC substrate where the single crystal diamond is to be grown. As a result, there is provided a base material for growing a single crystal diamond and a method for producing a single crystal diamond substrate which can grow the single crystal diamond having a large area and good crystallinity and produce a high quality single crystal diamond substrate at low cost. | 04-14-2011 |
20110089431 | COMPOUND SINGLE CRYSTAL AND METHOD FOR PRODUCING THE SAME - A method for producing a compound single crystal includes a process (I) of growing the compound single crystal while causing an anti-phase boundary and a stacking fault to equivalently occur in a <110> direction parallel to the surface, the stacking fault being attributable to the elements A and B; a process (II) of merging and annihilating the stacking fault, attributable to the element A, and the anti-phase boundary, which occurs in the process (I); a process (III) of vanishing the stacking fault attributable to the element B, which occurs in the process (I); and a process (IV) of completely merging and annihilating the anti-phase boundary. The process (IV) is carried out simultaneously with the processes (II) and (III) or after the processes (II) and (III). | 04-21-2011 |
20110089432 | WIDE BANDGAP DEVICE IN PARALLEL WITH A DEVICE THAT HAS A LOWER AVALANCHE BREAKDOWN VOLTAGE AND A HIGHER FORWARD VOLTAGE DROP THAN THE WIDE BANDGAP DEVICE - An electrical device on a single semiconductor substrate includes: an open base vertical PNP transistor placed in parallel with a wide bandgap, high voltage diode wherein the PNP transistor has a P doped collector region, an N-doped base layer, an N doped buffer layer, and a P doped emitter layer. | 04-21-2011 |
20110089433 | METHOD FOR MANUFACTURING NITROGEN COMPOUND SEMICONDUCTOR SUBSTRATE AND NITROGEN COMPOUND SEMICONDUCTOR SUBSTRATE, AND METHOD FOR MANUFACTURING SINGLE CRYSTAL SIC SUBSTRATE AND SINGLE CRYSTAL SIC SUBSTRATE - In order to provide a method for manufacturing a single crystal SiC substrate that can obtain an SiC layer with good crystallinity, an Si substrate | 04-21-2011 |
20110095301 | SILICON CARBIDE SEMICONDUCTOR DEVICE - There was a problem that it was difficult to manufacture silicon carbide semiconductor devices with suppressed variations in characteristics without increasing the number of process steps. A silicon carbide semiconductor device according to the present invention includes an N type SiC substrate and an N type SiC epitaxial layer as a silicon carbide semiconductor substrate of a first conductivity type, a plurality of recesses intermittently formed in a surface of the N type SiC epitaxial layer, P type regions as second-conductivity-type semiconductor layers formed in the N type SiC epitaxial layer in the bottoms of the plurality of recesses, and a Schottky electrode selectively formed over the surface of the N type SiC epitaxial layer, wherein the plurality of recesses all have an equal depth. | 04-28-2011 |
20110095302 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to provide a semiconductor device and its manufacturing method in which delay in switching and non-uniform operations are prevented and in which stresses occurring in trench regions are alleviated as much as possible. A gate electrode in a gate trench is formed of a polysilicon layer and a gate tungsten layer that is lower resistant than the polysilicon layer. Also, a source electrode is formed of source tungsten layers buried in source trenches and an AlSi layer in contact with the source tungsten layers and covering source layers and the gate electrodes with a thick insulating film interposed therebetween. | 04-28-2011 |
20110095303 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a cell region, an outer peripheral region, a field plate, an outermost peripheral ring, outer peripheral region layer, an insulator film, and a Zener diode. The semiconductor substrate has a superjunction structure. The outer peripheral region is disposed at an outer periphery of the cell region. The Zener diode is disposed on the insulator film for electrically connecting the field plate with the outermost peripheral ring. The Zener diode has a first conductivity type region and a second conductivity type region that are alternately arranged in a direction from the cell region to the outer peripheral region. | 04-28-2011 |
20110095304 | PROCESS FOR FORMING AN INTERFACE BETWEEN SILICON CARBIDE AND SILICON OXIDE WITH LOW DENSITY OF STATES - An embodiment of a process for forming an interface between a silicon carbide (SiC) layer and a silicon oxide (SiO | 04-28-2011 |
20110095305 | SEMICONDUCTOR DEVICE - The semiconductor device includes: a substrate | 04-28-2011 |
20110101374 | MONOLITHIC HIGH VOLTAGE SWITCHING DEVICES AND RELATED METHODS OF FABRICATING THE SAME - Metal oxide semiconductor (MOS) power devices are provided including a MOS channel including a semiconductor material having high electron mobility on a silicon carbide (SiC) layer. Related methods are also provided herein. | 05-05-2011 |
20110101375 | Power Semiconductor Devices Having Selectively Doped JFET Regions and Related Methods of Forming Such Devices - Semiconductor switching devices include a wide band-gap drift layer having a first conductivity type (e.g., n-type), and first and second wide band-gap well regions having a second conductivity type (e.g., p-type) on the wide band-gap drift layer. First and second wide band-gap source/drain regions of the first conductivity type are on the first and second wide band-gap well regions, respectively. A wide band-gap JFET region having the first conductivity type is provided between the first and second well regions. This JFET region includes a first local JFET region that is adjacent a side surface of the first well region and a second local JFET region that is adjacent a side surface of the second well region. The local JFET regions have doping concentrations that exceed a doping concentration of a central portion of the JFET region that is between the first and second local JFET regions of the JFET region. | 05-05-2011 |
20110101376 | Optically-Initiated Silicon Carbide High Voltage Switch - An improved photoconductive switch having a SIC or other wide band gap substrate material, such as GaAs and field-grading liners composed of preferably SiN formed on the substrate adjacent the electrode perimeters or adjacent the substrate perimeters for grading the electric fields. | 05-05-2011 |
20110101377 | HIGH TEMPERATURE ION IMPLANTATION OF NITRIDE BASED HEMTS - A method is disclosed for forming a high electron mobility transistor. The method includes the steps of implanting a Group III nitride layer at a defined position with ions that when implanted produce an improved ohmic contact between the layer and contact metals, with the implantation being carried out at a temperature higher than room temperature and hot enough to reduce the amount of damage done to the Group III nitride layer, but below a temperature at which surface problems causing leakage at the gate or epitaxial layer dissociation would occur. An ohmic contact selected from the group consisting of titanium, aluminum, nickel and alloys thereof is added to the implanted defined position on the Group III nitride layer. | 05-05-2011 |
20110101378 | SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRAIN AND METHODS OF MANUFACTURING AND DESIGN STRUCTURE - A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The method includes forming a gate structure for an NFET and a PFET and forming sidewalls on the gate structure for the NFET and the PFET using a same deposition and etching process. The method also includes providing stress materials in the source and drain regions of the NFET and the PFET. | 05-05-2011 |
20110108853 | COMPOUND SEMICONDUCTOR DEVICE - A compound semiconductor device having reduced contact resistance to an electrode is provided. The compound semiconductor device includes an n-substrate | 05-12-2011 |
20110108854 | SUBSTANTIALLY LATTICE MATCHED SEMICONDUCTOR MATERIALS AND ASSOCIATED METHODS - Semiconductor devices having atomic lattice matching template interlayers are provided. In one aspect, a semiconductor device can include a first semiconductor material, a second semiconductor material disposed on the first semiconductor material, and an atomic template interlayer disposed between the first semiconductor material and the second semiconductor material, the atomic template interlayer bonding together and facilitating a substantial lattice matching between the first semiconductor material and the second semiconductor material. | 05-12-2011 |
20110108855 | METHOD OF FORMING VIAS IN SILICON CARBIDE AND RESULTING DEVICES AND CIRCUITS - A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer. | 05-12-2011 |
20110114968 | Integrated Nitride and Silicon Carbide-Based Devices - A monolithic electronic device includes a first nitride epitaxial structure including a plurality of nitride epitaxial layers. The plurality of nitride epitaxial layers include at least one common nitride epitaxial layer. A second nitride epitaxial structure is on the common nitride epitaxial layer of the first nitride epitaxial structure. A first plurality of electrical contacts is on the first epitaxial nitride structure and defines a first electronic device in the first nitride epitaxial structure. A second plurality of electrical contacts is on the first epitaxial nitride structure and defines a second electronic device in the second nitride epitaxial structure. A monolithic electronic device includes a bulk semi-insulating silicon carbide substrate having implanted source and drain regions and an implanted channel region between the source and drain regions, and a nitride epitaxial structure on the surface of the silicon carbide substrate. Corresponding methods are also disclosed. | 05-19-2011 |
20110121315 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A recess along a sidewall is formed in a pMOS region and an nMOS region. An SiC layer of which thickness is thicker than a depth of the recess is formed in the recess. A sidewall covering a part of the SiC layer is formed at both lateral sides of a gate electrode in the pMOS region. A recess is formed by selectively removing the SiC layer in the pMOS region. A side surface of the recess at the gate insulating film side is inclined so that the upper region of the side surface, the closer to the gate insulating film in a lateral direction at a region lower than the surface of the silicon substrate. An SiGe layer is formed in the recess in the pMOS region. | 05-26-2011 |
20110121316 | SILICON CARBIDE SEMICONDUCTOR DEVICE - The area of each body region is minimized, and the gate oxide films at the bottoms of the trenches are more effectively protected by depletion layers extending from the body regions. | 05-26-2011 |
20110121317 | ANNEALING METHOD FOR SEMICONDUCTOR DEVICE WITH SILICON CARBIDE SUBSTRATE AND SEMICONDUCTOR DEVICE - In an atmosphere in which a silicon carbide (SiC) substrate implanted with impurities is annealed to activate the impurities, by setting a partial pressure of H | 05-26-2011 |
20110121318 | Silicon Carbide Switching Devices Including P-Type Channels - Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650° C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is in the channel region and includes p-type dopants at a dopant concentration of about 1×10 | 05-26-2011 |
20110127542 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor device contains a gate electrode, SiGe layers, Si layers, source/drain regions, and silicide layers. The gate electrode is formed on a semiconductor substrate via a gate insulating film. The SiGe layers are formed on both sides of the gate electrode on the semiconductor substrate. Over half of a region of the SiGe layers is higher than an interface between the semiconductor substrate and the gate insulating film. The Si layers are formed on the SiGe layers. The source/drain regions are formed on both sides of the gate electrode in the Si layers, the SiGe layers and the semiconductor substrate. The silicide layers are formed on the Si layers. | 06-02-2011 |
20110127543 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a semiconductor element disposed on the main surface of the substrate and generating a heat of 200° C. or more, an enclosure surrounding the semiconductor element, and a liquid sealant containing a heat-resistant oil. The enclosure controls the flow of the sealant and seals the semiconductor element. | 06-02-2011 |
20110127544 | GROUP III NITRIDE TEMPLATES AND RELATED HETEROSTRUCTURES, DEVICES, AND METHODS FOR MAKING THEM - A templated substate includes a base layer, and a template layer disposed on the base layer and having a composition including a single-crystal Group Ill nitride. The template layer includes a continuous sublayer on the base layer and a nanocolumnar sublayer on the first sublayer, wherein the nanocolumnar sublayer includes a plurality of nano-scale columns. | 06-02-2011 |
20110127545 | COMPOUND SEMICONDUCTOR DEVICE WITH T-SHAPED GATE ELECTRODE - A compound semiconductor device includes a compound semiconductor substrate; epitaxially grown layers formed over the compound semiconductor substrate and including a channel layer and a resistance lowering cap layer above the channel layer; source and drain electrodes in ohmic contact with the channel layer; recess formed by removing the cap layer between the source and drain electrodes; a first insulating film formed on an upper surface of the cap layer and having side edges at positions retracted from edges, or at same positions as the edges of the cap layer in a direction of departing from the recess; a second insulating film having gate electrode opening and formed covering a semiconductor surface in the recess and the first insulating film; and a gate electrode formed on the recess via the gate electrode opening. | 06-02-2011 |
20110133211 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A wide band gap semiconductor device having a JFET, a MESFET, or a MOSFET mainly includes a semiconductor substrate, a first conductivity type semiconductor layer, and a first conductivity type channel layer. The semiconductor layer is formed on a main surface of the substrate. A recess is formed in the semiconductor layer in such a manner that the semiconductor layer is divided into a source region and a drain region. The recess has a bottom defined by the main surface of the substrate and a side wall defined by the semiconductor layer. The channel layer has an impurity concentration lower than an impurity concentration of the semiconductor layer. The channel layer is formed on the bottom and the side wall of the recess by epitaxial growth. | 06-09-2011 |
20110133212 | METHODS OF MAKING SEMICONDUCTOR DEVICES HAVING IMPLANTED SIDEWALLS AND DEVICES MADE THEREBY - Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices are made using selective ion implantation using an implantation mask. The devices have implanted sidewalls formed by scattering of normal or near normal incident ions from the implantation mask. Vertical junction field-effect transistors with long channel length are also described. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications. | 06-09-2011 |
20110140126 | HEAT CONDUCTION FOR CHIP STACKS AND 3-D CIRCUITS - A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities. | 06-16-2011 |
20110140127 | SEMI-CONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor light-emitting device and a method for manufacturing the same is disclosed, which improves light extraction efficiency by forming a plurality of protrusions on a surface of a substrate for growing a nitride semiconductor material thereon, the semiconductor light-emitting device comprising a substrate; one or more first protrusions on the substrate, each first protrusion having a recess through which a surface of the substrate is exposed planarly; a first semiconductor layer on the substrate including the first protrusions; an active layer on the first semiconductor layer; a second semiconductor layer on the active layer; a first electrode on a predetermined portion of the first semiconductor layer, wherein the active layer and second semiconductor layer are not formed on the predetermined portion of the first semiconductor layer; and a second electrode on the second semiconductor layer. | 06-16-2011 |
20110147764 | TRANSISTORS WITH A DIELECTRIC CHANNEL DEPLETION LAYER AND RELATED FABRICATION METHODS - A metal-insulator-semiconductor field-effect transistor (MISFET) includes a semiconductor layer with source and drain regions of a first conductivity type spaced apart therein. A channel region of a first conductivity type extends between the source and drain regions. A gate contact is on the channel region. A dielectric channel depletion layer is between the gate contact and the channel region. The dielectric channel depletion layer provides a net charge having the same polarity as the first conductivity type charge carriers, and which may deplete the first conductivity type charge carriers from an adjacent portion of the channel region when no voltage is applied to the gate contact. | 06-23-2011 |
20110147765 | DUMMY STRUCTURE FOR ISOLATING DEVICES IN INTEGRATED CIRCUITS - The present disclosure provides an integrated circuit. The integrated circuit includes a first operational device having a first transistor of a first composition; a second operational device having a second transistor of the first composition; and an isolation transistor disposed between the first and second transistors, the isolation transistor having a second composition different from the first composition. | 06-23-2011 |
20110147766 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing a silicon carbide semiconductor device is provided that includes a step of forming in a surface of a silicon carbide wafer of first conductivity type a first region of second conductivity type having a predetermined space thereinside by ion-implanting aluminum as a first impurity and boron as a second impurity; a step of forming a JTE region in the surface of the silicon carbide wafer from the first region by diffusing the boron ion-implanted in the first region toward its neighboring zones by an activation annealing treatment; a step of forming a first electrode on the surface of the silicon carbide wafer at the space inside the first region and at an inner part of the first region; and a step of forming a second electrode on the opposite surface of the silicon carbide wafer. Thereby, a JTE region can be formed that has a wide range of impurity concentration and a desired breakdown voltage without increasing the number of steps of the manufacturing process. | 06-23-2011 |
20110147767 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - There is provided a semiconductor device including an ohmic junction layer which is excellent in surface flatness and uniformity of composition in an interface with a semiconductor substrate and thus can give a sufficiently high adhesiveness with a Schottky junction layer. Such a semiconductor device includes an n type SiC semiconductor substrate ( | 06-23-2011 |
20110156052 | Semiconductor device having JFET and method for manufacturing the same - A semiconductor device having a JFET includes: a substrate made of semi-insulating semiconductor material; a gate region in a surface portion of the substrate; a channel region disposed on and contacting the gate region; a source region and a drain region disposed on both sides of the gate region so as to sandwich the channel region, respectively; a source electrode electrically coupled with the source region; a drain electrode electrically coupled with the drain region; and a gate electrode electrically coupled with the gate region. An impurity concentration of each of the source region and the drain region is higher than an impurity concentration of the channel region. | 06-30-2011 |
20110156053 | SEMICONDUCTOR DEVICE HAVING D MODE JFET AND E MODE JFET AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a substrate; and depletion and enhancement mode JFETs. The depletion mode JFET includes: a concavity on the substrate; a channel layer in the concavity; a first gate region on the channel layer; first source and drain regions on respective sides of the first gate region in the channel layer; first gate, source and drain electrodes. The enhancement mode JFET includes: a convexity on the substrate; the channel layer on the convexity; a second gate region on the channel layer; second source and drain regions on respective sides of the second gate region in the channel layer; second gate, source and drain electrodes. A thickness of the channel layer in the concavity is larger than a thickness of the channel layer on the convexity. | 06-30-2011 |
20110156054 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A silicon carbide semiconductor device having a JFET or a MOSFET includes a semiconductor substrate and a trench. The semiconductor substrate has a silicon carbide substrate, a drift layer on the silicon carbide substrate, a first gate region on the drift layer, and a source region on the first gate region. The trench has a strip shape with a longitudinal direction and reaches the drift layer by penetrating the source region and the first gate region. The trench is filled with a channel layer and a second gate region on the channel layer. The source region is not located at an end portion of the trench in the longitudinal direction. | 06-30-2011 |
20110156055 | INTEGRATED DIAMOND TRANSDUCTION PIXELIZED IMAGER DEVICE AND MANUFACTURING PROCESS - Imaging device including several pixels, each pixel including at least: | 06-30-2011 |
20110156056 | WAVELENGTH-CONVERTED SEMICONDUCTOR LIGHT EMITTING DEVICE - A material such as a phosphor is optically coupled to a semiconductor structure including a light emitting region disposed between an n-type region and a p-type region, in order to efficiently extract light from the light emitting region into the phosphor. The phosphor may be phosphor grains in direct contact with a surface of the semiconductor structure, or a ceramic phosphor bonded to the semiconductor structure, or to a thin nucleation structure on which the semiconductor structure may be grown. The phosphor is preferably highly absorbent and highly efficient. When the semiconductor structure emits light into such a highly efficient, highly absorbent phosphor, the phosphor may efficiently extract light from the structure, reducing the optical losses present in prior art devices. | 06-30-2011 |
20110156057 | SUBSTRATE OF THE SEMICONDUCTOR ON INSULATOR TYPE WITH INTRINSIC AND DOPED DIAMOND LAYERS - A semiconductor substrate including at least a layer based on doped diamond with a thickness greater than or equal to approximately 10 μm, a layer based on at least one semiconductor or a stack of layers including the semiconductor-based layer, and a layer based on intrinsic diamond disposed against the layer based on doped diamond, between the layer based on doped diamond and the semiconductor-based layer. | 06-30-2011 |
20110156058 | SILICON CARBIDE MONOCRYSTAL SUBSTRATE AND MANUFACTURING METHOD THEREFOR - A method for producing a silicon carbide single crystal substrate according to the present invention includes steps of: (A) preparing a silicon carbide single crystal substrate having a mechanically polished main face; (B) performing chemical mechanical polishing on the main face of the silicon carbide single crystal substrate using a polishing slurry containing abrasive grains dispersed therein to finish the main face as a mirror surface; (C′1) oxidizing at least a part of the main face finished as a mirror surface by a gas phase to form an oxide; and (C′2) removing the oxide. | 06-30-2011 |
20110169013 | GROWING POLYGONAL CARBON FROM PHOTORESIST - A method of growing polygonal carbon from photoresist and resulting structures are disclosed. Embodiments of the invention provide a way to produce polygonal carbon, such as graphene, by energizing semiconductor photoresist. The polygonal carbon can then be used for conductive paths in a finished semiconductor device, to replace the channel layers in MOSFET devices on a silicon carbide base, or any other purpose for which graphene or graphene-like carbon material formed on a substrate is suited. In some embodiments, the photoresist layer forms both the polygonal carbon layer and an amorphous carbon layer over the polygonal carbon layer, and the amorphous carbon layer is removed to leave the polygonal carbon on the substrate. | 07-14-2011 |
20110169014 | COMPOUND SEMICONDUCTOR DEVICE - A compound semiconductor device includes: an electron transit layer made of GaN; a channel layer made of AlGaN; a source electrode, a gate electrode and a drain electrode that are provided on the channel layer; a cap layer that is provided at least between the source electrode and the gate electrode and between the gate electrode and the drain electrode and is made of GaN; a recess portion that is provided in the cap layer between the gate electrode and the drain electrode; and a thick portion that is provided in the cap layer between the recess portion and the drain electrode and has a thickness larger than the recess portion. | 07-14-2011 |
20110169015 | BIPOLAR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - Disclosed is a bipolar semiconductor device which is capable of reducing the surface state density of a bipolar transistor and increasing the current gain of the transistor, thereby improving the transistor performance. A bipolar semiconductor device ( | 07-14-2011 |
20110169016 | MOSFET AND METHOD FOR MANUFACTURING MOSFET - A MOSFET includes: a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. The MOSFET has a sub-threshold slope of not more than 0.4 V/Decade. | 07-14-2011 |
20110175106 | SEMICONDUCTOR RECTIFIER - A semiconductor rectifier includes: a wide bandgap semiconductor substrate of a first conductivity type; a wide bandgap semiconductor layer of the first conductivity type which is formed on an upper surface of the wide bandgap semiconductor substrate and has an impurity concentration of 1E+14 atoms/cm | 07-21-2011 |
20110175107 | SILICON CARBIDE SUBSTRATE - A base portion is made of silicon carbide and has a main surface. At least one silicon carbide layer is provided on the main surface of the base portion in a manner exposing a region of the main surface along an outer edge of the main surface. At least one protection layer is provided on this region of the main surface of the base portion along the outer edge of the main surface. Thus, a silicon carbide substrate can be polished with high in-plane uniformity. | 07-21-2011 |
20110175108 | LIGHT-EMITTING DEVICE - A silicon carbide substrate has a first layer facing a semiconductor layer and a second layer stacked on the first layer. Dislocation density of the second layer is higher than dislocation density of the first layer. Thus, quantum efficiency and power efficiency of a light-emitting device can both be high. | 07-21-2011 |
20110175109 | FILM OF N TYPE (100) ORIENTED SINGLE CRYSTAL DIAMOND SEMICONDUCTOR DOPED WITH PHOSPHOROUS ATOMS, AND A METHOD OF PRODUCING THE SAME - There is provided an n type (100) oriented single crystal diamond semiconductor film into which phosphorous atoms have been doped and a method of producing the same. The n type (100) oriented single crystal diamond semiconductor film, characterized in that (100) oriented diamond is epitaxially grown on a substrate under such conditions that; the diamond substrate is (100) oriented diamond, a means for chemical vapor deposition provides hydrogen, hydrocarbon and a phosphorous compound in the plasma vapor phase, the ratio of phosphorous atoms to carbon atoms in the plasma vapor phase is no less than 0.1%, and the ratio of carbon atoms to hydrogen atoms is no less than 0.05%, and the method of producing the same. | 07-21-2011 |
20110175110 | MOSFET AND METHOD FOR MANUFACTURING MOSFET - A MOSFET includes a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. When the insulating film has a thickness of not less than 30 nm and not more than 46 nm, the threshold voltage thereof is not more than 2.3V. When the insulating film has a thickness of more than 46 nm and not more than 100 nm, the threshold voltage thereof is more than 2.3 V and not more than 4.9 V. | 07-21-2011 |
20110175111 | SILICON CARBIDE SEMICONDUCTOR DEVICE - Provided is a silicon carbide semiconductor device capable of lowering the contact resistance of an ohmic electrode and achieving high reverse breakdown voltage characteristics. A semiconductor device includes a substrate and a p | 07-21-2011 |
20110180807 | INFRARED EXTERNAL PHOTOEMISSIVE DETECTOR - An infrared external photoemissive detector can have an n-p heterojunction comprising an n-type semiconductor layer and a p-layer; the n-layer semiconductor comprising doped silicon embedded with nanoparticles forming Schottky barriers; and the p-layer is a p-type diamond film. The nanoparticles can be about 20-30 atomic percentage metal particles (such as silver) having an average particle size of about 5-10 nm. The p-layer can have a surface layer that has a negative electron affinity. The n-layer can be in the range of about 3 μm to 10 μm thick, and preferably about 3 μm thick. The doped silicon can be doped with elements selected from the list consisting of phosphorus and antimony. | 07-28-2011 |
20110180808 | METHOD OF MAKING A MOUNTED GALLIUM NITRIDE DEVICE - A method of making a mounted gallium nitride (GaN) device includes obtaining a device structure comprising a silicon layer, a silicon carbide (SiC) layer over the silicon layer, and a GaN layer over the SiC layer. The GaN layer is processed to form an active layer of active devices and interconnect over the GaN layer. After the step of processing the GaN layer, a gold layer is formed on the silicon layer. The device structure is attached to a heat sink structure using the gold layer. The mounted GaN device includes the SiC layer over the polysilicon layer and the GaN layer over the SiC layer. The active layer is over the GaN layer. | 07-28-2011 |
20110180809 | SEMICONDUCTOR DEVICE MODULE - A P-side package unit and a N-side package unit are arranged on a main surface of a metal heatsink such that a main surface extends in a direction perpendicular to the main surface of the heatsink. Each of the P-side package unit and the N-side package unit is fixed by an end edge portion of a heatsink being clipped by a rail-shaped unit mounting part provided on the main surface of the heatsink. | 07-28-2011 |
20110180810 | Semiconductor Arrangement and Method for Producing a Semiconductor Arrangement - A semiconductor arrangement includes a ceramic mount and at least one semiconductor component fixed-to the ceramic mount. The ceramic mount includes a first section, and the first section is electrically conductive. | 07-28-2011 |
20110180811 | WIRELESS CHIP AND ELECTRONIC DEVICE HAVING WIRELESS CHIP - It is an object to provide a wireless chip which can increase a mechanical strength, and a wireless chip with a high durability. A wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, and a conductive layer connecting the chip and the antenna. Further, a wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, a sensor device, a conductive layer connecting the chip and the antenna, and a conductive layer connecting the chip and the sensor device. Moreover, a wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, a battery, a conductive layer connecting the chip and the antenna, and a conductive layer connecting the chip and the battery. | 07-28-2011 |
20110180812 | SEMICONDUCTOR DEVICE - A MOSFET which is a semiconductor device capable of achieving a stable reverse breakdown voltage and reduced on-resistance includes a SiC wafer of an n conductivity type, a plurality of p bodies of a p conductivity type formed to include a first main surface of the SiC wafer, and n | 07-28-2011 |
20110180813 | INSULATED GATE BIPOLAR TRANSISTOR - An IGBT, which is capable of reducing on resistance by reducing channel mobility, includes: an n type substrate made of SiC and having a main surface with an off angle of not less than 50° and not more than 65° relative to a plane orientation of {0001}; a p type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; an n type well region formed to include a second main surface of the reverse breakdown voltage holding layer; an emitter region formed in the well region to include the second main surface and including a p type impurity at a concentration higher than that of the reverse breakdown voltage holding layer; a gate oxide film formed on the reverse breakdown voltage holding layer; and a gate electrode formed on the gate oxide film. In a region including an interface between the well region and the gate oxide film, a high-concentration nitrogen region is formed to have a nitrogen concentration higher than those of the well region and the gate oxide film. | 07-28-2011 |
20110180814 | INSULATED GATE FIELD EFFECT TRANSISTOR - A MOSFET, which is capable of reducing on resistance by reducing channel mobility even when a gate voltage is high, includes: an n type substrate made of SiC and having a main surface with an off angle of 50°-65° relative to a {0001} plane; an n type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; a p type well region formed in the reverse breakdown voltage holding layer distant away from a first main surface thereof; a gate oxide film formed on the well region; an n type contact region disposed between the well region and the gate oxide film; a channel region connecting the n type contact region and the reverse breakdown voltage holding layer; and a gate electrode disposed on the gate oxide film. In a region including an interface between the channel region and the gate oxide film, a high-concentration nitrogen region is formed. | 07-28-2011 |
20110186861 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a JFET or a MESFET mainly includes a semiconductor substrate, a first conductivity type semiconductor channel layer on the substrate, a first conductivity type semiconductor layer on the channel layer, and an i-type sidewall layer on a sidewall of a recess that penetrates the semiconductor layer to divide the semiconductor layer into a source region and a drain region. The semiconductor layer has an impurity concentration greater than an impurity concentration of the channel layer. The semiconductor device further includes a second conductivity type gate region that is located on the channel layer in the recess and on the i-type sidewall layer. The gate region is spaced from the source region and the drain region by the i-type sidewall layer. | 08-04-2011 |
20110186862 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is provided a silicon carbide semiconductor device having excellent electrical characteristics such as channel mobility, and a method for manufacturing the same. A semiconductor device includes a substrate made of silicon carbide and having an off-angle of greater than or equal to 50° and less than or equal to 65° with respect to a surface orientation of {0001}, a p-type layer serving as a semiconductor layer, and an oxide film serving as an insulating film. The p-type layer is formed on the substrate and is made of silicon carbide. The oxide film is formed to contact with a surface of the p-type layer. A maximum value of the concentration of nitrogen atoms in a region within 10 nm of an interface between the semiconductor layer and the insulating film (interface between a channel region and the oxide film) is greater than or equal to 1×10 | 08-04-2011 |
20110193097 | Silicon carbide semiconductor - A hermetically sealed integrated circuit package that includes a cavity housing a semiconductor die, whereby the cavity is pressurized during assembly and when formed. The invention prevents the stress on a package created when the package is subject to high temperatures at atmospheric pressure and then cooled from reducing the performance of the die at high voltages. By packaging a die at a high pressure, such as up to 50 PSIG, in an atmosphere with an inert gas, and providing a large pressure in the completed package, the dies are significantly less likely to arc at higher voltages, allowing the realization of single die packages operable up to at least 1200 volts. Moreover, the present invention is configured to employ brazed elements compatible with Silicon Carbide dies which can be processed at higher temperatures. | 08-11-2011 |
20110193098 | High voltage high package pressure semiconductor package - A hermetically sealed integrated circuit package that includes a cavity housing a semiconductor die, whereby the cavity is pressurized during assembly and when formed. The invention prevents the stress on a package created when the package is subject to high temperatures at atmospheric pressure and then cooled from reducing the performance of the die at high voltages. By packaging a die at a high pressure, such as up to 50 PSIG, in an atmosphere with an inert gas, and providing a large pressure in the completed package, the dies are significantly less likely to arc at higher voltages, allowing the realization of single die packages operable up to at least 1200 volts. Moreover, the present invention is configured to employ brazed elements compatible with Silicon Carbide dies which can be processed at higher temperatures. | 08-11-2011 |
20110193099 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes: a low dielectric constant oxide film as an inorganic oxide film formed selectively on an n-type semiconductor substrate as a semiconductor substrate of a fist conductivity type; and anode electrodes as electrode layers formed on the n-type semiconductor substrate so as to sandwich the low dielectric constant oxide film therebetween, wherein the low dielectric constant oxide film is doped with an element for reducing a dielectric constant. | 08-11-2011 |
20110193100 | SIC SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) by using a single mask, etching regions of an SiC semiconductor layer which serve as an impurities implantation region and a mark region, to form recesses, (b) by using the same mask as in the step (a), performing ion-implantation in the recesses of the regions which serve as the impurities implantation region and the mark region, at least from an oblique direction relative to a surface of the SiC semiconductor layer and (c) positioning another mask based on the recess of the region which serves as the impurities implantation region or the mark region, and performing well implantation in a region containing the impurities implantation region. | 08-11-2011 |
20110193101 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a SiC layer of a first conductivity type, a SiC region of a second conductivity type, and a conductive layer of the second conductivity type. The SiC layer of the first conductivity type has a hexagonal crystal structure. The SiC region of the second conductivity type is formed in a surface of the SiC layer. The conductive layer of the second conductivity type is provided on the SiC region and is in contact with a portion of the SiC region including SiC of a cubic crystal structure. | 08-11-2011 |
20110198612 | SIC SEMICONDUCTOR DEVICE HAVING CJFET AND METHOD FOR MANUFACTURING THE SAME - A SiC semiconductor device includes: a SiC substrate made of intrinsic SiC having semi-insulating property; first and second conductive type SiC layers disposed in the substrate; an insulation separation layer made of intrinsic SiC for isolating the first conductive type SiC layer from the second conductive type SiC layer; first and second conductive type channel JFETs disposed in the first and second conductive type SiC layers, respectively. The first and second conductive type channel JFETs provide a complementary junction field effect transistor. Since an electric element is formed on a flat surface, a manufacturing method is simplified. Further, noise propagation at high frequency and current leakage at high temperature are restricted. | 08-18-2011 |
20110198613 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The leakage current generated in a pn junction region between a gate and a source is reduced in a junction FET using a silicon carbide substrate. In a trench junction FET using a silicon carbide substrate, nitrogen is introduced into a sidewall and a bottom surface of a trench, thereby forming an n type layer and an n | 08-18-2011 |
20110198614 | METHOD AND APPARATUS FOR MANUFACTURING A SiC SINGLE CRYSTAL FILM - A manufacturing method for a SiC single crystal film which allows stable growth of a SiC epitaxial film with a low doping concentration on a substrate with a diameter of at least 2 inches by the LPE method using a SiC solution in solvent of a melt includes an evacuation step in which the interior of a crystal growth furnace is evacuated with heating until the vacuum pressure at the crystal growth temperature is 5×10 | 08-18-2011 |
20110198615 | High-Sensitivity, High-Resolution Detector Devices and Arrays - Avalanche amplification structures including electrodes, an avalanche region, a quantifier, an integrator, a governor, and a substrate arranged to detect a weak signal composed of as few as several electrons are presented. Quantifier regulates the avalanche process. Integrator accumulates a signal charge. Governor drains the integrator and controls the quantifier. Avalanche amplifying structures include: normal quantifier, reverse bias designs; normal quantifier, normal bias designs; lateral quantifier, normal bias designs; changeable quantifier, normal bias, adjusting electrode designs; normal quantifier, normal bias, adjusting electrode designs; and lateral quantifier, normal bias, annular integrator designs. Avalanche amplification structures are likewise arranged to provide arrays of multi-channel devices. The described invention is expected to be used within photodetectors, electron amplifiers, chemical and biological sensors, and chemical and biological chips with lab-on-a-chip applications. Structures have immediately applicability to devices critical to homeland defense. | 08-18-2011 |
20110198616 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - Each unit cell includes: a drift layer | 08-18-2011 |
20110198617 | ELECTRODE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device comprising a p-type SiC semiconductor and an ohmic electrode having an Ni/Al laminated structure provided on the p-type SiC semiconductor. The semiconductor device simultaneously has improved contact resistance and surface roughness in the ohmic electrode. The semiconductor device comprises an ohmic electrode ( | 08-18-2011 |
20110204382 | LAYERED STRUCTURES COMPRISING SILICON CARBIDE LAYERS, A PROCESS FOR THEIR MANUFACTURE AND THEIR USE - A layered structure comprising in this order: (A) a silicon carbide layer, (B) at least one stratum (b1) located at least one major surface of the silicon carbide layer (A), (b2) chemically bonded to the bulk of the silicon carbide layer (A) by silicon-oxygen and/or silicon-carbon bonds, (b3) covering the at least one major surface of the silicon carbide layer (A) partially or completely, and (b4) having a higher polarity than a pure silicon carbide surface as exemplified by a contact angle with water which is lower than the contact angle of water with a pure silicon carbide surface; and (C) at least one dielectric layer, which covers the stratum or the strata (B) partially or completely and is selected from inorganic and inorganic-organic hybrid dielectric layers; a process for its manufacture and its use. | 08-25-2011 |
20110204383 | SIC SEMICONDUCTOR DEVICE HAVING SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING THE SAME - A SiC semiconductor device having a Schottky barrier diode includes: a substrate made of SiC and having a first conductive type, wherein the substrate includes a main surface and a rear surface; a drift layer made of SiC and having the first conductive type, wherein the drift layer is disposed on the main surface of the substrate and has an impurity concentration lower than the substrate; a Schottky electrode disposed on the drift layer and has a Schottky contact with a surface of the drift layer; and an ohmic electrode disposed on the rear surface of the substrate. The Schottky electrode directly contacts the drift layer in such a manner that a lattice of the Schottky electrode is matched with a lattice of the drift layer. | 08-25-2011 |
20110204384 | METHOD OF FORMING A PLANAR FIELD EFFECT TRANSISTOR WITH EMBEDDED AND FACETED SOURCE/DRAIN STRESSORS ON A SILICON-ON-INSULATOR (SOI) WAFER, A PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND A DESIGN STRUCTURE FOR THE PLANAR FIELD EFFECT TRANSISTOR - Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET. | 08-25-2011 |
20110210339 | SEMICONDUCTOR DEVICE - A semiconductor device including a non-volatile memory cell including a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor is provided. Data is written or rewritten to the memory cell by turning on the writing transistor and supplying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected to each other, and then turning off the writing transistor so that the predetermined amount of charge is held in the node. Further, when a transistor whose threshold voltage is controlled and set to a positive voltage is used as the reading transistor, a reading potential is a positive potential. | 09-01-2011 |
20110210340 | HIGH TEMPERATURE GATE DRIVERS FOR WIDE BANDGAP SEMICONDUCTOR POWER JFETS AND INTEGRATED CIRCUITS INCLUDING THE SAME - Gate drivers for wide bandgap (e.g., >2 eV) semiconductor junction field effect transistors (JFETs) capable of operating in high ambient temperature environments are described. The wide bandgap (WBG) semiconductor devices include silicon carbide (SiC) and gallium nitride (GaN) devices. The driver can be a non-inverting gate driver which has an input, an output, a first reference line for receiving a first supply voltage, a second reference line for receiving a second supply voltage, a ground terminal, and six Junction Field-Effect Transistors (JFETs) wherein the first JFET and the second JFET form a first inverting buffer, the third JFET and the fourth JFET form a second inverting buffer, and the fifth JFET and the sixth JFET form a totem pole which can be used to drive a high temperature power SiC JFET. An inverting gate driver is also described. | 09-01-2011 |
20110210341 | P-TYPE SiC SEMICONDUCTOR - A p-type SiC semiconductor includes a SiC crystal that contains Al and Ti as impurities, wherein the atom number concentration of Ti is equal to or less than the atom number concentration of Al. It is preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)≧5×10 | 09-01-2011 |
20110210342 | SILICON CARBIDE SUBSTRATE AND METHOD OF MANUFACTURING SILICON CARBIDE SUBSTRATE - A SiC substrate includes a first orientation flat parallel to the <11-20> direction, and a second orientation flat being in a direction intersecting the first orientation flat and being different from the first orientation flat in length. An alternative SiC substrate has a rectangular plane shape, and a main surface of the substrate includes a first side parallel to the <11-20> direction, a second side in a direction perpendicular to the first side, and a third side connecting the first side to the second side. A length of the third side projected in a direction in which the first side extends is different from a length of the third side projected in a direction in which the second side extends. | 09-01-2011 |
20110215340 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING SAME - A semiconductor light-emitting device according to the present invention includes: a GaN substrate | 09-08-2011 |
20110220913 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device provided with a structure, which prevents withstand voltage deterioration and may be manufactured at a low cost, is provided. The semiconductor device is provided with a semiconductor substrate, a first conductive type semiconductor layer formed of silicon carbide formed on the substrate, an active region formed on a surface of the semiconductor layer, a second conductive type first semiconductor region formed on the surface of the semiconductor layer so as to surround the active region, a second semiconductor region provided on the surface of the semiconductor layer so as to contact the outside of the first semiconductor region to surround the first semiconductor region in which a second conductive type impurity region having impurity concentration and a depth identical to those of the first semiconductor region is formed into a mesh shape, a first electrode provided on the active region, and a second electrode provided on a backside of the semiconductor substrate. | 09-15-2011 |
20110220914 | POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a power semiconductor device according to the present invention includes the steps of: (a) forming a silicon nitride film on a semiconductor substrate; (b) after the step (a), forming a ring-shaped trench along a peripheral portion of the semiconductor substrate | 09-15-2011 |
20110220915 | Off-Axis Silicon Carbide Substrates - A method of epitaxial growth of a material on a crystalline substrate includes selecting a substrate having a crystal plane that includes a plurality of terraces with step risers that join adjacent terraces. Each terrace of the plurality or terraces presents a lattice constant that substantially matches a lattice constant of the material, and each step riser presents a step height and offset that is consistent with portions of the material nucleating on adjacent terraces being in substantial crystalline match at the step riser. The method also includes preparing a substrate by exposing the crystal plane; and epitaxially growing the material on the substrate such that the portions of the material nucleating on adjacent terraces merge into a single crystal lattice without defects at the step risers. | 09-15-2011 |
20110220916 | ELECTRONIC CIRCUIT DEVICE - A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET. | 09-15-2011 |
20110220917 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor device of the present invention has a semiconductor element region | 09-15-2011 |
20110220918 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A high-performance semiconductor device capable of suppressing a leak current with little electric field concentration, reducing an invalid region in a PN junction region, securing a sufficient area for a Schottky junction region, and achieving efficient and easy manufacturing, in which, in one surface of a semiconductor substrate ( | 09-15-2011 |
20110227094 | STRAINED SILICON CARBIDE CHANNEL FOR ELECTRON MOBILITY OF NMOS - A semiconductor is formed on a (110) silicon (Si) substrate, with improved electron mobility. Embodiments include semiconductor devices having a silicon carbide (SiC) portion in the nFET channel region. An embodiment includes forming an nFET channel region and a pFET channel region in a Si substrate, such as a (110) Si substrate, and forming a silicon carbide (SiC) portion on the nFET channel region. The SiC portion may be formed by ion implantation of C followed by a recrystallization anneal or by epitaxial growth of SiC in a recess formed in the substrate. The use of SiC in the nFET channel region improves electron mobility without introducing topographical differences between NMOS and PMOS transistors. | 09-22-2011 |
20110227095 | Semiconductor Device Including a Normally-On Transistor and a Normally-Off Transistor - A semiconductor device is disclosed. One embodiment includes a first semiconductor die having a normally-off transistor. In a second semiconductor die a plurality of transistor cells of a normally-on transistor are formed, wherein one of a source terminal/drain terminal of the normally-on transistor is electrically coupled to a gate terminal of the normally-on transistor and the other one the source terminal/drain terminal of the normally-off transistor is electrically coupled to one of a source terminal/drain terminal of the normally-on transistor. The second semiconductor die includes a gate resistor electrically coupled between the gate terminal of the normally-off transistor and respective gates of the plurality of transistor cells. A voltage clamping element is electrically coupled between the gate terminal and the one of the source terminal/drain terminal of the normally-on transistor. | 09-22-2011 |
20110227096 | SEMICONDUCTOR DEVICE - A semiconductor device having a construction capable of achieving suppressed deterioration of electric characteristics in an insulating member is provided. An n | 09-22-2011 |
20110233560 | Electrode for silicon carbide, silicon carbide semiconductor element, silicon carbide semiconductor device and method for forming electrode for silicon carbide - An electrode for silicon carbide includes a silicide region which is provided in contact with a surface of a silicon carbide (SiC) layer and a carbide region which is provided on the silicide region. The silicide region contains a silicide of a first metal in more amount than a carbide of a second metal whose free energy of carbide formation is less than that of silicon (Si). The carbide region contains the carbide of the second metal in more amount than the silicide of the first metal. | 09-29-2011 |
20110233561 | SEMICONDUCTOR SUBSTRATE - A supporting portion is made of silicon carbide. At least one layer has first and second surfaces. The first surface is supported by the supporting portion. The at least one layer has first and second regions. The first region is made of silicon carbide of a single-crystal structure. The second region is made of graphite. The second surface has a surface formed by the first region. The first surface has a surface formed by the first region, and a surface formed by the second region. In this way, a semiconductor substrate can be provided which has a region made of silicon carbide having a single-crystal structure and a supporting portion made of silicon carbide and allows for reduced electric resistance of an interface therebetween. | 09-29-2011 |
20110233562 | SUBSTRATE, SUBSTRATE WITH THIN FILM, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A substrate achieving suppressed deterioration of processing accuracy of a semiconductor device due to bending of the substrate, a substrate with a thin film and a semiconductor device formed with the substrate above, and a method of manufacturing the semiconductor device above are obtained. A substrate according to the present invention has a main surface having a diameter of 2 inches or greater, a value for bow at the main surface being not smaller than −40 μm and not greater than −5 μm, and a value for warp at the main surface being not smaller than 5 μm and not greater than 40 μm. Preferably, a value for surface roughness Ra of the main surface of the substrate is not greater than 1 nm and a value for surface roughness Ra of a main surface is not greater than 100 nm. | 09-29-2011 |
20110233563 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing of a semiconductor device ( | 09-29-2011 |
20110241020 | HIGH ELECTRON MOBILITY TRANSISTOR WITH RECESSED BARRIER LAYER - Embodiments of a high electron mobility transistor with recessed barrier layer, and methods of forming the same, are disclosed. Other embodiments are also be described and claimed. | 10-06-2011 |
20110241021 | SILICON CARBIDE BARRIER DIODE - Improved semiconductor devices are fabricated utilizing nickel gallide and refractory borides deposited onto a silicon carbide semiconductor substrate. Varying the deposition and annealing parameters of fabrication can provide a more thermally stable device that has greater barrier height and a low ideality. This improvement in the electrical properties allows use of Schottky barrier diodes in high power and high temperature applications. In one embodiment, a refractory metal boride layer is joined to a surface of a silicon carbide semiconductor substrate. The refractory metal boride layer is deposited on the silicon carbon semiconductor substrate at a temperature greater than 200° C. In another embodiment, a Schottky barrier diode is fabricated via deposition of nickel gallide on a SiC substrate. | 10-06-2011 |
20110241022 | SUBSTRATE AND METHOD OF MANUFACTURING SUBSTRATE - A substrate, the presence of which can be detected with a method similar to a conventional method of detecting a Si substrate even if the substrate is transparent, and a method of manufacturing the substrate are provided. Light incident on an end portion of a transparent substrate is not transmitted through the substrate as with the light incident on a central portion of the substrate, but is totally reflected from a total reflection surface in a detection region present in at least a portion of the end portion of the substrate. A photoelectric sensor can recognize that a ratio of transmission of the light at the end portion of the substrate has become smaller, thereby detecting the presence of the substrate. | 10-06-2011 |
20110248284 | SCHOTTKY DIODE WITH IMPROVED SURGE CAPABILITY - An SiC Schottky diode die or a Si Schottky diode die is mounted with its epitaxial anode surface connected to the best heat sink surface in the device package. This produces a substantial increase in the surge current capability of the device. | 10-13-2011 |
20110248285 | SEMICONDUCTOR DEVICES INCLUDING SCHOTTKY DIODES HAVING OVERLAPPING DOPED REGIONS AND METHODS OF FABRICATING SAME - A semiconductor device includes a semiconductor layer having a first conductivity type and having a surface in which an active region of the semiconductor device is defined, and a plurality of spaced apart doped regions within the active region. The plurality of doped regions have a second conductivity type that is opposite the first conductivity type and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of doped regions include a plurality of rows extending in a longitudinal direction. Each of the rows includes a plurality of longitudinally extending segments, and the longitudinally extending segments in a first row at least partially overlap the longitudinally extending segments in an adjacent row in a lateral direction that is perpendicular to the longitudinal direction. | 10-13-2011 |
20110248286 | SEMICONDUCTOR DEVICE - For suggesting a structure capable of achieving both a low start-up voltage and high breakdown voltage, a SiC vertical diode includes a cathode electrode, an n | 10-13-2011 |
20110254015 | METHOD FOR IMPROVING DEVICE PERFORMANCE USING EPITAXIALLY GROWN SILICON CARBON (SiC) OR SILICON-GERMANIUM (SiGe) - A semiconductor substrate including a field effect transistor (FET) and a method of producing the same wherein a stressor is provided in a recess before the source/drain region is formed. The device has an increased carrier mobility in the channel region adjacent to the gate electrode. | 10-20-2011 |
20110254016 | VERTICAL JFET LIMITED SILICON CARBIDE METAL-OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS - Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) may include an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, an oxide layer on the drift layer, and an n-type silicon carbide limiting region disposed between the drift layer and a portion of the first p-type region. The limiting region may have a carrier concentration that is greater than the carrier concentration of the drift layer. | 10-20-2011 |
20110254017 | MANUFACTURING METHOD FOR CRYSTAL, CRYSTAL, AND SEMICONDUCTOR DEVICE - A manufacturing method for a crystal, a crystal, and a semiconductor device capable of growing a high-quality crystal are provided. The manufacturing method for a crystal of the present invention includes the steps of: preparing a seed crystal having a frontside surface and a backside surface opposite to the frontside surface; fixing the backside surface of the seed crystal to a pedestal; and growing the crystal on the frontside surface of the seed crystal. In the step of fixing, the seed crystal is fixed to the pedestal by coating the backside surface of the seed crystal with a Si layer or disposing a Si layer on the backside surface of the seed crystal, and carbonizing the Si layer. | 10-20-2011 |
20110254018 | Semiconductor Switching Arrangement Having a Normally on and a Normally off Transistor - A semiconductor switching arrangement includes a normally on semiconductor component of a first conduction type and a normally off semiconductor component of a second conduction type which is the complement of the first conduction type. A load path of the normally off semiconductor component is connected in series with the load path of the normally on semiconductor component. A first actuation circuit connected between the control connection of the normally on semiconductor component and a load path connection of the normally on semiconductor component. The load path connection of the normally on semiconductor component is arranged between the normally on and normally off semiconductor components. A second actuation circuit is connected between the control connection of the normally off semiconductor component and a load path connection of the normally off semiconductor component. The load path connection of the normally off semiconductor component is arranged between the normally on and normally off semiconductor components. | 10-20-2011 |
20110254019 | ADAPTED SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light-emitting device with light-modulating function and a method of fabrication the same are provided. The semiconductor light-emitting device as provided includes a light-emitting layer and a super-paramagnetic layer. The light-emitting layer functions for emitting a first light. In particular, a portion or most of the first light is modulated by the super-paramagnetic layer into a second light when the first light passes through the super-paramagnetic layer. In some embodiments, the semiconductor light-emitting device is designed in such a way that a portion of the first light, which is not modulated into the second light, blends with the second light into a third light, e.g., a white light. | 10-20-2011 |
20110254020 | DEVICE FORMED HARD MASK AND ETCH STOP LAYER - A method of etching a device in one embodiment includes providing a silicon carbide substrate, forming a silicon nitride layer on a surface of the silicon carbide substrate, forming a silicon carbide layer on a surface of the silicon nitride layer, forming a silicon dioxide layer on a surface of the silicon carbide layer, forming a photoresist mask on a surface of the silicon dioxide layer, and etching the silicon dioxide layer through the photoresist mask. | 10-20-2011 |
20110260174 | GaN BASED POWER DEVICES WITH INTEGRATED PROTECTION DEVICES: STRUCTURES AND METHODS - Exemplary embodiments provide structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS). In one embodiment, active devices can be formed over a substrate, while a clamp structure can be integrated outside the active regions of the power device, for example, under the active regions and/or inside the substrate. Integrating clamp structure outside active regions of power devices can maximize the active area for a given die size and improve robustness of the clamped device since the current will spread in the substrate by this integration. | 10-27-2011 |
20110260175 | SEMICONDUCTOR DEVICE - A silicon carbide layer is provided on a substrate, has a hexagonal single-crystal structure, and has a surface at which a depletion layer is formed. A protective film is insulative and provided on the silicon carbide layer to directly cover the surface. The surface thus directly covered with the protective film includes a portion having an off angle of not more than 10° relative to the {0-33-8} plane of the silicon carbide layer. This results in reduced leakage current flowing in an interface between the protective film and the semiconductor layer. | 10-27-2011 |
20110266556 | METHOD FOR CONTROLLED GROWTH OF SILICON CARBIDE AND STRUCTURES PRODUCED BY SAME - A method for controlled growth of silicon carbide and structures produced by the method are disclosed. A crystal of silicon carbide (SiC) can be grown by placing a sacrificial substrate in a growth zone with a source material. The source material may include a low-solubility impurity. SiC is then grown on the sacrificial substrate to condition the source material. The sacrificial substrate is then replaced with the final substrate, and SiC is grown on the final substrate. A single crystal of silicon carbide is produced, wherein the crystal of silicon carbide has substantially few micropipe defects. Such a crystal may also include a substantially uniform concentration of the low-solubility impurity, and may be used to make wafers and/or SiC die. | 11-03-2011 |
20110266557 | Semiconductor Devices Having Improved Adhesion and Methods of Fabricating the Same - Wide bandgap semiconductor devices are fabricated by providing a wide bandgap semiconductor layer, providing a plurality of recesses in the wide bandgap semiconductor layer, and providing a metal gate contact in the plurality of recesses. A protective layer may be provided on the wide bandgap semiconductor layer, the protective layer having a first opening extending therethrough, a dielectric layer may be provided on the protective layer, the dielectric layer having a second opening extending therethrough that is narrower than the first opening, and a gate contact may be provided in the first and second openings. The metal gate contact may be provided to include a barrier metal layer in the plurality of recesses, and a current spreading layer on the barrier metal layer remote from the wide bandgap semiconductor layer. Related devices and fabrication methods are also discussed. | 11-03-2011 |
20110266558 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SILICON CARBIDE SEMICONDUCTOR DEVICE - There is provided a silicon carbide semiconductor device equipped with an ohmic electrode that exhibits both low contact resistance and favorable surface conditions,
| 11-03-2011 |
20110272707 | SUBSTRATES AND METHODS OF FORMING FILM STRUCTURES TO FACILITATE SILICON CARBIDE EPITAXY - Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, wafers and methods to form film structures to facilitate formation of silicon carbide epitaxy on a substrate, such as a silicon-based substrate. In some embodiments, a method of preparing a substrate for silicon carbide epitaxial layer formation can include forming an ultrathin layer of oxide that is configured to inhibit contaminants from interacting with a silicon-based substrate. Further, the method can include forming a carbonized film on the silicon-based substrate that is configured to inhibit contaminants from interacting with the silicon-based substrate. The carbonized film can be configured to be transitory as fabrication parameters are modified to form an epitaxial layer of silicon carbide. | 11-10-2011 |
20110272708 | NITRIDE SEMICONDUCTOR DEVICE - According to one embodiment, a nitride semiconductor device includes a first, a second and a third semiconductor layer, a first and a second main electrode and a control electrode. The first layer made of a nitride semiconductor of a first conductivity type is provided on a substrate. The second layer made of a nitride semiconductor of a second conductivity type is provided on the first layer. The third layer made of a nitride semiconductor is provided on the second layer. The first electrode is electrically connected with the second layer. The second electrode is provided at a distance from the first electrode and electrically connected with the second layer. The control electrode is provided within a first trench via an insulating film. The first trench is disposed between the first and the second main electrodes, penetrates the third and the second layers, and reaches the first layer. | 11-10-2011 |
20110272709 | RADIATION HEATING EFFICIENCY BY INCREASING OPTICAL ABSORPTION OF A SILICON CONTAINING MATERIAL - Embodiments of the present invention generally provide a process and apparatus for increasing the absorption coefficient of a chamber component disposed in a thermal process chamber. In one embodiment, a method generally includes providing a substrate carrier having a first surface and a second surface, the first surface is configured to support a substrate and being parallel and opposite to the second surface, subjecting the second surface of the substrate carrier to a surface treatment process to roughen the second surface of the substrate carrier, wherein the substrate carrier contains a material comprising silicon carbide, and forming an oxide-containing layer on the roughened second surface of the substrate carrier. The formed oxide-containing layer has optical absorption properties at wavelengths close to the radiation delivered from one or more energy sources used to heat the chamber component. | 11-10-2011 |
20110272710 | Solid state energy photovoltaic device - A solid state energy conversion device and method of making is disclosed for converting energy between electromagnetic and electrical energy. The solid state energy conversion device comprises a wide bandgap semiconductor material having a first doped region. A thermal energy beam is directed onto the first doped region of the wide bandgap semiconductor material in the presence of a doping gas for converting a portion of the first doped region into a second doped region in the wide bandgap semiconductor material. A first and a second Ohmic contact are applied to the first and the second doped regions of the wide bandgap semiconductor material. In one embodiment, the solid state energy conversion device operates as a light emitting device to produce electromagnetic radiation upon the application of electrical power to the first and second Ohmic contacts. In another embodiment, the solid state energy conversion device operates as a photovoltaic device to produce electrical power between the first and second Ohmic contacts upon the application of electromagnetic radiation. | 11-10-2011 |
20110272711 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR APPARATUS - There is provided a method of manufacturing a semiconductor device, a semiconductor device, and a semiconductor apparatus, by which an electrode having an excellent ohmic property can be formed, and a semiconductor device having excellent device characteristics can be obtained with a high product yield. The method sequentially includes: a semiconductor device structure formation process in which a semiconductor device structure | 11-10-2011 |
20110278590 | Semiconductor Devices Having Gates Including Oxidized Nickel and Related Methods of Fabricating the Same - Schottky barrier semiconductor devices are provided including a wide bandgap semiconductor layer and a gate on the wide bandgap semiconductor layer. The gate includes a metal layer on the wide bandgap semiconductor layer including a nickel oxide (NiO) layer. Related methods of fabricating devices are also provided herein. | 11-17-2011 |
20110278591 | POWER SEMICONDUCTOR SWITCH - A SiC JFET that includes a plurality of trenches formed in a SiC semiconductor body of one conductivity each trench having a region of another conductivity formed in the bottom and sidewalls thereof. | 11-17-2011 |
20110278592 | SEMICONDUCTOR DEVICE - A semiconductor device which is designed based on RDR, suppresses the occurrence of a trouble at the boundary between an active region and a power wire and therearound and is small in size and highly integrated. The semiconductor device includes a first conductive impurity region for functional elements which is formed over the main surface of a semiconductor substrate and a second conductive impurity region for power potential to which power potential is applied in at least one standard cell. It also includes insulating layers which are formed over the main surface of the semiconductor substrate and have throughholes reaching the main surface of the semiconductor substrate, and a conductive layer for contact formed in the throughholes of the insulating layers. The impurity region for functional elements and the impurity region for power potential are electrically coupled to each other through the conductive layer for contact which is formed astride the impurity region for functional elements and the impurity region for power potential. | 11-17-2011 |
20110278593 | METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide substrate includes the steps of: preparing a SiC substrate made of single-crystal silicon carbide; disposing a base substrate in a crucible so as to face a main surface of the SiC substrate; and forming a base layer made of silicon carbide in contact with the main surface of the SiC substrate, by heating the base substrate in the crucible to fall within a range of temperature higher than a sublimation temperature of silicon carbide constituting the base substrate. In the step of forming the base layer, a gas containing silicon is introduced into the crucible. | 11-17-2011 |
20110278594 | METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide substrate includes the steps of: preparing a SiC substrate made of single-crystal silicon carbide; disposing a base substrate in a crucible so as to face a main surface of the SiC substrate; and forming a base layer made of silicon carbide in contact with the main surface of the SiC substrate by heating the base substrate in the crucible to fall within a range of temperature equal to or higher than a sublimation temperature of silicon carbide constituting the base substrate. The crucible has an inner wall at least a portion of which is provided with a coating layer made of silicon carbide. | 11-17-2011 |
20110278595 | METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide and a SiC substrate made of single-crystal silicon carbide; fabricating a stacked substrate by placing said SiC substrate on and in contact with a main surface of said base substrate; and connecting said base substrate and said SiC substrate to each other by heating said stacked substrate in a container to fall within a range of temperature equal to or greater than a sublimation temperature of silicon carbide constituting said base substrate. In the step of connecting said base substrate and said SiC substrate, a silicon carbide body made of silicon carbide and different from said base substrate and said SiC substrate is disposed in said container. | 11-17-2011 |
20110278596 | Epitaxial silicon carbide monocrystalline substrate and method of production of same - The present invention provides an epitaxial SiC monocrystalline substrate having a high quality epitaxial film suppressed in occurrence of step bunching in epitaxial growth using a substrate with an off angle of 6° or less and a method of production of the same, that is, an epitaxial silicon carbide monocrystalline substrate comprised of a silicon carbide monocrystalline substrate with an off angle of 6° or less on which a silicon carbide monocrystalline thin film is formed, the epitaxial silicon carbide monocrystalline substrate characterized in that the silicon carbide monocrystalline thin film has a surface with a surface roughness (Ra value) of 0.5 nm or less and a method of production of the same. | 11-17-2011 |
20110278597 | METHOD OF PRODUCING A LAYER OF CAVITIES - A method of producing a layer of cavities in a structure comprises at least one substrate formed from a material that can be oxidized or nitrided, the method comprising the following steps: implanting ions into the substrate in order to form an implanted ion concentration zone at a predetermined mean depth; heat treating the implanted substrate to form a layer of cavities at the implanted ion concentration zone; and forming an insulating layer in the substrate by thermochemical treatment from one surface of the substrate, the insulating layer that is formed extending at least partially into the layer of cavities. | 11-17-2011 |
20110278598 | SEMICONDUCTOR STRUCTURE, AN INTEGRATED CIRCUIT INCLUDING A SEMICONDUCTOR STRUCTURE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE - A monolithic semiconductor structure includes a stack of layers. The stack includes a substrate; a first layer made from a first semiconductor material; and a second layer made from a second semiconductor material. The first layer is situated between the substrate and the second layer and at least one of the first semiconductor material and the second semiconductor material contains a III-nitride material. The structure includes a power transistor, including a body formed in the stack of layers; a first power terminal at a side of the first layer facing the second layer; a second power terminal at least partly formed in the substrate; and a gate structure for controlling the propagation through the body of electric signals between the first power terminal and the second power terminal. The structure further includes a vertical Schottky diode, including: an anode; a cathode including the substrate, and a Schottky barrier between the cathode and the anode, the Schottky barrier being situated between the substrate and a anode layer in the stack of layers. | 11-17-2011 |
20110278599 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer. | 11-17-2011 |
20110284870 | METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE WITH A BURIED GROUND PLANE - A method for making a semiconducting structure, including: a) forming, on a surface of a final semiconductor substrate, a semiconducting layer, doped with elements from columns III and V of the Periodic Table so as to form a ground plane, b) forming a dielectric layer, c) then assembling, by direct adhesion of the source substrate, on the final substrate, the layer forming the ground plane between the final substrate and the source substrate, the dielectric layer being between the source substrate and the ground plane, d) then thinning the source substrate, leaving, on the surface of the semiconductor structure, a film made from a semiconducting material. | 11-24-2011 |
20110284871 | SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE - A silicon carbide substrate includes a base layer made of silicon carbide, an SiC layer made of single crystal silicon carbide, arranged on the base layer, and having a concentration of inevitable impurities lower than the concentration of inevitable impurities in the base layer, and a cover layer made of silicon carbide, formed on a main surface of the base layer at a side opposite to the SiC layer, and having a concentration of inevitable impurities lower than the concentration of inevitable impurities in the base layer. | 11-24-2011 |
20110284872 | METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide, and a SiC substrate made of single-crystal silicon carbide; fabricating a stacked substrate by placing the SiC substrate on and in contact with a main surface of the base substrate; connecting the base substrate and the SiC substrate by heating the stacked substrate to allow the base substrate to have a temperature higher than that of the SiC substrate; and forming an epitaxial growth layer on an opposite main surface, to the SiC substrate, of the base substrate connected to the SiC substrate. | 11-24-2011 |
20110284873 | SILICON CARBIDE SUBSTRATE - A silicon carbide substrate has a substrate region and a support portion. The substrate region has a first single crystal substrate. The support portion is joined to a first backside surface of the first single crystal. The dislocation density of the first single crystal substrate is lower than the dislocation density of the support portion. At least one of the substrate region and the support portion has voids. | 11-24-2011 |
20110284874 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is on the field oxide film, going around a periphery of the cell region, and electrically connected to the second gate electrode. The gate wiring is a silicide of a constituting substance of the second gate electrode. | 11-24-2011 |
20110284875 | HIGH EFFICIENCY GROUP III NITRIDE LED WITH LENTICULAR SURFACE - A high efficiency Group III nitride light emitting diode is disclosed. The diode includes a substrate selected from the group consisting of semiconducting and conducting materials, a Group III nitride-based light emitting region on or above the substrate, and, a lenticular surface containing silicon carbide on or above the light emitting region, and extending to said light emitting region. | 11-24-2011 |
20110284876 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten. | 11-24-2011 |
20110291104 | SMOOTHING METHOD FOR SEMICONDUCTOR MATERIAL AND WAFERS PRODUCED BY SAME - A smoothing method for semiconductor material and semiconductor wafers produced by the method are disclosed. Semiconductor wafers with reduced atomic steps, as well with reduced scratches and subsurface defects can be produced. Such wafers feature an improved growth surface that can provide for the growth of an epilayer with reduced macroscopic defects and defect densities. A method of smoothing the surface of a wafer according to example embodiments of the invention includes planarizing the surface of a semiconductor wafer, and then oxidizing the wafer to achieve a specified thickness of oxide on the surface of the wafer. The oxide can then be stripped from the surface of the semiconductor wafer. | 12-01-2011 |
20110291105 | SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - A semiconductor module according to the present invention includes: an insulating substrate ( | 12-01-2011 |
20110291106 | POWER SEMICONDUCTOR DEVICE - Provided is a power semiconductor device including: a power semiconductor element; a metal block as a first metal block that is connected to the power semiconductor element through an upper surface electrode pattern as a first upper surface electrode pattern selectively formed on an upper surface of the power semiconductor element; and a mold resin filled so as to cover the power semiconductor element and the metal block, wherein an upper surface of the metal block is exposed from a surface of the mold resin. | 12-01-2011 |
20110291107 | SELF-ALIGNED SEMICONDUCTOR DEVICES WITH REDUCED GATE-SOURCE LEAKAGE UNDER REVERSE BIAS AND METHODS OF MAKING - A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 μm to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described. | 12-01-2011 |
20110291108 | SEMICONDUCTOR PHOTODETECTOR WITH TRANSPARENT INTERFACE CHARGE CONTROL LAYER AND METHOD THEREOF - A detection device comprising a photodetector comprising a first semiconductor layer through which light first enters the photodetector; the first semiconductor layer to semiconductor material crystal lattice which terminates at an interface; the discontinuity of the semiconductor crystal lattice at the interface creating a first interface charge; the first semiconductor layer being an absorption layer in which photons in a predetermined wavelength range are absorbed and create photogenerated carriers; and a second polar semiconductor layer deposited on the crystal lattice of the first semiconductor layer, the second polar semiconductor being substantially transparent to light in the predetermined wavelength range, the second polar semiconductor layer having a total polarization different from the first semiconductor layer so that a second interface charge is induced at the interface between the first and second semiconductor layers; the induced second interface charge reduces or substantially cancels the first interface charge; whereby the reduction or substantial cancellation of the surface charge in the first semiconductor layer increases the collection of photogenerated carriers by the photodetector. A method of improving the quantum efficiency of a semiconductor photodetector comprising providing a semiconductor photodetector having a first layer which has a first interface through which light first enters the semiconductor photodetector; placing a layer of polar material transparent to the band of detection wavelengths that has a polarization substantially different than the polarization of the first layer such that the polarization charge induced at the interface between the layer of polar material and the first surface results in decreased interface recombination of photogenerated minority carriers and an increase in quantum efficiency of the photodetector. | 12-01-2011 |
20110291109 | POLARIZATION ENHANCED AVALANCHE PHOTODETECTOR AND METHOD THEREOF - An avalanche photodetector comprising a multiplication layer formed of a first material having a first polarization; the multiplication layer having a first electric field upon application of a bias voltage; an absorption layer formed of a second material having a second polarization forming an interface with the multiplication layer; the absorption layer having a second electric field upon application of the bias voltage, the second electric field being less than the first electric field or substantially zero, carriers created by light absorbed in the absorption layer being multiplied in the multiplication layer due to the first electric field; the absorption layer having a second polarization which is greater or less than the first polarization to thereby create an interface charge; the interface charge being positive when the first material predominately multiplies holes, the interface charge being negative when the first material predominately multiplies electrons, the change in electric field at the interface occurring abruptly at the atomic level; the interface charge creating electric field discontinuity causing first electric field to attain the breakdown field in the multiplication region and the second electric field to be low or zero in the absorption layer to thereby eliminate the need for a doped charge layer and the associated thickness of the doped charge layer required to transition from the low field to the high field. Also claimed is a method of making. | 12-01-2011 |
20110291110 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The silicon carbide semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate insulating layer, a gate electrode, a source electrode, a drain electrode, and a deep layer. The deep layer is disposed under the base region and is located to a depth deeper than the trench. The deep layer is divided into a plurality of portions in a direction that crosses a longitudinal direction of the trench. The portions include a group of portions disposed at positions corresponding to the trench and arranged at equal intervals in the longitudinal direction of the trench. The group of portions surrounds corners of a bottom of the trench. | 12-01-2011 |
20110291111 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A chip size package includes: a radio frequency substrate having a radio frequency semiconductor circuit formed on a principal surface; a semiconductor cover substrate arranged at a position facing the principal surface of the radio frequency substrate; and a joining frame arranged in a manner such as to surround the radio frequency semiconductor circuit between the radio frequency substrate and the semiconductor cover substrate, the joining frame joining the radio frequency substrate and the semiconductor cover substrate, wherein: the radio frequency substrate further has a wire formed on a surface opposite to the principal surface; and the radio frequency semiconductor circuit and the wire are electrically connected to each other through a via hole penetrating through the radio frequency substrate in a thickness direction thereof. | 12-01-2011 |
20110291112 | NORMALLY-OFF INTEGRATED JFET POWER SWITCHES IN WIDE BANDGAP SEMICONDUCTORS AND METHODS OF MAKING - Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described. | 12-01-2011 |
20110297962 | SCHOTTKY DIODE WITH DIAMOND ROD AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a Schottky diode with a diamond rod, which comprises: a substrate with a gate layer formed thereon; a patterned insulating layer disposed on the gate layer, wherein the patterned insulating layer comprises a first contact region and a second contact region; a diamond rod disposed on the patterned insulating layer, wherein a first end of the diamond rod connects to the first contact region, and a second end of the diamond rod connects to the second contact region; a first electrode corresponding to the first contact region of the patterned insulating layer, and covering the first end of the diamond rod; and a second electrode corresponding to the second contact region of the patterned insulating layer, and covering the second end of the diamond rod, and a method for manufacturing the same. | 12-08-2011 |
20110297963 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A silicon carbide semiconductor device is provided that includes a semiconductor layer made of silicon carbide and having a surface with a trench having a sidewall formed of a crystal plane tilted at an angle in a range of not less than 50° and not more than 65° relative to the {0001} plane, and an insulating film formed to contact the sidewall of the trench. A maximum value of the nitrogen concentration in a region within 10 nm from the interface between the sidewall of the trench and the insulating film is not less than 1×10 | 12-08-2011 |
20110297964 | AC SWITCH - An AC switch includes a first compound semiconductor MOSFET and a second compound semiconductor MOSFET whose sources are connected with each other, a first output terminal connected to the drain of the first compound semiconductor MOSFET, and a second output terminal connected to the drain of the second compound semiconductor MOSFET. The withstand voltage between the first output terminal and the second output terminal in an off state is not less than 400 V. The resistance between the first output terminal and the second output terminal in an on state is not more than 20 mΩ. | 12-08-2011 |
20110303925 | Semiconductor device and the method of manufacturing the same - A semiconductor device according to the invention includes p-type well region 3 and n | 12-15-2011 |
20110309375 | SEMICONDUCTOR DEVICE - A semiconductor device includes semiconductor elements mounted on a heat spreader, lead frames connected to the semiconductor elements, and a molding resin which holds them and forms a housing. Upper portions and side surfaces of the semiconductor elements are covered with an organic thin film which is formed between the semiconductor elements and the molding resin. | 12-22-2011 |
20110309376 | METHOD OF CLEANING SILICON CARBIDE SEMICONDUCTOR, SILICON CARBIDE SEMICONDUCTOR, AND SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of cleaning an SiC semiconductor capable of exhibiting an effect of cleaning an SiC semiconductor is provided. An SiC semiconductor and an SiC semiconductor device capable of achieving improved characteristics are provided. The method of cleaning an SiC semiconductor includes the steps of forming an oxide film on a surface of an SiC semiconductor (step S | 12-22-2011 |
20110316002 | CMOS IMAGE SENSOR - A complementary metal-oxide-semiconductor (CMOS) image sensor, including a wiring layer, a photodiode stacked with the wiring layer, a micro-lens stacked on the photodiode, an anti-reflection layer stacked on the photodiode. An anti-absorption layer may be provided between the photodiode and the anti-reflection layer. The photodiode may include a first portion and a second portion. Light may be focused on the first portion by the micro-lens and the second portion may at least partially surround the first portion. A material of the first portion may have a refractive index higher than a refractive index of a material of the second portion. The anti-absorption layer may include a compound semiconductor having an energy band gap greater than an energy band gap of a semiconductor included in the photodiode. | 12-29-2011 |
20110316003 | Multilayered Semiconductor Wafer and Process For Manufacturing The Same - Silicon carbide substrate wafers are prepared by transferring a monocrystalline silicon layer from a donor wafer onto a handle wafer, the silicon layer being implanted with carbon and annealed to form a monocrystalline SiC layer prior to or after transfer of the silicon layer. | 12-29-2011 |
20120001197 | LAYOUT FOR MULTIPLE-FIN SRAM CELL - The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region. | 01-05-2012 |
20120001198 | ISOLATION REGION, SEMICONDUCTOR DEVICE AND METHODS FOR FORMING THE SAME - An isolation region is provided. The isolation region includes a first groove and an insulation layer filling the first groove. The first groove is embedded into a semiconductor substrate and includes a first sidewall, a bottom surface and a second sidewall that extends from the bottom surface and joins to the first sidewall. An angle between the first sidewall and a normal line of the semiconductor substrate is larger than a standard value. A method for forming an isolation region is further provided. The method includes: forming a first trench on a semiconductor substrate, wherein an angle between a sidewall of the first trench and a normal line of the semiconductor substrate is larger than a standard value; forming a mask on the sidewall to form a second trench on the semiconductor substrate by using the mask; and forming an insulation layer to fill the first and second trenches. A semiconductor device and a method for forming the same are still further provided. In the semiconductor device, a material of the semiconductor substrate is interposed between a second groove bearing a semiconductor layer for forming an S/D region and the first and second sidewalls. The present invention is beneficial to reduce leakage current. | 01-05-2012 |
20120001199 | POWER SEMICONDUCTOR DEVICE - A bipolar power semiconductor device is provided with an emitter electrode on an emitter side and a collector electrode on a collector side. The device has a trench gate electrode and a structure with a plurality of layers of different conductivity types in the following order: at least one n doped source region, a p doped base layer, which surrounds the at least one source region, an n doped enhancement layer, a p doped additional well layer, an additional n doped enhancement layer, an additional p doped well layer, an n doped drift layer and a p doped collector layer. The trench gate electrode has a gate bottom, which is located closer to the collector side than the additional enhancement layer bottom. | 01-05-2012 |
20120001200 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a semiconductor chip; a protective film and an insulating film sequentially stacked over the semiconductor chip, and each having openings that expose source, drain, and gate pads; a heat dissipation terminal made of a material having a higher thermal conductivity than the insulating film; connection terminals formed on the source, drain, and gate pads and surrounded by the insulating film; and a mount substrate having connection pads. The semiconductor chip has a source electrode having a plurality of source fingers, a drain electrode having a plurality of drain fingers, and a gate electrode having a plurality of gate fingers. The source, drain, and gate pads are connected to the source electrode, the drain electrode, and the gate electrode, respectively. The connection terminals are respectively connected to the connection pads. The heat dissipation terminal is in close contact with the mount substrate. | 01-05-2012 |
20120007103 | SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR - The present disclosure relates to a silicon carbide (SiC) bipolar junction transistor (BJT), where the surface region between the emitter and base contacts ( | 01-12-2012 |
20120007104 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device employing silicon carbide, and the like are provided. In the semiconductor device, even when an electrode material and an upper electrode material are different, a problem does not take place at an interface at which these different types of metals are in contact with each other, thus obtaining high reliability in long-term use. | 01-12-2012 |
20120012860 | SIC SEMICONDUCTOR DEVICE - A SiC semiconductor device includes a reverse type MOSFET having: a substrate; a drift layer and a base region on the substrate; a base contact layer and a source region on the base region; multiple trenches having a longitudinal direction in a first direction penetrating the source region and the base region; a gate electrode in each trench via a gate insulation film; an interlayer insulation film covering the gate electrode and having a contact hole, through which the source region and the base contact layer are exposed; a source electrode coupling with the source region and the base region through the contact hole; a drain electrode on the substrate. The source region and the base contact layer extend along with a second direction perpendicular to the first direction, and are alternately arranged along with the first direction. The contact hole has a longitudinal direction in the first direction. | 01-19-2012 |
20120012861 | SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor layer of a first conductivity type; a plurality of body regions of a second conductivity type, each formed in a region extending from the surface of the semiconductor layer to a halfway portion of the same in the thickness direction, and each spaced apart from each other in a direction perpendicular to the thickness direction; source regions of the first conductivity type, each formed on the surface layer part of each body region and spaced away from the edges of each body region; a gate insulating film formed on the semiconductor layer; and gate electrodes formed on the gate insulating film. In the semiconductor layer, trenches extending between two neighboring source regions are formed by digging from the source of the semiconductor layer, the inside surface of the trenches are covered by the gate insulating film, and the gate electrodes comprise surface-facing parts, which face the surface of the semiconductor layer, and buried parts, which are buried in the trenches. | 01-19-2012 |
20120012862 | METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide and a SiC substrate made of single-crystal silicon carbide; and connecting the base substrate and SiC substrate to each other by forming an intermediate layer, which is made of carbon that is a conductor, between the base substrate and the SiC substrate. | 01-19-2012 |
20120018737 | ELECTRONIC DEVICE STRUCTURE INCLUDING A BUFFER LAYER ON A BASE LAYER - Electronic device structures that compensate for non-uniform etching on a semiconductor wafer and methods of fabricating the same are disclosed. In one embodiment, the electronic device includes a number of layers including a semiconductor base layer of a first doping type formed of a desired semiconductor material, a semiconductor buffer layer on the base layer that is also formed of the desired semiconductor material, and one or more contact layers of a second doping type on the buffer layer. The one or more contact layers are etched to form a second contact region of the electronic device. The buffer layer reduces damage to the semiconductor base layer during fabrication of the electronic device. Preferably, a thickness of the semiconductor buffer layer is selected to compensate for over-etching due to non-uniform etching on a semiconductor wafer on which the electronic device is fabricated. | 01-26-2012 |
20120018738 | ELECTRONIC DEVICE STRUCTURE WITH A SEMICONDUCTOR LEDGE LAYER FOR SURFACE PASSIVATION - Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer. | 01-26-2012 |
20120018739 | BODY CONTACT DEVICE STRUCTURE AND METHOD OF MANUFACTURE - The present invention provides a body contact device structure and a method for manufacturing the same. According to the present invention, an opening is formed by removing one end of a dummy gate stack after forming the dummy gate stack, wherein a residual portion of the dummy gate stack is a body stack comprising a body pile-up layer that directly contacts a substrate. Next, a replacement gate stack is formed in the opening, and then a body contact is formed on the body pile-up layer in the body stack. The body contact device structure formed by the method of the present invention effectively reduces the parasitic effects and the device area, and improves the performance of the device structure. | 01-26-2012 |
20120018740 | SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREFOR - A semiconductor device | 01-26-2012 |
20120018741 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus according to embodiments of the invention can include a first semiconductor device made of silicon, the first semiconductor devices being arranged collectively, whereby to form a first device group, and a second semiconductor device made of silicon carbide, the second semiconductor devices being arranged collectively, whereby to form a second device group. The apparatus can also include a wiring conductor connecting the first semiconductor device and the second semiconductor device, a cooling fin base comprising a projection formed thereon, whereby to dissipate heat generated from the first and second semiconductor devices, and the projections arranged under the second device group being spaced apart from each other more widely than the projections arranged under the first device group. | 01-26-2012 |
20120018742 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a SiC substrate, a semiconductor layer formed on the SiC substrate, a via hole penetrating through the SiC substrate and the semiconductor layer, a Cu pad that is formed on the semiconductor layer and is in contact with the via hole, and a barrier layer covering an upper face and side faces of the Cu pad, and restrains Cu diffusion. | 01-26-2012 |
20120018743 | SEMICONDUCTOR DEVICE - A MOSFET includes a silicon carbide substrate including a main surface having an off angle of not less than 50° and not more than 65° with respect to a {0001} plane, a buffer layer and a drift layer formed on the main surface, a gate oxide film formed on and in contact with the drift layer, and a p type body region of a p conductivity type formed in the drift layer to include a region in contact with the gate oxide film. The p type body region has a p type impurity density of not less than 5×10 | 01-26-2012 |
20120025204 | SEMICONDUCTOR DEVICE HAVING Si-SUBSTRATE AND PROCESS TO FORM THE SAME - A semiconductor device and a process to form the semiconductor device are disclosed. The semiconductor device includes a Si substrate, active devices primarily made of nitride based compound semiconductor material, and passive devices. The Si substrate includes a via hole piercing from the back surface to the primary surface of the Si substrate. The active device is mounted on the primary surface so as to cover at least a portion of the via hole. The metal layer cover the whole back surface, inner surfaces of the via hole, and the back surface of the active device exposed in the via hole. | 02-02-2012 |
20120025205 | SEMICONDUCTOR DEVICE - A semiconductor device includes an AlGaN layer that is provided on a SiC substrate and has an acceptor concentration equal to or higher than a donor concentration, a GaN layer provided on the AlGaN layer, and an electron supply layer that is provided on the GaN layer and has a band gap greater than that of GaN. | 02-02-2012 |
20120025206 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first GaN layer provided on a SIC substrate, a second GaN layer provided on the first GaN layer, and an electron supply layer that is provided on the second GaN layer and has a band gap greater than that of GaN, the first GaN layer having an acceptor concentration higher than that of the second GaN layer. | 02-02-2012 |
20120025207 | PROCESS FOR DIVIDING WAFER INTO INDIVIDUAL CHIPS AND SEMICONDUCTOR CHIPS - A process to divide a wafer into individual chips is disclosed. The process (1) etches semiconductor layers for an active device to form two grooves putting the virtual cut line therebetween, where the semiconductor wafer is to be divided along the virtual cut line; (2) etches the substrate in a region including the virtual cut line but offset from the groove from the back surface thereof so as to expose the semiconductor layers in the primary surface; and (3) etches the semiconductor layer exposed in step (2). | 02-02-2012 |
20120025208 | METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE AND SILICON CARBIDE SUBSTRATE - A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide and a SiC substrate made of single-crystal silicon carbide; forming a Si film made of silicon on a main surface of the base substrate; fabricating a stacked substrate by placing the SiC substrate on and in contact with the Si film; and connecting the base substrate and the SiC substrate to each other by heating the stacked substrate to convert, into silicon carbide, at least a region making contact with the base substrate and a region making contact with the SiC substrate in the Si film. | 02-02-2012 |
20120032189 | ORGANOPOLYSILOXANE COMPOSITION AND SEMICONDUCTOR APPARATUS - Provided is an organopolysiloxane composition that provides a cured product which has excellent heat resistance and does not peel or crack even under high temperatures. The organopolysiloxane composition comprises (A) an organopolysiloxane having difunctional siloxane units (D units) and trifunctional siloxane units (T units), and a weight-average molecular weight of 37,000 to 140,000 in which the molar ratio (T/D) of the T units to the D units is 0.3 to 0.8; and (B) an organopolysiloxane having the difunctional siloxane units (D units) and the trifunctional siloxane units (T units), and a weight-average molecular weight of 1,000 to 60,000 in which the molar ratio (T/D) of the T units to the D units is 0.15 or less, the organopolysiloxane composition being characterized by having a molar ratio (B/A) of the organopolysiloxane (B) to the organopolysiloxane (A) of 1.5 to 6.5. | 02-09-2012 |
20120032190 | PACKAGE AND FABRICATION METHOD OF THE SAME - According to one embodiment, provided are a package utilized for a high frequency semiconductor device and a fabrication method for such the package, the package including: a conductive base plate including a CTE control layer composed of compound material, and a heat conduction layer disposed on the CTE control layer and composed of Cu. | 02-09-2012 |
20120032191 | METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE AND SILICON CARBIDE SUBSTRATE - A method for manufacturing a silicon carbide substrate ( | 02-09-2012 |
20120037920 | Silicone Carbide Trench Semiconductor Device - A semiconductor device as described herein includes a silicon carbide semiconductor body. A trench extends into the silicon carbide semiconductor body at a first surface. A gate dielectric and a gate electrode are formed within the trench. A body zone of a first conductivity type adjoins to a sidewall of the trench, the body zone being electrically coupled to a contact via a body contact zone including a higher maximum concentration of dopants than the body zone. An extension zone of the first conductivity type is electrically coupled to the contact via the body zone, wherein a maximum concentration of dopants of the extension zone along a vertical direction perpendicular to the first surface is higher than the maximum concentration of dopants of the body zone along the vertical direction. A distance between the first surface and a bottom side of the extension zone is larger than the distance between the first surface and the bottom side of the trench. | 02-16-2012 |
20120037921 | Electrical Devices With Enhanced Electrochemical Activity and Manufacturing Methods Thereof - In some aspects, a device is provided having a member with a region of enhanced electrochemical activity. In one aspect, a sensor of enhanced electrochemical activity is provided for detecting an analyte concentration level in a bio-fluid sample. The sensor may include a sensor member of a semiconductor material wherein the sensor member has a surface region of enhanced electrochemical activity. In other aspects, the member may be made of semiconducting foam having a surface region of enhanced electrochemical activity. In some embodiments, the region may be thermally-induced. Manufacturing methods and apparatus are also provided, as are numerous other aspects. | 02-16-2012 |
20120037922 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method. A semiconductor device includes: a silicon carbide substrate; a first-conductive-type first silicon carbide layer provided on a first principal surface of the silicon carbide substrate; a second-conductive-type first silicon carbide region formed at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region formed at a surface of the first silicon carbide region; a second-conductive-type third silicon carbide region formed below the second silicon carbide region; a trench piercing through the second silicon carbide region to reach the third silicon carbide region; a gate insulating film; a gate electrode; an interlayer insulating film with which the gate electrode is covered; a first electrode that is formed on the second silicon carbide region and the interlayer insulating film in a side surface of the trench while containing a metallic element selected from a group consisting of Ni, Ti, Ta, Mo, and W; a second electrode that is formed on the third silicon carbide region in a bottom portion of the trench and the first electrode while containing Al; a first main electrode formed on the second electrode; and a second main electrode formed on a second principal surface of the silicon carbide substrate. | 02-16-2012 |
20120037923 | LIGHT EMITTING DIODE ELEMENT AND METHOD FOR PRODUCING THE SAME - [PROBLEM] To provide a light emitting diode which can obtain emission at shorter wavelength side of emission range of normal 6H-type SiC doped with B and N, and a method for manufacturing the same. | 02-16-2012 |
20120037924 | Junction Field-Effect Transistor - A junction field-effect transistor ( | 02-16-2012 |
20120043556 | EPITAXIAL GROWTH OF SILICON DOPED WITH CARBON AND PHOSPHORUS USING HYDROGEN CARRIER GAS - A method for depositing epitaxial films of silicon carbon (Si:C). In one embodiment, the method includes depositing an n-type doped silicon carbon (Si:C) semiconductor material on a semiconductor deposition surface using a deposition gas precursor composed of a silane containing gas precursor, a carbon containing gas precursor, and an n-type gas dopant source. The deposition gas precursor is introduced to the semiconductor deposition surface with a hydrogen (H | 02-23-2012 |
20120043557 | SEMICONDUCTOR LIGHT-EMITTING DEVICE WITH IMPROVED LIGHT EXTRACTION EFFICIENCY - The present invention provides a semiconductor light-emitting device. The light-emitting device comprises a first conductive clad layer, an active layer, and a second conductive clad layer sequentially formed on a substrate. In the light-emitting device, the substrate has one or more side patterns formed on an upper surface thereof while being joined to one or more edges of the upper surface. The side patterns consist of protrusions or depressions so as to scatter or diffract light to an upper portion or a lower portion of the light-emitting device. | 02-23-2012 |
20120056194 | BARRIER STRUCTURES AND METHODS OF FORMING SAME TO FACILITATE SILICON CARBIDE EPITAXY AND SILICON CARBIDE-BASED MEMORY FABRICATION - Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, wafers and methods to form barrier structures to facilitate formation of silicon carbide epitaxy on a substrate, such as a silicon-based substrate, for fabricating various silicon carbide-based semiconductor devices, including silicon carbide-based memory elements and cells. In some embodiments, a semiconductor wafer includes a silicon substrate, a barrier-seed layer disposed over the silicon substrate, and a silicon carbide layer formed over the barrier-seed layer. The semiconductor wafer can be used to form a variety of SiC-based semiconductor devices. In one embodiment, a silicon carbide-based memory element is formed to include barrier-seed layer, multiple silicon carbide layers formed over the barrier-seed layer, and a dielectric layer formed over the multiple silicon carbide layers. | 03-08-2012 |
20120056195 | SEMICONDUCTOR DEVICE - One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface. | 03-08-2012 |
20120056196 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to an embodiment includes a first-conductive-type semiconductor substrate; a first-conductive-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductive-type second semiconductor layer epitaxially formed on the first semiconductor layer; and a second-conductive-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer. The semiconductor device also includes a recess formed in the third semiconductor layer, and at least a corner portion of a side face and a bottom surface is located in the second semiconductor layer. The semiconductor device also includes a first electrode in contact with the third semiconductor layer; a second electrode connected to the first electrode while being in contact with the second semiconductor layer at the bottom surface of the recess; and a third electrode in contact with a lower surface of the semiconductor substrate. | 03-08-2012 |
20120056197 | SEMICONDUCTOR RECTIFYING DEVICE - A wide bandgap semiconductor rectifying device of an embodiment includes a first-conductive-type wide bandgap semiconductor substrate and a first-conductive-type semiconductor layer that has an impurity concentration lower than that of the substrate. The device also includes a first-conductive-type first semiconductor region, and a second-conductive-type second semiconductor region that is formed between the first regions. The device also includes second-conductive-type third semiconductor regions in which at least part of the third regions are connected to the second wide bandgap semiconductor region, the third regions being formed between the first regions, the third regions having a width narrower than that of the second region. The device also includes a first electrode and a second electrode. In the device, a direction in which a longitudinal direction of the third regions are projected onto a (0001) plane of the layer has an angle of 90±30 degrees with respect to a <11-20> direction of the layer. A gap between the third regions is not lower than 2 | 03-08-2012 |
20120056198 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device according to an embodiment includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the second conductivity type, a first electrode and a second electrode. The first semiconductor region is formed on at least a part of the first semiconductor layer formed on the semiconductor substrate. The second semiconductor region is formed on another part of the first semiconductor layer to reach an inside of the first semiconductor layer and having an impurity concentration higher than that of the first semiconductor region. The first electrode is formed on the second semiconductor region and a third semiconductor regions formed in a part of the first semiconductor region. The second electrode is formed to be in contact with a rear surface of the semiconductor substrate. | 03-08-2012 |
20120056199 | Self-supporting CVD diamond film and method for producing a self-supporting CVD diamond film - The invention relates to a self-supporting CVD diamond film comprising a plurality of diamond layers ( | 03-08-2012 |
20120056200 | INTEGRATED ELECTRONIC DEVICE WITH EDGE-TERMINATION STRUCTURE AND MANUFACTURING METHOD THEREOF - An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region. | 03-08-2012 |
20120056201 | INSULATED GATE BIPOLAR TRANSISTOR - An IGBT, which is a vertical type IGBT allowing for reduced on-resistance while restraining defects from being produced, includes: a silicon carbide substrate, a drift layer, a well region, an n | 03-08-2012 |
20120056202 | SEMICONDUCTOR DEVICE - A MOSFET, which is a semiconductor device allowing for reduced on-resistance while restraining stacking faults from being produced due to heat treatment in a device manufacturing process, includes: a silicon carbide substrate; an active layer made of single-crystal silicon carbide and disposed on one main surface of the silicon carbide substrate; a source contact electrode disposed on the active layer; and a drain electrode formed on the other main surface of the silicon carbide substrate. The silicon carbide substrate includes: a base layer made of silicon carbide; and a SiC layer made of single-crystal silicon carbide and disposed on the base layer. Further, the base layer has an impurity concentration greater than 2×10 | 03-08-2012 |
20120056203 | SEMICONDUCTOR DEVICE - A JFET, which is a semiconductor device allowing for reduced manufacturing cost, includes: a silicon carbide substrate; an active layer made of single-crystal silicon carbide and disposed on one main surface of the silicon carbide substrate; a source electrode disposed on the active layer; and a drain electrode formed on the active layer and separated from the source electrode. The silicon carbide substrate includes: a base layer made of single-crystal silicon carbide, and a SiC layer made of single-crystal silicon carbide and disposed on the base layer. The SiC layer has a defect density smaller than that of the base layer. | 03-08-2012 |
20120061681 | MECHANISM OF FORMING SIC CRYSTALLINE ON SI SUBSTRATES TO ALLOW INTEGRATION OF GAN AND SI ELECTRONICS - The mechanisms of forming SiC crystalline regions on Si substrate described above enable formation and integration of GaN-based devices and Si-based devices on a same substrate. The SiC crystalline regions are formed by implanting carbon into regions of Si substrate and then annealing the substrate. An implant-stop layer is used to cover the Si device regions during formation of the SiC crystalline regions. | 03-15-2012 |
20120061682 | SIC SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A SiC semiconductor device includes: a substrate, a drift layer, and a base region stacked in this order; first and second source regions and a contact layer in the base region; a trench penetrating the source and base regions; a gate electrode in the trench; an interlayer insulation film with a contact hole covering the gate electrode; a source electrode coupling with the source region and the contact layer via the contact hole; a drain electrode on the substrate; and a metal silicide film. The high concentration second source region is shallower than the low concentration first source region, and has a part covered with the interlayer insulation film, which includes a low concentration first portion near a surface and a high concentration second portion deeper than the first portion. The metal silicide film on the second part has a thickness larger than the first portion. | 03-15-2012 |
20120061683 | GROUP III NITRIDE SEMICONDUCTOR GROWTH SUBSTRATE, GROUP III NITRIDE SEMICONDUCTOR EPITAXIAL SUBSTRATE, GROUP III NITRIDE SEMICONDUCTOR ELEMENT AND GROUP III NITRIDE SEMICONDUCTOR FREE-STANDING SUBSTRATE, AND METHOD OF PRODUCING THE SAME - An object of the present invention is to provide a Group III nitride semiconductor epitaxial substrate, a Group III nitride semiconductor element, and a Group III nitride semiconductor free-standing substrate, which have good crystallinity, with not only AlGaN, GaN, and GaInN the growth temperature of which is 1050° C. or less, but also with Al | 03-15-2012 |
20120061684 | TRANSISTOR DEVICES AND METHODS OF MAKING - In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers. | 03-15-2012 |
20120061685 | Memory Devices And Memory Cells - A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel. | 03-15-2012 |
20120061686 | SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SILICON CARBIDE SUBSTRATE - A silicon carbide substrate allowing reduction in cost for manufacturing a semiconductor device including a silicon carbide substrate includes a base substrate composed of silicon carbide and an SiC layer composed of single crystal silicon carbide different from the base substrate and arranged on the base substrate in contact therewith. Thus, the silicon carbide substrate | 03-15-2012 |
20120061687 | SILICON CARBIDE SUBSTRATE AND SEMICONDUCTOR DEVICE - A silicon carbide substrate, which allows for reduced resistivity in the thickness direction thereof while restraining stacking faults from being produced due to heat treatment, includes: a base layer made of silicon carbide; and a SiC layer made of single-crystal silicon carbide and disposed on one main surface of the base layer. The base layer has an impurity concentration greater than 2×10 | 03-15-2012 |
20120061688 | POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE POWER SEMICONDUCTOR DEVICE - In a power semiconductor device that switches at a high speed, a displacement current flows at a time of switching, so that a high voltage occurs which may cause breakdown of a thin insulating film such as a gate insulating film. A semiconductor device includes: a semiconductor substrate of a first conductivity type; a drift layer of the first conductivity type formed on a first main surface of the semiconductor substrate; a first well region of a second conductivity type formed in a part of a surface layer of the drift layer; a second well region of the second conductivity type formed in a part of the surface layer of the drift layer at a distance from the first well region, the second well region having a smaller area than that of the first well region when seen above an upper surface thereof; a low-resistance region of the first conductivity type formed in a surface layer of the first well region, the low-resistance region having a higher impurity concentration than that of the first well region; a gate insulating film formed on and in contact with a surface of the first well region; and a gate electrode formed on and in contact with a surface of the gate insulating film. | 03-15-2012 |
20120068193 | STRUCTURE AND METHOD FOR INCREASING STRAIN IN A DEVICE - A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include growing an epitaxial layer, performing a cold carbon or cluster carbon pre-amorphization implantation to implant substitutional carbon into the epitaxial layer, forming a tensile cap over the epitaxial layer, and then annealing to recrystallize the amorphous layer to create a stress memorization technique (SMT) effect. The epitaxial layer will therefore include substitutional carbon and have a memorized tensile stress induced by the SMT. Embodiments of this invention can also include a lower epitaxial layer under the epitaxial layer, the lower epitaxial layer comprising for example, a silicon carbon phosphorous (SiCP) layer. | 03-22-2012 |
20120068194 | SILICON CARBIDE SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device, wherein the method comprises applying a first layer comprising silicon to a second layer comprising silicon carbide, wherein an interface is defined between the first and second layers; and oxidising sonic or all of the first layer. | 03-22-2012 |
20120068195 | METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE AND SILICON CARBIDE SUBSTRATE - A method for manufacturing a silicon carbide substrate includes the steps of: preparing a plurality of SiC substrates each made of single-crystal silicon carbide; forming a base layer made of silicon carbide and holding the plurality of SiC substrates, which are arranged side by side when viewed in a planar view; and forming a filling portion filling a gap between the plurality of SiC substrates. | 03-22-2012 |
20120074428 | SEMICONDUCTOR MODULE INCLUDING A SWITCH AND NON-CENTRAL DIODE - A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced. | 03-29-2012 |
20120074429 | GROWTH OF NON-POLAR M-PLANE III-NITRIDE FILM USING METALORGANIC CHEMICAL VAPOR DEPOSITION (MOCVD) - A method of growing non-polar m-plane III-nitride film, such as GaN, AlN, AlGaN or InGaN, wherein the non-polar m-plane III-nitride film is grown on a suitable substrate, such as an m-SiC, m-GaN, LiGaO | 03-29-2012 |
20120080690 | Method for Manufacturing a Composite Wafer Having a Graphite Core, and Composite Wafer Having a Graphite Core - According to an embodiment, a composite wafer includes a carrier substrate having a graphite core and a monocrystalline semiconductor layer attached to the carrier substrate. | 04-05-2012 |
20120091468 | SEMICONDUCTOR DEVICE WITH INTERPOSER AND METHOD MANUFACTURING SAME - A semiconductor device includes an interposer mounting a semiconductor chip. The interposer includes a silicon substrate having a recessed region formed on a first surface, a first through via penetrating a first region of the silicon substrate from the first surface to an opposing second surface, an insulator disposed in the recessed region, and a first wire pattern at least partially disposed on the insulator and electrically connecting the first through via to the semiconductor chip | 04-19-2012 |
20120091469 | Semiconductor Devices Having Shallow Junctions - Semiconductor devices are provided including a substrate having a first surface and a second surface recessed from opposite sides of the first surface, a gate pattern formed on the first surface and having a gate insulating layer and a gate electrode, a carbon-doped silicon buffer layer formed on the second surface, and source and drain regions doped with an n-type dopant or p-type dopant, epitaxially grown on the silicon buffer layer to be elevated from a top surface of the gate insulating layer. | 04-19-2012 |
20120091470 | Programmable Gate III-Nitride Power Transistor - A III-nitride semiconductor device which includes a charged floating gate electrode. | 04-19-2012 |
20120091471 | LIGHTLY DOPED SILICON CARBIDE WAFER AND USE THEREOF IN HIGH POWER DEVICES - A semiconductor device including a drift zone of a first conductivity type serving as a substrate layer having a front side and a back side. A first contact electrode is arranged at the front side of the drift zone. A control region is arranged at the front side and controls an injection of carriers of at least the first conductivity type into the drift zone. A second contact electrode is arranged at the backside of the drift zone. The drift zone is arranged to carry a carrier flow between the first and the second contact electrode. The drift zone includes a silicon carbide wafer with a net carrier concentration less than 10 | 04-19-2012 |
20120091472 | SILICON CARBIDE SUBSTRATE - A first circular surface is provided with a first notch portion having a first shape. A second circular surface is opposite to the first circular surface and is provided with a second notch portion having a second shape. A side surface connects the first circular surface and the second circular surface to each other. The first notch portion and the second notch portion are opposite to each other. The side surface has a first depression connecting the first notch portion and the second notch portion to each other. | 04-19-2012 |
20120097974 | POWER SEMICONDUCTOR DEVICE - A method and apparatus for achieving high current gain, and low on-resistance, from a Bipolar Junction Transistor (BJT) in high temperature and high power applications are disclosed. In some embodiments, a thin doped delta layer is inserted at the base emitter junction but inside the base layer. In addition, in some embodiments, a surface recombination layer is inserted between the emitter-base regions of the device. In some embodiments, use of an ion implantation step is avoided to achieve simplicity and low cost of manufacture. | 04-26-2012 |
20120097975 | Nitride-Based Semiconductor Substrates Having Hollow Member Pattern And Methods Of Fabricating The Same - A nitride-based semiconductor substrate may includes a plurality of hollow member patterns arranged on a substrate, a nitride-based seed layer formed on the substrate between the plurality of hollow member patterns, and a nitride-based buffer layer on the nitride-based seed layer so as to cover the plurality of hollow member patterns, wherein the plurality of hollow member patterns contact the substrate in a first direction and both ends of each of the plurality of hollow member patterns are open in the first direction. | 04-26-2012 |
20120097976 | LIGHT EMITTING DIODE CHIP AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode chip includes an electrically conductive substrate, a reflecting layer disposed on the substrate, a semiconductor structure formed on the reflecting layer, an electrode disposed on the semiconductor structure, and a plurality of slots extending through the semiconductor structure. The semiconductor structure includes a P-type semiconductor layer formed on the reflecting layer, a light-emitting layer formed on the P-type semiconductor layer, and an N-type semiconductor layer formed on the light-emitting layer. A current diffusing region is defined in the semiconductor structure and around the electrode. The slots are located outside the current diffusing region. | 04-26-2012 |
20120097977 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device of the present invention has a (110)-plane-orientation silicon substrate and a p channel type field effect transistor formed in a pMIS region. The p channel type field effect transistor includes a gate electrode disposed via a gate insulation film, and source/drain regions disposed inside a trench disposed in the silicon substrate on the opposite sides of the gate electrode, and including SiGe larger in lattice constant than Si. The trench has a (100)-plane-orientation first inclined surface, and a (100)-plane-orientation second inclined surface crossing the first inclined surface at a sidewall part situated on the gate electrode side. With the configuration, the angle formed between the surface (110) plane and the (100) plane of the substrate is 45°, so that the first inclined surface is formed at a relatively acute angle. This can effectively apply a compressive strain to a channel region of the p channel type MISFET. | 04-26-2012 |
20120097978 | PHOTO-SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A photo-semiconductor device comprises a photoconductive semiconductor film provided with electrodes and formed on a second substrate, the semiconductor film being formed by epitaxial growth on a first semiconductor substrate different from the second substrate, the second substrate being also provided with electrodes, the electrodes of the second substrate and the electrodes of the photoconductive semiconductor film being held in contact with each other. | 04-26-2012 |
20120097979 | STRUCTURALLY ROBUST POWER SWITCHING ASSEMBLY - A structurally robust power switching assembly, that has a first rigid structural unit, defining a first unit major surface that is patterned to define a plurality of mutually electrically isolated, electrically conductive paths. Also, a similar, second rigid structural unit is spaced apart from the first unit major surface. Finally, a transistor is interposed between and electrically connected to the first unit major surface and the second unit major surface. | 04-26-2012 |
20120097980 | SILICON CARBIDE INSULATING GATE TYPE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A termination configuration of a silicon carbide insulating gate type semiconductor device includes a semiconductor layer of a first conductivity type having a first main face, a gate electrode, and a source interconnection, as well as a circumferential resurf region. The semiconductor layer includes a body region of a second conductivity type, a source region of the first conductivity type, a contact region of the second conductivity type, and a circumferential resurf region of the second conductivity type. A width of a portion of the circumferential resurf region excluding the body region is greater than or equal to ½ the thickness of at least the semiconductor layer. A silicon carbide insulating gate type semiconductor device of high breakdown voltage and high performance can be provided. | 04-26-2012 |
20120104414 | MINIATURE PACKAGING FOR DISCRETE CIRCUIT COMPONENTS - A miniature packaging for a discrete circuit component that comprises a core dice for the circuit component fabricated on a semiconductor substrate. The core dice has at least a pair of metallization electrodes formed on the same or different surfaces of the semiconductor substrate. An end electrode covers a corresponding side surface of the core dice and electrically connects to a corresponding one of the pair of metallization electrodes. The end electrode extends toward the center of the core dice on both the top and bottom surface of the core dice. | 05-03-2012 |
20120104415 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an emitter electrode formed of a silicide film, and provided on a semiconductor layer; an insulating film provided on the emitter electrode; and an electrode pad made of Al, and provided on the insulating film. | 05-03-2012 |
20120104416 | BIPOLAR JUNCTION TRANSISTOR GUARD RING STRUCTURES AND METHOD OF FABRICATING THEREOF - Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer. | 05-03-2012 |
20120104417 | SILICON CARBIDE SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING THE SAME, AND SILICON CARBIDE DEVICE - A silicon carbide semiconductor element and a manufacturing method thereof are disclosed in which a low contact resistance is attained between an electrode film and a wiring conductor element, and the wiring conductor element is hardly detached from the electrode film. In the method, a nickel film and a nickel oxide film are laminated in this order on a surface of an n-type silicon carbide substrate or an n-type silicon carbide region of a silicon carbide substrate, followed by a heat treatment under a non-oxidizing condition. The heat treatment transforms a portion of the nickel film into a nickel silicide film. Then, the nickel oxide film is removed with hydrochloric acid solution, and subsequently, a nickel aluminum film and an aluminum film are laminated in this order on a surface of the nickel silicide film. | 05-03-2012 |
20120112206 | ASYMMETRIC HETERO-STRUCTURE FET AND METHOD OF MANUFACTURE - An asymmetric hetero-structure FET and method of manufacture is provided. The structure includes a semiconductor substrate and an epitaxially grown semiconductor layer on the semiconductor substrate. The epitaxially grown semiconductor layer includes an alloy having a band structure and thickness that confines inversion carriers in a channel region, and a thicker portion extending deeper into the semiconductor structure at a doped edge to avoid confinement of the inversion carriers at the doped edge. | 05-10-2012 |
20120112207 | METHOD TO REDUCE GROUND-PLANE POISONING OF EXTREMELY-THIN SOI (ETSOI) LAYER WITH THIN BURIED OXIDE - The present disclosure, which is directed to ultra-thin-body-and-BOX and Double BOX fully depleted SOI devices having an epitaxial diffusion-retarding semiconductor layer that slows dopant diffusion into the SOI channel, and a method of making these devices. Dopant concentrations in the SOI channels of the devices of the present disclosure having an epitaxial diffusion-retarding semiconductor layer between the substrate and SOI channel are approximately 50 times less than the dopant concentrations measured in SOI channels of devices without the epitaxial diffusion-retarding semiconductor layer. | 05-10-2012 |
20120112208 | STRESSED TRANSISTOR WITH IMPROVED METASTABILITY - An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material. | 05-10-2012 |
20120112209 | SILICON CARBIDE SUBSTRATE FABRICATION METHOD, SEMICONDUCTOR DEVICE FABRICATION METHOD, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method of fabricating a silicon carbide substrate that can reduce the fabrication cost of a semiconductor device employing the silicon carbide substrate includes the steps of: preparing a SiC substrate made of single crystal silicon carbide; arranging a base substrate in a vessel so as to face one main face of the SiC substrate; forming a base layer made of silicon carbide so as to contact one main face of the SiC substrate by heating a base substrate to a temperature range greater than or equal to a sublimation temperature of silicon carbide constituting the base substrate. In the step of forming a base layer, a silicon generation source made of a substance including silicon is arranged in the vessel, in addition to the SiC substrate and the base substrate. | 05-10-2012 |
20120119224 | COMPOSITE SUBSTRATE AND METHOD FOR MANUFACTURING COMPOSITE SUBSTRATE - A metal film | 05-17-2012 |
20120119225 | SILICON CARBIDE SUBSTRATE, EPITAXIAL LAYER PROVIDED SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE - The present invention provides a silicon carbide substrate, an epitaxial layer provided substrate, a semiconductor device, and a method for manufacturing the silicon carbide substrate, each of which achieves reduced on-resistance. The silicon carbide substrate is a silicon carbide substrate having a main surface, and includes: a SiC single-crystal substrate formed in at least a portion of the main surface; and a base member disposed to surround the SiC single-crystal substrate. The base member includes a boundary region and a base region. The boundary region is adjacent to the SiC single-crystal substrate in a direction along the main surface, and has a crystal grain boundary therein. The base region is adjacent to the SiC single-crystal substrate in a direction perpendicular to the main surface, and has an impurity concentration higher than that of the SiC single-crystal substrate. | 05-17-2012 |
20120119226 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - A semiconductor device includes a substrate; a nitride based compound semiconductor layer placed on the substrate; an active area which is placed on the nitride based compound semiconductor layer, and is composed of an aluminum gallium nitride layer (Al | 05-17-2012 |
20120126243 | TRANSISTOR INCLUDING SHALLOW TRENCH AND ELECTRICALLY CONDUCTIVE SUBSTRATE FOR IMPROVED RF GROUNDING - Disclosed is an RF power FET or HEMT including an electrically-conductive substrate, a grounding metallization layer disposed on a bottom surface of the electrically-conductive substrate, an active area comprising at least one cell including source, gate and drain electrodes disposed over a top surface of the electrically-conductive substrate, and an electrically-conductive shallow trench electrically connecting the source electrode to the grounding metallization layer by way of the electrically-conductive substrate. This configuration results in the effective RF ground being very close to the active area of the FET in order to reduce parasitic source inductance and resistance. This results in potentially higher gain, higher saturation point, higher 3 | 05-24-2012 |
20120126244 | SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME - The invention provides a STI structure and a method for manufacturing the same. The STI includes a semiconductor substrate; a first trench formed on the upper surface of the semiconductor substrate and filled with an epitaxial layer, wherein the upper surface of the epitaxial layer is higher than that of the semiconductor substrate; and a second trench formed on the epitaxial layer and filled with a first dielectric layer, wherein the upper surface of the first dielectric layer is flush with that of the epitaxial layer, and the width of the second trench is smaller than that of the first trench. The invention reduces the influences of divots on performance of the semiconductor device. | 05-24-2012 |
20120126245 | SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME - The invention provides a STI structure and method for forming the same. The STI structure includes a semiconductor substrate; a first trench embedded in the semiconductor substrate and filled up with a first dielectric layer; and a second trench formed on a top surface of the semiconductor substrate and interconnected with the first trench, wherein the second trench is filled up with a second dielectric layer, a top surface of the second dielectric layer is flushed with that of the semiconductor substrate, and the second trench has a width smaller than that of the first trench. The invention reduces dimension of divots and improves performance of the semiconductor device. | 05-24-2012 |
20120126246 | PACKAGE AND HIGH FREQUENCY TERMINAL STRUCTURE FOR THE SAME - According to one embodiment, provided is a package and high frequency terminal structure for the same including: a conductive base plate; a semiconductor device disposed on the conductive base plate; a metal wall disposed on the conductive base plate to house the semiconductor device; a through-hole disposed in input and output units of the metal wall; a lower layer feed through inserted into the through-hole and disposed on the conductive base plate; and an upper layer feed through disposed on the lower layer feed through, and adhered to a sidewall of the metal wall. The lower layer feed through is surrounded by the metal wall. | 05-24-2012 |
20120126247 | SELF-POWERED INTEGRATED CIRCUIT WITH MULTI-JUNCTION PHOTOVOLTAIC CELL - A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a multiple photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the multiple photovoltaic cell portion. | 05-24-2012 |
20120126248 | MEMBRANE HAVING MEANS FOR STATE MONITORING - The invention relates to a membrane. Partly permeable membranes often have holes or perforations having a specific diameter to allow substances having a smaller particle diameter to pass through, but to hold back substances having a larger particle diameter. Such membranes are subject to wear primarily at the holes, i.e. cracks form which grow through the membrane proceeding from a hole. Particularly in the case of micromechanical membranes having holes having a small diameter in the range of 1 μm or less, it is very difficult to detect the state of the membrane, in particular whether the latter has cracks. Membranes having cracks can then undesirably allow passage even of those particles which should actually be held back. In medical or hygienic applications, the function can then be impaired. | 05-24-2012 |
20120126249 | SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes: a semiconductor layer made of SiC; an impurity region formed by doping the semiconductor layer with an impurity; and a contact wire formed on the semiconductor layer in contact with the impurity region, while the contact wire has a polysilicon layer in the portion in contact with the impurity region, and has a metal layer on the polysilicon layer. | 05-24-2012 |
20120126250 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - The present invention provides a silicon carbide semiconductor device having an ohmic electrode improved in adhesion of a wire thereto by preventing deposition of carbon so as not to form a Schottky contact, as well as a method for manufacturing such a silicon carbide semiconductor device. In the SiC semiconductor device, upon forming the ohmic electrode, a first metal layer made of one first metallic element is formed on one main surface of a SiC layer. Further, a Si layer made of Si is formed on an opposite surface of the first metal layer to its surface facing the SiC layer. The stacked structure thus formed is subjected to thermal treatment. In this way, there can be obtained a silicon carbide semiconductor device having an ohmic electrode adhered well to a wire by preventing deposition of carbon atoms on the surface layer of the electrode and formation of a Schottky contact resulting from Si and SiC. | 05-24-2012 |
20120126251 | METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide substrate achieves reduced manufacturing cost. The method includes the steps of: preparing a base substrate and a SiC substrate; fabricating a stacked substrate by stacking the base substrate and the SiC substrate; fabricating a connected substrate by heating the stacked substrate; transferring a void, formed at a connection interface, in a thickness direction of the connected substrate by heating the connected substrate to cause the base substrate to have a temperature higher than that of the SiC substrate; and removing the void by removing a region including a main surface of the base substrate opposite to the SiC substrate. | 05-24-2012 |
20120132923 | SUBSTRATE FOR INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME - The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer. | 05-31-2012 |
20120132924 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 μm from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak. | 05-31-2012 |
20120132925 | METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE, AND A CORRESPONDING SEMICONDUCTOR STRUCTURE - A method for manufacturing a semiconductor structure is provided which includes the following steps: a crystalline semiconductor substrate ( | 05-31-2012 |
20120132926 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type made of SiC having an Si surface; a gate trench dug down from the surface of the semiconductor layer; a gate insulating film formed on a bottom surface and a side surface of the gate trench so that the ratio of the thickness of a portion located on the bottom surface to the thickness of a portion located on the side surface is 0.3 to 1.0; and a gate electrode embedded in the gate trench through the gate insulating film. | 05-31-2012 |
20120132927 | OHMIC ELECTRODE AND METHOD OF FORMING THE SAME - An ohmic electrode for a p-type SiC semiconductor, and a method of forming the ohmic electrode. The ohmic electrode has an ohmic electrode layer, which has an amorphous structure and which is made of a Ti | 05-31-2012 |
20120132928 | OHMIC ELECTRODE FOR USE IN A SEMICONDUCTOR DIAMOND DEVICE - In a semiconductor diamond device, there is provided an ohmic electrode that is chemically, and thermally stable, and is excellent in respect of low contact resistance, and high heat resistance. A nickel-chromium alloy, or a nickel-chromium compound, containing Ni, and Cr such as Ni | 05-31-2012 |
20120138953 | STRUCTURE AND METHOD FOR Vt TUNING AND SHORT CHANNEL CONTROL WITH HIGH K/METAL GATE MOSFETs - A semiconductor device is provided that includes a semiconductor substrate having a well region located within an upper region thereof. A semiconductor material stack is located on the well region. The semiconductor material stack includes, from bottom to top, a semiconductor-containing buffer layer and a non-doped semiconductor-containing channel layer; the semiconductor-containing buffer layer of the semiconductor material stack is located directly on an upper surface of the well region. The structure also includes a gate material stack located directly on an upper surface of the non-doped semiconductor-containing channel layer. The gate material stack employed in the present disclosure includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a polysilicon layer. | 06-07-2012 |
20120138954 | SEMICONDUCTOR DEVICE - According to one embodiment, provided is a semiconductor device includes: a high frequency semiconductor chip; an input matching circuit disposed at the input side of the high frequency semiconductor chip; an output matching circuit disposed at the output side of the high frequency semiconductor chip; a high frequency input terminal connected to the input matching circuit; a high frequency output terminal connected to the output matching circuit, and a smoothing capacitor terminal connected to the high frequency semiconductor chip. The high frequency semiconductor chip, the input matching circuit and the output matching circuit are housed by one package. | 06-07-2012 |
20120138955 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A compound semiconductor device includes a substrate; an initial layer formed over the substrate; and a core layer which is formed over the initial layer and contains a Group III-V compound semiconductor. The initial layer is a layer of Group III atoms of the Group III-V compound semiconductor contained in the core layer. | 06-07-2012 |
20120138956 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device includes: a substrate; an electron transit layer formed over the substrate; an electron supply layer formed over the electron transit layer; and a buffer layer formed between the substrate and the electron transit layer and including Al | 06-07-2012 |
20120138957 | LIGHT EMITTING DEVICE - Embodiments disclose a light emitting device including a substrate, a buffer layer disposed on an R-plane of the substrate, the buffer layer having a rock salt structured nitride, and a light emitting structure arranged on the buffer layer, the light emitting structure being grown in an a-plane. | 06-07-2012 |
20120138958 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device is provided which has a lower on-resistance and a higher breakdown voltage than those of a conventional silicon carbide semiconductor device. A JFET includes an n type substrate, a p type layer, an n type layer, a source region, a drain region, and a gate region. The n type substrate has a main surface having an off angle of not less than 32° relative to the {0001} plane, and is made of silicon carbide (SiC). The p type layer is formed on the main surface of the n type substrate, and has p type conductivity. The n type layer is formed on the p type layer, and has n type conductivity. The source region and the drain region are formed in n type layer with a space interposed therebetween. The gate region is formed in the n type layer at a region between the source region and the drain region. | 06-07-2012 |
20120146050 | MEASUREMENT OF CMOS DEVICE CHANNEL STRAIN BY X-RAY DIFFRACTION - A direct measurement of lattice spacing by X-ray diffraction is performed on a periodic array of unit structures provided on a substrate including semiconductor devices. Each unit structure includes a single crystalline strained material region and at least one stress-generating material region. For example, the single crystalline strained material region may be a structure simulating a channel of a field effect transistor, and the at least one stress-generating material region may be a single crystalline semiconductor region in epitaxial alignment with the single crystalline strained material region. The direct measurement can be performed in-situ at various processing states to provide in-line monitoring of the strain in field effect transistors in actual semiconductor devices. | 06-14-2012 |
20120146051 | NITRIDE BASED SEMICONDUCTOR DEVICE - Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device including a base substrate; a semiconductor layer disposed on the base substrate; and an electrode structure disposed on the semiconductor layer, wherein the electrode structure includes: a first ohmic electrode ohmic-contacting the semiconductor layer; a second ohmic electrode ohmic-contacting the semiconductor layer and spaced apart from the first ohmic electrode; and a schottky electrode unit schottky-contacting the semiconductor layer and covering the second ohmic electrode. | 06-14-2012 |
20120146052 | NITRIDE BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device including: a base substrate; an epitaxial growth layer disposed on the base substrate and generating 2-dimensional electron gas (2DEG) therein; and an electrode structure disposed on the epitaxial growth layer and having an extension extending into the epitaxial growth layer, wherein the epitaxial growth layer includes a depressing part depressed thereinto from the surface of the epitaxial growth layer, and the depressing part includes: a first area in which the extension is disposed; and a second area that is an area other than the first area. | 06-14-2012 |
20120146053 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, first gate sidewalls formed on both sides of the gate electrode, and a source/drain semiconductor layer formed on the semiconductor substrate to sandwich the first gate sidewalls with the gate electrode. Further, second gate sidewalls are provided on the first gate sidewalls and the source/drain semiconductor layer at both sides of the gate electrode, wherein the boundary of each of the second gate sidewalls with each of the first gate sidewalls is terminated at the side surface of the gate electrode, and each of the second gate sidewalls has a smaller Young's modulus and a lower dielectric constant than each of the first gate sidewalls. | 06-14-2012 |
20120146054 | MOSFET WITH SOURCE SIDE ONLY STRESS - An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved. | 06-14-2012 |
20120146055 | SiC SEMICONDUCTOR DEVICE - A SiC semiconductor device includes a SiC semiconductor layer having a first-conductivity-type impurity, a field insulation film formed on a front surface of the SiC semiconductor layer and provided with an opening for exposing therethrough the front surface of the SiC semiconductor layer, an electrode connected to the SiC semiconductor layer through the opening of the field insulation film, and a guard ring having a second-conductivity-type impurity and being formed in a surface layer portion of the SiC semiconductor layer to make contact with a terminal end portion of the electrode connected to the SiC semiconductor layer. A second-conductivity-type impurity concentration in a surface layer portion of the guard ring making contact with the electrode is smaller than a first-conductivity-type impurity concentration in the SiC semiconductor layer. | 06-14-2012 |
20120146056 | SILICON CARBIDE EPITAXIAL WAFER AND MANUFACTURING METHOD THEREFOR - Provided is a silicon carbide epitaxial wafer, the entire surface of which is free of step bunching. Also provided is a method for manufacturing said silicon carbide epitaxial wafer. The provided method for manufacturing a silicon carbide semiconductor device includes: a step wherein a 4H—SiC single-crystal substrate having an off-axis angle of 5° or less is polished until the lattice disorder layer on the surface of the substrate is 3 nm or less; a step wherein, in a hydrogen atmosphere, the polished substrate is brought to a temperature between 1400° C. and 1600° C. and the surface of the substrate is cleaned; a step wherein silicon carbide is epitaxially grown on the surface of the cleaned substrate as the amounts of SiH | 06-14-2012 |
20120146057 | METHOD OF FABRICATING SPACERS IN A STRAINED SEMICONDUCTOR DEVICE - The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack. | 06-14-2012 |
20120153298 | EPITAXIAL GROWTH SYSTEM FOR FAST HEATING AND COOLING - A system for crystal growth having rapid heating and cooling. A fluid-cooling jacket having a reflective shield contained therein is disposed around a heating cylinder in which crystal growth takes place. A heating coil is disposed round the cooling jacket. The invention also includes a method of crystal growth and semiconductor devices formed using the inventive methods and systems. | 06-21-2012 |
20120153299 | LED CHIP - The present invention provides a LED chip structure. The LED chip structure comprises a substrate and an N type layer disposed on the substrate; a P type layer disposed on the N type layer; a N type contact pad and a P type contact pad disposed below the substrate; conductive through holes disposed through the substrate to electrically connect the N type layer to the N type contact pad and the P type layer to the conduct heat generated by the P type layer and the N type layer downward. | 06-21-2012 |
20120153300 | SEMICONDUCTOR DEVICES WITH BACK SURFACE ISOLATION - Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided. | 06-21-2012 |
20120153301 | III-V SEMICONDUCTOR STRUCTURES INCLUDING ALUMINUM-SILICON NITRIDE PASSIVATION - A semiconductor structure includes a semiconductor layer that is passivated with an aluminum-silicon nitride layer. When the semiconductor layer in particular comprises a III-V semiconductor material such as a group III nitride semiconductor material or a gallium nitride semiconductor material, the aluminum-silicon nitride material provides a superior passivation in comparison with a silicon nitride material. | 06-21-2012 |
20120153302 | RECESSED GATE-TYPE SILICON CARBIDE FIELD EFFECT TRANSISTOR AND METHOD OF PRODUCING SAME - A SiC MISFET, in which a source region and a drain region ( | 06-21-2012 |
20120153303 | SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING SAME - A semiconductor device | 06-21-2012 |
20120161154 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An SiC semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate oxide film, a gate electrode, a source electrode and a drain electrode. The substrate has a Si-face as a main surface. The source region has the Si-face. The trench is provided from a surface of the source region to a portion deeper than the base region and extends longitudinally in one direction and has a Si-face bottom. The trench has an inverse tapered shape, which has a smaller width at an entrance portion than at a bottom, at least at a portion that is in contact with the base region. | 06-28-2012 |
20120161155 | SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SILICON CARBIDE SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A main surface of a silicon carbide substrate is inclined by an off angle in an off direction from {0001} plane of a hexagonal crystal. The main surface has such a characteristic that, among emitting regions emitting photoluminescent light having a wavelength exceeding 650 nm of the main surface caused by excitation light having higher energy than band-gap of the hexagonal silicon carbide, the number of those having a dimension of at most 15 μm in a direction perpendicular to the off direction and a dimension in a direction parallel to the off direction not larger than a value obtained by dividing penetration length of the excitation light in the hexagonal silicon carbide by a tangent of the off angle is at most 1×10 | 06-28-2012 |
20120161156 | TRIBOLOGY COMBINED WITH CORROSION RESISTANCE: A NEW FAMILY OF PVD- AND PACVD COATINGS - The present invention relates to a coating system on a substrate with improved protection against wear as well as corrosion. According to the invention the substrate is coated with a diamond like carbon (DLC) layer. This DLC layer is coated with an additional layer with material different from the DLC coating material, thereby closing the pin holes of the DLC layer. | 06-28-2012 |
20120161157 | SILICON CARBIDE SUBSTRATE - A silicon carbide substrate, which achieves restrained warpage even when a different-type material layer made of a material other than silicon carbide, includes: a base layer made of silicon carbide; and a plurality of SiC layers arranged side by side on the base layer when viewed in a planar view and each made of single-crystal silicon carbide. A gap is formed between end surfaces of adjacent SiC layers. | 06-28-2012 |
20120161158 | COMBINED SUBSTRATE HAVING SILICON CARBIDE SUBSTRATE - A first silicon carbide substrate has a first backside surface connected to a supporting portion, a first front-side surface opposite to the first backside surface, and a first side surface connecting the first backside surface and the first front-side surface to each other. A second silicon carbide substrate has a second backside surface connected to the supporting portion, a second front-side surface opposite to the second backside surface, and a second side surface connecting the second backside surface and the second front-side surface to each other and forming a gap between the first side surface and the second side surface. A closing portion closes the gap. Thereby, foreign matters can be prevented from remaining in a gap between a plurality of silicon carbide substrates provided in a combined substrate. | 06-28-2012 |
20120168773 | SEMICONDUCTOR-ON-DIAMOND DEVICES AND ASSOCIATED METHODS - Semiconductor-on-diamond (SOD) substrates and methods for making such substrates are provided. In one aspect, a method of making an SOD substrate may include depositing a base layer onto a lattice-orienting silicon (Si) substrate such that the base layer lattice is substantially oriented by the Si substrate, depositing a semiconductor layer onto the base layer such that the semiconductor layer lattice is substantially oriented with respect to the base layer lattice, and disposing a layer of diamond onto the semiconductor layer. The base layer may include numerous materials, including, without limitation, aluminum phosphide (AlP), boron arsenide (BAs), gallium nitride (GaN), indium nitride (InN), and combinations thereof. Additionally, the method may further include removing the lattice-orienting Si substrate and the base layer from the semiconductor layer. In one aspect, the Si substrate may be of a single crystal orientation. | 07-05-2012 |
20120168774 | SILICON CARBIDE SUBSTRATE AND METHOD FOR MANUFACTURING SAME - A silicon carbide substrate and a method for manufacturing the silicon carbide substrate are obtained, each of which achieves reduced manufacturing cost of semiconductor devices using the silicon carbide substrate. A method for manufacturing a SiC-combined substrate includes the steps of: preparing a plurality of single-crystal bodies each made of silicon carbide (SiC); forming a collected body; connecting the single-crystal bodies to each other; and slicing the collected body. In the step, the plurality of SiC single-crystal ingots are arranged with a silicon (Si) containing Si layer interposed therebetween, so as to form the collected body including the single-crystal bodies. In the step, adjacent SiC single-crystal ingots are connected to each other via at least a portion of the Si layer, the portion being formed into silicon carbide by heating the collected body. In step, the collected body in which the SiC single-crystal ingots are connected to each other is sliced. | 07-05-2012 |
20120168775 | STRESS ENHANCED TRANSISTOR DEVICES AND METHODS OF MAKING - A transistor device includes a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material. | 07-05-2012 |
20120175634 | Transistor Arrangement with a First Transistor and with a Plurality of Second Transistors - A transistor arrangement includes a first transistor having a drift region and a number of second transistors, each having a source region, a drain region and a gate electrode. The second transistors are coupled in series to form a series circuit that is coupled in parallel with the drift region of the first transistor. | 07-12-2012 |
20120175635 | Semiconductor Device Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices - A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device. | 07-12-2012 |
20120175636 | PHOTODIODE DEVICE BASED ON WIDE BANDGAP MATERIAL LAYER AND BACK-SIDE ILLUMINATION (BSI) CMOS IMAGE SENSOR AND SOLAR CELL INCLUDING THE PHOTODIODE DEVICE - According to example embodiments, a photodiode system may include a substrate, and at least one photodiode in the substrate, and a wideband gap material layer on a first surface of the substrate. The at least one photodiode may be between an insulating material in a horizontal plane. According to example embodiments, a back-side-illumination (BSI) CMOS image sensor and/or a solar cell may include a photodiode device. The photodiode device may include a substrate, at least one photodiode in the substrate, a wide bandgap material layer on a first surface of the substrate, and an anti-reflective layer (ARL) on the wide bandgap material layer. | 07-12-2012 |
20120175637 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - According to one embodiment, a semiconductor device including: a substrate; a gate electrode formed above the substrate; a gate insulating film formed under the gate electrode; a channel layer formed under the gate insulating film by using a channel layer material; a source region and a drain region formed in the substrate so as to interpose the channel layer therebetween in a channel direction; and a source extension layer formed in the substrate between the channel layer and the source region so as to overlap a source-side end portion of the channel layer. The source extension layer forms a heterointerface with the channel layer. The heterointerface is a tunnel channel for carries. | 07-12-2012 |
20120175638 | SEMICONDUCTOR DEVICE - A MOSFET includes: a silicon carbide substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; an active layer; a gate oxide film; a p type body region having p type conductivity and formed to include a region of the active layer, the region being in contact with the gate oxide film; an n | 07-12-2012 |
20120175639 | TANTALUM CARBIDE, METHOD FOR PRODUCING TANTALUM CARBIDE, TANTALUM CARBIDE WIRING AND TANTALUM CARBIDE ELECTRODE - It is an object of the present invention to provide a method for manufacturing tantalum carbide which can form tantalum carbide having a prescribed shape using a simple method, can form the tantalum carbide having a uniform thickness even when the tantalum carbide is coated on the surface of an article and is not peeled off by a thermal history, tantalum carbide obtained by the manufacturing method, wiring of tantalum carbide, and electrodes of tantalum carbide. | 07-12-2012 |
20120175640 | SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING - Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers. The structure further includes an epitaxially grown straining material directly on the polysilicon layer and between portions of the sidewalls. The epitaxially grown straining material, in a relaxed state, strains the polysilicon layer. | 07-12-2012 |
20120175641 | DIAMOND N-TYPE SEMICONDUCTOR, METHOD OF MANUFACTURING THE SAME, SEMICONDUCTOR DEVICE, AND ELECTRON EMITTING DEVICE - The present invention relates to a diamond n-type semiconductor in which the amount of change in carrier concentration is fully reduced in a wide temperature range. The diamond n-type semiconductor comprises a diamond substrate, and a diamond semiconductor formed on a main surface thereof and turned out to be n-type. The diamond semiconductor exhibits a carrier concentration (electron concentration) negatively correlated with temperature in a part of a temperature region in which it is turned out to be n-type, and a Hall coefficient positively correlated with temperature. The diamond n-type semiconductor having such a characteristic is obtained, for example, by forming a diamond semiconductor doped with a large amount of a donor element while introducing an impurity other than the donor element onto the diamond substrate. | 07-12-2012 |
20120181549 | STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS - A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers. | 07-19-2012 |
20120181550 | COMPOUND SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME - A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal silicon carbide. In each of the first substrate and the second substrate, one surface is a (000-1) C-face and an opposite surface is a (0001) Si-face. The first substrate and the second substrate are bonded to each other in a state where the (0001) Si-face of the first substrate and the (0001) Si-face of the second substrate face each other, and the (000-1) C-face of the first substrate and the (000-1) C-face of the second substrate are exposed. | 07-19-2012 |
20120181551 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate and a trench. The silicon carbide semiconductor substrate has an offset angle with respect to a ( | 07-19-2012 |
20120187416 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a collector layer in which the carrier concentration is maximized at a carrier concentration peak position that is 1 μm or more from a surface of the semiconductor substrate. The semiconductor device further includes a collector electrode formed in contact with a surface of the collector layer. | 07-26-2012 |
20120187417 | SEMICONDUCTOR DEVICE - A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. Another problem is that an increase in memory capacity leads to an increase in the area, despite an attempt at integration through advancement of transistor miniaturization. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. In addition, a plurality of memory elements each including the transistor having a trench structure and including an oxide semiconductor is stacked in a semiconductor device, whereby the circuit area of the semiconductor device can be reduced. | 07-26-2012 |
20120187418 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate, a semiconductor fin located on the semiconductor substrate, and an etch stop layer located between the semiconductor substrate and the semiconductor fin, wherein a lateral sidewall of the semiconductor fin is substantially on the Si { | 07-26-2012 |
20120187419 | Production Method for a Unipolar Semiconductor Component and Semiconductor Device - The invention relates to a production method for a unipolar semiconductor component having a drift layer ( | 07-26-2012 |
20120187420 | STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL - An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure. | 07-26-2012 |
20120187421 | VERTICAL JUNCTION FIELD EFFECT TRANSISTORS AND DIODES HAVING GRADED DOPED REGIONS AND METHODS OF MAKING - Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications. | 07-26-2012 |
20120193640 | CRYSTALLINE ALUMINUM CARBIDE THIN FILM, SEMICONDUCTOR SUBSTRATE HAVING THE ALUMINUM CARBIDE THIN FILM FORMED THEREON AND METHOD OF FABRICATING THE SAME - Embodiments of the invention provide a crystalline aluminum carbide thin film, a semiconductor substrate having the crystalline aluminum carbide thin film formed thereon, and a method of fabricating the same. Further, the method of fabricating the AlC thin film includes supplying a carbon containing gas and an aluminum containing gas to a furnace, to growing AlC crystals on a substrate. | 08-02-2012 |
20120193641 | NORMALLY-OFF POWER JFET AND MANUFACTURING METHOD THEREOF - In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times. | 08-02-2012 |
20120193642 | DIAMOND SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS - Semiconductor devices and methods for making such devices are provided. One such method may include forming a transparent diamond layer having a SiC layer coupled thereto, where the SiC layer has a crystal structure that is substantially epitaxially matched to the transparent diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer, and coupling a diamond substrate to at least one of the plurality of semiconductor layers such that the diamond support is oriented parallel to the transparent diamond layer. In one aspect such a method may further include electrically coupling at least one of a p-type electrode or an n-type electrode to at least one of the plurality of semiconductor layers. | 08-02-2012 |
20120193643 | SEMICONDUCTOR DEVICE - A MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a p type body region in which an inversion layer is formed when the gate electrode is fed with a voltage. The inversion layer has an electron mobility μ dependent more strongly on an acceptor concentration N | 08-02-2012 |
20120193644 | BORON-DOPED DIAMOND SEMICONDUCTOR - First and second synthetic diamond regions are doped with boron. The second synthetic diamond region is doped with boron to a greater degree than the first synthetic diamond region, and in physical contact with the first synthetic diamond region. In a further example embodiment, the first and second synthetic diamond regions form a diamond semiconductor, such as a Schottky diode when attached to at least one metallic lead. | 08-02-2012 |
20120199845 | METALLIC CARRIER FOR LAYER TRANSFER AND METHODS FOR FORMING THE SAME - Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate a semiconductor substrate by forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A metallic layer is formed on the attachment surface and provides an ohmic contact between the metallic layer and the transfer layer, a matched Coefficient of Thermal Expansion (CTE) for the metallic layer that closely matches a CTE of the transfer layer, and sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer the metallic layer. | 08-09-2012 |
20120199846 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device of an embodiment at least includes: a SiC substrate; and a gate insulating film formed on the SiC substrate, wherein at an interface between the SiC substrate and the gate insulating film, some of elements of both of or one of Si and C in an outermost surface of the SiC substrate are replaced with at least one type of element selected from nitrogen, phosphorus, and arsenic. | 08-09-2012 |
20120199847 | SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment includes: a unit FET cell(s) having multi-fingers composed of parallel connection of a unit finger; a designated gate bus line(s) configured to connect gate fingers of the unit FET cell having multi-fingers in parallel; and a gate extracting line(s) configured to be connected to the designated gate bus line, wherein a connecting point between the gate extracting line and the designated gate bus line is shifted from a center in the unit FET cell having multi-fingers, and thereby the numbers of the gate fingers connected to one side of the connecting point is more than the number of the gate fingers connected to another side of the connecting point. | 08-09-2012 |
20120199848 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A buffer layer is provided on a substrate, is made of silicon carbide containing an impurity, and has a thickness larger than 1 μm and smaller than 7 μm. A drift layer is provided on the buffer layer and is made of silicon carbide having an impurity concentration smaller than that of the buffer layer. In this way, there can be provided a silicon carbide semiconductor device having the drift layer having a desired impurity concentration and a high crystallinity. | 08-09-2012 |
20120199849 | METHOD OF FABRICATION OF METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR - A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved. | 08-09-2012 |
20120199850 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A silicon carbide semiconductor device is provided that includes a semiconductor layer made of silicon carbide and having a surface tilted at an angle in a range of not less than 50° and not more than 65° relative to the {0001} plane, and an insulating film formed to contact the surface of the semiconductor layer. A maximum value of the nitrogen concentration in a region within 10 nm from the interface between the semiconductor layer and the insulating film is not less than 1×10 | 08-09-2012 |
20120205666 | JUNCTION TERMINATION STRUCTURES INCLUDING GUARD RING EXTENSIONS AND METHODS OF FABRICATING ELECTRONIC DEVICES INCORPORATING SAME - An electronic device includes a semiconductor layer, a primary junction in the semiconductor layer, a lightly doped region surrounding the primary junction and a junction termination structure in the lightly doped region adjacent the primary junction. The junction termination structure has an upper boundary, a side boundary, and a corner between the upper boundary and the side boundary, and the lightly doped region extends in a first direction away from the primary junction and normal to a point on the upper boundary by a first distance that is smaller than a second distance by which the lightly doped region extends in a second direction away from the primary junction and normal to a point on the corner. At least one floating guard ring segment may be provided in the semiconductor layer outside the corner of the junction termination structure. Related methods are also disclosed. | 08-16-2012 |
20120205667 | Semiconductor Device with Low-Conducting Field-controlling Element - A semiconductor device including a low conducting field-controlling element is provided. The device can include a semiconductor including an active region, and a set of contacts to the active region. The field-controlling element can be coupled to one or more of the contacts in the set of contacts. The field-controlling element can be formed of a low conducting layer having a sheet resistance between approximately 10 | 08-16-2012 |
20120205668 | SWITCHING SEMICONDUCTOR DEVICES AND FABRICATION PROCESS - A switching semiconductor device is provided, in which a negative gate voltage can be applied to the semiconductor device in an OFF state so as to increase a breakdown voltage of the gate junction without impairing a normally-off function of the semiconductor device and the ON-resistance. The switching semiconductor device is fabricated by using a semiconductor substrate with a band gap of 2.0 eV or more. In a JFET structure where a p | 08-16-2012 |
20120205669 | POWER SEMICONDUCTOR DEVICE - In a semiconductor device according to the present invention, a p-type well region disposed in an outer peripheral portion of the power semiconductor device is divided into two parts, that is, an inside and an outside, and a field oxide film having a greater film thickness than the gate insulating film is provided on a well region at the outside to an inside of an inner periphery of the well region. Therefore, it is possible to prevent, in the gate insulating film, a dielectric breakdown due to the voltage generated by the flow of the displacement current in switching. | 08-16-2012 |
20120205670 | SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCTION THEREOF - A semiconductor device | 08-16-2012 |
20120211767 | POWER CONVERTER - The present power converter includes a power conversion semiconductor device, an electrode connection conductor which electrically connects multiple electrodes having the same potential, and also has a generally flat upper surface for electrically connecting to an exterior portion, and a sealing material provided so as to cover the power conversion semiconductor device, and also to expose the generally flat upper surface of the electrode connection conductor. | 08-23-2012 |
20120211768 | WIDE-BAND-GAP REVERSE-BLOCKING MOS-TYPE SEMICONDUCTOR DEVICE - A wide-band-gap reverse-blocking MOS-type semiconductor device includes a SiC n | 08-23-2012 |
20120211769 | Sic single crystal wafer and process for production thereof - A SiC single crystal wafer on which a good quality epitaxial film by suppressing defects derived from the wafer can be grown has an affected surface layer with a thickness of at most 50 nm and a SiC single crystal portion with an oxygen content of at most 1.0×10 | 08-23-2012 |
20120211770 | SEMICONDUCTOR DEVICE, COMBINED SUBSTRATE, AND METHODS FOR MANUFACTURING THEM - There are provided a semiconductor device of low cost and high quality, a combined substrate used for manufacturing the semiconductor device, and methods for manufacturing them. The method for manufacturing the semiconductor device includes the steps of: preparing a single-crystal semiconductor member; preparing a supporting base; connecting the supporting base and the single-crystal semiconductor member to each other through a connecting layer containing carbon; forming an epitaxial layer on a surface of the single-crystal semiconductor member; forming a semiconductor element using the epitaxial layer; separating the single-crystal semiconductor member from the supporting base by oxidizing and accordingly decomposing the connecting layer after the step of forming the semiconductor element; and dividing the single-crystal semiconductor member separated from the supporting base. | 08-23-2012 |
20120217513 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility. | 08-30-2012 |
20120223330 | SEMICONDUCTOR DEVICE HAVING HIGH PERFORMANCE CHANNEL - Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior. | 09-06-2012 |
20120223331 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device comprises: a semiconductor substrate located on an insulating layer; and an insulator located on the insulating layer and embedded in the semiconductor substrate, wherein the insulator applies stress therein to the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a cavity within the semiconductor substrate so as to expose the insulating layer; forming an insulator in the cavity, wherein the insulator applies stress therein to the semiconductor substrate. It facilitates the reduction of the short channel effect, the resistance of source/drain regions and parasitic capacitance. | 09-06-2012 |
20120223332 | SEMICONDUCTOR RECTIFYING DEVICE - A semiconductor rectifying device of an embodiment includes a first-conductive-type semiconductor substrate made of a wide bandgap semiconductor, a first-conductive-type semiconductor layer formed on an upper surface of the semiconductor substrate and made of the wide bandgap semiconductor having an impurity concentration lower than that of the semiconductor substrate, a first-conductive-type first semiconductor region formed at a surface of the semiconductor layer and made of the wide bandgap semiconductor, a second-conductive-type second semiconductor region formed around the first semiconductor region and made of the wide bandgap semiconductor, a second-conductive-type third semiconductor region formed around the first semiconductor region and made of the wide bandgap semiconductor having a junction depth deeper than a junction depth of the second semiconductor region, a first electrode that is formed on the first, second, and third semiconductor regions, and a second electrode formed on a lower surface of the semiconductor substrate. | 09-06-2012 |
20120223333 | SEMICONDUCTOR RECTIFIER DEVICE - A semiconductor rectifier device according to an embodiment includes a semiconductor substrate of a first conductive type of a wide gap semiconductor, a semiconductor layer of the first conductive type of the wide gap semiconductor formed on an upper surface of the semiconductor substrate, wherein an impurity concentration of the semiconductor layer is between 1E+14 atoms/cm | 09-06-2012 |
20120223334 | DOPED DIAMOND LED DEVICES AND ASSOCIATED METHODS - LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode. | 09-06-2012 |
20120223335 | METHOD OF MARKING SiC SEMICONDUCTOR WAFER AND SiC SEMICONDUCTOR WAFER - Marking of an SiC wafer with an identifier is realized by irradiation with a pulsed laser using a harmonic of a wavelength four times that of a YAG laser. A speed at which a laser head moves, an orbit in which the laser head moves, the output power and Q-switch frequency of a pulsed laser to be applied, and the like are determined such that pulse-irradiated marks formed as a result of irradiation with corresponding pulses of the pulsed laser do not overlap each other. | 09-06-2012 |
20120223336 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a collector layer of a first conductivity type and a drift layer of a second conductivity type in contact with said collector layer, said drift layer receiving a supply of carriers from said collector layer. The semiconductor device further includes a lattice defect formed to penetrate through said semiconductor substrate and enclose a predetermined portion of said semiconductor substrate, a sense emitter electrode formed on the top surface of said predetermined portion, and a collector electrode formed on the bottom surface of said predetermined portion. | 09-06-2012 |
20120223337 | NITRIDE SEMICONDUCTOR DIODE - In a Schottky electrode formation region on a nitride semiconductor, the total length of junctions of Schottky electrodes and a surface of a nitride semiconductor layer is longer than the perimeter of the Schottky electrode formation region. The total length is preferably 10 times longer than the perimeter. For example, the Schottky electrodes are formed concentrically and circularly. | 09-06-2012 |
20120223338 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon carbide substrate, annealing the silicon carbide substrate and the silicon oxide film in gas containing hydrogen, and forming an aluminum oxynitride film on the silicon oxide film after the annealing of the silicon carbide substrate and the silicon oxide film. | 09-06-2012 |
20120223339 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first conduction type semiconductor substrate, a first conduction type semiconductor deposition layer, a trench, second conduction type wells, a JFET region, a first conduction type first source region, a first source region, a trench-type source electrode, a gate insulator film, a gate electrode, and a drain electrode. The trench is formed substantially perpendicularly to the semiconductor deposition layer so that the semiconductor deposition layer exposes to a bottom of the trench. The second conduction type second source region are formed in the first conduction type first source region. The trench-type source electrode is in contact with the first source region, the second source region, and the first conduction type semiconductor deposition layer to configure a Schottky junction. | 09-06-2012 |
20120223340 | VERTICAL JUNCTION FIELD EFFECT TRANSISTORS HAVING SLOPED SIDEWALLS AND METHODS OF MAKING - Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation. | 09-06-2012 |
20120228628 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and methods of fabricating semiconductor devices are provided. A method involves forming a semiconductor substrate on a source region and a drain region, the semiconductor substrate comprises a first crystal. The method also involves forming an epitaxial layer of a second crystal on the semiconductor substrate. The first crystal has a first lattice constant and the second crystal has a second lattice constant. The first epitaxial layer does not touch a spacer or a gate electrode. Forming the epitaxial layer can comprise forming a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer has a conductivity type impurity that is less than the conductivity type impurity of the second epitaxial layer. | 09-13-2012 |
20120228629 | Thyristors, Methods of Programming Thyristors, and Methods of Forming Thyristors - Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors. | 09-13-2012 |
20120228630 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device according to an embodiment includes a first electrode and a first silicon carbide (SiC) semiconductor part. The first electrode uses a conductive material and the first silicon carbide (SiC) semiconductor part is connected to the first electrode, in which at least one element of magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba) is contained in an interface portion with the first electrode in such a way that a surface density thereof peaks, and whose conduction type is a p-type. | 09-13-2012 |
20120228631 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon carbide region and the third silicon carbide region; and a fourth electrode formed on the second principal surface of the silicon carbide substrate. | 09-13-2012 |
20120228632 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes: a semiconductor substrate; a field-effect transistor formed on the semiconductor substrate; and a diode forming area which is adjacent to a forming area of the field-effect transistor, wherein the diode forming area is insulated from the forming area of the transistor on the semiconductor substrate, and includes a first diode electrode in which a gate electrode of the field-effect transistor is placed in Schottky barrier junction and/or ohmic contact with the semiconductor substrate through a bus wiring or a pad; and a second diode electrode in which a source electrode of the field-effect transistor is placed in ohmic contact and/or Schottky barrier junction with the semiconductor substrate through a bus interconnection or a pad to form a diode between the gate electrode and the source electrode. | 09-13-2012 |
20120228633 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a first conductivity type semiconductor layer that is formed on the substrate and is made of silicon carbide; an active area formed on a surface of the semiconductor layer; a first semiconductor area of a second conductivity type formed on the surface of the semiconductor layer to surround the active area; a second semiconductor area, provided to adjoin an outer side of the first semiconductor area on the surface of the semiconductor layer and surround the first semiconductor area, in which a second conductivity type impurity area having the same impurity concentration and the same depth as those of the first semiconductor area is formed in a mesh shape; a first electrode provided on the active area; and a second electrode provided on the rear surface of the semiconductor substrate. | 09-13-2012 |
20120228634 | COMBINED SEMICONDUCTOR DEVICE - A combined semiconductor device performs low conduction loss and low recovery loss characteristics suited to a circuit technology in a soft switching mode at a low cost. The device has a SJ-MOSFET and a wide band gap Schottky barrier diode connected in parallel to a built-in body diode in the SJ-MOSFET. The device includes a MOS type semiconductor element having a superjunction structure and a wide band gap Schottky barrier diode antiparallel-connected to the MOS type semiconductor element. The MOS type semiconductor element has a resistance section series-connected to a built-in body diode in the element. A resistance value of the resistance section is such a value that the forward voltage drop of the built-in body diode in the MOS type semiconductor element is higher than the forward voltage drop of the wide band gap Schottky barrier diode at a rated current of the MOS type semiconductor element. | 09-13-2012 |
20120228635 | SEMICONDUCTOR RECTIFIER DEVICE - A semiconductor rectifier device using an SiC semiconductor at least includes: an anode electrode; an anode area that adjoins the anode electrode and is made of a second conductivity type semiconductor; a drift layer that adjoins the anode area and is made of a first conductivity type semiconductor having a low concentration; a minority carrier absorption layer that adjoins the drift layer and is made of a first conductivity type semiconductor having a higher concentration than that of the drift layer; a high-resistance semiconductor area that adjoins the minority carrier absorption layer, has less thickness than the drift layer and is made of a first conductivity type semiconductor having a concentration lower than that of the minority carrier absorption layer; a cathode contact layer that adjoins the semiconductor area; and a cathode electrode. | 09-13-2012 |
20120228636 | SCHOTTKY BARRIER DIODE - A third insulating layer is formed in a periphery region of a substrate over a first surface (main surface) of the substrate so as to straddle a second semiconductor layer closest to a guard ring layer and a second semiconductor layer closest to the second semiconductor layer. In other words, the third insulating layer is formed to cover a portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers. Thereby, the third insulating layer electrically insulates the metal layer from the portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers. | 09-13-2012 |
20120228637 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes a first conductive type silicon carbide substrate having first and second main surfaces, a first conductive type silicon carbide layer formed on the first main surface, a second conductive type first silicon carbide region formed in the silicon carbide layer, and a first conductive type second silicon carbide region formed in the first silicon carbide region. The device includes a trench penetrating through the first and second silicon carbide regions, and a second conductive type third silicon carbide region formed on a bottom and a side surface of the trench. The third silicon carbide region is in contact with the first silicon carbide region, and is formed between the trench and the silicon carbide layer. In addition, the device includes a gate insulating film formed in the trench, a gate electrode, a first electrode, and a second electrode. | 09-13-2012 |
20120228638 | Methods of Fabricating Silicon Carbide Devices Having Smooth Channels and Related Devices - Methods of forming silicon carbide power devices are provided. An n | 09-13-2012 |
20120228639 | SELF ALIGNED DEVICE WITH ENHANCED STRESS AND METHODS OF MANUFACTURE - A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer. | 09-13-2012 |
20120228640 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes: a substrate having a main surface; and a silicon carbide layer formed on the main surface of the substrate and including a side surface inclined relative to the main surface. The side surface substantially includes a {03-3-8} plane. The side surface includes a channel region. | 09-13-2012 |
20120235162 | POWER CONVERTER - This power converter includes a power-conversion semiconductor element, an electrode conductor having a substantially flat upper end surface, and a sealant. The sealant allows the substantially flat upper end surface of the electrode conductor to be exposed at an upper surface of the sealant, and provides electrical connection with an external device at the upper end surface of the exposed electrode conductor. | 09-20-2012 |
20120235163 | SEMICONDUCTOR SUBSTRATE AND METHOD FOR PRODUCING SEMICONDUCTOR SUBSTRATE - A semiconductor substrate includes: single crystal silicon; a mask material formed on a surface of the single crystal silicon and having an opening; a silicon carbide film formed on a portion exposed in the opening of the single crystal silicon; and a single crystal silicon carbide film formed so as to cover the silicon carbide film and the mask material. The mask material has a viscosity of 10 | 09-20-2012 |
20120235164 | TRANSISTOR WITH A-FACE CONDUCTIVE CHANNEL AND TRENCH PROTECTING WELL REGION - A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner. | 09-20-2012 |
20120235165 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a substrate made of silicon carbide and having a main surface having an off angle of not less than −° and not more than +5° relative to a (0-33-8) plane in a <01-10> direction; a p type layer made of silicon carbide and formed on the main surface of the substrate by means of epitaxial growth; and an oxide film formed in contact with a surface of the p type layer. A maximum value of nitrogen atom concentration is 1×10 | 09-20-2012 |
20120241761 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor device includes a first semiconductor layer of a first conductive type, a first main electrode provided on a first major surface side of the first semiconductor layer, and a second main electrode provided on a second major surface side of the first semiconductor layer. A pair of first control electrodes is provided within a trench provided from the first major surface side to the second major surface in the first semiconductor layer; and the first control electrodes are provided separately from each other in a direction parallel to the first major surface. Each of the first control electrodes faces an inner face of the trench via a first insulating film. A second control electrode is provided between the first control electrodes and a bottom face of the trench, and faces the inner face of the trench via a second insulating film. | 09-27-2012 |
20120241762 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor layer of a first conductivity type, a first region of a second conductivity type selectively provided in a first major surface of the semiconductor layer, a second region of the second conductivity type selectively provided in the first major surface and connected to the first region, a first electrode provided in contact with the semiconductor layer and the first region, a second electrode provided in contact with the second region, and a third electrode electrically connected to a second major surface of the semiconductor layer opposite to the first major surface. | 09-27-2012 |
20120241763 | ELECTRONIC FIELD EFFECT DEVICES AND METHODS FOR THEIR MANUFACTURE - Electronic field effect devices, and methods of manufacture of these electronic field effect devices are disclosed. In particular, there is disclosed an electronic field effect device which has improved electrical properties due to the formation of a highly mobile two-dimensional charge-carrier gas in a simple structure formed from diamond in combination with polar materials. | 09-27-2012 |
20120241764 | SEMICONDUCTOR DEVICE BASED ON THE CUBIC SILICON CARBIDE SINGLE CRYSTAL THIN FILM - A semiconductor apparatus includes a cubic silicon carbide single crystal thin film of a multilayer structure including an Al | 09-27-2012 |
20120241765 | SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRAIN AND METHODS OF MANUFACTURING AND DESIGN STRUCTURE - A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The gate structures for an NFET and a PFET have identically formed sidewalls, and stress materials are provided in recesses in source and drain regions of the NFET and the PFET. | 09-27-2012 |
20120241766 | EPITAXIAL WAFER AND SEMICONDUCTOR ELEMENT - A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1). | 09-27-2012 |
20120241767 | SIC SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD FOR SAME - Disclosed are an SiC semiconductor element and manufacturing method for an SiC semiconductor element in which the interface state density of the interface of the insulating film and the SiC is reduced, and channel mobility is improved. Phosphorus ( | 09-27-2012 |
20120248460 | SYSTEMS AND METHODS FOR DEPOSITING MATERIALS ON EITHER SIDE OF A FREESTANDING FILM USING LASER-ASSISTED CHEMICAL VAPOR DEPOSITION (LA-CVD), AND STRUCTURES FORMED USING SAME - Embodiments of the present invention provide systems and methods for depositing materials on either side of a freestanding film using laser-assisted chemical vapor deposition (LA-CVD), and structures formed using same. A freestanding film, which is suspended over a cavity defined in a substrate, is exposed to a fluidic CVD precursor that reacts to form a solid material when exposed to light and/or heat. The freestanding film is then exposed to a laser beam in the presence of the precursor. The CVD precursor preferentially deposits on the surface(s) of the freestanding film. | 10-04-2012 |
20120248461 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×10 | 10-04-2012 |
20120248462 | IGBT - An IGBT includes a groove provided in a silicon carbide semiconductor layer, a body region of a first conductivity type provided in the silicon carbide semiconductor layer, and an insulating film covering at least a sidewall surface of the groove, the sidewall surface of the groove being a surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, the sidewall surface of the groove including a surface of the body region, the insulating film being in contact with at least the surface of the body region at the sidewall surface of the groove, and a first conductivity type impurity concentration in the body region being 5×10 | 10-04-2012 |
20120248463 | EPITAXIAL GROWTH ON LOW DEGREE OFF-AXIS SILICON CARBIDE SUBSTRATES AND SEMICONDUCTOR DEVICES MADE THEREBY - A method of epitaxially growing a SiC layer on a single crystal SiC substrate is described. The method includes heating a single-crystal SiC substrate to a first temperature of at least 1400° C. in a chamber, introducing a carrier gas, a silicon containing gas and carbon containing gas into the chamber; and epitaxially growing a layer of SiC on a surface of the SiC substrate. The SiC substrate is heated to the first temperature at a rate of at least 30° C./minute. The surface of the SiC substrate is inclined at an angle of from 1° to 3° with respect to a basal plane of the substrate material. | 10-04-2012 |
20120256192 | RECESSED TERMINATION STRUCTURES AND METHODS OF FABRICATING ELECTRONIC DEVICES INCLUDING RECESSED TERMINATION STRUCTURES - An electronic device includes a drift region, a Schottky contact on a surface of the drift region, and an edge termination structure in the drift region adjacent the Schottky contact. The edge termination structure includes a recessed region that is recessed from the surface of the drift region by a distance d that may be about 0.5 microns. | 10-11-2012 |
20120256193 | MONOLITHIC INTEGRATED CAPACITORS FOR HIGH-EFFICIENCY POWER CONVERTERS - A semiconductor structure such as a power converter with an integrated capacitor is provided, and comprises a semiconductor substrate, a high-side output power device over the substrate at a first location, and a low-side output power device over the substrate at a second location adjacent to the first location. A first metal layer is over the high-side output power device and electrically coupled to the high-side output power device, and a second metal layer is over the low-side output power device and electrically coupled to the low-side output power device. A dielectric layer is over a portion of the first metal layer and a portion of the second metal layer, and a top metal layer is over the dielectric layer. The integrated capacitor comprises a first bottom electrode that includes the portion of the first metal layer, a second bottom electrode that includes the portion of the second metal layer, the dielectric layer over the portions of the first and second metal layers, and a top electrode that includes the top metal layer over the dielectric layer. | 10-11-2012 |
20120256194 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device having a structure capable of reducing the self-inductance of internal wiring. The semiconductor device includes: a lower board having a lower conductor layer formed on the surface thereof; a switching element bonded to the lower conductor layer in an element bonding area; a terminal bonded to the lower conductor layer in a terminal bonding area; an upper board stacked on the lower board in a board bonding area between the element bonding area and the terminal bonding area, and having an upper conductor layer on the surface thereof; and a switching element connecting member which connects the switching element with the upper conductor layer. | 10-11-2012 |
20120256195 | SEMICONDUCTOR DEVICE - A semiconductor device capable of decreasing a reverse leakage current and a forward voltage is provided. In the semiconductor device, an anode electrode undergoes Schottky junction by being connected to a surface of an SiC epitaxial layer that has the surface, a back surface, and trapezoidal trenches formed on the side of the surface each having side walls and a bottom wall. Furthermore, an edge portion of the bottom wall of each of the trapezoidal trenches is formed to be in the shape bent towards the outside of the trapezoidal trench in the manner that a radius of curvature R satisfies 0.0110-11-2012 | |
20120256196 | SCHOTTKY DIODE - A semiconductor system of a Schottky diode is described having an integrated PN diode as a clamping element, which is suitable in particular as a Zener diode having a breakdown voltage of approximately 20 V for use in motor vehicle generator systems. The semiconductor system of the Schottky diode includes a combination of a Schottky diode and a PN diode. The breakdown voltage of the PN diode is much lower than the breakdown voltage of the Schottky diode, the semiconductor system being able to be operated using high currents during breakdown operation. | 10-11-2012 |
20120261672 | MINIMIZING LEAKAGE CURRENT AND JUNCTION CAPACITANCE IN CMOS TRANSISTORS BY UTILIZING DIELECTRIC SPACERS - A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor. Accordingly, the application of dielectric spacers and epitaxial layers to minimize leakage current and transistor junction capacitance in CMOS transistors can enhance the utility and performance of the CMOS transistors in low power applications. | 10-18-2012 |
20120261673 | SiC Semiconductor Power Device - A semiconductor power device includes a SiC semiconductor body. At least part of the SiC semiconductor body constitutes a drift zone. A first contact is at a first side of the SiC semiconductor body. A second contact is at a second side of the SiC semiconductor body. The first side is opposite the second side. A current path between the first contact and the second contact includes at least one graphene layer. | 10-18-2012 |
20120261674 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - The present invention provides a semiconductor device, which is formed on a semiconductor substrate, comprising a gate stack, a channel region, and source/drain regions, wherein the gate stack is on the channel region, the channel region is in the semiconductor substrate, the source/drain regions are embedded in the semiconductor substrate, and each of the source/drain regions comprises a sidewall and a bottom, a second semiconductor layer being sandwiched between the channel region and a portion of the sidewall distant from the bottom, a first semiconductor layer being sandwiched between the semiconductor substrate and at least a portion of the bottom distant from the sidewall, and an insulating layer being sandwiched between the semiconductor substrate and the other portions of the bottom and/or the other portions of the sidewall. The present invention also provides a method for forming the semiconductor device. The present invention helps preventing the dopants in the source/drain regions from diffusing into the substrate. | 10-18-2012 |
20120261675 | VERTICAL JUNCTION FIELD EFFECT TRANSISTORS WITH IMPROVED THERMAL CHARACTERISTICS AND METHODS OF MAKING - Vertical junction field effect transistors (VJFETs) having improved heat dissipation at high current flow while maintaining the desirable specific on-resistance and normalized saturated drain current properties characteristic of devices having small pitch lengths are described. The VJFETs comprise one or more electrically active source regions in electrical contact with the source metal of the device and one or more electrically inactive source regions not in electrical contact with the source metal of the device. The electrically inactive source regions dissipate heat generated by the electrically active source regions during current flow. | 10-18-2012 |
20120261676 | SiC FIELD EFFECT TRANSISTOR - A SiC field effect transistor includes: a SiC semiconductor layer; and a MIS transistor structure including a first conductivity type source region in the semiconductor layer, a second conductivity type body region in the semiconductor layer in contact with the source region, a first conductivity type drift region in the semiconductor layer in contact with the body region, a gate electrode opposed to the body region with a gate insulation film interposed between the electrode and the body region for forming a channel in the body region to cause electric current to flow between the drift region and the source region, and a barrier forming layer in contact with the drift region to form a junction barrier by the contact with the drift region, the junction barrier being lower than a diffusion potential of a body diode defined by a junction between the body region and the drift region. | 10-18-2012 |
20120261677 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND THE SILICON CARBIDE SEMICONDUCTOR DEVICE - Silicon carbide semiconductor device includes trench, in which connecting trench section is connected to straight trench section. Straight trench section includes first straight trench and second straight trench extending in parallel to each other. Connecting trench section includes first connecting trench perpendicular to straight trench section, second connecting trench that connects first straight trench and first connecting trench to each other, and third connecting trench that connects second straight trench and first connecting trench to each other. Second connecting trench extends at 30 degrees of angle with the extension of first straight trench. Third connecting trench extends at 30 degrees of angle with the extension of second straight trench. A manufacturing method according to the invention for manufacturing a silicon carbide semiconductor device facilitates preventing defects from being causes in a silicon carbide semiconductor device during the manufacture thereof. | 10-18-2012 |
20120267642 | Nitride semicondutor device and manufacturing method thereof - Provided is a nitride semiconductor device including: a nitride semiconductor layer over a substrate wherein the nitride semiconductor has a two-dimensional electron gas (2DEG) channel inside; a drain electrode in ohmic contact with the nitride semiconductor layer; a source electrode in Schottky contact with the nitride semiconductor layer wherein the source electrode is spaced apart from the drain electrode; a dielectric layer formed on the nitride semiconductor layer between the drain electrode and the source electrode and on at least a portion of the source electrode; and a gate electrode disposed on the dielectric layer to be spaced apart from the drain electrode, wherein a portion of the gate electrode is formed over a drain-side edge portion of the source electrode with the dielectric layer interposed therebetween, and a manufacturing method thereof. | 10-25-2012 |
20120273798 | METHOD OF FORMING SILICIDE CONTACTS OF DIFFERENT SHAPES SELECTIVELY ON REGIONS OF A SEMICONDUCTOR DEVICE - A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications. | 11-01-2012 |
20120273799 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - According to an embodiment, a semiconductor device includes: a conductive base plate; a semiconductor chip bonded on the conductive base plate, a first adhesive agent disposed on a central part of a bonded surface between the semiconductor chip and the conductive base plate; and a second adhesive agent disposed on a peripheral part of the central part of the bonded surface between the semiconductor chip and the conductive base plate. A coefficient of thermal conductivity of the first adhesive agent is relatively higher than that of the second adhesive agent, and a bonding strength of the second adhesive agent is relatively higher than that of the first adhesive agent. | 11-01-2012 |
20120273800 | COMPOSITE SUBSTRATE HAVING SINGLE-CRYSTAL SILICON CARBIDE SUBSTRATE - A first vertex of a first single-crystal silicon carbide substrate and a second vertex of a second single-crystal silicon carbide substrate abut each other such that a first side of the first single-crystal silicon carbide substrate and a second side of the second single-crystal silicon carbide substrate are aligned. In addition, at least a part of the first side and at least a part of the second side abut on a third side of a third single-crystal silicon carbide substrate. Thus, in manufacturing a semiconductor device including a composite substrate, process fluctuations caused by a gap between the single-crystal silicon carbide substrates can be suppressed. | 11-01-2012 |
20120273801 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A SiC semiconductor device includes: a SiC substrate including a first or second conductive type layer and a first conductive type drift layer and including a principal surface having an offset direction; a trench disposed on the drift layer and having a longitudinal direction; and a gate electrode disposed in the trench via a gate insulation film. A sidewall of the trench provides a channel formation surface. The vertical semiconductor device flows current along with the channel formation surface of the trench according to a gate voltage applied to the gate electrode. The offset direction of the SiC substrate is perpendicular to the longitudinal direction of the trench. | 11-01-2012 |
20120273802 | JUNCTION BARRIER SCHOTTKY DIODES WITH CURRENT SURGE CAPABILITY - An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing. | 11-01-2012 |
20120273803 | THERMAL DISSIPATION SUBSTRATE - The present invention related to a method for manufacturing a thermal dissipation substrate and a thermal dissipation substrate. The method includes steps of: (a) providing a substrate body having a surface; (b) forming a plurality of concave regions on the surface; and (c) filling the plurality of concave regions with a plurality of diamond materials. The thermal dissipation substrate includes: a substrate having a surface at a first horizontal; a plurality of regions formed on the surface at a second horizontal; and a plurality of diamond materials having a relatively high thermal coefficient and disposed on the plurality of regions. | 11-01-2012 |
20120280250 | SPACER AS HARD MASK SCHEME FOR IN-SITU DOPING IN CMOS FINFETS - A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described. | 11-08-2012 |
20120280251 | CAVITY-FREE INTERFACE BETWEEN EXTENSION REGIONS AND EMBEDDED SILICON-CARBON ALLOY SOURCE/DRAIN REGIONS - A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that sidewalls of the source/drain extension regions are exposed. Within each trench, an n-doped silicon liner is deposited on the sidewalls of the trenches by a first selective epitaxy process so that the interface between the dielectric spacer and the source/drain extension region is covered. Within each trench, an n-doped single crystalline silicon-carbon alloy is subsequently deposited to fill the trench by a second selective epitaxy process. A combination of an n-doped single crystalline silicon liner and an n-doped single crystalline silicon-carbon alloy functions as embedded source/drain regions of an n-type field effect transistor (NFET), which applies a tensile stress to the channel of the transistor. | 11-08-2012 |
20120280252 | Field Effect Transistor Devices with Low Source Resistance - A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region. | 11-08-2012 |
20120280253 | Stress Regulated Semiconductor Devices and Associated Methods - Stress regulated semiconductor devices and associated methods are provided. In one aspect, for example, a stress regulated semiconductor device can include a semiconductor layer, a stress regulating interface layer including a carbon layer formed on the semiconductor layer, and a heat spreader coupled to the carbon layer opposite the semiconductor layer. The stress regulating interface layer is operable to reduce the coefficient of thermal expansion difference between the semiconductor layer and the heat spreader to less than or equal to about 10 ppm/° C. | 11-08-2012 |
20120280254 | SIC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SAME - According to the present invention, there is provided an SiC epitaxial wafer which reduces triangular defects and stacking faults, which is highly uniform in carrier concentration and film thickness, and which is free of step bunching, and its method of manufacture. The SiC epitaxial wafer of the present invention is an SiC epitaxial wafer in which an SiC epitaxial layer is formed on a 4H—SiC single crystal substrate that is tilted at an off angle of 0.4°-5°, wherein the density of triangular-shaped defects of said SiC epitaxial layer is 1 defect/cm | 11-08-2012 |
20120280255 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode. The body region includes a low concentration region arranged at a region where an inversion layer is formed, and containing impurities of low concentration, and a high concentration region adjacent to the low concentration region in the carrier mobile direction in the inversion layer, arranged in a region where the inversion layer is formed, and containing impurities higher in concentration than in the low concentration region. | 11-08-2012 |
20120286288 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR ELEMENT - A semiconductor device includes a semiconductor element including a first element portion having a first gate and a second element portion having a second gate, wherein the turning on and off of the first and second element portions are controlled by a signal from the first and second gates respectively. The semiconductor device further includes signal transmission means connected to the first gate and the second gate and transmitting a signal to the first gate and the second gate so that when the semiconductor element is to be turned on, the first element portion and the second element portion are simultaneously turned on, and so that when the semiconductor element is to be turned off, the second element portion is turned off a delay time after the first element portion is turned off. | 11-15-2012 |
20120286289 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The invention concerns a semiconductor device comprising a structure, wherein the structure comprising a substrate, a first layer onto the substrate comprising GaN and a second layer comprising AlGaN. The second layer is deposited onto the first layer and the first and the second layer cover at least partially the substrate, and wherein the structure comprises a third layer comprising diamond | 11-15-2012 |
20120286290 | SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE - A semiconductor element according to the present invention includes: a semiconductor substrate of a first conductivity type; a first silicon carbide semiconductor layer of the first conductivity type on the semiconductor substrate; a body region of a second conductivity type defined in the first silicon carbide semiconductor layer; an impurity region of the first conductivity type defined in the body region; a second silicon carbide semiconductor layer of the first conductivity type on the first silicon carbide semiconductor layer; a gate insulating film on the second silicon carbide semiconductor layer; a gate electrode on the gate insulating film; a first ohmic electrode connected to the impurity region; and a second ohmic electrode on the back surface of the semiconductor substrate. The body region includes first and second body regions. The average impurity concentration of the first body region is twice or more as high as that of the second body region. And the bottom of the impurity region is deeper than that of the first body region. | 11-15-2012 |
20120286291 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A silicon carbide semiconductor device having excellent electrical characteristics including channel mobility and a method for manufacturing the same are provided. The method for manufacturing a silicon carbide semiconductor device includes: an epitaxial layer forming step of preparing a semiconductor film of silicon carbide; a gate insulating film forming step of forming an oxide film on a surface of the semiconductor film; a nitrogen annealing step of performing heat treatment on the semiconductor film on which the oxide film is formed, in a nitrogen-containing atmosphere; and a post heat treatment step of performing, after the nitrogen annealing step, post heat treatment on the semiconductor film on which the oxide film is formed, in an atmosphere containing an inert gas. The heat treatment temperature in the post heat treatment step is higher than that in the nitrogen annealing step and lower than a melting point of the oxide film. | 11-15-2012 |
20120286292 | POWER SEMICONDUCTOR MODULE - A power semiconductor module in which temperature rise of switching elements made of a Si semiconductor can be suppressed low and efficiency of cooling the module can be enhanced. To that end, the power semiconductor module includes switching elements made of the Si semiconductor and diodes made of a wide-bandgap semiconductor, the diodes are arranged in the middle region of the power semiconductor module, and the switching elements are arranged in both sides or in the periphery of the middle region of the power semiconductor module. | 11-15-2012 |
20120286293 | ELECTRONIC DEVICE AND MANUFACTURING THEREOF - An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane. | 11-15-2012 |
20120292636 | SIC DEVICES WITH HIGH BLOCKING VOLTAGE TERMINATED BY A NEGATIVE BEVEL - A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode. | 11-22-2012 |
20120292637 | Dual Cavity Etch for Embedded Stressor Regions - Generally, the present disclosure is directed to methods for forming embedded stressor regions in semiconductor devices such as transistor elements and the like. One illustrative method disclosed herein includes forming a first material in first cavities formed in a first active area adjacent to a first channel region of a semiconductor device, wherein the first material induces a first stress in the first channel region. The method also includes, among other things, forming a second material in second cavities formed in a second active area adjacent to a second channel region of the semiconductor device, wherein the second material induces a second stress in the second channel region that is of an opposite type of the first stress in the first channel region, and wherein the first and second cavities are formed during a common etch process. | 11-22-2012 |
20120292638 | PROCESS FOR MANUFACTURING STRESS-PROVIDING STRUCTURE AND SEMICONDUCTOR DEVICE WITH SUCH STRESS-PROVIDING STRUCTURE - A process for manufacturing a stress-providing structure is applied to the fabrication of a semiconductor device. Firstly, a substrate with a channel structure is provided. A silicon nitride layer is formed over the substrate by chemical vapor deposition in a halogen-containing environment. An etching process is performed to partially remove the silicon nitride layer to expose a portion of a surface of the substrate beside the channel structure. The exposed surface of the substrate is etched to form a recess in the substrate. Then, the substrate is thermally treated at a temperature between 750° C. and 820° C. After the substrate is thermally treated, a stress-providing material is filled in the recess to form a stress-providing structure within the recess. The semiconductor device includes a substrate, a recess and a stress-providing structure. The recess has a round inner surface. The stress-providing structure has a round outer surface. | 11-22-2012 |
20120292639 | STRESSED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer. | 11-22-2012 |
20120292640 | Solid State Device - A solid state energy conversion device and method of making is disclosed for converting energy between electromagnetic and electrical energy. The solid state energy conversion device comprises a wide bandgap semiconductor material having a first doped region. A thermal energy beam is directed onto the first doped region of the wide bandgap semiconductor material in the presence of a doping gas for converting a portion of the first doped region into a second doped region in the wide bandgap semiconductor material. In one embodiment, the solid state energy conversion device operates as a light emitting device. In another embodiment, the solid state energy conversion device operates as a photovoltaic device. | 11-22-2012 |
20120292641 | SEMICONDUCTOR DEVICE HAVING AT LEAST ONE CONTACT, AND MANUFACTURING METHOD FOR A SEMICONDUCTOR DEVICE HAVING AT LEAST ONE CONTACT - A semiconductor device having a substrate, and at least one contact, situated on and/or above a surface of the substrate, having at least one layer made of a conductive material, the conductive material including at least one metal. The layer made of the conductive material is sputtered on, and has tear-off marks on at least one outer side area between an outer base area facing the surface and an outer contact area facing away from the surface. A manufacturing method for a semiconductor device having at least one contact is also described. | 11-22-2012 |
20120292642 | FUNCTIONAL ELEMENT AND MANUFACTURING METHOD OF SAME - Provided is a functional element which is obtained by forming a lamination film on a substrate and then dividing the substrate and the lamination film into a desired shape. The functional element has a hexagonal substrate, a lamination film formed on a C surface of the substrate, and a plurality of divided surfaces which are exposed by dividing the substrate into quadrilaterals. At least one line of division lines in the case of dividing the substrate into quadrilaterals is perpendicular to any one of equivalent directions of [ | 11-22-2012 |
20120299013 | SEMICONDUCTOR LIGHT EMITTING STRUCTURE - A semiconductor light emitting structure including a substrate, a patterned structure, a first semiconductor layer, an active layer and a second semiconductor layer is provided. The patterned structure is protruded from or indented into a surface of the substrate, so that the surface of the substrate becomes a roughed surface. The patterned structure has an asymmetrical geometric shape. The first semiconductor layer is disposed on the roughed surface. The active layer is disposed on the first semiconductor layer. The second semiconductor is disposed on the active layer. | 11-29-2012 |
20120299014 | SEMICONDUCTOR LIGHT EMITTING DEVICE, NITRIDE SEMICONDUCTOR LAYER GROWTH SUBSTRATE, AND NITRIDE SEMICONDUCTOR WAFER - According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type and having a major surface, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first and second semiconductor layers. The major surface is opposite to the light emitting layer. The first semiconductor layer has structural bodies provided in the major surface. The structural bodies are recess or protrusion. A centroid of a first structural body aligns with a centroid of a second structural body nearest the first structural. hb, rb, and Rb satisfy rb/(2·hb)≦0.7, and rb/Rb<1, where hb is a depth of the recess, rb is a width of a bottom portion of the recess, and Rb is a width of the protrusion. | 11-29-2012 |
20120305940 | Defect Free Si:C Epitaxial Growth - A method and structure are disclosed for a defect free Si:C source/drain in an NFET device. A wafer is accepted with a primary surface of {100} crystallographic orientation. A recess is formed in the wafer in such manner that the bottom surface and the four sidewall surfaces of the recess are all having {100} crystallographic orientations. A Si:C material is eptaxially grown in the recess, and due to the crystallographic orientations the defect density next to each of the four sidewall surfaces is essentially the same as next to the bottom surface. The epitaxially filled recess is used in the source/drain fabrication of an NFET device. The NFET device is oriented along the <100> crystallographic direction, and has the device channel under a tensile strain due to the defect free Si:C in the source/drain. | 12-06-2012 |
20120305941 | WELL REGION FORMATION METHOD AND SEMICONDUCTOR BASE - A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to till the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to till the grooves. | 12-06-2012 |
20120305942 | EPITAXIAL SUBSTRATE, LIGHT-EMITTING DIODE, AND METHODS FOR MAKING THE EPITAXIAL SUBSTRATE AND THE LIGHT-EMITTING DIODE - An epitaxial substrate includes: a base member; and a plurality of spaced apart light-transmissive members, each of which is formed on and tapers from an upper surface of the base member, and each of which is made of a light-transmissive material having a refractive index lower than that of the base member. A light-emitting diode having the epitaxial substrate, and methods for making the epitaxial substrate and the light-emitting diode are also disclosed. | 12-06-2012 |
20120305943 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A drift layer has a thickness direction throughout which a current flows and has an impurity concentration N | 12-06-2012 |
20120305944 | SEMICONDUCTOR ELEMENT - A semiconductor element according to the present invention can perform both a transistor operation and a diode operation via its channel layer. If the potential Vgs of its gate electrode | 12-06-2012 |
20120305945 | POWER SEMICONDUCTOR DEVICE - Provided is a power semiconductor device comprising a bonding joint that, even under a temperature environment of 150° C. or greater enabling operation of a wide bandgap semiconductor, reduces cracking-destruction occurring owing to thermal cycle while conductively connecting an electrode, connection terminal, and semiconductor device substrate. | 12-06-2012 |
20120313111 | DIE ALIGNMENT WITH CRYSTALLOGRAPHIC AXES IN GaN-ON-SiC AND OTHER NON-CUBIC MATERIAL SUBSTRATES - A semiconductor chip comprises: a semiconductor structure having a single crystal substrate having a non-cubic crystallographic structure and epitaxial layers disposed on the substrate wherein adjacent sides of the semiconductor structure are at oblique angles. A method for separating a plurality of integrated circuit chips. The method includes: providing a semiconductor wafer having single crystal substrate, such substrate having a non-cubic crystallographic structure with an epitaxial layer disposed on the substrate; forming scribe lines at oblique angles to one another in the epitaxial layer; and cutting or cleaving through the substrate along the scribe lines to separate the chips. | 12-13-2012 |
20120313112 | SEMICONDUCTOR DEVICE - A MOSFET includes a silicon carbide substrate, a drift layer made of silicon carbide and including a main surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, and a gate oxide film formed on and in contact with the main surface of the drift layer. The drift layer includes a p type body region formed to include a region in contact with the gate oxide film. The p type body region has an impurity density of 5×10 | 12-13-2012 |
20120319132 | SPLIT-GATE STRUCTURE IN TRENCH-BASED SILICON CARBIDE POWER DEVICE - An integrated structure includes a plurality of split-gate trench MOSFETs. A plurality of trenches is formed within the silicon carbide substrate composition, each trench is lined with a passivation layer, each trench being substantially filled with a first conductive region a second conductive region and an insulating material having a dielectric constant similar to a dielectric constant of the silicon carbide substrate composition. The first conductive region is separated from the passivation layer by the insulating material. The first and second conductive regions form gate regions for each trench MOSFET. The first conductive region is separated from the second conductive region by the passivation layer. A doped body region of a first conductivity type formed at an upper portion of the substrate composition and a doped source region of a second conductivity type formed inside the doped body region. | 12-20-2012 |
20120319133 | OPTICALLY ASSIST-TRIGGERED WIDE BANDGAP THYRISTORS HAVING POSITIVE TEMPERATURE COEFFICIENTS - A thyristor includes a first conductivity type semiconductor layer, a first conductivity type carrier injection layer on the semiconductor layer, a second conductivity type drift layer on the carrier injection layer, a first conductivity type base layer on the drift layer, and a second conductivity type anode region on the base layer. The thickness and doping concentration of the carrier injection layer are selected to reduce minority carrier injection by the carrier injection layer in response to an increase in operating temperature of the thyristor. A cross-over current density at which the thyristor shifts from a negative temperature coefficient of forward voltage to a positive temperature coefficient of forward voltage is thereby reduced. | 12-20-2012 |
20120319134 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A gate electrode includes a polysilicon film in contact with a gate insulating film, a barrier film provided on the polysilicon film, a metal film provided on the barrier film and made of refractory metal. An interlayer insulating film is arranged so as to cover the gate insulating film and the gate electrode provided on the gate insulating film. The interlayer insulating film has a substrate contact hole partially exposing a silicon carbide substrate in a region in contact with the gate insulating film. A interconnection is electrically connected to the silicon carbide substrate through the substrate contact hole and is electrically insulated from the gate electrode by the interlayer insulating film. | 12-20-2012 |
20120319135 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An electrode layer lies on a silicon carbide substrate in contact therewith and has Ni atoms and Si atoms. The number of Ni atoms is not less than 67% of the total number of Ni atoms and Si atoms. A side of the electrode layer at least in contact with the silicon carbide substrate contains a compound of Si and Ni. On a surface side of the electrode layer, C atom concentration is lower than Ni atom concentration. Thus, improvement in electrical conductivity of the electrode layer and suppression of precipitation of C atoms at the surface of the electrode layer can both be achieved. | 12-20-2012 |
20120319136 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A SiC device includes an inversion type MOSFET having: a substrate, a drift layer, and a base region stacked in this order; source and contact regions in upper portions of the base region; a trench penetrating the source and base regions; a gate electrode on a gate insulating film in the trench; a source electrode coupled with the source and base region; a drain electrode on a back of the substrate; and multiple deep layers in an upper portion of the drift layer deeper than the trench. Each deep layer has an impurity concentration distribution in a depth direction, and an inversion layer is provided in a portion of the deep layer on the side of the trench under application of the gate voltage. | 12-20-2012 |
20120319137 | Electrostatic Discharge Protection Element and Electrostatic Discharge Protection Chip and Method of Producing the Same - An electrostatic discharge (ESD) protection element includes a collector area, a first barrier area, a semiconductor area, a second barrier area and an emitter area. The collector area has a first conductivity type. The first barrier area borders on the collector area and has a second conductivity type. The semiconductor area borders on the first barrier area and is an intrinsic semiconductor area, or has the first or second conductivity type and a dopant concentration which is lower than a dopant concentration of the first barrier area. The second barrier area borders on the semiconductor area and has the second conductivity type and a higher dopant concentration than the semiconductor area. The emitter area borders on the second barrier area and has the first conductivity type. | 12-20-2012 |
20120326162 | PROCESS FOR FORMING REPAIR LAYER AND MOS TRANSISTOR HAVING REPAIR LAYER - A repair layer forming process includes the following steps. Firstly, a substrate is provided, and a gate structure is formed on the substrate, wherein the gate structure at least includes a gate dielectric layer and a gate conductor layer. Then, a nitridation process is performed to form a nitrogen-containing superficial layer on a sidewall of the gate structure. Then, a thermal oxidation process is performed to convert the nitrogen-containing superficial layer into a repair layer. Moreover, a metal-oxide-semiconductor transistor includes a substrate, a gate dielectric layer, a gate conductor layer and a repair layer. The gate dielectric layer is formed on the substrate. The gate conductor layer is formed on the gate dielectric layer. The repair layer is at least partially formed on a sidewall of the gate conductor layer. | 12-27-2012 |
20120326163 | SEMICONDUCTOR DEVICE WITH INCREASED CHANNEL MOBILITY AND DRY CHEMISTRY PROCESSES FOR FABRICATION THEREOF - Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device. | 12-27-2012 |
20120326164 | BETAVOLTAIC APPARATUS AND METHOD - An exemplary thinned-down betavoltaic device includes an N+ doped silicon carbide (SiC) substrate having a thickness between about 3 to 50 microns, an electrically conductive layer disposed immediately adjacent the bottom surface of the SiC substrate; an N− doped SiC epitaxial layer disposed immediately adjacent the top surface of the SiC substrate, a P+ doped SiC epitaxial layer disposed immediately adjacent the top surface of the N− doped SiC epitaxial layer, an ohmic conductive layer disposed immediately adjacent the top surface of the P+ doped SiC epitaxial layer, and a radioisotope layer disposed immediately adjacent the top surface of the ohmic conductive layer. The radioisotope layer can be | 12-27-2012 |
20120326165 | HEMT INCLUDING AIN BUFFER LAYER WITH LARGE UNEVENNESS - A HEMT comprised of nitride semiconductor materials is disclosed. The HEMT includes, on a SiC substrate, a AlN buffer layer, a GaN channel layer, and a AlGaN doped layer. A feature of the HEMT is that the AlN buffer layer is grown on an extraordinary condition of the pressure, and has a large unevenness in a thickness thereof to enhance the release of carriers captured in traps in the substrate back to the channel layer. | 12-27-2012 |
20120326166 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A substrate has a surface made of a semiconductor having a hexagonal single-crystal structure of polytype 4H. The surface of the substrate is constructed by alternately providing a first plane having a plane orientation of (0-33-8), and a second plane connected to the first plane and having a plane orientation different from the plane orientation of the first plane. A gate insulating film is provided on the surface of the substrate. A gate electrode is provided on the gate insulating film. | 12-27-2012 |
20120326167 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A silicon carbide substrate has a substrate surface. A gate insulating film is provided to cover a part of the substrate surface. A gate electrode covers a part of the gate insulating film. A contact electrode is provided on the substrate surfaces, adjacent to and in contact with the gate insulating film, and it contains an alloy having Al atoms. Al atoms do not diffuse from the contact electrode into a portion of the gate insulating film lying between the substrate surface and the gate electrode. Thus, in a case where a contact electrode having Al atoms is employed, reliability of the gate insulating film of a semiconductor device can be improved | 12-27-2012 |
20120326168 | TRANSISTOR WITH BURIED SILICON GERMANIUM FOR IMPROVED PROXIMITY CONTROL AND OPTIMIZED RECESS SHAPE - A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base. | 12-27-2012 |
20130001591 | FINFET DESIGN AND METHOD OF FABRICATING SAME - An integrated circuit device and method for manufacturing the same are disclosed. An exemplary device includes a semiconductor substrate having a substrate surface and a trench isolation structure disposed in the semiconductor substrate for isolating an NMOS region of the device and from a PMOS region of the device. The device further includes a first fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant greater than that of Ge; a second fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant smaller than that of Ge; and a gate structure disposed over and arranged perpendicular to the first and second fin structures. | 01-03-2013 |
20130001592 | SILICON CARBIDE SEMICONDUCTOR DEVICE - In a silicon carbide semiconductor device, a plurality of trenches has a longitudinal direction in one direction and is arranged in a stripe pattern. Each of the trenches has first and second sidewalls extending in the longitudinal direction. The first sidewall is at a first acute angle to one of a (11-20) plane and a (1-100) plane, the second sidewall is at a second acute angle to the one of the (11-20) plane and the (1-100) plane, and the first acute angle is smaller than the second acute angle. A first conductivity type region is in contact with only the first sidewall in the first and second sidewalls of each of the trenches, and a current path is formed on only the first sidewall in the first and second sidewalls. | 01-03-2013 |
20130001593 | SEMICONDUCTOR DEVICE STRUCTURES INCLUDING TRANSISTORS WITH ENERGY BARRIERS ADJACENT TO TRANSISTOR CHANNELS AND ASSOCIATED METHODS - A semiconductor device structure includes a transistor with an energy barrier beneath its transistor channel. The energy barrier prevents leakage of stored charge from the transistor channel into a bulk substrate. Methods for fabricating semiconductor devices that include energy barriers are also disclosed. | 01-03-2013 |
20130009167 | LIGHT EMITTING DIODE WITH PATTERNED STRUCTURES AND METHOD OF MAKING THE SAME - A light emitting diode is provided which includes an active region in combination with a current spreading layer; and a crystalline epitaxial film light extraction layer in contact with the current spreading layer, the light extraction layer being patterned with nano/micro structures which increase extraction of light emitted from the active region. | 01-10-2013 |
20130009168 | SEMICONDUCTOR MODULE - A semiconductor module is disclosed that includes a semiconductor element, a capacitor configured to be electrically connected to the semiconductor element and a heat sink, wherein the semiconductor and the capacitor are stacked with each other via the heat sink, and wherein the semiconductor element is disposed in a position overlapping with the capacitor as viewed from a stack direction. | 01-10-2013 |
20130009169 | METHODS OF MAKING VERTICAL JUNCTION FIELD EFFECT TRANSISTORS AND BIPOLAR JUNCTION TRANSISTORS WITHOUT ION IMPLANTATION AND DEVICES MADE THEREWITH - Methods of making semiconductor devices such as vertical junction field effect transistors (VJFETs) or bipolar junction transistors (BJTs) are described. The methods do not require ion implantation. The VJFET device has an epitaxially regrown n-type channel layer and an epitaxially regrown p-type gate layer as well as an epitaxially grown buried gate layer. Devices made by the methods are also described. | 01-10-2013 |
20130009170 | EPITAXIAL SiC SINGLE CRYSTAL SUBSTRATE AND METHOD OF MANUFACTURE OF EPITAXIAL SiC SINGLE CRYSTAL SUBSTRATE - An epitaxial SiC single crystal substrate including a SiC single crystal wafer whose main surface is a c-plane or a surface that inclines a c-plane with an angle of inclination that is more than 0 degree but less than 10 degrees, and SiC epitaxial film that is formed on the main surface of the SiC single crystal wafer, wherein the dislocation array density of threading edge dislocation arrays that are formed in the SiC epitaxial film is 10 arrays/cm | 01-10-2013 |
20130009171 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device has a semiconductor layer and a substrate. The semiconductor layer constitutes at least a part of a current path, and is made of silicon carbide. The substrate has a first surface supporting the semiconductor layer, and a second surface opposite to the first surface. Further, the substrate is made of silicon carbide having a 4H type single-crystal structure. Further, the substrate has a physical property in which a ratio of a peak strength in a wavelength of around 500 nm to a peak strength in a wavelength of around 390 nm is 0.1 or smaller in photoluminescence measurement. In this way, the semiconductor device is obtained to have a low on-resistance. | 01-10-2013 |
20130015467 | System and Method for Wafer Level PackagingAANM Krumbein; UlrichAACI RosenheimAACO DEAAGP Krumbein; Ulrich Rosenheim DEAANM Lohninger; GerhardAACI MuenchenAACO DEAAGP Lohninger; Gerhard Muenchen DEAANM Dehe; AlfonsAACI ReutlingenAACO DEAAGP Dehe; Alfons Reutlingen DE - In an embodiment, a semiconductor device includes a semiconductor substrate. The semiconductor substrate has a first cavity disposed through it, and conductive material covers at least the bottom portion of the first cavity. An integrated circuit is disposed on the top surface of the conductive material. The device further includes a cap disposed on the top surface of the substrate, such that a cavity disposed on a surface of the cap overlies the first cavity in the substrate. | 01-17-2013 |
20130015468 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEAANM KIKUCHI; MasaoAACI TokyoAACO JPAAGP KIKUCHI; Masao Tokyo JP - A semiconductor device of the present invention comprises a semiconductor element, a first metal body formed on a back surface of the semiconductor element, a first insulating layer formed on a back surface of the first metal body, a second metal body formed on a back surface of the first insulating layer, a third metal body formed on a front surface of the semiconductor element, a second insulating layer formed on a front surface of the third metal body and a fourth metal body formed on a front surface of the second insulating layer, and the second metal body is thinner than the first metal body and the fourth metal body is thicker than the third metal body. With this structure, it is possible to increase the heat radiation performance while suppressing stress to be exerted on the semiconductor element. | 01-17-2013 |
20130015469 | METHOD FOR MANUFACTURING DIODE, AND DIODE - A semiconductor substrate having a first side and a second side made of single crystal silicon carbide is prepared. A mask layer having a plurality of openings and made of silicon oxide is formed on the second side. The plurality of openings expose a plurality of regions included in the second side, respectively. A plurality of diamond portions are formed by epitaxial growth on the plurality of regions, respectively. The epitaxial growth is stopped before the plurality of diamond portions come into contact with each other. A Schottky electrode is formed on each of the plurality of diamond portions. An ohmic electrode is formed on the first side. | 01-17-2013 |
20130020585 | SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING THEM - A silicon carbide substrate capable of reducing on-resistance and improving yield of semiconductor devices is made of single-crystal silicon carbide, and sulfur atoms are present in one main surface at a ratio of not less than 60×10 | 01-24-2013 |
20130020586 | SEMICONDUCTOR DEVICE - A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another. | 01-24-2013 |
20130020587 | POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole. | 01-24-2013 |
20130026489 | AlN BUFFER N-POLAR GaN HEMT PROFILE - An N-face GaN HEMT device including a semiconductor substrate, a buffer layer including AlN or AlGaN deposited on the substrate, a barrier layer including AlGaN or AlN deposited on the buffer layer and a GaN channel layer deposited on the barrier layer. The channel layer, the barrier layer and the buffer layer create a two-dimensional electron gas (2-DEG) layer at a transition between the channel layer and the barrier layer. | 01-31-2013 |
20130026490 | GLASS/CERAMICS REPLACEMENT OF EPOXY FOR HIGH TEMPERATURE HERMETICALLY SEALED NON-AXIAL ELECTRONIC PACKAGES - A high temperature, non-cavity package for non-axial electronics is designed using a glass ceramic compound with that is capable of being assembled and operating continuously at temperatures greater that 300-400° C. Metal brazes, such as silver, silver colloid or copper, are used to connect the semiconductor die, lead frame and connectors. The components are also thermally matched such that the packages can be assembled and operating continuously at high temperatures and withstand extreme temperature variations without the bonds failing or the package cracking due to a thermal mismatch. | 01-31-2013 |
20130026491 | LED STRUCTURE AND METHOD FOR MANUFACTURING THEREOF - The present invention discloses a LED structure and a method for manufacturing the LED structure. The LED structure includes a substrate, a reflection layer, a first conducting layer, a light emitting layer, and a second conducting layer. The substrate has a plurality of grooves, and the reflection layer is disposed inside the plurality of grooves. The reflection layer is formed as a reflection block inside each of the grooves. The first conducting layer is disposed on the substrate, that is, the reflection layer is disposed between the first conducting layer and the substrate. The light emitting layer and the second conducting layer are sequentially disposed on the first conducting layer. The light emitting layer generates light when a current pass through the light emitting layer. Accordingly, the light generated by the light emitting layer can be emitted to the same side of the LED structure. | 01-31-2013 |
20130026492 | Diamond Semiconductor System and Method - Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond material having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice. | 01-31-2013 |
20130026493 | SIC DEVICES WITH HIGH BLOCKING VOLTAGE TERMINATED BY A NEGATIVE BEVEL - The present disclosure relates to a Silicon Carbide (SiC) semiconductor device having both a high blocking voltage and low on-resistance. In one embodiment, the semiconductor device has a blocking voltage of at least 10 kilovolts (kV) and an on-resistance of less than 10 milli-ohms centimeter squared (mΩ·cm | 01-31-2013 |
20130026494 | SILICON CARBIDE SEMICONDUCTOR DEVICE - An SiC semiconductor device includes a semiconductor element formed in an SiC substrate, a source electrode and a gate pad formed by using an interconnect layer having barrier metal provided at the bottom surface thereof, and a temperature measuring resistive element formed by using part of the barrier metal in the interconnect line. | 01-31-2013 |
20130026495 | III-Nitride Metal Insulator Semiconductor Field effect Transistor - A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers. | 01-31-2013 |
20130026496 | Semiconductor Device and Manufacturing Method Thereof - A method for manufacturing a semiconductor device, comprising forming a tunneling dielectric layer, a storage dielectric layer, a gate dielectric layer and a gate layer sequentially on a semiconductor substrate of a first semiconductor material; patterning the tunneling dielectric layer, the storage dielectric layer, the gate dielectric layer and the gate layer to form a gate stack; forming a groove in the semiconductor substrate on the sides of the gate stack; filling the groove with a second semiconductor material different from the first semiconductor material, meanwhile, the entire device is covered by the dielectric layer. The surface energy level in the channel is made to change by the stress generated by the second semiconductor material and the covering dielectric layer, thereby increasing tunneling current and improving the storage efficiency of the device. | 01-31-2013 |
20130026497 | SILICON CARBIDE SUBSTRATE MANUFACTURING METHOD AND SILICON CARBIDE SUBSTRATE - Silicon carbide single crystal is prepared. Using the silicon carbide single crystal as a material, a silicon carbide substrate having a first face and a second face located at a side opposite to the first face is formed. In the formation of the silicon carbide substrate, a first processed damage layer and a second processed damage layer are formed at the first face and second face, respectively. The first face is polished such that at least a portion of the first processed damage layer is removed and the surface roughness of the first face becomes less than or equal to 5 nm. At least a portion of the second processed damage layer is removed while maintaining the surface roughness of the second plane greater than or equal to 10 nm. | 01-31-2013 |
20130032821 | SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING THE SAME - A Schottky barrier diode (SBD) is provided, which improves electrical characteristics and optical characteristics by securing high crystallinity by including an n-gallium nitride (GaN) layer and a GaN layer which are doped with aluminum (Al). In addition, by providing a p-GaN layer on the Al-doped GaN layer, a depletion layer may be formed when a reverse current is applied, thereby reducing a leakage current. The SBD may be manufactured by etching a part of the Al-doped GaN layer and growing a p-GaN layer from the etched part of the Al-doped GaN layer. Therefore, a thin film crystal is not damaged, thereby increasing reliability. Also, since dedicated processes for ion implantation and thermal processing are not necessary, simplified process and reduced cost may be achieved. | 02-07-2013 |
20130032822 | SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation σ of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation σ of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm. | 02-07-2013 |
20130032823 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A first layer has a first conductivity type. A second layer is provided on the first layer such that a part of the first layer is exposed, and it has a second conductivity type. First to third impurity regions penetrate the second layer and reach the first layer. Each of the first and second impurity regions has the first conductivity type. | 02-07-2013 |
20130032824 | SILICON CARBIDE SEMICONDUCTOR DEVICE - First, second, fourth, and fifth impurity regions have a first conductivity type, and a third impurity region has a second conductivity type. The first to third impurity regions reach a first layer having the first conductivity type. The fourth and fifth impurity regions are provided on a second layer. First to fifth electrodes are provided on the first to fifth impurity regions, respectively. Electrical connection is established between the first and fifth electrodes, and between the third and fourth electrodes. A sixth electrode is provided on a gate insulating film covering a portion between the fourth and fifth impurity regions. | 02-07-2013 |
20130037821 | Semiconductor Device and Manufacturing Method thereof - The present invention provides a semiconductor device, comprising: a substrate; shallow trench isolations embedded into the substrate and forming at least one opening area; a channel region located in the opening area; a gate stack comprising a gate dielectric layer and a gate electrode layer and located above the channel region; source/drain regions located at both sides of the channel region and comprising a stress layer that provides a strain to the channel region; wherein, there is a liner layer between the shallow trench isolation and the stress layer, which serves as the seed layer of the stress layer. A liner layer that is of the same or similar material as the stress layer in the source/drain region is inserted between the STI and the stress layer of the source/drain region as a seed layer or nucleation layer for the epitaxial growth, thereby eliminating the STI edge effect during the source/drain strain engineering, i.e. eliminating the gap between the STI and the stress layer of the source/drain region, as a result, the reduction of the channel stress produced by the source/drain strain is prevented, the carrier mobility of the MOS device is increased and the driving capability of the device is enhanced. | 02-14-2013 |
20130037822 | Semiconductor Device and Manufacturing Method Thereof - A semiconductor device and its manufacturing method are provided. The semiconductor device comprises: a semiconductor substrate of a first semiconductor material, a gate structure on the semiconductor substrate, a crystal lattice dislocation line in a channel under the gate structure for generating channel stress, wherein the crystal lattice dislocation line being at an angle to the channel. | 02-14-2013 |
20130037823 | SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer. | 02-14-2013 |
20130037824 | POWER SEMICONDUCTOR DEVICE - Cell electrodes are provided respectively for cell structures on a semiconductor substrate. The cell electrodes are divided into groups each including two or more cell electrodes. Conductive members are respectively electrically connected to the groups. The conductive members have a used portion and an unused portion. The used portion has two or more conductive members electrically connected to each other. The unused portion has at least one of the conductive members and is electrically insulated from the used portion. | 02-14-2013 |
20130043489 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A compound semiconductor device includes: a substrate; a GaN compound semiconductor multilayer structure disposed over the substrate; and a stress relief layer which is AlN-based and which is disposed between the substrate and the GaN compound semiconductor multilayer structure, wherein a surface of the stress relief layer that is in contact with the GaN compound semiconductor multilayer structure includes recesses that have a depth of 5 nm or more and that are formed at a number density of 2×10 | 02-21-2013 |
20130043490 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE DEVICE - The semiconductor device | 02-21-2013 |
20130043491 | Schottky Diodes Including Polysilicon Having Low Barrier Heights - Hybrid semiconductor devices including a PIN diode portion and a Schottky diode portion are provided. The PIN diode portion is provided on a semiconductor substrate and has an anode contact on a first surface of the semiconductor substrate. The Schottky diode portion is also provided on the semiconductor substrate and includes a polysilicon layer on the semiconductor substrate and a ohmic contact on the polysilicon layer. Related Schottky diodes are also provided herein. | 02-21-2013 |
20130043492 | NITRIDE SEMICONDUCTOR TRANSISTOR - A nitride semiconductor transistor includes a heterojunction layer including a plurality of nitride semiconductor layers having different polarizations, and a gate electrode disposed on the heterojunction layer. An electron current reduction layer having a p-type conductivity is disposed between the heterojunction layer and the gate electrode to pass hole current therethrough and reduce electron current. | 02-21-2013 |
20130056752 | SILICON CARBIDE SUBSTRATE, SILICON CARBIDE SUBSTRATE MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - An edge region has a width of 5 mm. A valid region is surrounded by the edge region, and has an area greater than or equal to 100 cm | 03-07-2013 |
20130056753 | Semiconductor Device with Low-Conducting Field-controlling Element - A semiconductor device including a low conducting field-controlling element is provided. The device can include a semiconductor including an active region (e.g., a channel), and a set of contacts to the active region. The field-controlling element can be coupled to one or more of the contacts in the set of contacts. The field-controlling element can be formed of a low conducting layer of material and have a lateral resistance that is both larger than an inverse of a minimal operating frequency of the device and smaller than an inverse of a maximum control frequency of the device. | 03-07-2013 |
20130056754 | ELECTRONIC CIRCUIT DEVICE - A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET. | 03-07-2013 |
20130056755 | POWER SEMICONDUCTOR MODULE - A transistor chip formed from a wide band gap semiconductor, on which transistor elements for an upper arm are formed is mounted on a front surface of an insulating substrate. A transistor chip formed from a wide band gap semiconductor, on which transistor elements for a lower arm are formed is mounted on a rear surface of the insulating substrate. | 03-07-2013 |
20130062619 | EDGE TERMINATION STRUCTURE EMPLOYING RECESSES FOR EDGE TERMINATION ELEMENTS - Elements of an edge termination structure, such as multiple concentric guard rings, are effectively doped regions in a drift layer. To increase the depth of these doped regions, individual recesses may be formed in a surface of the drift layer where the elements of the edge termination structure are to be formed. Once the recesses are formed in the drift layer, these areas about and at the bottom of the recesses are doped to form the respective edge termination elements. | 03-14-2013 |
20130062620 | SCHOTTKY DIODE EMPLOYING RECESSES FOR ELEMENTS OF JUNCTION BARRIER ARRAY - The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the substrate. A junction barrier array is provided in the drift layer just below the Schottky layer. The elements of the junction barrier array are generally doped regions in the drift layer. To increase the depth of these doped regions, individual recesses may be formed in the surface of the drift layer where the elements of the junction barrier array are to be formed. Once the recesses are formed in the drift layer, areas about and at the bottom of the recesses are doped to form the respective elements of the junction barrier array. | 03-14-2013 |
20130062621 | III-N DEVICE STRUCTURES HAVING A NON-INSULATING SUBSTRATE - Embodiments of the present disclosure includes a III-N device having a substrate layer, a first III-N material layer on one side of the substrate layer, a second III-N material layer on the first III-N material layer, and a barrier layer disposed on another side of the substrate layer, the barrier layer being less electrically conductive than the substrate layer. | 03-14-2013 |
20130062622 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present embodiment includes a semiconductor substrate having a first n-type silicon carbide layer and a second n-type silicon carbide layer, a first p-type impurity region formed in the n-type silicon carbide layer, a first n-type impurity region of 4H—SiC structure formed in the n-type silicon carbide layer, a second n-type impurity region of 3C—SiC structure formed in the n-type silicon carbide layer having a depth shallower than the first n-type impurity region, a gate insulating film, a gate electrode formed on the gate insulating film, and a metallic silicide layer formed above the first n-type impurity region and having a bottom portion and a side surface portion such that the second n-type impurity region is sandwiched between the first n-type impurity region and at least the side surface portion. | 03-14-2013 |
20130062623 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a semiconductor device including: a first electrode formed of a conductive material; a p-type first silicon carbide (SiC) semiconductor section and an n-type second SiC semiconductor section | 03-14-2013 |
20130062624 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes a silicon carbide, a metal silicide formed on the silicon carbide and including a first layer and a second layer having a carbon ratio lower than that of the first layer, and a metallic electrode formed on the metal silicide, wherein the second layer is formed on the first layer, and the second layer is in contact with the metallic electrode, and an average grain diameter of a metal silicide in the second layer is larger than an average grain diameter of a metal silicide in the first layer. | 03-14-2013 |
20130062625 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device including: a semiconductor substrate; a field effect transistor formed on the semiconductor substrate; and a diode forming area adjacent to a forming area of the field effect transistor, wherein the diode forming area is insulated from the forming area of the field effect transistor on the semiconductor substrate, the diode forming area includes an anode electrode and a cathode electrode arranged side by side in a multi-finger shape, and the anode electrode and the cathode electrode are formed in a direction different from directions of a gate electrode, a source electrode, and a drain electrode of the field effect transistor arranged side by side in a multi-finger shape. | 03-14-2013 |
20130062626 | POWER SEMICONDUCTOR MODULE - Disclosed is a power semiconductor module which includes a unipolar type switching device using a wide bandgap semiconductor (wide bandgap semiconductor switching device) and an insulated gate bipolar transistor using a silicon semiconductor (Si-IGBT) connected in parallel, in which a chip area of the wide bandgap semiconductor switching device is smaller than that of the Si-IGBT. | 03-14-2013 |
20130062627 | STRESS REGULATED SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS - Stress regulated semiconductor devices and associated methods are provided. In one aspect, for example, a stress regulated semiconductor device can include a semiconductor layer, a stress regulating interface layer including a carbon layer formed on the semiconductor layer, and a heat spreader coupled to the carbon layer opposite the semiconductor layer. The stress regulating interface layer is operable to reduce the coefficient of thermal expansion difference between the semiconductor layer and the heat spreader to less than or equal to about 10 ppm/° C. | 03-14-2013 |
20130062628 | METHODS FOR THE EPITAXIAL GROWTH OF SILICON CARBIDE - A method for the epitaxial growth of SiC is described which includes contacting a surface of a substrate with hydrogen and HCl, subsequently increasing the temperature of the substrate to at least 1550° C. and epitaxially growing SiC on the surface of the substrate. A method for the epitaxial growth of SiC is also described which includes heating a substrate to a temperature of at least 1550° C., contacting a surface of the substrate with a C containing gas and a Si containing gas at a C/Si ratio of 0.5-0.8 to form a SiC buffer layer and subsequently contacting the surface with a C containing gas and a Si containing gas at a C/Si ratio >0.8 to form a SiC epitaxial layer on the SiC buffer layer. The method results in silicon carbide epitaxial layers with improved surface morphology. | 03-14-2013 |
20130062629 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A substrate is provided with a main surface having an off angle of 5° or smaller relative to a reference plane. The reference plane is a {000-1} plane in the case of hexagonal system and is a {111} plane in the case of cubic system. A silicon carbide layer is epitaxially formed on the main surface of the substrate. The silicon carbide layer is provided with a trench having first and second side walls opposite to each other. Each of the first and second side walls includes a channel region. Further, each of the first and second side walls substantially includes one of a {0-33-8} plane and a {01-1-4} plane in the case of the hexagonal system and substantially includes a {100} plane in the case of the cubic system. | 03-14-2013 |
20130069080 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a silicon carbide substrate having a first surface and a second surface on a side opposite to the first surface, a semiconductor layer having an element region and a peripheral region provided on the second surface of the silicon carbide substrate, an insulating film provided on a surface of the peripheral region of the semiconductor layer, a reinforcing substrate provided on the insulating film in the peripheral region, a first electrode provided in contact with the first surface of the silicon carbide substrate, and a second electrode provided in contact with a surface of the element region. The peripheral region is further on an edge portion side than is the element region. | 03-21-2013 |
20130069081 | Layout Method To Minimize Context Effects and Die Area - An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor. | 03-21-2013 |
20130069082 | SEMICONDUCTOR DEVICE AND SOLID STATE RELAY USING SAME - A semiconductor device includes one or more unipolar compound semiconductor element; and bypass semiconductor elements externally connected to the respective compound semiconductor elements in parallel. A turn-on voltage of the bypass semiconductor elements is smaller than a turn-on voltage of the compound semiconductor elements in the direction from the source to the drain. | 03-21-2013 |
20130075756 | SEMICONDUCTOR DEVICE AND METHOD FOR REDUCED BIAS THRESHOLD INSTABILITY - According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate. | 03-28-2013 |
20130075757 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present embodiment includes a diamond substrate having a surface plane inclined from a (100) plane in a range of 10 degrees to 40 degrees in a direction of <011> ±10 degrees, and an n-type diamond semiconductor layer containing phosphorus (P) and formed above the surface plane described above. | 03-28-2013 |
20130075758 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A MOSFET includes a semiconductor substrate having a trench formed in a main surface, a gate oxide film, a gate electrode, and a source interconnection. A semiconductor substrate includes an n-type drift layer and a p-type body layer. The trench is formed to penetrate the body layer and to reach the drift layer. The trench includes an outer peripheral trench arranged to surround an active region when viewed two-dimensionally. On the main surface opposite to the active region when viewed from the outer peripheral trench, a potential fixing region where the body layer is exposed is formed. The source interconnection is arranged to lie over the active region when viewed two-dimensionally. The potential fixing region is electrically connected to the source interconnection. | 03-28-2013 |
20130075759 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A first layer has n type conductivity. A second layer is epitaxially formed on the first layer and having p type conductivity. A third layer is on the second layer and having n type conductivity. ND is defined to represent a concentration of a donor type impurity. NA is defined to represent a concentration of an acceptor type impurity. D | 03-28-2013 |
20130075760 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present application relates to technology for improving a withstand voltage of a semiconductor device. The semiconductor device includes a termination area that surrounds a cell area. The cell area is provided with a plurality of main trenches. The termination area is provided with one or more termination trenches surrounding the cell area. A termination trench is disposed at an innermost circumference of one or more termination trenches. A body region is disposed on a surface of a drift region. Each main trench reaches the drift region. A gate electrode is provided within each main trench. The termination trench reaches the drift region. Sidewalls and a bottom surface of the termination trench are covered with a insulating layer. A surface of the insulating layer covering the bottom surface of the termination trench is covered with a buried electrode. A gate potential is applied to the buried electrode. | 03-28-2013 |
20130082280 | LIGHT EMITTING DEVICES HAVING LIGHT COUPLING LAYERS - A light emitting device comprises a first layer of an n-type semiconductor material, a second layer of a p-type semiconductor material, and an active layer between the first layer and the second layer. A light coupling layer is disposed adjacent to one of the first layer and the second layer. In some cases, the light coupling layer is formed by roughening a buffer layer of the light emitting device. The light emitting device includes an electrode in electrical communication with one of the first layer and the second layer through a portion of the light coupling layer. | 04-04-2013 |
20130082281 | METHOD AND STRUCTURE HAVING MONOLITHIC HETEROGENEOUS INTEGRATION OF COMPOUND SEMICONDUCTORS WITH ELEMENTAL SEMICONDUCTOR - A semiconductor structure having compound semiconductor (CS) device formed in a compound semiconductor of the structure and an elemental semiconductor device formed in an elemental semiconductor layer of the structure. The structure includes a layer having an elemental semiconductor device is disposed over a buried oxide (BOX) layer. A selective etch layer is disposed between the BOX layer and a layer for a compound semiconductor device. The selective etch layer enables selective etching of the BOX layer to thereby maximize vertical and lateral window etch process control for the compound semiconductor device grown in etched window. The selective etch layer has a lower etch rate than the etch rate of the BOX layer. | 04-04-2013 |
20130082282 | SILICON CARBIDE SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device which includes a silicon carbide layer, a trench formed in the silicon carbide layer, and a channel formed on at least one of a bottom of the trench, a side-wall surface, or the silicon carbide layer, in which an electrical conduction direction of the channel is parallel to a surface of the silicon carbide layer. | 04-04-2013 |
20130082283 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - A semiconductor device includes an insulating substrate, a wiring pattern formed on the insulating substrate, a semiconductor chip secured to the wiring pattern, a junction terminal formed of the same material as the wiring pattern and electrically connected to the semiconductor chip, one end of the junction terminal being secured to the insulating substrate, the other end of the junction terminal extending upward away from the insulating substrate, and a control circuit for transmitting a control signal for the semiconductor chip, the control circuit being electrically connected to the junction terminal. | 04-04-2013 |
20130082284 | ELECTRONIC CIRCUIT - An electronic circuit includes a bipolar device, a unipolar device connected in parallel to the bipolar device, and an output line connected to the bipolar device and to the unipolar device. An inductance between the unipolar device and the output line is smaller than an inductance between the bipolar device and the output line. | 04-04-2013 |
20130082285 | SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCTION THEREOF - A semiconductor device according to the present invention includes a contact region | 04-04-2013 |
20130087808 | SIC BIPOLAR JUNCTION TRANSISTOR WITH OVERGROWN EMITTER - New designs for silicon carbide (SiC) bipolar junction transistors (BJTs) and new methods of manufacturing such SiC BJTs are provided. The SiC BJT can include a collector region, a base region, and an emitter region where the collector region, the base region, and the emitter region are arranged as a stack. The emitter region can form an elevated structure defined by outer sidewalls disposed on the stack. The base region can have a portion interfacing the emitter region and defining an intrinsic base region. The intrinsic base region can include a first portion laterally spaced away from the outer sidewalls of the emitter region by a second portion of the base region that has a dopant dose higher than a dopant dose of the first portion. | 04-11-2013 |
20130087809 | METHOD OF MANUFACTURING A SiC BIPOLAR JUNCTION TRANSISTOR AND SiC BIPOLAR JUNCTION TRANSISTOR THEREOF - A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT are provided. The SiC BJT comprises an emitter region, a base region and a collector region. The collector region is arranged on a substrate having an off-axis orientation of about 4 degrees or lower. Further, a defect termination layer (DTL) is arranged between the substrate and the collector region. A thickness and a doping level of the DTL are configured to terminate basal plane dislocations in the DTL and reduce the growth of defects from the DTL to the collector region. At least some of the embodiments are advantageous in that SiC BJTs with improved stability are provided. Further, a method of evaluating the degradation performance of a SiC BJT is provided. | 04-11-2013 |
20130087810 | FIN FIELD-EFFECT TRANSISTOR STRUCTURE - A fin field-effect transistor structure comprises a substrate, a fin channel, a source/drain region, a high-k metal gate and a plurality of slot contact structures. The fin channel is formed on the substrate. The source/drain region is formed in the fin channel. The high-k metal gate formed on the substrate and the fin channel comprises a high-k dielectric layer and a metal gate layer, wherein the high-k dielectric layer is arranged between the metal gate layer and the fin channel. The slot contact structures are disposed at both sides of the metal gate. | 04-11-2013 |
20130092954 | Strained Silicon Channel Semiconductor Structure and Method of Making the Same - A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased. | 04-18-2013 |
20130092955 | LIGHT EMITTING DIODE AND FABRICATING METHOD THEREOF - A light-emitting diode (LED) and fabricating method thereof. The method includes: providing a first substrate and forming an epitaxial portion on the first substrate; forming at least one reflection layer on the epitaxial portion; forming a metal barrier portion on the reflection layer; etching the epitaxial portion and the barrier portion by a first etching process, so as to form a plurality of epitaxial layers and a plurality of metal barrier layers, an etch channel is formed between adjacent epitaxial layers, and each metal barrier layer enwraps a corresponding reflection layer and covers all of a surface of a corresponding epitaxial layer; forming a first bonding layer on the metal barrier layer; and forming a second substrate on the first bonding layer and removing the first substrate. | 04-18-2013 |
20130092956 | SILICON CARBIDE SUBSTRATE, SILICON CARBIDE SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - Single crystal substrates are made of silicon carbide, and each have a first front-side surface and a first backside surface opposite to each other. A support substrate has a second front-side surface and a second backside surface opposite to each other. A connection layer has silicon carbide as a main component, and lies between the single crystal substrates and the support substrate for connecting each of the first backside surfaces and the second front-side surface such that each of the first backside surfaces faces the second front-side surface. | 04-18-2013 |
20130092957 | SELF-ALIGNED SILICIDATION FOR REPLACEMENT GATE PROCESS - A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer. | 04-18-2013 |
20130092958 | NORMALLY-OFF III-NITRIDE METAL-2DEG TUNNEL JUNCTION FIELD-EFFECT TRANSISTORS - Structures, devices and methods are provided for creating heterojunction AlGaN/GaN metal two-dimensional electron gas (2DEG) tunnel-junction field-effect transistors (TJ-FET). In one aspect, metal-2DEG Schottky tunnel junctions can be employed in group III-Nitride field-effect devices that enable normally-off operation, large breakdown voltage, low leakage current, and high on/off current ratio. As a further advantage, AlGaN/GaN metal-2DEG TJ-FETs are disclosed that can be fabricated in a lateral configuration and/or a vertical configuration. Further non-limiting embodiments are provided that illustrate the advantages and flexibility of the disclosed structures. | 04-18-2013 |
20130099250 | STRUCTURE OF SEMICONDUCTOR CHIPS WITH ENHANCED DIE STRENGTH AND A FABRICATION METHOD THEREOF - An improved structure of semiconductor chips with enhanced die strength and a fabrication method thereof are disclosed. The improved structure comprises a substrate, an active layer, and a backside metal layer, in which the active layer is formed on the front side of the substrate and includes at least one integrated circuit; the backside metal layer is formed on the backside of the substrate, which fully covers the area corresponding to the area covered by the integrated circuits in the active layer. By using the specific dicing process of the present invention, the backside metal layer and the substrate can be diced tidily. Die cracking on the border between the substrate and the backside metal layer of the diced single chip can be prevented, and thereby the die strength can be significantly enhanced. | 04-25-2013 |
20130099251 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - When viewed in a plan view, a termination region (TM) surrounds an element region (CL). A first side of a silicon carbide substrate (SB) is thermally etched to form a side wall (ST) and a bottom surface (BT) in the silicon carbide substrate (SB) at the termination region (TM). The side wall (ST) has a plane orientation of one of {0-33-8} and {0-11-4}. The bottom surface (BT) has a plane orientation of {000-1}. On the side wall (ST) and the bottom surface (BT), an insulating film ( | 04-25-2013 |
20130099252 | METHOD OF MANUFACTURING SILICON CARBIDE SUBSTRATE AND SILICON CARBIDE SUBSTRATE - A method of manufacturing a silicon carbide substrate includes the steps of preparing an ingot composed of single crystal silicon carbide, obtaining a silicon carbide substrate by slicing the ingot, and polishing a surface of the silicon carbide substrate. In the step of obtaining a silicon carbide substrate, the ingot is sliced such that cutting proceeds in a direction in which an angle formed with respect to a <11-20> direction or a <1-100> direction is 15±5° in an orthogonal projection on a {0001} plane. In the step of polishing a surface of the silicon carbide substrate, at least one of main surfaces of the silicon carbide substrate is polished while the entire surface of at least one of the main surfaces of the silicon carbide substrate is in contact with a polishing surface. | 04-25-2013 |
20130099253 | EPITAXIAL WAFER AND SEMICONDUCTOR DEVICE - A semiconductor device that can suppress deterioration in crystal quality caused by a lattice mismatch between a substrate and an epitaxial layer and that also can ensure a voltage sustaining performance, and a wafer for forming the semiconductor device. An epitaxial wafer of silicon carbide (SiC), which is used for manufacturing a semiconductor device, includes a low resistance substrate and an epitaxial layer provided thereon. The epitaxial layer is doped with the same dopant as a dopant doped into the substrate, and has a laminated structure including a low concentration layer and an ultrathin high concentration layer. A doping concentration in the low concentration layer is lower than that in the silicon carbide substrate. A doping concentration in the ultrathin high concentration layer is equal to that in the silicon carbide substrate. | 04-25-2013 |
20130105816 | METHOD AND SYSTEM FOR TRANSIENT VOLTAGE SUPPRESSORS | 05-02-2013 |
20130105817 | HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE AND METHOD | 05-02-2013 |
20130105818 | MOSFET WITH THIN SEMICONDUCTOR CHANNEL AND EMBEDDED STRESSOR WITH ENHANCED JUNCTION ISOLATION AND METHOD OF FABRICATION | 05-02-2013 |
20130105819 | SEMICONDUCTOR DEVICE | 05-02-2013 |
20130105820 | TRENCH TYPE SCHOTTKY JUNCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 05-02-2013 |
20130112991 | SILICON CARBIDE SCHOTTKY-BARRIER DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a silicon carbide Schottky-barrier diode device and a method for manufacturing the same. The silicon carbide Schottky bather diode device includes a primary n− epitaxial layer, an n+ epitaxial region, and a Schottky metal layer. The primary n− epitaxial layer is deposited on an n+ substrate joined with an ohmic metal layer at an undersurface thereof. The n+ epitaxial region is formed by implanting n+ ions into a central region of the primary n− epitaxial layer. The Schottky metal layer is deposited on the n+ epitaxial layer. | 05-09-2013 |
20130112992 | HIGH TEMPERATURE TRANSDUCER USING SOI, SILICON CARBIDE OR GALLIUM NITRIDE ELECTRONICS - There is disclosed a high temperature pressure sensing system which includes a SOI, silicon carbide, or gallium nitride Wheatstone bridge including piezoresistors. The bridge provides an output which is applied to an analog to digital converter also fabricated using SOI, silicon carbide, or gallium nitride materials. The output of the analog to digital converter is applied to microprocessor, which microprocessor processes the data or output of the bridge to produce a digital output indicative of bridge value. The microprocessor also receives an output from another analog to digital converter indicative of the temperature of the bridge as monitored by a span resistor coupled to the bridge. The microprocessor has a separate memory coupled thereto which is also fabricated from SOI, silicon carbide, or gallium nitride materials and which memory stores various data indicative of the microprocessor also enabling the microprocessor test and system test to be performed. | 05-09-2013 |
20130112993 | SEMICONDUCTOR DEVICE AND WIRING SUBSTRATE - A semiconductor device according to one embodiment of the present invention includes an insulating substrate, a wiring layer formed on a first main surface of the insulating substrate and having a conductive property, and a semiconductor element mounted on the wiring layer. In the semiconductor device, the insulating substrate is composed of cBN or diamond. | 05-09-2013 |
20130112994 | SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE - The semiconductor module includes a base and at least one circuit substrate. The at least one circuit substrate has a supporting substrate and a semiconductor element supported by the supporting substrate. The base and/or the supporting substrate has a structure for fitting the at least one circuit substrate with the base. | 05-09-2013 |
20130112995 | SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING THE SAME - An embodiment of a method for manufacturing a semiconductor wafer includes providing a monocrystalline silicon wafer, epitaxially growing a first layer of a first material on the silicon wafer, and epitaxially growing a second layer of a second material on the first layer. For example, said first material may be monocrystalline silicon carbide, and said second material may be monocrystalline silicon. | 05-09-2013 |
20130112996 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes a substrate having a main surface, and a silicon carbide layer. The silicon carbide layer is formed on the main surface of the substrate. The silicon carbide layer includes a side surface as an end surface inclined relative to the main surface. The side surface substantially includes one of a {03-3-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type. | 05-09-2013 |
20130112997 | SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE, AND SOI WAFER - Disclosed is a silicon carbide substrate which has less high frequency loss and excellent heat dissipating characteristics. The silicon carbide substrate (S) is provided with a first silicon carbide layer ( | 05-09-2013 |
20130119405 | SEMICONDUCTOR DEVICE WITH ENHANCED STRAIN - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate that is disposed over the substrate. The substrate has a recess. The semiconductor device includes a trench liner that is coated along the recess. The trench liner contains a semiconductor crystal material. The trench liner directly abuts the source/drain stressor device. The semiconductor device also includes a dielectric trench component that is disposed on the trench liner and filling the recess. The semiconductor device includes a source/drain stressor device that is disposed in the substrate. The source/drain stressor device is disposed between the gate and the trench liner. | 05-16-2013 |
20130119406 | SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING THEM - A silicon carbide substrate includes a base layer made of silicon carbide, silicon carbide layers made of single-crystal silicon carbide and arranged side by side on the base layer when viewed in plan view, and a filling portion made of silicon carbide and filling a gap formed between the adjacent silicon carbide layers. The filling portion has a surface roughness of not more than 50 μm in RMS value. | 05-16-2013 |
20130119407 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of: preparing a substrate made of silicon carbide; forming, in the substrate, a trench opened on one main surface side of the substrate; and forming an oxide film in a region including a surface of the trench. In the step of forming the oxide film, the substrate is heated at a temperature of not less than 1250° C. in an atmosphere containing oxygen. | 05-16-2013 |
20130126903 | DIAMOND GaN DEVICES AND ASSOCIATED METHODS - Semiconductor devices and methods of making thereof are provided. In one aspect, for example, a method for making a semiconductor device can include polishing a working surface of a diamond layer to a substantially flat surface, depositing a buffer layer on the working surface of the diamond layer, and depositing a semiconductor layer on the buffer layer. In one specific aspect, the c-axis of the buffer layer is oriented perpendicular to the working surface of the diamond layer. | 05-23-2013 |
20130126904 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A silicon carbide layer includes a first region having a first conductivity type, a second region provided on the first region and having a second conductivity type, and a third region provided on the second region and having the first conductivity type. A trench having an inner surface is formed in the silicon carbide layer. The trench penetrates the second and third regions. The inner surface of the trench has a first side wall and a second side wall located deeper than the first side wall and having a portion made of the second region. Inclination of the first side wall is smaller than inclination of the second side wall. | 05-23-2013 |
20130126905 | SEMICONDUCTOR DEVICE WITH LOW-CONDUCTING BURIED AND/OR SURFACE LAYERS - A device including one or more low-conducting layers is provided. A low-conducting layer can be located below the channel and one or more attributes of the low-conducting layer can be configured based on a minimum target operating frequency of the device and a charge-discharge time of a trapped charge targeted for removal by the low-conducting layer or a maximum interfering frequency targeted for suppression using the low-conducting layer. For example, a product of the lateral resistance and a capacitance between the low-conducting layer and the channel can be configured to be larger than an inverse of the minimum target operating frequency and the product can be smaller than at least one of: the charge-discharge time or an inverse of the maximum interfering frequency. | 05-23-2013 |
20130126906 | SILICON CARBIDE EPITAXIAL WAFER AND MANUFACTURING METHOD THEREFOR, SILICON CARBIDE BULK SUBSTRATE FOR EPITAXIAL GROWTH AND MANUFACTURING METHOD THEREFOR AND HEAT TREATMENT APPARATUS - A method is provided in order to manufacture a silicon carbide epitaxial wafer whose surface flatness is very good and has a very low density of carrot defects and triangular defects arising after epitaxial growth. The silicon carbide epitaxial wafer is manufactured by a first step of annealing a silicon carbide bulk substrate that is tilted less than 5 degrees from <0001> face, in a reducing gas atmosphere at a first temperature T | 05-23-2013 |
20130126907 | GROUP III NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - [Problem] To provide a group III nitride semiconductor device and a method for manufacturing the same in which dislocation density in a semiconductor layer can be precisely reduced. | 05-23-2013 |
20130126908 | Memory Cells, And Methods Of Forming Memory Cells - Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type as the floating bodies, and such sections of the gated diodes may be electrically connected to the floating bodies. The floating bodies may be adjacent channel regions, and spaced from the channel regions by a dielectric structure. The dielectric structure of a memory cell may have a first portion between the floating body and the diode, and may have a second portion between the floating body and the channel region. The first portion may be more leaky to charge carriers than the second portion. The diodes may be formed in semiconductor material that is different from a semiconductor material that the channel regions are in. The floating bodies may have bulbous lower regions. Some embodiments include methods of making memory cells. | 05-23-2013 |
20130126909 | ELECTRONIC FIELD EFFECT DEVICES AND METHODS FOR THEIR MANUFACTURE - Electronic field effect devices, and methods of manufacture of these electronic field effect devices are disclosed. In particular, there is disclosed an electronic field effect device which has improved electrical properties due to the formation of a highly mobile two-dimensional charge-carrier gas in a simple structure formed from diamond in combination with polar materials. | 05-23-2013 |
20130126910 | SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR - In at least one aspect, an apparatus can include a silicon carbide material, a base contact disposed on a first portion of the silicon carbide material, and an emitter contact disposed on a second portion of the silicon carbide material. The apparatus can also include a dielectric layer disposed on the silicon carbide material and disposed between the base contact and the emitter contact, and a surface electrode disposed on the dielectric layer and separate from the base contact and the emitter contact. | 05-23-2013 |
20130126911 | STRESS ENHANCED JUNCTION ENGINEERING FOR LATCHUP SCR - A latchup silicon controlled rectifier (SCR) includes a p+ region and an n+ region located in a p-well of the latchup SCR; and a p+ region and an n+ region located in a n-well of the latchup SCR, wherein the latchup SCR further comprises one of embedded silicon germanium (eSiGe) in the p+ region in the n-well of the latchup SCR and silicon carbide (SiC) in the n+ region in the p-well of the latchup SCR. | 05-23-2013 |
20130134442 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A MOSFET includes: a substrate provided with a trench having a side wall surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; an oxide film; and a gate electrode. The substrate includes a source region, a body region, and a drift region formed to sandwich the body region between the source region and the drift region. The source region and the body region are formed by means of ion implantation. The body region has an internal region sandwiched between the source region and the drift region and having a thickness of 1 μm or smaller in a direction perpendicular to a main surface thereof. The body region has an impurity concentration of 3×10 | 05-30-2013 |
20130134443 | NITRIDE SEMICONDUCTOR DIODE - Disclosed is a high performance nitride semiconductor having a reverse leak current characteristic with two-dimensional electron gas as a conductive layer. A desired impurity is diffused into or a nitride semiconductor to which a desired impurity is added is re-grown on the bottom surface and the side face portion of a recessed portion formed by dry etching using chlorine gas on the upper surface of a nitride semiconductor stacked film to increase resistance of the side face portion of the nitride semiconductor stacked film contacting an anode electrode, reducing the reverse leak current. | 05-30-2013 |
20130134444 | STRESSED TRANSISTOR WITH IMPROVED METASTABILITY - An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material. | 05-30-2013 |
20130140583 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - First, third, and fourth regions have a first conductivity type, and a second region has a second conductivity type. The second region is provided with a plurality of through holes exposing the first region. The third region includes a contact portion, a connecting portion, and a filling portion. The contact portion is in contact with a first portion of the second region. The connecting portion extends from the contact portion to each of the plurality of through holes in the second region. The filling portion fills each of the plurality of through holes in the second region. The fourth region, is provided on the first portion of the second region. | 06-06-2013 |
20130140584 | SEMICONDUCTOR DEVICE - Disclosed is a JBS diode wherein an increase in an on-voltage is suppressed by sufficiently spreading a current to the lower portion of a junction barrier (p | 06-06-2013 |
20130140585 | JUNCTION BARRIER SCHOTTKY RECTIFIERS HAVING EPITAXIALLY GROWN P+-N JUNCTIONS AND METHODS OF MAKING - A junction barrier Schottky (JBS) rectifier device and a method of making the device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p | 06-06-2013 |
20130140586 | SILICON CARBIDE SEMICONDUCTOR ELEMENT AND METHOD FOR PRODUCING THE SAME - This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface. | 06-06-2013 |
20130146894 | BIPOLAR JUNCTION TRANSISTOR STRUCTURE FOR REDUCED CURRENT CROWDING - The present disclosure relates to a bipolar junction transistor (BJT) structure that significantly reduces current crowding while improving the current gain relative to conventional BJTs. The BJT includes a collector, a base region, and an emitter. The base region is formed over the collector and includes at least one extrinsic base region and an intrinsic base region that extends above the at least one extrinsic base region to provide a mesa. The emitter is formed over the mesa. The BJT may be formed from various material systems, such as the silicon carbide (SiC) material system. In one embodiment, the emitter is formed over the mesa such that essentially none of the emitter is formed over the extrinsic base regions. Typically, but not necessarily, the intrinsic base region is directly laterally adjacent the at least one extrinsic base region. | 06-13-2013 |
20130146895 | PINCH-OFF CONTROL OF GATE EDGE DISLOCATION - The embodiments of processes and structures described provide mechanisms for improving the mobility of carriers. A dislocation is formed in a source or drain region between gate structures or between a gate structure and an isolation structure by first amortizing the source or drain region and then recrystallizing the region by using an annealing process with a low pre-heat temperature. A doped epitaxial material may be formed over the recrystallized region. The dislocation and the strain created by the doped epitaxial material in the source or drain region help increase carrier mobility. | 06-13-2013 |
20130146896 | SEMICONDUCTOR OPTICAL DEVICE HAVING AN AIR MEDIA LAYER AND THE METHOD FOR FORMING THE AIR MEDIA LAYER THEREOF - A method for fabricating air media layer within the semiconductor optical device is provided. The step of method includes a substrate is provided, a GaN thin film is formed on the substrate, a sacrificial layer is formed on the GaN thin film, and a nitride-containing semiconductor layer is formed on the sacrificial layer. The semiconductor optical device is immersed with an acidic solution to remove the portion of sacrificial layer to form an air media layer around the residual sacrificial layer. | 06-13-2013 |
20130146897 | 4h-SiC SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE - A trench groove is formed and a silicon oxide film is buried in the periphery of a channel region of (0001) surface 4h-SiC semiconductor element. The oxide film in the trench groove is defined in such a planar layout that a tensile strain is applied along the direction of the c-axis and a compressive strain is applied along two or more of axes on a plane perpendicular to the c-axis. For example, trench grooves buried with an oxide film may be configured to such a layout that they are in a trigonal shape surrounding the channel, or are arranged symmetrically with respect to the channel as a center when arranged discretely. | 06-13-2013 |
20130146898 | SiC MOSFETS AND SELF-ALIGNED FABRICATION METHODS THEREOF - The present application provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided. | 06-13-2013 |
20130153924 | PIEZOELECTRIC DEVICES AND METHODS FOR THEIR PREPARATION AND USE - Methods for fabricating a piezoelectric device are provided. The methods can include providing a substrate and forming a nanocrystalline diamond layer on a first surface of the substrate. The methods can also include depositing a piezoelectric layer on a first surface of the nanocrystalline diamond layer. | 06-20-2013 |
20130153925 | SEMICONDUCTOR DEVICE - A MOSFET includes: a substrate having a trench formed therein and made of silicon carbide, the trench being opened on one main surface side and having a side wall surface; a gate insulating film formed on the side wall surface in contact therewith; and a gate electrode formed on the gate insulating film in contact therewith, wherein a square region with each side of 100 nm in the side wall surface has a surface roughness of not more than 1.0 nm in RMS. | 06-20-2013 |
20130153926 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A MOSFET includes: a substrate made of silicon carbide and having a first trench and a second trench formed therein, the first trench having an opening at the main surface side, the second trench having an opening at the main surface side and being shallower than the first trench; a gate insulating film; a gate electrode; and a source electrode disposed on and in contact with a wall surface of the second trench. The substrate includes a source region, a body region, and a drift region. The first trench is formed to extend through the source region and the body region and reach the drift region. The second trench is formed to extend through the source region and reach the body region. | 06-20-2013 |
20130153927 | SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATION METHODS - Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a gate structure overlying a region of semiconductor material, wherein the width of the gate structure is aligned with a <100> crystal direction of the semiconductor material. The method continues by forming recesses about the gate structure and forming a stress-inducing semiconductor material in the recesses. | 06-20-2013 |
20130153928 | METHOD FOR CONTROLLED GROWTH OF SILICON CARBIDE AND STRUCTURES PRODUCED BY SAME - A method for controlled growth of silicon carbide and structures produced by the method are disclosed. A crystal of silicon carbide (SiC) can be grown by placing a sacrificial substrate in a growth zone with a source material. The source material may include a low-solubility impurity. SiC is then grown on the sacrificial substrate to condition the source material. The sacrificial substrate is then replaced with the final substrate, and SiC is grown on the final substrate. A single crystal of silicon carbide is produced, wherein the crystal of silicon carbide has substantially few micropipe defects. Such a crystal may also include a substantially uniform concentration of the low-solubility impurity, and may be used to make wafers and/or SiC die. | 06-20-2013 |
20130153929 | METHOD AND STRUCTURE FOR FORMING HIGH-K/METAL GATE EXTREMELY THIN SEMICONDUCTOR ON INSULATOR DEVICE - A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers. | 06-20-2013 |
20130153930 | PHENYL GROUP-CONTAINING ORGANIC/INORGANIC HYBRID PREPOLYMER, HEAT RESISTANT ORGANIC/INORGANIC HYBRID MATERIAL, AND ELEMENT ENCAPSULATION STRUCTURE - The object of the present invention is to provide an organic-inorganic hybrid material having heat resistance, and said object of the present invention can be attained by providing an organic-inorganic hybrid prepolymer containing a phenyl group which is prepared by the polycondensation reaction accompanying dehydration between a polydimethylsiloxane and a metal and/or semimetal alkoxide, wherein (a) phenyl group(s) is (are) partially or wholly introduced into said polydimethylsiloxane and/or said metal and/or semimetal alkoxide. | 06-20-2013 |
20130153931 | N-DOPED SINGLE CRYSTAL DIAMOND SUBSTRATES AND METHODS THEREFOR - The disclosure relates to the formation of n-doped single crystal diamond (SCD). In general, a SCD substrate is preferentially anisotropically etched to provide one or more recesses in the SCD substrate, where the recesses are defined by ( | 06-20-2013 |
20130161642 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises an SOI substrate; a semiconductor fin formed on the SOI substrate, the semiconductor fin having a first side and a second side which are opposite to each other and stand upward on a surface of the SOI substrate, and a trench which is opened at a central portion of the second side and opposite to the first side; a channel region formed in the fin and being between the first side and the trench at the second side; source and drain regions formed in the fin and sandwiching the channel region; and a gate stack formed on the SOI substrate and being adjacent to the first side of the fin, wherein the gate stack comprises a first gate dielectric extending away from the first side and being adjacent to the channel region, a first conductor layer extending away from the first side and being adjacent to the first gate dielectric, a second gate dielectric extending away from the first side and being adjacent laterally to one side of the first conductor layer, and a second conductor layer extending away from the first side and being adjacent laterally to one side of the second gate dielectric. The embodiments of the invention can be applied in manufacturing an FinFET. | 06-27-2013 |
20130161643 | Method for Fabricating Three-Dimensional Gallium Nitride Structures with Planar Surfaces - A method is provided for fabricating three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. After providing a substrate, the method grows a GaN film overlying a top surface of the substrate and forms cavities in a top surface of the GaN film. The cavities are formed using a laser ablation, ion implantation, sand blasting, or dry etching process. The cavities in the GaN film top surface are then wet etched, forming planar sidewalls extending into the GaN film. More explicitly, the cavities are formed into a c-plane GaN film top surface, and the planar sidewalls are formed perpendicular to a c-plane, in the m-plane or a-plane family. | 06-27-2013 |
20130161644 | SEMICONDUCTOR MODULE - Provided is a semiconductor module having high inrush-current tolerance. A semiconductor module includes a switching element formed of a wide bandgap semiconductor, and a free wheel diode connected in antiparallel with the switching element, wherein the free wheel diode is made of silicon and has negative temperature characteristics. | 06-27-2013 |
20130161645 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a principal surface, and an insulating film formed on the principal surface and continuously covering a top surface of a first boundary region and a top surface of a second boundary region, the first boundary region including a boundary between a well layer and a RESURF layer, the second boundary region including a boundary between the RESURF layer and a first impurity region. The semiconductor device further includes a plurality of lower field plates formed in the insulating film in such a manner that the plurality of lower field plates do not lie directly above the first and second boundary regions, and a plurality of upper field plates formed on the insulating film in such a manner that the plurality of upper field plates do not lie directly above the first and second boundary regions. | 06-27-2013 |
20130161646 | SEMICONDUCTOR SUBSTRATE - A semiconductor substrate has a main surface and formed of single crystal silicon carbide. The main surface includes a central area, which is an area other than the area within 5 mm from the outer circumference. When the central area is divided into square areas of 1 mm×1 mm, in any square area, density of dislocations of which Burgers vector is parallel to <0001> direction is at most 1×10 | 06-27-2013 |
20130161647 | INGOT, SUBSTRATE, AND SUBSTRATE GROUP - An ingot, a substrate, and a substrate group are obtained each of which is made of silicon carbide and is capable of suppressing variation of characteristics of semiconductor devices. The ingot is made of single-crystal silicon carbide, and has p type impurity. The ingot has a thickness of 10 mm or greater in a growth direction thereof. Further, the ingot has an average carrier density of 1×10 | 06-27-2013 |
20130161648 | Diamond Semiconductor System and Method - Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer. | 06-27-2013 |
20130161649 | STRUCTURE AND METHOD FOR INCREASING STRAIN IN A DEVICE - A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device having a source region and a drain region, the NFET CMOS including: an n-type doped layer in at least one of the source region and the drain region, wherein the n-type doped layer includes substitutional carbon and has a memorized tensile stress induced by a stress memorization technique (SMT). | 06-27-2013 |
20130161650 | DEVICE WITH SELF ALIGNED STRESSOR AND METHOD OF MAKING SAME - A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material. | 06-27-2013 |
20130161651 | LOW 1C SCREW DISLOCATION 3 INCH SILICON CARBIDE WAFER - A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 3 inches and a 1 c screw dislocation density from about 500 cm | 06-27-2013 |
20130168694 | SUPER INTEGRATED CIRCUIT CHIP SEMICONDUCTOR DEVICE - The CP555 Super Integrated Circuit Chip has a ceramic package casing made from (B4-C) Boron Carbide: a non-conducting ceramic material. The IC is connected to connector pins by microcircuits and a custom formulated bond wire. The CP555 Integrated Circuit's ceramic Boron Carbide (B4-C) outer package casing, Heterodiamond substrates and dielectric components allows these integrated circuits to reduce electro-migration to a minimum, produce superior radiation hardness, heat resistance, electromagnetic shielding, and resistance to damage from harsh elements and environments. The CP555 Integrated Circuit can be used as a CMOS, PIC or DIE microcontroller circuit or computer processor (CPU). | 07-04-2013 |
20130168695 | CMOS HAVING A SIC/SIGE ALLOY STACK - A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer. | 07-04-2013 |
20130168696 | Silicon Carbide Schottky Diode Device with Mesa Termination and Manufacturing Method Thereof - A silicon carbide Schottky diode device with mesa terminations and the manufacturing method thereof are provided. The silicon carbide Schottky diode device includes an n-type epitaxial silicon carbide layer with mesa terminations on an n-type silicon carbide substrate, two p-type regions in the n-type epitaxial silicon carbide layer and a Schottky metal contact on the n-type epitaxial silicon carbide layer and the p-type regions, a dielectric layer on sidewalls and planes of the mesa terminations. | 07-04-2013 |
20130168697 | SILICON CARBIDE STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a silicon carbide structure includes forming a silicon carbide layer by depositing silicon carbide on a base plate by chemical vapor deposition, removing the base plate, decreasing electrical conductivity by heat-treating the silicon carbide structure, and removing a thickness of 200 μm from an upper surface and a lower surface of the silicon carbide structure. In the present invention, silicon carbide is deposited by a CVD method, and the electrical conductivity of the silicon carbide is reduced to the electrical conductivity required for a protection ring of a plasma device through a post-treatment and a post-process. The electrical conductivity may be adjusted even without using separate additives. | 07-04-2013 |
20130168698 | POWER DEVICES AND METHOD FOR MANUFACTURING THE SAME - A power device includes a substrate, a silicon carbide (Si | 07-04-2013 |
20130168699 | SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film. | 07-04-2013 |
20130168700 | POWER SEMICONDUCTOR DEVICE - In a high speed switching power semiconductor device having a sense pad, a high voltage is generated during switching operations in well regions under the sense pad due to a displacement current flowing through its flow path with a resistance, whereby the power semiconductor device sometimes breaks down by dielectric breakdown of a thin insulating film such as a gate insulating film. In a power semiconductor device according to the invention, sense-pad well contact holes are provided on well regions positioned under the sense pad and penetrate a field insulating film thicker than the gate insulating film to connect to the source pad, thereby improving reliability. | 07-04-2013 |
20130168701 | SILICON CARBIDE SEMICONDUCTOR ELEMENT AND METHOD FOR FABRICATING THE SAME - A SiC semiconductor element includes: a SiC substrate which has a principal surface tilted with respect to a (0001) Si plane; a SiC layer arranged on the principal surface of the substrate; a trench arranged in the SiC layer and having a bottom, a sidewall, and an upper corner region located between the sidewall and the upper surface of the SiC layer; a gate insulating film arranged on at least a part of the sidewall and on at least a part of the upper corner region of the trench and on at least a part of the upper surface of the SiC layer; and a gate electrode arranged on the gate insulating film. The upper corner region has a different surface from the upper surface of the SiC layer and from a surface that defines the sidewall. The gate electrode contacts with both of a first portion of the gate insulating film located on the upper corner region and a second portion of the gate insulating film located on the sidewall. The first portion of the gate insulating film is thicker than a third portion of the gate insulating film located on the upper surface of the SiC layer. And an end portion of the gate electrode is located on the upper corner region. | 07-04-2013 |
20130175545 | SEMICONDUCTOR DEVICE WITH STRAIN-INDUCING REGIONS AND METHOD THEREOF - Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions. | 07-11-2013 |
20130175546 | Diamond Semiconductor System and Method - Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein at least 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm | 07-11-2013 |
20130175547 | FIELD EFFECT TRANSISTOR DEVICE - A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material. | 07-11-2013 |
20130175548 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - A fabrication method for a semiconductor device includes the step of forming a gate insulating film on the side of a trench, the bottom thereof, and the periphery thereof. The step of forming a gate insulating film includes a step of forming a first insulating film on the side of the trench and a step of forming a second insulating film on the bottom and periphery of the trench using a high-density plasma chemical vapor deposition method. The thickness of the portions of the gate insulating film formed on the bottom and periphery of the trench is made larger than that of the portion of the gate insulating film formed on the side of the trench. | 07-11-2013 |
20130175549 | SEMICONDUCTOR DEVICE - A semiconductor device ( | 07-11-2013 |
20130181227 | LED Package with Slanting Structure and Method of the Same - The LED package comprises a substrate with a first conductive type through-hole and a second conductive type through-hole through the substrate; a reflective layer formed on an upper surface of the substrate; a LED die having first conductive type pad and second conductive type pad, wherein the first conductive type pad is aligned with the first conductive type through-hole; a slanting structure of dielectric layer formed adjacent at least one side of the LED die for carrying conductive traces; a conductive trace formed on upper surface of the slanting structure to offer path between the second conductive type pad and the conductive type through-hole; and a refilling material within the first conductive type through-hole and second conductive type through-hole. | 07-18-2013 |
20130181228 | POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - First chip main surfaces of first semiconductor chips are bonded to a heat spreader, and second chip main surfaces of the first semiconductor chips are bonded to a first electrode. First chip main surfaces of second semiconductor chips are bonded to a heat spreader, and second chip main surfaces of the second semiconductor chips are bonded to a first electrode. A plurality of electrodes are provided by a lead frame. An insulating member is provided on a side opposite to the chips when viewed from the heat spreader. An insulating substrate is provided on a side opposite to the chips when viewed from the first electrodes. | 07-18-2013 |
20130181229 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A MOSFET includes: a substrate having a first trench formed therein, the first trench opening on a side of one main surface; a gate insulating film; and a gate electrode. The substrate includes an n type source region, a p type body region, an n type drift region, and a p type deep region making contact with the body region and extending to a region deeper than the first trench. The first trench is formed such that a distance between the wall surface and the deep region increases with increasing distance from the main surface of the substrate. | 07-18-2013 |
20130181230 | SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR SUBSTRATE MANUFACTURING METHOD - A semiconductor substrate includes: a silicon substrate; a monocrystalline silicon carbide film formed on a surface of the silicon substrate; and a stress relieving film formed on the surface of the silicon substrate opposite from the side on which the monocrystalline silicon carbide film is formed, and that relieves stress in the silicon substrate by applying compressional stress to the silicon substrate surface on which the stress relieving film is formed, wherein a plurality of spaces is present in the monocrystalline silicon carbide film in portions on the side of the silicon substrate and along the interface between the monocrystalline silicon carbide film and the silicon substrate. | 07-18-2013 |
20130181231 | MICROPIPE-FREE SILICON CARBIDE AND RELATED METHOD OF MANUFACTURE - Micropipe-free, single crystal, silicon carbide (SiC) and related methods of manufacture are disclosed. The SiC is grown by placing a source material and seed material on a seed holder in a reaction crucible of the sublimation system, wherein constituent components of the sublimation system including the source material, reaction crucible, and seed holder are substantially free from unintentional impurities. By controlling growth temperature, growth pressure, SiC sublimation flux and composition, and a temperature gradient between the source material and the seed material or the SiC crystal growing on the seed material during the PVT process, micropipe-inducing process instabilities are eliminated and micropipe-free SiC crystal is grown on the seed material. | 07-18-2013 |
20130187171 | METHOD TO FORM SILICIDE CONTACT IN TRENCHES - A method for forming silicide contacts includes forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer. The first semiconductor layer comprises source/drain regions. Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions. A second semiconductor layer is formed within the contact trenches. A metallic layer is formed on the second semiconductor layer. An anneal is performed to form a silicide region between the second semiconductor layer and the metallic layer. A conductive contact layer is formed on the metallic layer or the silicide region. | 07-25-2013 |
20130187172 | NITRIDE SEMICONDUCTOR EPITAXIAL WAFER AND FIELD EFFECT NITRIDE TRANSISTOR - A nitride semiconductor epitaxial wafer includes a substrate, a GaN layer provided over the substrate, and an AlGaN layer provided over the GaN layer. The GaN layer has a wurtzite crystal structure, and a ratio c/a of a lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in an a-axis orientation of the GaN layer is not more than 1.6266. | 07-25-2013 |
20130187173 | CONDUCTIVITY MODULATION IN A SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR - In one general aspect, a silicon carbide bipolar junction transistor (BJT) can include a collector region, a base region on the collector region, and an emitter region on the base region. The silicon carbide BJT can include a base contact electrically contacting the base region where the base region having an active part interfacing the emitter region. The silicon carbide BJT can also include an intermediate region of semiconductor material having at least a part extending from the active part of the base region to the base contact where the intermediate region having a doping level higher than a doping level of the active part of the base region. | 07-25-2013 |
20130193445 | SOI STRUCTURES INCLUDING A BURIED BORON NITRIDE DIELECTRIC - Boron nitride is used as a buried dielectric of an SOI structure including an SOI layer and a handle substrate. The boron nitride is located between an SOI layer and a handle substrate. Boron nitride has a dielectric constant and a thermal expansion coefficient close to silicon dioxide. Yet, boron nitride has a wet as well as a dry etch resistance that is much better than silicon dioxide. In the SOI structure, there is a reduced material loss of boron nitride during multiple wet and dry etches so that the topography and/or bridging are not an obstacle for device integration. Boron nitride has a low dielectric constant so that devices built in SOI active regions do not suffer from a charging effect. | 08-01-2013 |
20130193446 | FINFET AND METHOD OF FABRICATING THE SAME - The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a major surface; a first fin and a second fin extending upward from the substrate major surface to a first height; an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, whereby portions of the fins extend beyond the top surface of the insulation layer; each fin covered by a bulbous epitaxial layer defining an hourglass shaped cavity between adjacent fins, the cavity comprising upper and lower portions, wherein the epitaxial layer bordering the lower portion of the cavity is converted to silicide. | 08-01-2013 |
20130193447 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes an insulation film, and a silicon carbide layer having a surface covered with the insulation film. The surface includes a first region. The first region has a first plane orientation at least partially. The first plane orientation is any of a (0-33-8) plane, (30-3-8) plane, (-330-8) plane, (03-3-8) plane, (-303-8) plane, and (3-30-8) plane. | 08-01-2013 |
20130193448 | PATTERNED SUBSTRATE AND STACKED LIGHT EMITTING DIODE - A patterned substrate is provided, including: a substrate having a (0001) crystal plane and a plurality of alternatively arranged recess structures therein, thereby forming a plurality of alternatively arranged top surfaces; and a dielectric barrier layer covering the bottom surface and/or the sidewalls of the recess structures. Each of the alternatively arranged recess structures includes a bottom surface and a plurality of sidewalls surrounding the bottom surface. | 08-01-2013 |
20130193449 | PRODUCTION OF AN INTEGRATED CIRCUIT INCLUDING ELECTRICAL CONTACT ON SiC - Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate. | 08-01-2013 |
20130200392 | Semicondictor Device with Edge Termination and Method for Manufacturing a Semiconductor Device - According to an embodiment, a semiconductor device includes a semiconductor body having a first semiconductor material and a second semiconductor material having a band gap larger than a band gap of the first semiconductor material. A first pn-junction is formed in the first semiconductor material. A second pn-junction is formed by the second semiconductor material and extends deeper into the semiconductor body than the first pn-junction. The second semiconductor material is in contact with the first semiconductor material and forms part of an edge termination zone of the semiconductor device. | 08-08-2013 |
20130200393 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided. | 08-08-2013 |
20130200394 | SEMICONDUCTOR-ON-DIAMOND DEVICES AND ASSOCIATED METHODS - Semiconductor-on-diamond devices and methods for making such devices are provided. One such method may include depositing a semiconductor layer on a semiconductor substrate, depositing an adynamic diamond layer on the semiconductor layer opposite the semiconductor substrate, and coupling a support substrate to the adynamic diamond layer opposite the semiconductor layer to support the adynamic layer. | 08-08-2013 |
20130200395 | LAYOUT FOR MULTIPLE-FIN SRAM CELL - The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region. | 08-08-2013 |
20130207122 | METHOD FOR FABRICATING FINFETS AND SEMICONDUCTOR STRUCTURE FABRICATED USING THE METHOD - A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method. | 08-15-2013 |
20130207123 | HIGH CURRENT DENSITY POWER MODULE - A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm | 08-15-2013 |
20130207124 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A first region of a silicon carbide layer constitutes a first surface, and is of a first conductivity type. A second region is provided on the first region, and is of a second conductivity type. A third region is provided on the second region, and is of the first conductivity type. A fourth region is provided in the first region, located away from each of the first surface and the second region, and is of the second conductivity type. A gate insulation film is provided on the second region so as to connect the first region with the third region. A gate electrode is provided on the gate insulation film. A first electrode is provided on the first region. A second electrode is provided on the third region. | 08-15-2013 |
20130214289 | Short-Resistant Metal-Gate MOS Transistor and Method of Forming the Transistor - A protective cap is formed on the metal gate of a MOS transistor to protect the metal gate during an etch that forms a source contact opening and a drain contact opening. The protective cap also electrically isolates the source metal contact and the drain metal contact from the metal gate. | 08-22-2013 |
20130214290 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide layer having a first surface and a second surface includes a first region constituting the first surface and of a first conductivity type, a second region provided on the first region and of said second conductivity type, and a third region provided on the second region and of the first conductivity type. At the second surface is formed a gate electrode having a bottom and sidewall, passing through the third region and the second region up to the first region. An additional trench is formed, extending from the bottom of the gate trench in the thickness direction. A fourth region of the second conductivity type is formed to fill the additional trench. | 08-22-2013 |
20130214291 | SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREFOR - As viewed along a normal to the principal surface of a substrate | 08-22-2013 |
20130221373 | SOLAR CELL MADE USING A BARRIER LAYER BETWEEN P-TYPE AND INTRINSIC LAYERS - A method for forming a photovoltaic device includes depositing a p-type layer on a substrate. A barrier layer is formed on the p-type layer by exposing the p-type layer to an oxidizing agent. An intrinsic layer is formed on the barrier layer, and an n-type layer is formed on the intrinsic layer. | 08-29-2013 |
20130221374 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate comprising a semiconductor material. The substrate has a surface that defines a surface normal direction and includes a P-N junction comprising an interface between a first region and a second region, where the first (second) region includes a first (second) dopant type, so as to have a first (second) conductivity type. The substrate includes a termination extension region disposed adjacent to the P-N junction and having an effective concentration of the second dopant type that is generally the effective concentration of the second dopant type in the second doped region. The substrate includes an adjust region disposed adjacent to the surface and between the surface and at least part of the termination extension region, where the effective concentration of the second dopant type generally decreases when moving from the termination extension region into the adjust region along the surface normal direction. | 08-29-2013 |
20130221375 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A silicon carbide semiconductor device includes an epitaxial layer, a gate insulating film, a gate electrode, a drain electrode, and a source electrode. The epitaxial layer is made of silicon carbide includes a mesa structure region having a top surface forming a first main surface and a side surface. The gate insulating film is provided on the top surface of the mesa structure region. The gate electrode is provided on the gate insulating film. The mesa structure region includes a first impurity region, a second impurity region, and a third impurity region. The source electrode is in contact with the third impurity region. In this way, there can be provided a silicon carbide semiconductor device having breakdown voltage improved by reducing electric field strength in the gate insulating film, as well as a method for manufacturing such a silicon carbide semiconductor device. | 08-29-2013 |
20130221376 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten. | 08-29-2013 |
20130221377 | HETEROGROWTH - A method comprises bonding a silicon wafer or silicon-on-insulator wafer having a monocrystalline silicon surface region and a wafer-like carrier comprising silicon carbide so as to form a composite wafer having a surface with the monocrystalline silicon surface region for silicon carbide heterogrowth, such as heteroepitaxy. The composite wafer can help avoid wafer bow. | 08-29-2013 |
20130228796 | HIGH VOLTAGE SEMICONDUCTOR DEVICES INCLUDING ELECTRIC ARC SUPPRESSION MATERIAL AND METHODS OF FORMING THE SAME - A high voltage semiconductor device can include a high voltage semiconductor device package that includes a wall defining a recess within the high voltage semiconductor device package. A high voltage semiconductor chip can be in the recess and a high voltage electric arc suppression material can be in the recess. | 09-05-2013 |
20130228797 | SILICON CARBIDE SUBSTRATE AND SEMICONDUCTOR DEVICE - To provide a silicon carbide substrate having at least one or more main surfaces, including: a plurality of encapsulated regions inside, wherein the plurality of encapsulated regions are distributed in a direction approximately parallel to one of the main surfaces, with each encapsulated region positioned at a distance of 100 nm or more and 100 μm or less from the main surfaces to inside a substrate, and each encapsulated region having a width of 100 nm or more and 100 μm or less in a direction parallel to the main surfaces. | 09-05-2013 |
20130234158 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth, and a fifth semiconductor region, an insulating film, a control electrode, and a first and a second electrode. The first, the second, the third, the fourth and the fifth semiconductor region include silicon carbide. The first semiconductor region has a first impurity concentration, and has a first portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided between the first portion and the second semiconductor region. The fourth semiconductor region is provided between the first portion and the third semiconductor region. The fifth semiconductor region includes a first region provided between the first portion and the second semiconductor region, and has a second impurity concentration higher than the first impurity concentration. | 09-12-2013 |
20130234159 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes: a substrate formed of a single-crystal first semiconductor; a gate insulating film on the substrate; a gate electrode including a layered structure of a semiconductor layer formed of a polycrystalline second semiconductor and a metal semiconductor compound layer formed of a first metal semiconductor compound that is a reaction product of a metal and the second semiconductor; and electrodes formed of a second metal semiconductor compound that is a reaction product of the metal and the first semiconductor, and formed on the substrate with the gate electrode interposed therebetween, and an aggregation temperature of the first metal semiconductor compound on the polycrystalline second semiconductor is lower than an aggregation temperature of the second metal semiconductor compound on the single-crystal first semiconductor, and a cluster-state high carbon concentration region is included in an interface between the semiconductor layer and the metal semiconductor compound layer. | 09-12-2013 |
20130234160 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention includes an n+ type substrate, a drift epitaxial layer formed on the n+ type substrate and having a lower concentration of impurity than the n+ type substrate, a Schottky electrode formed on the drift epitaxial layer, and a PI formed as an insulating film by covering at least an end of the Schottky electrode and an end and a side surface of the drift epitaxial layer. | 09-12-2013 |
20130234161 | SIC SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, an SiC semiconductor device comprises a p-type 4H—SiC region formed on at least part of a surface portion of an SiC substrate, a defect reduction layer formed on a surface portion of the 4H—SiC region, a gate insulating film formed on the defect reduction layer, and a gate electrode formed on the gate insulating film. The defect reduction layer has the C defect density that is defined as follows and is set to Cdef<10 | 09-12-2013 |
20130234162 | SMOOTHING METHOD FOR SEMICONDUCTOR MATERIAL AND WAFERS PRODUCED BY SAME - A smoothing method for semiconductor material and semiconductor wafers produced by the method are disclosed. Semiconductor wafers with reduced atomic steps, as well with reduced scratches and subsurface defects can be produced. Such wafers feature an improved growth surface that can provide for the growth of an epilayer with reduced macroscopic defects and defect densities. A method of smoothing the surface of a wafer according to example embodiments of the invention includes planarizing the surface of a semiconductor wafer, and then oxidizing the wafer to achieve a specified thickness of oxide on the surface of the wafer. The oxide can then be stripped from the surface of the semiconductor wafer. | 09-12-2013 |
20130234163 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A MOSFET having a high mobility may be obtained by introducing nitrogen to the channel region or the interface between the gate dielectric film and the SiC substrate of the SiC MOSFET, but there is a problem that a normally-on MOSFET is obtained. For realizing both a high mobility and normally-off, and for providing a SiC MOSFET having further high reliability, nitrogen is introduced to the channel region of the SiC substrate or the interface between the gate dielectric film and the SiC substrate, and furthermore a metal oxide film having a thickness of 10%, or less of the total thickness of the gate dielectric film is inserted in the gate dielectric film. | 09-12-2013 |
20130234164 | SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE - There is provided a silicon carbide substrate composed of silicon carbide, including encapsulated regions inside, which form incoherent boundaries between the silicon carbide and the encapsulated regions, wherein propagation of stacking faults in the silicon carbide is blocked. | 09-12-2013 |
20130234165 | METHOD FOR COATING MICROMECHANICAL PARTS WITH DUAL DIAMOND COATING - Method for coating micromechanical components of a micromechanical system, in particular a watch movement, comprising:
| 09-12-2013 |
20130240902 | Semiconductor Arrangement - A first semiconductor zone of a first conduction type is formed from a semiconductor base material doped with first and second dopants. The first and second dopants are different substances and also different from the semiconductor base material. The first dopant is electrically active and causes a doping of the first conduction type in the semiconductor base material, and causes either a decrease or an increase of a lattice constant of the pure, undoped first semiconductor zone. The second dopant may be electrically active, and may be of the same doping type as the first dopant, causes one or both of: a hardening of the first semiconductor zone; an increase of the lattice constant of the pure, undoped first semiconductor zone if the first dopant causes a decrease, and a decrease of the lattice constant of the pure, undoped first semiconductor zone if the first dopant causes an increase, respectively. | 09-19-2013 |
20130240903 | METHOD AND SYSTEM FOR ULTRA MINIATURIZED PACKAGES FOR TRANSIENT VOLTAGE SUPPRESSORS - A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The transient voltage suppressor (TVS) assembly includes a semiconductor die including a contact surface on a single side of the die, the die further including a substrate comprising a layer of at least one of an electrical insulator material, a semi-insulating material, and a first wide band gap semiconductor having a conductivity of a first polarity, at least a TVS device including a plurality of wide band gap semiconductor layers formed on the substrate; a first electrode coupled in electrical contact with the TVS device and extending to the contact surface, and a second electrode electrically coupled to the substrate extending to the contact surface. | 09-19-2013 |
20130240904 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, an insulating film, a control electrode, a first electrode, and a second electrode. The first semiconductor region includes silicon carbide, and has a first portion. The second semiconductor region is provided on the first semiconductor region, and includes silicon carbide. The third semiconductor region and the fourth semiconductor region are provided on the second semiconductor region, and includes silicon carbide. The electrode is provided on the film. The second semiconductor region has a first region and a second region. The first region contacts with the third semiconductor region and the fourth semiconductor region. The second region contacts with the first portion. The impurity concentration of the first region is higher than an impurity concentration of the second region. | 09-19-2013 |
20130240905 | Silicon Carbide Rectifier - Silicon carbide PiN diodes are presented with reduced temperature coefficient crossover points by limited p type contact area to limit hole injection in the n type drift layer in order to provide a lower current at which the diode shifts from negative temperature coefficient to a positive temperature coefficient of forward voltage for mitigating thermal runaway. | 09-19-2013 |
20130240906 | SIC SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, an SiC semiconductor device including a p-type 4H—SiC region formed on at least part of a surface portion of an SiC substrate, a first gate insulating film formed on the 4H—SiC region and formed of a 3C—SiC thin film having p-type dopant introduced therein, a second gate insulating film formed on the first gate insulating film, and a gate electrode formed on the second gate insulating film. | 09-19-2013 |
20130240907 | ELECTRON MULTIPLIER DEVICE HAVING A NANODIAMOND LAYER - An electron multiplier for a system for detecting electromagnetic radiation or an ion flow is disclosed. The multiplier includes at least one active structure intended to receive a flow of incident electrons, and to emit in response a flow of electrons called secondary electrons. The active structure includes a substrate on which is positioned a thin nanodiamond layer formed from diamond particles the average size of which is less than or equal to about 100 nm. | 09-19-2013 |
20130240908 | BIDIRECTIONAL SILICON CARBIDE TRANSIENT VOLTAGE SUPRESSION DEVICES - An electronic device includes a silicon carbide layer having a first conductivity type and having a first surface and a second surface opposite the first surface, and first and second silicon carbide Zener diodes on the silicon carbide layer. Each of the first and second silicon carbide Zener diodes may include a first heavily doped silicon carbide region having a second conductivity type opposite the first conductivity type on the silicon carbide layer, and an ohmic contact on the first heavily doped silicon carbide region. | 09-19-2013 |
20130240909 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element substrate, wherein an electrode pattern is formed on one surface of an insulating substrate and a back-surface electrode is formed on the other surface of the insulating substrate; a stress-relaxation adhesive layer made of resin that covers at least a part of a portion of the surface of the insulating substrate where the electrode pattern and the back-surface electrode are not formed; and a semiconductor element affixed, using a bonding material, to the surface of the electrode pattern opposite the insulating substrate, and a first sealing resin member which covers the semiconductor element and the semiconductor element substrate, and a modulus of elasticity of the stress-relaxation adhesive layer is lower than that of the first sealing resin member. | 09-19-2013 |
20130240910 | BIPOLAR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor crystal having a recombination-inhibiting semiconductor layer of a second conductive type that is disposed in the vicinity of the surface between a base contact region and emitter regions and that separates the semiconductor surface having a large number of surface states from the portion that primarily conducts the positive hole electric current and the electron current. Recombination is inhibited, and the current amplification factor is thereby improved and the ON voltage reduced. | 09-19-2013 |
20130240911 | III-Nitride Multi-Channel Heterojunction Device - A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions. | 09-19-2013 |
20130240912 | SEMICONDUCTOR DEVICE - A semiconductor device including: a semiconductor element; a lead frame connected to the semiconductor element; a metal base plate mounted on the lead frame via a first insulation layer; and a second insulation layer disposed on the opposite side of the metal base plate face on which the first insulation layer is disposed; wherein the first insulation layer is an insulation layer whose heat-dissipation performance is higher than that of the second insulation layer, and the second insulation layer is an insulation layer whose insulation performance is the same as that of the first insulation layer or higher than that of the first insulation layer. | 09-19-2013 |
20130248879 | DIRECT GROWTH OF DIAMOND IN BACKSIDE VIAS FOR GAN HEMT DEVICES - A GaN high electron mobility transistor (HEMT) device having a silicon carbide substrate including a top surface and a bottom surface, where the substrate further includes a via formed through the bottom surface and into the substrate. The device includes a plurality of epitaxial layers provided on the top surface of the substrate, a plurality of device layers provided on the epitaxial layers, and a diamond layer provided within the via. | 09-26-2013 |
20130248880 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first, a second, a third, and a fourth semiconductor region, a control electrode, a floating electrode, and an insulating film. The first region contains silicon carbide. The second region is provided on the first region and contains silicon carbide. The third region is provided on the second region and contains silicon carbide. The fourth region is provided on the third region and contains silicon carbide. The control electrode is provided in a trench formed in the fourth, the third, and the second region. The floating electrode is provided between the control electrode and a bottom surface of the trench. The insulating film is provided between the trench and the control electrode, between the trench and the floating electrode, and between the control electrode and the floating electrode. | 09-26-2013 |
20130248881 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth semiconductor region, a control electrode, and an insulating film. The first region contains silicon carbide. The second region is provided on the first region and contains silicon carbide. The third region is provided on the second region and contains silicon carbide. The fourth region is provided on the third region and contains silicon carbide. The control electrode is provided in a trench. The trench is formed in the fourth, the third, and the second semiconductor region. The insulating film is provided between a side surface of the trench and the control electrode. The insulating film contains a high-dielectric constant region. The high-dielectric constant region contacts with at least the third semiconductor region. The high-dielectric constant region has a higher dielectric constant than a dielectric constant of silicon oxide. | 09-26-2013 |
20130248882 | SEMICONDUCTOR DEVICE - In a semiconductor device, transistor cells and diode cells are formed on a single semiconductor substrate of a first conductivity type. A first semiconductor layer of a second conductivity type is formed in a transistor cell region and at a lower side of the substrate. A second semiconductor layer of the first conductivity type is formed in a region adjacent to the transistor cell region and at the lower side of the substrate. Gate electrodes are formed at an upper side of the substrate. A third semiconductor layer of the second conductivity type and a fourth semiconductor layer of the first conductivity type are formed between the gate electrodes. A fifth semiconductor layer of the first conductivity type is formed above the first semiconductor layer in the transistor cell region. A first and a second electrode are formed on both sides of the substrate. | 09-26-2013 |
20130248883 | HIGH PERFORMANCE POWER MODULE - The present disclosure relates to a power module that has a housing with an interior chamber and a plurality of switch modules interconnected to facilitate switching power to a load. Each of the plurality of switch modules comprises at least one transistor and at least one diode mounted within the interior chamber and both the at least one transistor and the at least one diode are majority carrier devices, are formed of a wide bandgap material system, or both. The switching modules may be arranged in virtually any fashion depending on the application. For example, the switching modules may be arranged in a six-pack, full H-bridge, half H-bridge, single switch or the like. | 09-26-2013 |
20130248884 | III-Nitride Power Device - A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof. | 09-26-2013 |
20130248885 | Transistors Comprising a SiC-Containing Channel - A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel. | 09-26-2013 |
20130256698 | LOW LOSS SIC MOSFET - A Vertical Multiple Implanted Silicon Carbide Power MOSFET (VMIMOSFET) includes a first conductivity semiconductor substrate, a first conductivity semiconductor drift layer on the top of the substrate, a multitude of second conductivity layers implanted in the drift layer. The body layer is where the channel is formed. A first conductivity source layer is interspaced appropriately inside of the second conductivity layers. A gate oxide of a certain thickness and another oxide of a different thickness, a greater thickness than the gate oxide, placed in between the body layers but in such way that its shape does not distort the gate oxide in the channel. A charge compensated body layer of the second conductivity formed outside of the channel region and only at specific high electric field locations in the structure. The device and the manufacturing method deliver a power SiC MOSFET with increased frequency of operation and reduced switching losses. | 10-03-2013 |
20130256699 | Gate Overvoltage Protection for Compound Semiconductor Transistors - A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region. A gate is provided for controlling the channel region. The transistor device further includes a gate overvoltage protection device connected between the source and the gate, the gate overvoltage protection device including p-type and n-type silicon-containing semiconductor material. | 10-03-2013 |
20130256700 | SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING THEM - A silicon carbide substrate has a first main surface, and a second main surface opposite to the first main surface. A region including at least one main surface of the first and second main surfaces is made of single-crystal silicon carbide. In the one main surface, sulfur atoms are present at not less than 60×10 | 10-03-2013 |
20130256701 | STRAINED SILICON CHANNEL SEMICONDUCTOR STRUCTURE - A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses. | 10-03-2013 |
20130264581 | BIPOLAR JUNCTION TRANSISTOR WITH IMPROVED AVALANCHE CAPABILITY - A bipolar junction transistor (BJT), which includes a collector layer, a base layer on the collector layer, an emitter layer on the base layer, and a recess region embedded in the collector layer, is disclosed. A base-collector plane is between the base layer and the collector layer. The recess region is may be below the base-collector plane. Further, the recess region and the base layer are a first type of semiconductor material. By embedding the recess region in the collector layer, the recess region and the collector layer form a first P-N junction, which may provide a point of avalanche for the BJT. Further, the collector layer and the base layer form a second P-N junction. By separating the point of avalanche from the second P-N junction, the BJT may avalanche robustly, thereby reducing the likelihood of avalanche induced failures, particularly in silicon carbide (SiC) BJTs. | 10-10-2013 |
20130264582 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A trench having a sidewall is provided on a first face of a silicon carbide substrate of a first conductivity type. A first region of a second conductivity type is provided on the first face. A second region is provided on the first region, and is separated from the silicon carbide substrate by the first region. The second region is of the first conductivity type. A charge compensation region is provided on the sidewall of the trench. The charge compensation region is of the second conductivity type. A gate insulation film is provided on the first face and above the first region. A first main electrode is provided on the first region. A second main electrode is provided on a second face of the silicon carbide substrate. | 10-10-2013 |
20130264583 | POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A first region is interposed between a drain electrode and a source electrode in a thickness direction, and has first conductivity type. The first region includes a drift layer and a channel layer. The drift layer faces the drain electrode. The channel layer is provided on the drift layer and faces the source electrode. The drift layer has an impurity concentration higher than that of the channel layer. A second region has second conductivity type different from the first conductivity type. The second region has a charge compensation portion and a gate portion. The drift layer is interposed in the charge compensation portion in an in-plane direction that crosses the thickness direction. The channel layer is interposed in the gate portion in the in-plane direction. | 10-10-2013 |
20130264584 | SILICON CARBIDE SINGLE-CRYSTAL SUBSTRATE AND METHOD FOR MANUFACTURING SAME - A silicon carbide single-crystal substrate includes a first surface, a second surface opposite to the first surface, and a peripheral edge portion sandwiched between the first surface and the second surface. A plurality of grinding traces are formed in a surface of the peripheral edge portion. A chamfer width as a distance from an outermost peripheral end portion of the peripheral edge portion to one of the plurality of grinding traces which is located on an innermost peripheral side of the peripheral edge portion in a direction parallel to the first surface is not less than 50 μm and not more than 400 μm. Thereby, a silicon carbide single-crystal substrate capable of suppressing occurrence of a crack, and a method for manufacturing the same can be provided. | 10-10-2013 |
20130264585 | SEMICONDUCTOR DEVICE WITH STRESS-PROVIDING STRUCTURE - A semiconductor device is provided. The semiconductor device includes a substrate, a recess and a stress-providing structure. A channel structure is formed in the substrate. The recess is formed in the substrate and arranged beside the channel structure. The recess has a round inner surface. The stress-providing structure is formed within the recess. Corresponding to the profile of the round inner surface of the recess, the stress-providing structure has a round outer surface. | 10-10-2013 |
20130270576 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device has a planar layout configured by periodically arranging unit cells. The unit cells include valid cells and invalid cells. Each of the valid cells has a switchable channel surface. The invalid cells are to relax electric field in the valid cells. At least one of the valid cells is disposed between adjacent ones of the invalid cells. | 10-17-2013 |
20130270577 | GRID-UMOSFET WITH ELECTRIC FIELD SHIELDING OF GATE OXIDE - A trench metal oxide semiconductor field effect transistor or UMOSFET, includes a buried region that extends beneath the trench and beyond a corner of the trench. The buried region is tied to a source potential of the UMOSFET, and splits the potential realized across the structure. This effectively shields the electric field from the corners of the trench to reduce gate oxide stress, and resultantly improves device performance and reliability. | 10-17-2013 |
20130270578 | SEMICONDUCTOR DEVICE WITH HEAT REMOVAL STRUCTURE AND RELATED PRODUCTION METHOD - According to the invention, a semiconductor device composite structure is provided which comprises an initial substrate with discreet, integrated devices and a heat removal structure. The heat removal structure comprises: a bond layer which is attached to the initial substrate or the devices, a heat removal structure which is attached on the bond layer and which consists of a material with a specific thermal conductivity which is at least double the level of the average specific heat conductivity of the initial substrate or the devices, and one or more metallic thermal bridges which thermally connect the devices with the heat removal structure via the bond layer. The thermal bridges are designed as vertical through connections (vias) through the bond and heat removal structure. The invention furthermore relates to an associated production method. | 10-17-2013 |
20130270579 | Epitaxy Silicon on Insulator (ESOI) - Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region. | 10-17-2013 |
20130277685 | SOI TRANSISTORS WITH IMPROVED SOURCE/DRAIN STRUCTURES WITH ENHANCED STRAIN - A transistor structure with improved device performance, and a method for forming the same is provided. The transistor structure is an SOI (silicon-on-insulator) transistor. In one embodiment, a silicon layer over the oxide layer is a relatively uniform film and in another embodiment, the silicon layer over the oxide layer is a silicon fin. The transistor devices include source/drain structures formed of a strain material that extends through the silicon layer, through the oxide layer and into the underlying substrate which may be silicon. The source/drain structures also include portions that extend above the upper surface of the silicon layer thereby providing an increased volume of the strain layer to provide added carrier mobility and higher performance. | 10-24-2013 |
20130277686 | Semiconductor Structure with Metal Gate and Method of Fabricating the Same - A metal gate process comprises the steps of providing a substrate, forming a dummy gate on said substrate, forming dummy spacers on at least one of the surrounding sidewalls of said dummy gate, forming a source and a drain respectively in said substrate at both sides of said dummy gate, performing a replacement metal gate process to replace said dummy gate with a metal gate, removing said dummy spacers, and forming low-K spacers to replace said dummy spacers. | 10-24-2013 |
20130277687 | HIGH VOLTAGE FIELD EFFECT TRANSITOR FINGER TERMINATIONS - A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation. | 10-24-2013 |
20130277688 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device of the present invention includes a semiconductor layer composed of SiC, a metal layer directly bonded to one face of the semiconductor layer, and a high carbon concentration layer formed on a surface layer portion at one side of the semiconductor layer and containing more highly concentrated carbon than a surface layer portion of the other side. Further, a manufacturing method of a semiconductor device of the present invention includes the steps of forming, on a surface layer portion at one face side of a semiconductor layer composed of SiC, a high carbon concentration layer containing more highly concentrated carbon than a surface layer portion at the other face side by heat treatment and directly bonding metal to the high carbon concentration layer. | 10-24-2013 |
20130285068 | SOLID STATE RADIATION DETECTOR WITH ENHANCED GAMMA RADIATION SENSITIVITY - A silicon carbide Schottky diode solid state radiation detector that has an electron donor layer such as platinum placed over and spaced above the Schottky contact to contribute high energy Compton and photoelectrical electrons from the platinum layer to the active region of the detector to enhance charged particle collection from incident gamma radiation. | 10-31-2013 |
20130285069 | SiC SEMICONDUCTOR ELEMENT - The invention provides an SiC semiconductor element having fewer interface defects at the interface between the SiC and the insulating film of the SiC semiconductor, as well as improved channel mobility. The semiconductor element is provided with at least an SiC semiconductor substrate and an insulating film in contact with the substrate, wherein the insulating film is formed on a specific crystal plane of the SiC semiconductor substrate, the specific crystal plane being a plane having an off-angle of 10-20° relative to the {11-20} plane toward the [000-1] direction or at an off-angle of 70-80° relative to the (000-1) plane toward the <11-20> direction. Through the use of a specific crystal plane unknown in the prior art, interface defects between the SiC semiconductor substrate and the insulating film can be reduced, and channel mobility of the semiconductor element can be improved. | 10-31-2013 |
20130285070 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a manufacturing method of a silicon carbide semiconductor device, a semiconductor substrate made of single crystal silicon carbide is prepared. At a portion of the semiconductor substrate where a first electrode is to be formed, a metal thin film made of electrode material including an impurity is formed. After the metal thin film is formed, the first electrode including a metal reaction layer in which the impurity is introduced is formed by irradiating the metal thin film with a laser light. | 10-31-2013 |
20130285071 | SEMICONDUCTOR DEVICE - On a front surface of a region where a junction termination extension structure of a semiconductor device using silicon carbide is formed, a structure having an n-type semiconductor region with a concentration relatively higher than a concentration of an n | 10-31-2013 |
20130285072 | WIDE BAND GAP SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A wide band gap semiconductor device is disclosed. A first trench in a gate electrode part and second trench in a source electrode part (Schottky diode) are disposed close to each other, and the second trench is deeper than the first trench. A metal electrode is formed in the second trench to form a Schottky junction on a surface of an n-type drift layer in the bottom of the second trench. Further, a p+-type region is provided in part of the built-in Schottky diode part being in contact with the surface of the n-type drift layer, preferably in the bottom of the second trench. The result is a small wide band gap semiconductor device which is low in on-resistance and loss. Electric field concentration applied on a gate insulating film is relaxed to suppress lowering of withstand voltage and increase avalanche breakdown tolerance at turning-off time. | 10-31-2013 |
20130292701 | Doped Core Trigate FET Structure and Method - Techniques for fabricating a field effect transistor (FET) device having a doped core and an undoped or counter-doped epitaxial shell are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A wafer is provided having a semiconductor material selected from the group consisting of silicon, silicon germanium and silicon carbon. At least one fin core is formed in the wafer. Ion implantation is used to dope the fin core. Corners of the fin core are reshaped to make the corners rounded or faceted. An epitaxial shell is grown surrounding the fin core, wherein the epitaxial shell includes a semiconductor material selected from the group consisting of silicon, silicon germanium and silicon carbon. | 11-07-2013 |
20130292702 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a substrate, a gate insulating film, a gate electrode, an interlayer insulating film, and a buffer film containing Ti and N and containing no Al, and a source electrode containing Ti, Al, and Si. In the semiconductor device, a contact hole is formed away from the gate electrode so as to extend through the interlayer insulating film. The gate insulating film is formed on a main surface of the substrate, which is formed of a plane having an off angle of not less than 50° and not more than 65° relative to a {0001} plane. The buffer film is formed in contact with a side wall surface of the contact hole. The source electrode is formed on and in contact with the buffer film and the main surface of the substrate. | 11-07-2013 |
20130292703 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A MOSFET includes: a substrate; a gate insulating film; a gate electrode; an interlayer insulating film formed on the gate insulating film to surround the gate electrode; a buffer film containing Ti and N and containing no Al; and a source electrode containing Ti, Al, and Si. In the MOSFET, a contact hole is formed away from the gate electrode so as to extend through the interlayer insulating film and expose a main surface of the substrate. The buffer film is formed in contact with a side wall surface of the contact hole. The source electrode is formed on and in contact with the buffer film and the main surface of the substrate exposed by forming the contact hole. | 11-07-2013 |
20130292704 | SILICON CARBIDE STRUCTURE AND METHOD OF PRODUCING THE SAME - To provide a block-constituted structure of silicon carbide for use as a construction material, and a method of producing the block-constituted silicon carbide structure, which method realizes thorough compatibility with the natural environment by consuming carbon dioxide and releasing oxygen during the block production process. The silicon carbide structure is formed by injecting carbon dioxide into silicon-oxide-rich silica sand sealed a form to react therewith and form the resulting silicon carbide into a block of fixed shape, and is waterproofed for use as a construction material. | 11-07-2013 |
20130299848 | Semiconductor Packages and Methods of Formation Thereof - In one embodiment, a semiconductor package includes a vertical semiconductor chip having a first major surface on one side of the vertical semiconductor chip and a second major surface on an opposite side of the vertical semiconductor chip. The first major surface includes a first contact region and the second major surface includes a second contact region. The vertical semiconductor chip is configured to regulate flow of current from the first contact region to the second contact region along a current flow direction. A back side conductor is disposed at the second contact region of the second major surface. The semiconductor package further includes a first encapsulant in which the vertical semiconductor chip and the back side conductor are disposed. | 11-14-2013 |
20130299849 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - The present invention provides a technique capable of realizing a silicon carbide semiconductor device having high performance and high reliability. By constituting a channel region by an n | 11-14-2013 |
20130306985 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - An aluminum material can be used on a surface of the electrode of a semiconductor element, this aluminum layer need not be formed thick unnecessarily, a copper wire is bonded strongly to the semiconductor element irrespective of a diameter of the wire, and high heat resistance can be achieved. Silicon carbide (SiC) is used as a substrate of the semiconductor element | 11-21-2013 |
20130306986 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide substrate includes a first layer of a first conductivity type, a second layer of a second conductivity type provided on the first layer, and a third layer provided on the second layer and doped with an impurity for providing the first conductivity type. The silicon carbide substrate has a trench formed through the third layer and the second layer to reach the first layer. The first layer has a concentration peak of the impurity in a position away from the trench in the first layer. As a result, a silicon carbide semiconductor device having an electric field relaxation structure that can be readily formed is provided. | 11-21-2013 |
20130306987 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A first layer is of a first conductivity type. A second layer is provided on the first layer and is of a second conductivity type. A third layer is provided on the second layer and isolated from the first layer by the second layer, and is of the first conductivity type. A trench is formed through the third layer and the second layer to reach the first layer. The first layer includes a relaxation region sandwiching a gate insulating film between itself and a gate electrode. The relaxation region is doped with a first impurity for providing the first conductivity type. The relaxation region is also doped with a second impurity for providing the second conductivity type in a concentration lower than that of the first impurity. As a result, an electric field relaxation structure for improving the breakdown voltage can be readily formed. | 11-21-2013 |
20130306988 | DIAMOND AND DIAMOND COMPOSITE MATERIAL - A structure having: a substrate and a diamond layer on the substrate having diamond nanoparticles. The diamond nanoparticles are formed by colliding diamond particles with the substrate. A method of: directing an aerosol of submicron diamond particles toward a substrate, and forming on the substrate a diamond layer of diamond nanoparticles formed by the diamond particles colliding with the substrate. | 11-21-2013 |
20130306989 | DIAMOND AND DIAMOND COMPOSITE MATERIAL - A structure having: a substrate and a diamond layer on the substrate having diamond nanoparticles. The diamond nanoparticles are formed by colliding diamond particles with the substrate. A method of: directing an aerosol of submicron diamond particles toward a substrate, and forming on the substrate a diamond layer of diamond nanoparticles formed by the diamond particles colliding with the substrate. | 11-21-2013 |
20130306990 | WAFER PRECURSOR PREPARED FOR GROUP III NITRIDE EPITAXIAL GROWTH ON A COMPOSITE SUBSTRATE HAVING DIAMOND AND SILICON CARBIDE LAYERS, AND SEMICONDUCTOR LASER FORMED THEREON - A high power, wide-bandgap device is disclosed that exhibits reduced junction temperature and higher power density during operation and improved reliability at a rated power density. The device includes a diamond substrate for providing a heat sink with a thermal conductivity greater than silicon carbide, a single crystal silicon carbide layer on the diamond substrate for providing a supporting crystal lattice match for wide-bandgap material structures that is better than the crystal lattice match of diamond, and a Group III nitride heterostructure on the single crystal silicon carbide layer for providing device characteristics. | 11-21-2013 |
20130306991 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor-element substrate in which a front-surface electrode pattern is formed on a surface of an insulating substrate and a back-surface electrode is formed on another surface; semiconductor elements affixed to the surface of the front-surface electrode pattern opposite the insulating substrate; and a sealing resin member which covers the semiconductor element and the semiconductor-element substrate, wherein at a position of the front-surface electrode pattern where the position has potential equivalent to that of the front-surface electrode pattern at a position where a semiconductor element is bonded, an insulating terminal table formed with a conductive relay terminal and an insulating member that insulates the relay terminal and the front-surface electrode pattern from each other are provided, and wiring from the semiconductor element to the outside is led out via the relay terminal. | 11-21-2013 |
20130306992 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A silicon carbide semiconductor device includes: a silicon carbide layer, a reaction layer which is in contact with the silicon carbide layer, a conductive oxidation layer which is in contact with the reaction layer, and an electrode layer which is formed over the reaction layer with the conductive oxidation layer interposed therebetween. A thickness of the conductive oxidation layer falls within a range of 0.3 nm to 2.25 nm. | 11-21-2013 |
20130313568 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A silicon carbide substrate has a first conductivity type. The silicon carbide substrate has a first surface provided with a first electrode and a second surface provided with first trenches arranged to be spaced from one another. A gate layer covers an inner surface of each of the first trenches. The gate layer has a second conductivity type different from the first conductivity type. A filling portion fills each of the first trenches covered with the gate layer. A second electrode is separated from the gate layer and provided on the second surface of the silicon carbide substrate. A gate electrode is electrically insulated from the silicon carbide substrate and electrically connected to the gate layer. Thereby, a silicon carbide semiconductor device capable of being easily manufactured can be provided. | 11-28-2013 |
20130313569 | Semiconductor Gas Sensor And Method For Producing The Same - A technique capable of realizing a semiconductor gas sensor having a high rising response speed is provided. A gate insulating film (e.g., a SiO | 11-28-2013 |
20130313570 | MONOLITHICALLY INTEGRATED SIC MOSFET AND SCHOTTKY BARRIER DIODE - A SIC VDMOS transistor is integrated with a SiC SBD, in a seamless way, without any increase of the device area. The SiC SBD is integrated in the active area of the VDMOS by splitting the P-Wells, such that the lightly doped drift region extents all the way to the surface of semiconductor, and by trenching through the source of the VDMOS and partially through the P-Wells to reach the peak of the P-type doping in the P-Well regions. The source of the VDMOS is contacted from the top surface and from the vertical sidewalls of the trenched source and the forward voltage of the Schottky Barrier diode is tailored by using two different metals for the ohmic contact on the source and for the SBD. | 11-28-2013 |
20130313571 | SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR COMPRISING SHIELDING REGIONS AND METHODS OF MANUFACTURING THE SAME - A silicon carbide (SiC) bipolar junction transistor (BJT) and a method of manufacturing such a SiC BJT is provided. The SiC BJT can include a collector region having a first conductivity type, a base region having a second conductivity type opposite the first conductivity type, and an emitter region having the first conductivity type, the collector region, the base region and the emitter region being arranged as a stack. The emitter region defining an elevated structure defined at least in part by an outer sidewall on top of the stack. The base region having a portion capped by the emitter region and defining an intrinsic base region where the intrinsic base region includes a portion extending from the emitter region to the collector region. The SiC BJT can include a first shielding region and a second shield region each having the second conductivity type. | 11-28-2013 |
20130313572 | SEMICONDUCTOR DEVICE WITH STRAIN-INDUCING REGIONS AND METHOD THEREOF - Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions. | 11-28-2013 |
20130313573 | SEMICONDUCTOR RECTIFIER - A semiconductor rectifier includes a first conductivity type wide bandgap semiconductor substrate having a first conductivity type wide bandgap semiconductor layer on an upper surface of which is formed a plurality of first wide bandgap semiconductor regions of the first conductivity type sandwiching a plurality of second wide bandgap semiconductor regions of a second conductivity type, and a plurality of third wide bandgap semiconductor regions of the second conductivity type, at least a part of the third wide bandgap semiconductor regions being connected to the second wide bandgap semiconductor regions and each of the third wide bandgap semiconductor regions having a width smaller than that of the second wide bandgap semiconductor regions. A first electrode is formed on the first and second wide bandgap semiconductor regions and a second electrode is formed on a lower surface of the wide bandgap semiconductor substrate. | 11-28-2013 |
20130313574 | SEMICONDUCTOR POWER MODULE AND METHOD OF MANUFACTURING THE SAME - A semiconductor power module according to the present invention includes a base member, a semiconductor power device having a surface and a rear surface with the rear surface bonded to the base member, a metal block, having a surface and a rear surface with the rear surface bonded to the surface of the semiconductor power device, uprighted from the surface of the semiconductor power device in a direction separating from the base member and employed as a wiring member for the semiconductor power device, and an external terminal bonded to the surface of the metal block for supplying power to the semiconductor power device through the metal block. | 11-28-2013 |
20130313575 | SEMI-INSULATING SILICON CARBIDE MONOCRYSTAL AND METHOD OF GROWING THE SAME - A semi-insulating silicon carbide monocrystal and a method of growing the same are disclosed. The semi-insulating silicon carbide monocrystal comprises intrinsic impurities, deep energy level dopants and intrinsic point defects. The intrinsic impurities are introduced unintentionally during manufacture of the silicon carbide monocrystal, and the deep energy level dopants and the intrinsic point defects are doped or introduced intentionally to compensate for the intrinsic impurities. The intrinsic impurities include shallow energy level donor impurities and shallow energy level acceptor impurities. A sum of a concentration of the deep energy level dopants and a concentration of the intrinsic point defects is greater than a difference between a concentration of the shallow energy level donor impurities and a concentration of the shallow energy level acceptor impurities, and the concentration of the intrinsic point defects is less than the concentration of the deep energy level dopants. The semi-insulating SiC monocrystal has resistivity greater than 1×10 | 11-28-2013 |
20130313576 | SEMICONDUCTOR POWER DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor power device of the present invention includes a first electrode and a second electrode, a breakdown voltage holding layer that is made of a semiconductor having a predetermined thickness and a predetermined impurity concentration, to which the first electrode and the second electrode are joined, and that has an active region in which carriers to generate electric conduction between the first electrode and the second electrode move, and an insulation film that is formed on the breakdown voltage holding layer and that has a high dielectric-constant portion having a higher dielectric constant than SiO | 11-28-2013 |
20130313577 | LAMINATE SUBSTRATE AND METHOD OF FABRICATING THE SAME - Embodiments of the invention provide a crystalline aluminum carbide layer, a laminate substrate having the crystalline aluminum carbide layer formed thereon, and a method of fabricating the same. The laminate substrate has a GaN layer including a GaN crystal and an AlC layer including an AlC crystal. Further, the method of fabricating the laminate substrate, which has the AlN layer including the AlN crystal and the AlC layer including the AlC crystal, includes supplying a carbon containing gas and an aluminum containing gas to grow the AlC layer. | 11-28-2013 |
20130320356 | SEMICONDUCTOR STRUCTURE HAVING A NITRIDE ACTIVE LAYER ON A DOPED SILICON CARBIDE HEAT SPREADER - A semiconductor structure having: a doped silicon carbide heat spreader; a semi-insulating silicon carbide layer disposed over the doped silicon carbide heat spreader; and a nitride (such as GaN, Indium nitride, Aluminum nitride) semiconductor layer disposed on the semi-insulating silicon carbide layer. | 12-05-2013 |
20130320357 | EPITAXIAL SILICON CARBIDE SINGLE CRYSTAL SUBSTRATE AND METHOD FOR PRODUCING SAME - Provided are an epitaxial silicon carbide single crystal substrate having a high-quality silicon carbide single crystal thin film with less stacking faults on a silicon carbide single crystal substrate and a production method therefor. The epitaxial silicon carbide single crystal substrate is produced by growing a silicon carbide epitaxial layer on a silicon carbide single crystal substrate having an off-angle of 4° or less so that the number of stacking faults emitting light at wavelengths ranging from 400 to 600 nm by photoluminescence on the substrate is less than 10/cm | 12-05-2013 |
20130328061 | NORMALLY-OFF GALLIUM NITRIDE TRANSISTOR WITH INSULATING GATE AND METHOD OF MAKING THE SAME - A normally-off transistor includes a channel layer, an electron supply layer overlaying the channel layer, a source electrode and a drain electrode on the electron supply layer, an area in the electrode supply layer between the source electrode and the drain electrode treated with a fluoride based plasma followed by a chlorine based plasma treatment, a gate insulator overlaying the area, and a gate electrode overlaying the gate insulator. | 12-12-2013 |
20130328062 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - In a MOSFET using a SiC substrate, a source region having low resistance and high injection efficiency is formed without performing a high-temperature heat treatment. | 12-12-2013 |
20130328063 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE - An object is to provide a novel manufacturing method of a semiconductor substrate containing silicon carbide, and another object is to provide a semiconductor device using silicon carbide. A semiconductor substrate is manufactured through the steps of: adding ions to a silicon carbide substrate to form an embrittlement region in the silicon carbide substrate; bonding the silicon carbide substrate to a base substrate with insulating layers interposed therebetween; heating the silicon carbide substrate and separating the silicon carbide substrate at the embrittlement region to form a silicon carbide layer over the base substrate with the insulating layers interposed between therebetween; and performing heat treatment on the silicon carbide layer at a temperature of 1000° C. to 1300° C. to reduce defects of the silicon carbide layer. A semiconductor device is manufactured using the semiconductor substrate formed as described above. | 12-12-2013 |
20130328064 | METHOD AND SYSTEM FOR TRANSIENT VOLTAGE SUPPRESSORS - A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity. | 12-12-2013 |
20130328065 | SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR ELEMENT MANUFACTURING METHOD - A method for fabricating a semiconductor element according to the present disclosure includes the steps of: (A) forming a first silicon carbide semiconductor layer of a first conductivity type on a semiconductor substrate; (B) forming a first mask to define a body region on the first silicon carbide semiconductor layer; (C) forming a body implanted region of a second conductivity type in the first silicon carbide semiconductor layer using the first mask; (D) forming a sidewall on side surfaces of the first mask; (E) defining a dopant implanted region of the first conductivity type and a first body implanted region of the second conductivity type in the first silicon carbide semiconductor layer using the first mask and the sidewall; and (F) thermally treating the first silicon carbide semiconductor layer. | 12-12-2013 |
20130334541 | THREE DIMENSIONAL STRAINED SEMICONDUCTORS - In one embodiment, an apparatus includes a three dimensional structure comprising a semiconductor material, and at least one thin film in contact with at least one exterior surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the three dimensional structure. In another embodiment, a method includes forming a three dimensional structure comprising a semiconductor material, and depositing at least one thin film on at least one surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the structure. | 12-19-2013 |
20130334542 | NORMALLY-OFF POWER JFET AND MANUFACTURING METHOD THEREOF - In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times. | 12-19-2013 |
20130341638 | MULTI-GATE FIELD-EFFECT TRANSISTOR AND PROCESS THEREOF - A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor. | 12-26-2013 |
20130341639 | DEEP DEPLETED CHANNEL MOSFET WITH MINIMIZED DOPANT FLUCTUATION AND DIFFUSION LEVELS - CMOS devices are fabricated with a channel layer having minimized dopant fluctuation and diffusion. Embodiments include forming a dummy gate, on a substrate, between a pair of spacers, forming, in the substrate, a source and drain separated by a ground plane layer, removing the dummy gate from the substrate, forming a cavity between the pair of spacers, forming, after removal of the dummy gate, a channel layer on the substrate, forming a high-k layer on the channel layer and on side surfaces of the cavity, and forming a replacement gate in the cavity. | 12-26-2013 |
20130341640 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor device includes a semiconductor, a source electrode, a drain electrode, an insulating layer and a gate electrode. The semiconductor layer includes an GaN layer and a AlGaN layer provided on the GaN layer. The source electrode and the drain electrode are provided on the semiconductor layer. The insulating layer is provided on the semiconductor layer between the source electrode and the drain electrode. The gate electrode includes a penetrating portion and a gate field plate, the penetrating portion being in contact with the semiconductor layer through the insulating layer and containing platinum in contact with the semiconductor layer, the gate field plate being in contact with an upper face of the insulating layer with a contact length of not less than 0.1 micrometers and not more than 0.3 micrometers and containing platinum in contact with the upper surface. | 12-26-2013 |
20130341641 | RECTIFIER CIRCUIT - A rectifier circuit has a rectifier element and a unipolar field-effect transistor connected in series between a first terminal and a second terminal. The rectifier element comprises a first electrode and a second electrode disposed in a direction of a forward current flowing from the first terminal to the second terminal. The field-effect transistor has a gate electrode having a potential identical to a potential at the first electrode, and a source electrode and a drain electrode connected in series to the rectifier element and passing a current depending on the potential at the gate electrode. A breakdown voltage between the gate electrode and drain electrode of the field-effect transistor in a reverse bias mode, where a potential at the second terminal is higher than a potential at the first terminal, being set higher than a breakdown voltage of the rectifier element. | 12-26-2013 |
20130341642 | MOS TRANSISTOR, FABRICATION METHOD THEREOF, AND SRAM MEMORY CELL CIRCUIT - Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a channel region including an asymmetric stressing layer having a stress gradually varied from a compressive stress to a tensile stress or from a tensile stress to a compressive stress from a first end of the channel region adjacent to a source region to a second end of the channel region adjacent to a drain region. The MOS transistor can be used as a transfer transistor in an SRAM memory cell circuit to increase a source-drain saturation current in a write operation and to reduce a source-drain saturation current in a read operation. Read and write margins of the SRAM can be increased. | 12-26-2013 |
20130341643 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE DEVICE - A first first-conductivity-type impurity region ( | 12-26-2013 |
20130341644 | METHOD AND DESIGN OF AN RF THRU-VIA INTERCONNECT - In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the substrate to the semiconductor device while at the same time permitting the heat generated by the semiconductor device to flow through the high thermal conductivity substrate, through the back side of the substrate and to a beat sink. | 12-26-2013 |
20130341645 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A collector layer is made of silicon carbide having a first conductivity type. A switching element is provided on the collector layer. The switching element includes a junction gate for controlling a channel having a second conductivity type different from the first conductivity type. | 12-26-2013 |
20130341646 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A silicon carbide semiconductor device includes a silicon carbide substrate and a contact electrode. The silicon carbide substrate includes an n type region and a p type region that makes contact with the n type region. The contact electrode makes contact with the n type region and the p type region. The contact electrode contains Ni atoms and Si atoms. The number of the Ni atoms is not less than 87% and not more than 92% of the total number of the Ni atoms and the Si atoms. Accordingly, there can be provided a silicon carbide semiconductor device, which can achieve ohmic contact with an n type impurity region and can achieve a low contact resistance for a p type impurity region, as well as a method for manufacturing such a silicon carbide semiconductor device. | 12-26-2013 |
20130341647 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a silicon carbide substrate, and a contact electrode. The silicon carbide substrate includes an n type region and a p type region in contact with the n type region. The contact electrode forms contact with the silicon carbide substrate. The contact electrode includes a first region containing TiSi, and a second region containing Al. The first region includes an n contact region in contact with the n type region and a p contact region in contact with the p type region. The second region is formed to contact the p type region and the n type region, and to surround the p contact region and the n contact region. Accordingly, there can be provided a silicon carbide semiconductor device including an electrode allowing ohmic contact with both a p type impurity region and an n type impurity region formed at a silicon carbide substrate. | 12-26-2013 |
20130341648 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE - A first layer of a first conductivity type made of silicon carbide is formed. A second layer of a second conductivity type different from the first conductivity type positioned on the first layer, and a third layer of the first conductivity type positioned on the second layer are formed. The step of forming second and third layers includes the steps of performing impurity ion implantation, and performing heat treatment for activating impurities implanted by the impurity ion implantation. After the step of performing heat treatment, a trench having a side wall penetrating the third layer and the second layer and having a bottom reaching the first layer is formed. A gate insulating film to cover the side wall of the trench is formed. As a result, a silicon carbide semiconductor device having a low ON resistance is provided. | 12-26-2013 |
20130341649 | METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE WITH A BURIED GROUND PLANE - The invention relates to a method for making a semiconducting structure, including:
| 12-26-2013 |
20140001488 | Electronic Device Including Silicon Carbide Diode Dies | 01-02-2014 |
20140001489 | DOUBLE-RECESSED TRENCH SCHOTTKY BARRIER DEVICE | 01-02-2014 |
20140001490 | SCHOTTKY-BARRIER DEVICE WITH LOCALLY PLANARIZED SURFACE AND RELATED SEMICONDUCTOR PRODUCT | 01-02-2014 |
20140001491 | Electrostatic Discharge Protection Element and Electrostatic Discharge Protection Chip and Method of Producing the Same | 01-02-2014 |
20140008666 | SILICON CARBIDE VERTICAL FIELD EFFECT TRANSISTOR - A silicon carbide vertical field effect transistor includes a first-conductive-type silicon carbide substrate; a low-concentration first-conductive-type silicon carbide layer formed on a surface of the first-conductive-type silicon carbide substrate; second-conductive-type regions selectively formed on a surface of the first-conductive-type silicon carbide layer; first-conductive-type source regions formed in the second-conductive-type regions; a high-concentration second-conductive-type region formed between the first-conductive-type source regions in the second-conductive-type region; a source electrode electrically connected to the high-concentration second-conductive-type region and a first-conductive-type source region; a gate insulating film formed from the first-conductive-type source regions formed in adjacent second-conductive-type regions, onto the second-conductive-type regions and the first-conductive-type silicon carbide layer; a gate electrode formed on the gate insulating film; and a drain electrode on the back side of the first-conductive-type silicon carbide substrate, wherein an avalanche generating unit is disposed between the second-conductive-type region and the first-conductive-type silicon carbide layer. | 01-09-2014 |
20140008667 | METHOD FOR MANUFACTURING A MONOLITHIC LED MICRO-DISPLAY ON AN ACTIVE MATRIX PANEL USING FLIP-CHIP TECHNOLOGY AND DISPLAY APPARATUS HAVING THE MONOLITHIC LED MICRO-DISPLAY - A high-resolution, Active Matrix (AM) programmed monolithic Light Emitting Diode (LED) micro-array is fabricated using flip-chip technology. The fabrication process includes fabrications of an LED micro-array and an AM panel, and combining the resulting LED micro-array and AM panel using the flip-chip technology. The LED micro-array is grown and fabricated on a sapphire substrate and the AM panel can be fabricated using CMOS process. LED pixels in a same row share a common N-bus line that is connected to the ground of AM panel while p-electrodes of the LED pixels are electrically separated such that each p-electrode is independently connected to an output of drive circuits mounted on the AM panel. The LED micro-array is flip-chip bonded to the AM panel so that the AM panel controls the LED pixels individually and the LED pixels exhibit excellent emission uniformity. According to this constitution, incompatibility between the LED process and the CMOS process can be eliminated. | 01-09-2014 |
20140014968 | TRANSISTOR DEVICE AND FABRICATION METHOD - Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate. | 01-16-2014 |
20140014969 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit. | 01-16-2014 |
20140014970 | METHOD OF FABRICATING SINGLE-LAYER GRAPHENE - A method of fabricating a single-layer graphene on a silicon carbide (SiC) wafer includes forming a plurality of graphene layers on the SiC wafer such that the plurality of graphene layers are on a buffer layer of the SiC wafer, the buffer layer being formed of carbon; removing the plurality of graphene layers from the buffer layer; and converting the buffer layer to a single-layer graphene. | 01-16-2014 |
20140014971 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a SiC layer of a first conductivity type, a SiC region of a second conductivity type, and a conductive layer of the second conductivity type. The SiC layer of the first conductivity type has a hexagonal crystal structure. The SiC region of the second conductivity type is formed in a surface of the SiC layer. The conductive layer of the second conductivity type is provided on the SiC region and is in contact with a portion of the SiC region including SiC of a cubic crystal structure. | 01-16-2014 |
20140014972 | SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film. | 01-16-2014 |
20140014973 | 3C-SiC TRANSISTOR - A bipolar power semiconductor transistor is disclosed. The transistor includes a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type disposed on the semiconductor substrate; a semiconductor drift region of a second conductivity type, opposite the first conductivity type, disposed on the first semiconductor region, a body region of the first conductivity type located within the semiconductor drift region, a source region of the second conductivity type located within the body region, a gate placed above and in contact to the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region. The semiconductor substrate includes a material having silicon (Si) and the first semiconductor region includes a material having 3-step cubic silicon carbide (3C-SiC). | 01-16-2014 |
20140021484 | Semiconductor Device - A manufacturing method provides a semiconductor device having a semiconductor body defining a source region, a body region, a drift region and a diode region. The drift region has a first drift region section and a second drift region section. The diode region is buried within the drift region, and has a semiconductor type opposite to the drift region to form a diode. The diode region is separated from the gate electrode by the first drift region section extending from the diode region in a vertical direction. The gate electrode is adjacent the body region and insulated from the body region by a gate dielectric. A source electrode is electrically connected to the source region, the body region and the diode region. A semiconductor region of a doping type opposite to the doping type of the drift region is arranged between the first drift region section and the source electrode. | 01-23-2014 |
20140021485 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A vertical channel transistor includes a pillar formed over a substrate, and a gate electrode formed on sidewalls of the pillar, wherein the pillar includes a source area, a vertical channel area over the source area, a drain area over the vertical channel area, and a leakage prevention area interposed between the vertical channel area and the drain area. | 01-23-2014 |
20140021486 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) includes a substrate and an eputaxial layer on the substrate. The epitaxial layer includes a N-type GaN-based layer, a light emitting layer, and a P-type GaN-based layer. The LED further includes a first electrode on the N-type GaN-based layer and a second electrode on the P-type GaN-based layer. The P-type GaN-based layer has a inactive portion, and the second electrode is located and covers the inactive portion. | 01-23-2014 |
20140021487 | Modular Power Converter Having Reduced Switching Loss - In one implementation, a modular power converter having a reduced switching loss includes a package, a field-effect transistor (FET) including a gate terminal, a drain terminal, and a source terminal, and fabricated on a semiconductor die situated inside the package, and a driver circuit inside the package. The driver circuit is configured to drive the gate terminal of the FET. The driver circuit is further configured to sample a drain-to-source voltage (V | 01-23-2014 |
20140021488 | NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING NITRIDE-BASED SEMICONDUCTOR DEVICE - In a nitride-based semiconductor device, an undoped gallium nitride (GaN) layer is formed on an aluminum gallium nitride (AlGaN) layer, and a silicon carbon nitride (Si | 01-23-2014 |
20140021489 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device having a high withstand voltage in which a stable withstand voltage can be obtained and a method for manufacturing the same. A JTE region having a second conductivity type is formed in a portion on an outer peripheral end side of an SiC substrate from a second conductivity type SiC region in a vicinal portion of a surface on one of sides in a thickness direction of a first conductivity type SiC epitaxial layer. A first conductivity type SiC region having a higher concentration of an impurity having the first conductivity type than that of the SiC epitaxial layer is formed in at least a vicinal portion of a surface on one of sides in a thickness direction of a portion in which the JTE regions are bonded to each other. | 01-23-2014 |
20140021490 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - Fabrication of a termination structure in a semiconductor device increases in some cases the numbers of ion implantation processes or of photolithography processes, thus leading to an increase in fabrication costs. To overcome this problem, a semiconductor device is provided which includes an n-type drift layer formed on a semiconductor substrate; an element region formed in a surface portion of the drift layer; a recess formed in a loop in a laterally outer portion of the drift layer, spaced away a predetermined distance from the element region; and a p-type dopant region formed ranging from a bottom of the recess to a position away from the recess and toward the element region, a thickness of the dopant region where no recess is provided being greater than that where the recess is provided. | 01-23-2014 |
20140027781 | MONOLITHIC BIDIRECTIONAL SILICON CARBIDE SWITCHING DEVICES AND METHODS OF FORMING THE SAME - A monolithic bidirectional switching device includes a drift layer having a first conductivity type and having an upper surface, and first and second vertical metal-oxide semiconductor (MOS) structures at the upper surface of the drift layer. The drift layer provides a common drain for the first and second vertical MOS structures. The first and second vertical MOS structures are protected by respective first and second edge termination structures at the upper surface of the drift layer. A monolithic bidirectional switching device according to further embodiments includes a vertical MOS structure at the upper surface of the drift layer, and a diode at the upper surface of the drift layer. The drift layer provides a drain for the vertical MOS structure and a cathode for the diode, and the vertical MOS structure and the diode are protected by respective first and second edge termination structures. | 01-30-2014 |
20140027782 | SEMICONDUCTOR DEVICE AND METHOD FOR REDUCED BIAS TEMPERATURE INSTABILITY (BTI) IN SILICON CARBIDE DEVICES - A system includes a silicon carbide (SiC) semiconductor device and a hermetically sealed packaging enclosing the SiC semiconductor device. The hermetically sealed packaging is configured to maintain a particular atmosphere near the SiC semiconductor device. Further, the particular atmosphere limits a shift in a threshold voltage of the SiC semiconductor device to less than 1 V during operation. | 01-30-2014 |
20140027783 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located between the plurality of source and drain regions along a first direction; characterized in that the plurality of gate stack structures enclose the plurality of channel regions. In accordance with the semiconductor device and the method of manufacturing the same of the present invention, an all-around nanowire metal multi-gate is formed in self-alignment by punching through and etching the fins at which the channel regions are located using a combination of the hard mask and the dummy gate, thus the device performance is enhanced. | 01-30-2014 |
20140027784 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A drift layer forms a first main surface of a silicon carbide layer and has a first conductivity type. A source region is provided to be spaced apart from the drift layer by a body region, forms a second main surface, and has the first conductivity type. A relaxing region is provided within the drift layer and has a distance L | 01-30-2014 |
20140027785 | CASCODED SEMICONDUCTOR DEVICES - A cascoded power semiconductor circuit is provided for power switches based on depletion-mode (normally on) devices. The control circuit makes use of a bootstrap arrangement that allows an active control of both power switches of a cascode circuit using a single gate driver. | 01-30-2014 |
20140027786 | HIGH EFFICIENCY LIGHT-EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - A high efficiency light-emitting diode and a method for manufacturing the same are described. The high efficiency light-emitting diode comprises: a permanent substrate; a first contact metal layer and a second contact metal layer respectively deposed on two opposite surfaces of the permanent substrate; a bonding layer deposed on the second contact metal layer; a diffusion barrier layer deposed on the bonding layer, wherein the permanent substrate, the bonding layer and the diffusion barrier layer are electrically conductive; a reflective metal layer deposed on the diffusion barrier layer; a transparent conductive oxide layer deposed on the reflective metal layer; an illuminant epitaxial structure deposed on the transparent conductive oxide layer, wherein the illuminant epitaxial structure includes a first surface and a second surface opposite to the first surface; and a second conductivity type compound electrode pad deposed on the second surface of the illuminant epitaxial structure. | 01-30-2014 |
20140027787 | SIC SINGLE CRYSTAL, SIC WAFER, AND SEMICONDUCTOR DEVICE - An SiC single crystal having at least one orientation region where a basal plane dislocation has a high linearity and is oriented to three crystallographically-equivalent <11-20> directions, and an SiC wafer and a semiconductor device which are manufactured from the SiC single crystal. The SiC single crystal can be manufactured by using a seed crystal in which the offset angle on a {0001} plane uppermost part side is small and the offset angle on an offset direction downstream side is large and growing another crystal on the seed crystal. | 01-30-2014 |
20140027788 | ELECTRICAL CONDUCTOR - The invention provides circuits and electronic devices which comprise an electrical flow path, at least part of which is formed by a body of a substrate material at least part of which is a doped part having a surface and implanted atoms at or below the surface, at least part of the surface defining a low resistance section of the electrical flow path. | 01-30-2014 |
20140034963 | DEVICE HAVING REDUCED BIAS TEMPERATURE INSTABILITY (BTI) - A semiconductor device is disclosed along with methods for manufacturing such a device. In certain embodiments, the semiconductor device includes a source electrode formed using a metal that limits a shift, such as due to bias temperature instability, in a threshold voltage of the semiconductor device during operation. In certain embodiments the semiconductor device may be based on silicon carbide. | 02-06-2014 |
20140034964 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first and a second transistor. The first transistor includes a first and a second region of a first conductivity type and a third region of a second conductivity type. The first region is disposed along a first crystal face of a silicon carbide region. The silicon carbide region has the first crystal face and a second crystal face. The second and the third region are disposed along the first face. The third region is provided between the first and the second region. The second transistor includes a fourth and fifth region of the second type and a sixth region of the first type. The fourth, the fifth and the sixth region are disposed along the second face of the silicon carbide region. The sixth region is provided between the fourth and the fifth region. | 02-06-2014 |
20140034965 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device, includes: a first semiconductor region of a first conductivity type; a second semiconductor region provided on the first semiconductor region, an impurity concentration of the second semiconductor region being lower than an impurity concentration of the first semiconductor region; a third semiconductor region of a second conductivity type provided on the second semiconductor region; and a fourth semiconductor region provided on the third semiconductor region or in a portion of the third semiconductor region. A lattice strain of the fourth semiconductor region is greater than a lattice strain of the third semiconductor region. | 02-06-2014 |
20140034966 | TRANSISTOR AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a transistor includes: a structural body; an insulating film; a control electrode; a first electrode; and a second electrode. The structural body includes a first through a third semiconductor regions, and includes a compound semiconductor having a first and a second elements. The first electrode is electrically continuous with the third semiconductor region. The second electrode is electrically continuous with the first semiconductor region. The structural body has a first region provided above a lower end of the second semiconductor region and a second region other than the first region. The first region is a region formed by making a ratio of concentration of source gas of the second element to concentration of source gas of the first element larger than 1.0. Impurity concentration of the first conductivity type in the first region is higher than that in the second region. | 02-06-2014 |
20140034967 | DIODE - A diode is provided which includes at least one diode element which has a plurality of N-type regions and a plurality of P-type regions, the N-type regions and the P-type regions being alternately arranged in series to form PN junctions, and an insulated substrate which has electric insulation. The N-type regions and the P-type regions are formed on the insulated substrate. | 02-06-2014 |
20140034968 | BIPOLAR JUNCTION TRANSISTOR WITH SPACER LAYER - New designs for silicon carbide (SiC) bipolar junction transistors (BJTs) and new methods of manufacturing such SiC BJTs are described. The SiC BJT comprises a collector region, a base region and an emitter region disposed as a stack, the emitter region and part of the base region forming a mesa. The intrinsic part of the base region includes a first portion having a first doping concentration and a second portion having a second doping concentration lower than the first doping concentration. Further, the second portion is vertically disposed between the first portion and the emitter region in the stack. | 02-06-2014 |
20140034969 | SILICON CARBIDE TRENCH MOSFET HAVING REDUCED ON-RESISTANCE, INCREASED DIELECTRIC WITHSTAND VOLTAGE, AND REDUCED THRESHOLD VOLTAGE - A semiconductor device (A | 02-06-2014 |
20140034970 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURING THE SAME - A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures. | 02-06-2014 |
20140034971 | SEMICONDUCTOR APPARATUS AND METHOD FOR MAKING SEMICONDUCTOR APPARATUS - A semiconductor apparatus invention includes a substrate ( | 02-06-2014 |
20140042459 | SILICON CARBIDE SCHOTTKY DIODE - A SiC Schottky diode which includes a Schottky barrier formed on a silicon face 4H-SiC body. | 02-13-2014 |
20140042460 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide substrate has a first surface and a second surface, and includes a first region and a third region each having first conductivity type, as well as a second region and a fourth region each having second conductivity type. The third region surrounds the second region on the second surface. The fourth region has an impurity concentration higher than that of the second region, is in contact with the second region, and surrounds the third region on the second surface. A first main electrode is provided on the first surface. A second main electrode is in contact with each of the third and fourth regions. A gate insulating film is provided on the second region. | 02-13-2014 |
20140042461 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTUING SAME - A method for manufacturing a silicon carbide semiconductor device includes the steps of preparing a silicon carbide substrate, forming a silicon dioxide film on the silicon carbide substrate, and forming an electrode containing Al and Ti to make contact with the silicon carbide substrate and the silicon dioxide film. The step of forming the electrode includes the steps of forming a metal film containing Al and Ti on the silicon carbide substrate, and heating the metal film to not less than 500° C. in an atmosphere in which oxygen gas is introduced. Thereby, the method for manufacturing the silicon carbide semiconductor device capable of improving insulation reliability of an insulating film can be provided. | 02-13-2014 |
20140042462 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present embodiment includes a semiconductor substrate having a first n-type silicon carbide layer and a second n-type silicon carbide layer, a first p-type impurity region formed in the n-type silicon carbide layer, a first n-type impurity region of 4H—SiC structure formed in the n-type silicon carbide layer, a second n-type impurity region of 3C—SiC structure formed in the n-type silicon carbide layer having a depth shallower than the first n-type impurity region, a gate insulating film, a gate electrode formed on the gate insulating film, and a metallic silicide layer formed above the first n-type impurity region and having a bottom portion and a side surface portion such that the second n-type impurity region is sandwiched between the first n-type impurity region and at least the side surface portion. | 02-13-2014 |
20140054608 | COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT - A compound semiconductor integrated circuit is provided, comprising a substrate, at least one compound semiconductor electronic device, a first metal layer, a protection layer, a plurality of second metal layers, and at least one dielectric layer. The first metal layer contains Au but does not contain Cu, and is at least partly electrically connected to the compound semiconductor electronic device. The protection layer covers the compound semiconductor electronic device and at least part of the first metal layer. Each of the plurality of second metal layers contains at least a Cu layer, and at least one of the plurality of second metal layers is partly electrically connected to the first metal layer described above. The at least one dielectric layer separates each pair of adjacent second metal layers. The second metal layers are used to form passive electronic components. | 02-27-2014 |
20140054609 | LARGE HIGH-QUALITY EPITAXIAL WAFERS - Large high-quality epitaxial wafers are disclosed. Embodiments of the invention provide silicon carbide epitaxial wafers with low basal plane dislocation (BPD) densities. In some embodiments, these wafers are of the 4H polytype. These wafers can be at least about 100 mm in diameter and have an epitaxial layer from about 1 micron to about | 02-27-2014 |
20140054610 | SEMICONDUCTOR DEVICE AND METHOD FOR GROWING SEMICONDUCTOR CRYSTAL - A semiconductor device comprises a base substrate, a pattern on the base substrate, a buffer layer on the base substrate, and an epitaxial layer on the buffer. The pattern is a self-assembled pattern. A method for growing a semiconductor crystal comprises cleaning a silicon carbide substrate, forming a self-assembled pattern on the silicon carbide substrate, forming a buffer layer on the silicon carbide substrate, and forming an epitaxial layer on the buffer layer. A semiconductor device comprises a base substrate comprising a pattern groove and an epitaxial layer on the base substrate. A method for growing a semiconductor crystal comprises cleaning a silicon carbide substrate, forming a self-assembled projection on the silicon carbide substrate, forming a pattern groove in the silicon carbide, and forming an epitaxial layer on the silicon carbide. | 02-27-2014 |
20140054611 | SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor layer of a first conductivity type; a plurality of body regions of a second conductivity type; source regions of the first conductivity type, formed on a surface layer part of each body region and spaced away from the edges of each body region; a gate insulating film formed on the semiconductor layer; and gate electrodes formed on the gate insulating film. In the semiconductor layer, trenches extending between two neighboring source regions are formed, the inside surface of the trenches are covered by a gate insulating film, and the gate electrodes comprise surface-facing parts, which are buried in the trenches. | 02-27-2014 |
20140054612 | BIPOLAR JUNCTION TRANSISTOR IN SILICON CARBIDE WITH IMPROVED BREAKDOWN VOLTAGE - A silicon carbide (SiC) bipolar junction transistor (BJT) including a collector region and a base region having an extrinsic part. The SiC BJT including an emitter region and a surface passivation layer deposited on the extrinsic part between an emitter contact contacting the emitter region and a base contact contacting the base region. The SiC BJT also including a surface gate at the surface passivation layer. | 02-27-2014 |
20140061669 | CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE - A chip package is provided, the chip package including: a carrier including at least one cavity; a chip disposed at least partially within the at least one cavity; at least one intermediate layer disposed over at least one side wall of the chip; wherein the at least one intermediate layer is configured to thermally conduct heat from the chip to the carrier. | 03-06-2014 |
20140061670 | WIDE GAP SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A wide gap semiconductor device has a substrate and a Schottky electrode. The substrate is made of a wide gap semiconductor material and has a first conductivity type. The Schottky electrode is arranged on the substrate to be in contact therewith and is made of a single material. The Schottky electrode includes a first region having a first barrier height and a second region having a second barrier height higher than the first barrier height. The second region includes an outer peripheral portion of the Schottky electrode. Thus, a wide gap semiconductor device capable of achieving less leakage current and a method for manufacturing the same can be provided. | 03-06-2014 |
20140061671 | WIDE GAP SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A wide gap semiconductor device includes a substrate and a Schottky electrode. The substrate formed of a wide gap semiconductor material has a main face, and includes a first-conductivity-type region and a second-conductivity-type region. The Schottky electrode is arranged adjoining the main face of the substrate. At the substrate, there is foamed a trench having a side face continuous with the main face and a bottom continuous with the side face. The Schottky electrode adjoins the first-conductivity-type region at the side face of the trench and the main face, and adjoins the second-conductivity-type region at the bottom of the trench. The side face of the trench is inclined relative to the main face of the substrate. | 03-06-2014 |
20140061672 | SEMICONDUCTOR DEVICE - A semiconductor device includes an active region in which current flows when the semiconductor device is in an on state and a breakdown voltage structure portion which surrounds the active region. In the active region, a MOS gate structure includes, a p well region, an n | 03-06-2014 |
20140061673 | SEMICONDUCTOR UNIT AND SEMICONDUCTOR DEVICE USING THE SAME - In some aspects of the invention, semiconductor unit can produce chips performing uniform parallel operation and a low-thermal-resistance. Aspects of the invention can include a plurality of small semiconductor chips of one and the same kind formed by use of an SiC substrate, which is a wide gap substrate are sandwiched between two conductive plates. In this manner, there can be provided a high-reliability semiconductor unit in which parallel operation of the semiconductor chips is uniformized so that breakdown caused by current concentration can be prevented. | 03-06-2014 |
20140061674 | SiC SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In some aspects of the invention, a layer containing titanium and nickel is formed on an SiC substrate. A nickel silicide layer containing titanium carbide can be formed by heating. A carbon layer precipitated is removed by reverse sputtering. Thus, separation of an electrode of a metal layer formed on nickel silicide in a subsequent step is suppressed. The effect of preventing the separation can be further improved when the relation between the amount of precipitated carbon and the amount of carbon in titanium carbide in the surface of nickel silicide from which the carbon layer has not yet been removed satisfies a predetermined condition. | 03-06-2014 |
20140061675 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device that is able to increase the gate reliability, and to provide a method for manufacturing the silicon carbide semiconductor device, and that includes: a source electrode selectively formed on a source region; a gate insulating film formed so as to extend over the source region; and a gate electrode formed on the gate insulating film. The source region includes a first source region located below the source electrode, and a second source region surrounding the first source region. The doping concentration in a superficial layer of the second source region is lower than the doping concentration in a superficial layer of the first source region. The doping concentration in the second source region is higher in a deep portion than in a superficial portion thereof. | 03-06-2014 |
20140070229 | SYSTEMS AND METHODS FOR TERMINATING JUNCTIONS IN WIDE BANDGAP SEMICONDUCTOR DEVICES - An electrical device includes a blocking layer disposed on top of a substrate layer, wherein the blocking layer and the substrate layer each are wide bandgap semiconductors, and the blocking layer and the substrate layer form a buried junction in the electrical device. The device comprises a termination feature disposed at a surface of the blocking layer and a filled trench disposed proximate to the termination feature. The filled trench extends through the blocking layer to reach the substrate layer and is configured to direct an electrical potential associated with the buried junction toward the termination feature disposed near the surface of the blocking layer to terminate the buried junction. | 03-13-2014 |
20140070230 | USING A CARBON VACANCY REDUCTION MATERIAL TO INCREASE AVERAGE CARRIER LIFETIME IN A SILICON CARBIDE SEMICONDUCTOR DEVICE - A semiconductor die and a process for fabricating the semiconductor die are disclosed. The semiconductor die has a substrate and a silicon carbide (SiC) epitaxial structure on the substrate. The SiC epitaxial structure includes at least a first N-type SiC layer, at least a first P-type SiC layer, and carbon vacancy reduction material, which has been implanted into a surface of the SiC epitaxial structure. Further, the SiC epitaxial structure has been annealed to mobilize the carbon vacancy reduction material to diffuse carbon atoms substantially throughout the SiC epitaxial structure, thereby increasing an average carrier lifetime in the SiC epitaxial structure. | 03-13-2014 |
20140070231 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME - A semiconductor device is provided. The semiconductor device includes an avalanche photodiode unit and a thyristor unit. The avalanche photodiode unit is configured to receive incident light to generate a trigger current and comprises a wide band-gap semiconductor. The thyristor unit is configured to be activated by the trigger current to an electrically conductive state. A semiconductor device and a method for making a semiconductor device are also presented. | 03-13-2014 |
20140070232 | Method for Manufacturing a Composite Wafer Having a Graphite Core, and Composite Wafer Having a Graphite Core - A composite wafer including a carrier substrate having a graphite core and a monocrystalline semiconductor substrate or layer attached to the carrier substrate and a corresponding method for manufacturing such a composite wafer is provided. | 03-13-2014 |
20140070233 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A gate insulating film is provided on a trench. The gate insulating film has a trench insulating film and a bottom insulating film. The trench insulating film covers each of a side wall and a bottom portion. The bottom insulating film is provided on the bottom portion with a trench insulating film being interposed therebetween. The bottom insulating film has a carbon atom concentration lower than that of the trench insulating film. The gate electrode is in contact with a portion of the trench insulating film on the side wall. Accordingly, a low threshold voltage and a large breakdown voltage can be attained. | 03-13-2014 |
20140070234 | HIGH VOLTAGE POWER SEMICONDUCTOR DEVICES ON SIC - 4H SiC epiwafers with thickness of 50-100 μm are grown on 4° off-axis substrates. Surface morphological defect density in the range of 2-6 cm | 03-13-2014 |
20140077224 | Pre-Cutting a Back Side of a Silicon Substrate for Growing Better III-V Group Compound Layer on a Front Side of the Substrate - The present disclosure involves an apparatus. The apparatus includes a substrate having a front side a back side opposite the front side. The substrate includes a plurality of openings formed from the back side of the substrate. The openings collectively define a pattern on the back side of the substrate from a planar view. In some embodiments, the substrate is a silicon substrate or a silicon carbide substrate. Portions of the silicon substrate vertically aligned with the openings have vertical dimensions that vary from about 100 microns to about 300 microns. A III-V group compound layer is formed over the front side of the silicon substrate. The III-V group compound layer is a component of one of: a light-emitting diode (LED), a laser diode (LD), and a high-electron mobility transistor (HEMT). | 03-20-2014 |
20140077225 | SCHOTTKY BARRIER DIODE AND METHOD OF MANUFACTURING THE SAME - A schottky barrier diode may include a first n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate, a first p+ region disposed in the first n− type epitaxial layer, a second n type epitaxial layer disposed on the first n− type epitaxial layer and the first p+ region, a second p+ region disposed in the second n type epitaxial layer, a schottky electrode disposed on the second n type epitaxial layer and the second p+ region, and an ohmic electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein the first p+ region and the second p+ region may be in contact with each other. | 03-20-2014 |
20140077226 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device of the present invention comprises a silicon carbide drift layer formed on a silicon carbide substrate, a P-type region formed in a surface layer of the silicon carbide drift layer, and a Schottky electrode formed above the silicon carbide drift layer correspondingly to a forming portion of the P-type region. The P-type region is formed of a plurality of unit cells arranged therein. Each of the unit cells has at least a first distribution region in which the P-type impurity is distributed at first concentration and a second distribution region in which the P-type impurity is distributed at second concentration higher than the first concentration. With this structure, it is possible to provide a silicon carbide semiconductor device in which a sufficient breakdown voltage can be achieved with less number of ion implantations. | 03-20-2014 |
20140077227 | Semiconductor Devices Including Polar Insulation Layer Capped By Non-Polar Insulation Layer - Illustrative embodiments of semiconductor devices including a polar insulation layer capped by a non-polar insulation layer, and methods of fabrication of such semiconductor devices, are disclosed. In at least one illustrative embodiment, a semiconductor device may comprise a semiconductor substrate, a polar insulation layer disposed on the semiconductor substrate and comprising a Group V element configured to increase a carrier mobility in at least a portion of the semiconductor substrate, and a non-polar insulation layer disposed above the polar insulation layer. | 03-20-2014 |
20140077228 | JUNCTION BARRIER SCHOTTKY DIODES WITH CURRENT SURGE CAPABILITY - An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing. | 03-20-2014 |
20140077229 | SEMICONDUCTOR STRUCTURE - A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures. | 03-20-2014 |
20140077230 | DEVICE LAYOUT FOR REFERENCE AND SENSOR CIRCUITS - A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction. | 03-20-2014 |
20140077231 | DIAMOND SENSORS, DETECTORS, AND QUANTUM DEVICES - A thin plate of synthetic single crystal diamond material, the thin plate of synthetic single crystal diamond material having: a thickness in a range 100 nm to 50 μιη; a concentration of quantum spin defects greater than 0.1 ppb (parts-per-billion); a concentration of point defects other than the quantum spin defects of below 200 ppm (parts-per-million); and wherein at least one major face of the thin plate of synthetic single crystal diamond material comprises surface termination species which have zero nuclear spin and/or zero electron spin. | 03-20-2014 |
20140077232 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains. | 03-20-2014 |
20140084301 | LATERAL SILICON-ON-INSULATOR BIPOLAR JUNCTION TRANSISTOR RADIATION DOSIMETER - A radiation dosimeter includes a semiconductor substrate and a buried insulator layer disposed on the semiconductor substrate. The buried insulator layer has a plurality of charge traps. A semiconductor layer is disposed on the buried insulator layer. The semiconductor layer has an emitter, an intrinsic base, and a collector laterally arranged with respect to one another. In response to radiation exposure by the radiation dosimeter, positive charges are trapped in the plurality of charge traps in the buried insulator layer, the amount of positive charge trapped being used to determine the amount of radiation exposure. A method for radiation dosimetry includes providing a radiation dosimeter, where the radiation dosimeter includes a lateral silicon-on-insulator bipolar junction transistor having a buried insulator layer; exposing the radiation dosimeter to ionizing radiation; determining a change in one of the collector current and current gain of the radiation dosimeter; and determining an amount of the radiation dose based on the change in one of the collector current and current gain. | 03-27-2014 |
20140084302 | INTEGRATED CIRCUIT, A CHIP PACKAGE AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT - An integrated circuit is provided, the integrated circuit including: a carrier including at least one electronic component and at least one contact area disposed on a first side of the carrier, wherein the at least one electronic component is electrically connected to the at least one contact area; an inorganic material layer wafer bonded to the first side of the carrier, wherein the carrier has a first coefficient of thermal expansion, and wherein the inorganic material layer has a second coefficient of thermal expansion, wherein the second coefficient of thermal expansion has a difference of less than 100% compared with the first coefficient of thermal expansion; and at least one contact via formed through the inorganic material layer, wherein the at least one contact via contacts the at least one contact area. | 03-27-2014 |
20140084303 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a structural body, an insulating film, and a control electrode. The structural body has a first surface, and includes a first semiconductor region including silicon carbide of a first conductivity type, a second semiconductor region including silicon carbide of a second conductivity type, and a third semiconductor region including silicon carbide of the first conductivity type. The structural body has a portion in which the first semiconductor region, the second semiconductor region, and the third semiconductor region are arranged in this order in a first direction along the first surface. The insulating film is provided on the first surface of the structural body. The control electrode is provided on the insulating film. The structural body has a buried region provided between the second semiconductor region and the first surface. The buried region is doped with a group V element. | 03-27-2014 |
20140084304 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a structure, an insulating film, a control electrode, first and second electrodes. The structure has a first surface, and includes a first, a second, and a third semiconductor region. The structure has a portion including the first, second, and third semiconductor regions arranged in a first direction along the first surface. The insulating film is provided on the first surface. The control electrode is provided on the insulating film. The first electrode is electrically connected to the third semiconductor region. The second electrode is electrically connected to the first semiconductor region. The insulating film includes a charge trap region. A bias voltage is applied to the first and second electrodes, and includes a shift voltage. The shift voltage shifts a reference potential of a voltage applied to the first and second electrodes by a certain voltage. | 03-27-2014 |
20140091324 | SWITCHING CIRCUIT AND SEMICONDUCTOR MODULE - A switching circuit includes: a first switching element (Q | 04-03-2014 |
20140091325 | SiC SINGLE CRYSTAL, PRODUCTION METHOD THEREFOR, SiC WAFER AND SEMICONDUCTOR DEVICE - When an SiC single crystal having a large diameter of a {0001} plane is produced by repeating a-plane growth, the a-plane growth of the SiC single crystal is carried out so that a ratio S | 04-03-2014 |
20140097447 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor device and method of manufacturing the semiconductor, including an n type buffer layer disposed on a first surface of an n+ type silicon carbide substrate, an n− type epitaxial layer disposed on the n type buffer layer, a first type of trench disposed on each side of a second type of trench, wherein the trenches are disposed in the n− type epitaxial layer, an n+ region disposed on the n− type epitaxial layer, a p+ region disposed in each first type of trench, a gate insulating layer disposed in the second trench, a gate material disposed on the gate insulating layer, an oxidation layer disposed on the gate material, a source electrode disposed on the n+ region, oxidation layer, and p+ region, and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate. | 04-10-2014 |
20140097448 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a drift layer including a trench formed on a semiconductor substrate. A well in the drift layer overlaps an edge of the trench, and at least one gate electrode is formed at this overlapping edge region. The drift layer and semiconductor may be doped with a first type of impurity and the well may be doped with a second type of impurity. Through this arrangement, an improved distribution of carriers may be formed in the drift layer. | 04-10-2014 |
20140097449 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress. | 04-10-2014 |
20140097450 | Diffused Junction Termination Structures for Silicon Carbide Devices - An electronic device includes a silicon carbide layer having a first conductivity type and a main junction adjacent a surface of the silicon carbide layer, and a junction termination region at the surface of the silicon carbide layer adjacent the main junction. Charge in the junction termination region decreases with lateral distance from the main junction, and a maximum charge in the junction termination region may be less than about 2×10 | 04-10-2014 |
20140103363 | USING STRESS REDUCTION BARRIER SUB-LAYERS IN A SEMICONDUCTOR DIE - A semiconductor die, which includes a substrate, a group of primary conduction sub-layers, and a group of separation sub-layers, is disclosed. The group of primary conduction sub-layers is over the substrate. Each adjacent pair of the group of primary conduction sub-layers is separated by at least one of the group of separation sub-layers. As a result, the group of separation sub-layers mitigates grain growth in the group of primary conduction sub-layers. | 04-17-2014 |
20140103364 | SWITCHING DEVICE - A switching device according to the present invention is a switching device for switching a load by on-off control of voltage, and includes an SiC semiconductor layer where a current path is formed by on-control of the voltage, a first electrode arranged to be in contact with the SiC semiconductor layer, and a second electrode arranged to be in contact with the SiC semiconductor layer for conducting with the first electrode due to the formation of the current path, while the first electrode has a variable resistance portion made of a material whose resistance value increases under a prescribed high-temperature condition for limiting current density of overcurrent to not more than a prescribed value when the overcurrent flows to the current path. | 04-17-2014 |
20140103365 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a substrate made of silicon carbide; an insulating film formed on a surface of the substrate; a buffer film containing no Al; and an electrode containing Al. The substrate has an electrically conductive region. In the semiconductor device, a contact hole is formed above the electrically conductive region so as to extend through the insulating film and expose the surface of the substrate. The buffer film extends upward on a side wall surface of the contact hole from a bottom surface of the contact hole. The electrode is formed in contact with the electrically conductive region on the bottom surface of the contact hole, and is formed on the insulating film with the buffer film being interposed therebetween. | 04-17-2014 |
20140103366 | SILICON DEVICE ON SI:C-OI AND SGOI AND METHOD OF MANUFACTURE - A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island. | 04-17-2014 |
20140110722 | Semiconductor Structure or Device Integrated with Diamond - Semiconductor devices that include a semiconductor structure integrated with one or more diamond material layers. A first diamond material layer is formed on a bottom surface and optionally, the side surfaces of the semiconductor structure. In some embodiments, at least a portion of the semiconductor structure is embedded in the diamond. An electrical device can be formed on a top surface of the semiconductor structure. A second diamond material layer can be formed on the top surface of the semiconductor structure. The semiconductor structure can include a III-nitride material such as GaN, which can be embedded within a the first diamond material layer or encased by the first and/or second diamond material layer. | 04-24-2014 |
20140110723 | SEMICONDUCTOR ELEMENT AND METHOD OF MANUFACTURING THEREOF - A semiconductor device disclosed in the present application includes: a semiconductor substrate; a first silicon carbide semiconductor layer located on a principal surface of the semiconductor substrate, the first silicon carbide semiconductor layer including a drift region of a first conductivity type, a body region of a second conductivity type, and an impurity region of a first conductivity type; a trench provided in the first silicon carbide semiconductor layer so as to reach inside of the drift region; a second silicon carbide semiconductor layer of the first conductivity type located at least on a side surface of the trench so as to be in contact with the impurity region and the drift region; a gate insulating film; a gate electrode; a first ohmic electrode; and a second ohmic electrode. The body region includes a first body region which is in contact with the second silicon carbide semiconductor layer on the side surface of the trench, and a second body region which is in contact with the drift region and has a smaller average impurity concentration than the first body region. | 04-24-2014 |
20140117379 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes sequentially forming an n− type epitaxial layer, a p type epitaxial layer, and a first n+ region on a first surface of an n+ type silicon carbide substrate, and forming a trench through the first n+ region and the p type epitaxial layer, wherein the forming of the trench includes forming a photosensitive layer pattern on the first n+ region, etching the first n+ region and the p type epitaxial layer by using the photosensitive layer pattern as a mask, forming a buffer layer by using amorphous carbon on the first n+ region after the photosensitive layer pattern is removed, forming a buffer layer pattern by etching the buffer layer, etching using the buffer layer pattern as the mask, isotropically etching to form a second portion of the trench, and removing the buffer layer pattern. | 05-01-2014 |
20140117380 | FLAT SIC SEMICONDUCTOR SUBSTRATE - Methods for manufacturing silicon carbide wafers having superior specifications for bow, warp, total thickness variation (TTV), local thickness variation (LTV), and site front side least squares focal plane range (SFQR). The resulting SiC wafer has a mirror-like surface that is fit for epitaxial deposition of SiC. The specifications for bow, warp, total thickness variation (TTV), local thickness variation (LTV), and site front side least squares focal plane range (SFQR) of the wafer are preserved following the addition of the epitaxy layer. | 05-01-2014 |
20140117381 | Epitaxial Wafer, Method for Fabricating the Same, and Semiconductor Device Including the Same - Disclosed is an epitaxial wafer including a substrate and an epitaxial structure disposed on the substrate, wherein the epitaxial structure is doped with an n-type or p-type dopant and has a doping uniformity of 10% or less. | 05-01-2014 |
20140117382 | Epitaxial Wafer, Method for Fabricating the Wafer, and Semiconductor Device Including the Wafer - Disclosed is an epitaxial wafer including a substrate, and an epitaxial structure disposed on the substrate, wherein the epitaxial structure includes a first epitaxial layer, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed between the first epitaxial layer and the second epitaxial layer, the third epitaxial layer having a first doping concentration around a first boundary adjacent to the first epitaxial layer and a second doping concentration different from the first doping concentration around a second boundary adjacent to the second epitaxial layer. | 05-01-2014 |
20140124792 | NI-RICH SCHOTTKY CONTACT - Embodiments of a Nickel-rich (Ni-rich) Schottky contact for a semiconductor device and a method of fabrication thereof are disclosed. Preferably, the semiconductor device is a radio frequency or power device such as, for example, a High Electron Mobility Transistor (HEMT), a Schottky diode, a Metal Semiconductor Field Effect Transistor (MESFET), or the like. In one embodiment, the semiconductor device includes a semiconductor body and a Ni-rich Schottky contact on a surface of the semiconductor body. The Ni-rich Schottky contact includes a multilayer Ni-rich contact metal stack. The semiconductor body is preferably formed in a Group III nitride material system (e.g., includes one or more Gallium Nitride (GaN) and/or Aluminum Gallium Nitride (AlGaN) layers). Because the Schottky contact is Ni-rich, leakage through the Schottky contact is substantially reduced. | 05-08-2014 |
20140124793 | SMOOTH DIAMOND SURFACES AND CMP METHOD FOR FORMING - A method of chemical mechanical polishing (CMP) a diamond containing surface includes providing a slurry including a plurality of particles, at least one oxidizer, and at least one acid, wherein the slurry has a pH≦3 or pH greater than 11. At least an outer surface of the plurality of particles is softer than the diamond surface or the particles are diamond particles averaging less than (<)2 μm in size. The diamond surface is pressed with respect to a polishing pad providing a Shore D Hardness less than 99 having the slurry in between while rotating the polishing pad relative to the diamond surface to form a smooth diamond surface having a root mean square (rms) surface roughness less than 15 nm. | 05-08-2014 |
20140124794 | FABRICATION OF REVERSE SHALLOW TRENCH ISOLATION STRUCTURES WITH SUPER-STEEP RETROGRADE WELLS - Generally, the present disclosure is directed to methods for forming reverse shallow trench isolation structures with super-steep retrograde wells for use with field effect transistor elements. One illustrative method disclosed herein includes performing a thermal oxidation process to form a layer of thermal oxide material on a semiconductor layer of a semiconductor substrate, and forming a plurality of openings in the layer of thermal oxide material to form a plurality of isolation regions from the layer of thermal oxide material, wherein each of the plurality of openings exposes a respective surface region of the semiconductor layer. | 05-08-2014 |
20140124795 | DOUBLE LAYERED TRANSPARENT CONDUCTIVE OXIDE FOR REDUCED SCHOTTKY BARRIER IN PHOTOVOLTAIC DEVICES - A device and method for fabricating a photovoltaic device includes forming a double layer transparent conductive oxide on a transparent substrate. The double layer transparent conductive oxide includes forming a doped electrode layer on the substrate, and forming a buffer layer on the doped electrode layer. The buffer layer includes an undoped or p-type doped intrinsic form of a same material as the doped electrode layer. A light-absorbing semiconductor structure includes a p-type semiconductor layer on the buffer layer, an intrinsic layer and an n-type semiconductor layer. | 05-08-2014 |
20140131735 | SOURCE AND DRAIN DOPING USING DOPED RAISED SOURCE AND DRAIN REGIONS - A method comprises providing a semiconductor structure comprising a substrate, an electrically insulating layer on the substrate and a semiconductor feature on the electrically insulating layer. A gate structure is formed on the semiconductor feature. An in situ doped semiconductor material is deposited on portions of the semiconductor feature adjacent the gate structure. Dopant is diffused from the in situ doped semiconductor material into the portions of the semiconductor feature adjacent the gate structure, the diffusion of the dopant into the portions of the semiconductor feature adjacent the gate structure forming doped source and drain regions in the semiconductor feature. | 05-15-2014 |
20140131736 | SEMICONDUCTOR DEVICE AND METHOD FOR GROWING SEMICONDUCTOR CRYSTAL - A semiconductor device according to the embodiment comprises a base substrate; patterns on the base substrate; and an epitaxial layer on the base substrate, wherein the epitaxial layer is formed on a surface of the substrate exposed among the patterns. A method for growing a semiconductor crystal comprises the steps of cleaning a silicon carbide substrate; forming patterns on the silicon carbide substrate; and forming an epitaxial layer on the silicon carbide substrate. | 05-15-2014 |
20140131737 | LIGHT-EMITTING ELEMENT - A light-emitting element, a light-emitting element unit and a light-emitting element package are provided, which are each reduced in reflection loss and intra-film light absorption by suppressing multiple light reflection in a transparent electrode layer and hence have higher luminance. The light-emitting element | 05-15-2014 |
20140131738 | SEMICONDUCTOR DEVICE - A semiconductor device capable of decreasing a reverse leakage current and a forward voltage is provided. In the semiconductor device, an anode electrode undergoes Schottky junction by being connected to a surface of an SiC epitaxial layer that has the surface, a back surface, and trapezoidal trenches formed on the side of the surface each having side walls and a bottom wall. Furthermore, an edge portion of the bottom wall of each of the trapezoidal trenches is formed to be in the shape bent towards the outside of the trapezoidal trench in the manner that a radius of curvature R satisfies 0.01 L05-15-2014 | |
20140138705 | SUPER SURGE DIODES - The present disclosure relates to a semiconductor device having a Schottky contact that provides both super surge capability and low reverse-bias leakage current. In one preferred embodiment, the semiconductor device is a Schottky diode and even more preferably a Silicon Carbide (SiC) Schottky diode. However, the semiconductor device may more generally be any type of semiconductor device having a Schottky contact such as, for example, a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). | 05-22-2014 |
20140138706 | ELECTRONIC CIRCUIT, PRODUCTION METHOD THEREOF, AND ELECTRONIC COMPONENT - An electronic circuit according to this invention includes a printed circuit board and an electronic component that is soldered onto the printed circuit board. The electronic component is a flat package including a die pad exposed to outside and external electrode terminals. A gap is provided between the printed circuit board and the electronic component. The printed circuit board is provided with a hole between the die pad and the external electrode terminals in planar view. The gap is filled with insulating resin at least partially between the die pad and the external electrode terminals. The insulating resin is injected through the hole. | 05-22-2014 |
20140138707 | POWER SEMICONDUCTOR MODULE - A power semiconductor module is provided which is capable of keeping low the degrees of increases in temperatures of wide bandgap semiconductor elements, reducing the degree of increase in chip's total surface area of the wide bandgap semiconductor elements, and being fabricated at low costs, when Si semiconductor elements and the wide bandgap semiconductor elements are placed within one and the same power semiconductor module. The Si semiconductor elements are placed in a central region of the power semiconductor module, and the wide bandgap semiconductor elements are placed on opposite sides relative to the central region or in edge regions surrounding the central region. | 05-22-2014 |
20140138708 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon carbide substrate, annealing the silicon carbide substrate and the silicon oxide film in gas containing hydrogen, and forming an aluminum oxynitride film on the silicon oxide film after the annealing of the silicon carbide substrate and the silicon oxide film. | 05-22-2014 |
20140138709 | SILICON CARBIDE SUBSTRATE - A first circular surface ( | 05-22-2014 |
20140138710 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor device includes a circuit substrate which is configured with an insulative substrate formed of a ceramic material and provided on its one surface with an electrode formed of a copper material, and a power semiconductor element bonded with the electrode using a sinterable silver-particle bonding material, wherein the electrode has a Vickers hardness of 70 HV or more in its portion from the bonding face with the power semiconductor element toward the insulative substrate to a depth of 50 μm, and has a Vickers hardness of 50 HV or less in its portion at the side toward the insulative substrate. | 05-22-2014 |
20140145206 | Semiconductor Device - A semiconductor device includes at least two device cells integrated in a semiconductor body. Each device cell includes a drift region, a source region, a drain region arranged between the source region and the drift region, a diode region, a pn junction between the diode region and the drift region, and a trench with a first sidewall, a second sidewall opposite the first sidewall, and a bottom. The body region adjoins the first sidewall, the diode region adjoins the second sidewall, and the pn junction adjoins the bottom of the trench. Each device cell further includes a gate electrode arranged in the trench and dielectrically insulated from the body region, the diode region and the drift region by a gate dielectric. The diode regions of the at least two device cells are distant in a lateral direction of the semiconductor body. | 05-29-2014 |
20140145207 | Schottky Barrier Diode and Fabricating Method Thereof - A Schottky barrier diode and fabricating method thereof are disclosed. A semiconductor substrate may have a first surface and a second surface positioned oppositely to be provided. Several trenches are formed on the first surface. Each trench has a sidewall with a first depth and a first bottom surface. An insulating material is formed on the first surface of the semiconductor substrate and on the sidewall and the first bottom surface of each trench, wherein the insulating material has a first thickness on the sidewall. The insulating material on the sidewall is patterned to define a second bottom surface having a second depth smaller than the first depth, and the removed portion of the insulating material on the sidewall has a second thickness smaller than the first thickness. Afterward, a contact metal layer is at least formed on the first surface between adjacent trenches. | 05-29-2014 |
20140145208 | CASCODED SEMICONDUCTOR DEVICES - A cascoded power semiconductor circuit has a clamp circuit between the source and gate of a gallium nitride or silicon carbide FET to provide avalanche protection for the cascode MOSFET transistor. | 05-29-2014 |
20140145209 | WIDE BAND GAP SEMICONDUCTOR DEVICE - A semiconductor device comprises an n+ type SiC semiconductor substrate, an n type low concentration drift layer of an SiC semiconductor on the substrate, p type channel regions selectively arranged in the drift layer with a specified distance between the channel regions, an n type source region selectively arranged in the channel region, a source electrode in common contact with the source region and the channel region, and a gate electrode disposed over the drift layer between two channel regions, and over a part of the channel region positioned between the drift layer and the source region intercalating a gate oxide film therebetween. The drift layer has a low concentration of at most 70% of the concentration that is required to exhibit a specified withstand voltage at a minimum ON resistance. | 05-29-2014 |
20140145210 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes: a first diamond semiconductor layer of a first conductivity type including a main surface having a first plane orientation; a trench structure formed in the first diamond semiconductor layer; a second diamond semiconductor layer formed on the first diamond semiconductor layer in the trench structure and having a lower dopant concentration than the first diamond semiconductor layer; a third diamond semiconductor layer of a second conductivity type formed on the second diamond semiconductor layer and having a higher dopant concentration than the second diamond semiconductor layer; a first electrode electrically connected to the first diamond semiconductor layer; and a second electrode electrically connected to the third diamond semiconductor layer. | 05-29-2014 |
20140145211 | PROTECTIVE INTERFACE IN SILICON CARBIDE SEMICONDUCTOR DEVICES - Methods, systems, and devices are disclosed for implementing high power circuits and semiconductor devices. In one aspect, a method for fabricating a silicon carbide (SiC) device includes forming a thin layer of a protection material over a SiC substrate, in which the protection material has a lattice constant that substantially matches a lattice constant of SiC and the thin layer has a thickness of less than a critical layer thickness for the protection material over SiC to form a uniform interface between the protection material and SiC, forming a layer of an insulator material over the thin layer of the protection material, and forming one or more transistor structures over the insulator material. | 05-29-2014 |
20140145212 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a silicon carbide semiconductor substrate, a transistor formed in a cell region of the semiconductor substrate, and a voltage-breakdown-resistant structure formed in a region which surrounds an outer periphery of the cell region. The semiconductor substrate includes a first conductivity type substrate, a first conductivity type drift layer on the first conductivity type substrate, a second conductivity type layer on the drift layer, and a first conductivity type layer on the second conductivity type layer. The voltage-breakdown-resistant structure includes a first recess which surrounds the outer periphery of the cell region and reaches the drift layer, a trench located at a side surface of the recess on an inner periphery of the recess, and a second conductivity type buried layer buried in the trench to provide the side surface of the first recess. | 05-29-2014 |
20140145213 | SCHOTTKY DIODE - The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer. | 05-29-2014 |
20140145214 | SIC EPITAXIAL WAFER AND METHOD FOR PRODUCING SAME, AND DEVICE FOR PRODUCING SIC EPITAXIAL WAFER - A SiC epitaxial wafer manufacturing method of the present invention includes: manufacturing a SiC epitaxial wafer including a SiC epitaxial layer on a surface of a SiC single crystal wafer while supplying a raw material gas into a chamber using a SIC epitaxial wafer manufacturing apparatus; and manufacturing a subsequent SiC epitaxial wafer after measuring a surface density of triangular defects originating from a material piece of an internal member of the chamber on the SiC epitaxial layer of the previously manufactured SiC epitaxial wafer. | 05-29-2014 |
20140151717 | Packaged Vertical Power Device Comprising Compressive Stress and Method of Making a Packaged Vertical Power Device - A packaged vertical semiconductive device including a compressive stress and a method of making such a packaged vertical semiconductive device are disclosed. In one embodiment an assembled device includes a carrier, a connection layer disposed on the carrier, the connection layer having a first height, and a chip disposed on the connection layer, the chip having a second height, wherein the second height is smaller than the first height. | 06-05-2014 |
20140151718 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to the present invention includes a die pad, a semiconductor element joined to an upper surface of the die pad, and a resin sheet making close contact with a lower surface of the die pad, wherein the semiconductor element is resin-sealed together with the die pad and the resin sheet, wherein a recess is formed in the lower surface of the die pad, and a part of the resin sheet is filled into the recess bring the resin sheet into close contact with the lower surface of the die pad including an inside of the recess. | 06-05-2014 |
20140151719 | SILICON CARBIDE SEMICONDUCTOR ELEMENT - This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface. | 06-05-2014 |
20140159052 | METHOD AND STRUCTURE FOR TRANSISTOR WITH REDUCED DRAIN-INDUCED BARRIER LOWERING AND ON RESISTANCE - Embodiments of the invention provide an improved method and structure for a transistor with reduced DIBL and R | 06-12-2014 |
20140159053 | SIC TRENCH GATE TRANSISTOR WITH SEGMENTED FIELD SHIELDING REGION AND METHOD OF FABRICATING THE SAME - A SiC trench gate transistor with segmented field shielding region is provided. A drain region of a first conductivity type is located in a substrate. A first drift layer of the first conductivity type is located on the substrate and a second drift layer of the first conductivity type is located on the first drift layer. A base region of a second conductivity type is located on the second drift layer. A gate trench is located between the adjacent base regions. A plurality of segmented field shielding regions of the second conductivity type is placed under a bottom of the gate trench and the space between segmented field shielding regions is the first drift region. A gate dielectric layer is located on a bottom and at a sidewall of the gate trench and a trench gate is formed in the gate trench. | 06-12-2014 |
20140159054 | POWER MODULE SEMICONDUCTOR DEVICE - There is provided a power module semiconductor device allowing reduction in size and weight of a thin type SiC power module. The power module semiconductor device ( | 06-12-2014 |
20140159055 | SUBSTRATES FOR SEMICONDUCTOR DEVICES - A method of manufacturing a composite substrate for a semiconductor device, the method comprising:
| 06-12-2014 |
20140159056 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is provided a silicon carbide semiconductor device having excellent electrical characteristics such as channel mobility, and a method for manufacturing the same. A semiconductor device includes a substrate made of silicon carbide and having an off-angle of greater than or equal to 50° and less than or equal to 65° with respect to a surface orientation of {0001}, a p-type layer serving as a semiconductor layer, and an oxide film serving as an insulating film. The p-type layer is formed on the substrate and is made of silicon carbide. The oxide film is formed to contact with a surface of the p-type layer. A maximum value of the concentration of nitrogen atoms in a region within 10 nm of an interface between the semiconductor layer and the insulating film (interface between a channel region and the oxide film) is greater than or equal to 1×10 | 06-12-2014 |
20140159057 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is provided a silicon carbide semiconductor device having excellent electrical characteristics such as channel mobility, and a method for manufacturing the same. A semiconductor device includes a substrate made of silicon carbide and having an off-angle of greater than or equal to 50° and less than or equal to 65° with respect to a surface orientation of {0001}, a p-type layer serving as a semiconductor layer, and an oxide film serving as an insulating film. The p-type layer is formed on the substrate and is made of silicon carbide. The oxide film is formed to contact with a surface of the p-type layer. A maximum value of the concentration of nitrogen atoms in a region within 10 nm of an interface between the semiconductor layer and the insulating film (interface between a channel region and the oxide film) is greater than or equal to 1×10 | 06-12-2014 |
20140159058 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SILICON CARBIDE SEMICONDUCTOR DEVICE - In a silicon carbide semiconductor device, a trench penetrates a source region and a first gate region and reaches a drift layer. On an inner wall of the trench, a channel layer of a first conductivity-type is formed by epitaxial growth. On the channel layer, a second gate region of a second conductivity-type is formed. A first depressed portion is formed at an end portion of the trench to a position deeper than a thickness of the source region so as to remove the source region at the end portion of the trench. A corner portion of the first depressed portion is covered by a second conductivity-type layer. | 06-12-2014 |
20140167068 | SYSTEMS AND METHODS FOR OHMIC CONTACTS IN SILICON CARBIDE DEVICES - A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device. | 06-19-2014 |
20140167069 | SYSTEMS AND METHODS FOR INTEGRATING BOOTSTRAP CIRCUIT ELEMENTS IN POWER TRANSISTORS AND OTHER DEVICES - Embodiments relate to bootstrap circuits integrated with at least one other device, such as a power transistor or other semiconductor device. In embodiments, the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap diode, or the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap transistor. The bootstrap capacitor comprises a semiconductor-based capacitor, as opposed to an electrolytic, ceramic or other capacitor, in embodiments. The integration of the bootstrap circuit with another circuit or device, such as a power transistor device in one embodiment, is at a silicon-level in embodiments, rather than as a module-like system-in-package of conventional approaches. In other words, the combination of the bootstrap circuit elements and power transistor or other device forms a system-on-silicon, or an integrated circuit, in embodiments, and additionally can be arranged in a single package. | 06-19-2014 |
20140167070 | ELECTRONIC CHIP AND METHOD OF FABRICATING THE SAME - Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer. | 06-19-2014 |
20140167071 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a plurality of n type pillar regions and an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; a p type epitaxial layer and an n+ region disposed on the plurality of n type pillar regions and the n− type epitaxial layer; a trench penetrating the n+ region and the p type epitaxial layer and disposed on the plurality of n type pillar regions and the n− type epitaxial layer; a gate insulating film disposed within the trench; a gate electrode disposed on the gate insulating film; an oxide film disposed on the gate electrode; a source electrode disposed on the p type epitaxial layer, the n+ region, and the oxide film; and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein each corner portion of the trench is in contact with a corresponding n type pillar region. | 06-19-2014 |
20140167072 | SCHOTTKY BARRIER DIODE AND METHOD OF MANUFACTURING THE SAME - A schottky barrier diode includes an n− type epitaxial layer disposed at a first surface of an n+ type silicon carbide substrate, a plurality of n type pillar areas disposed in the n− type epitaxial layer at a first portion of a first surface of the n+ type silicon carbide substrate, a plurality of p+ areas disposed at a surface of the n− type epitaxial layer and separated from the n type pillar area, a schottky electrode disposed on the n− type epitaxial layer and the p+ area, and an ohmic electrode disposed at a second surface of the n+ type silicon carbide substrate. A doping density of the n type pillar area is larger than a doping density of the n− type epitaxial layer. | 06-19-2014 |
20140167073 | SILICON CARBIDE SEMICONDUCTOR DEVICES HAVING NITROGEN-DOPED INTERFACE - Methods, systems, and devices are disclosed for implementing high power circuits and semiconductor devices. In one aspect, a method for fabricating a silicon carbide semiconductor device includes forming a thin epitaxial layer of a nitrogen doped SiC material on a SiC epitaxial layer formed on a SiC substrate, and thermally growing an oxide layer to form an insulator material on the nitrogen doped SiC epitaxial layer, in which the thermally grown oxide layer results in at least partially consuming the nitrogen doped SiC epitaxial layer in the oxide layer to produce an interface including nitrogen between the SiC epitaxial layer and the oxide layer. | 06-19-2014 |
20140175457 | SIC-BASED TRENCH-TYPE SCHOTTKY DEVICE - A SiC-based trench-type Schottky device is disclosed. The device includes: a SiC substrate having first and second surfaces; a first contact metal formed on the second surface and configured for forming an ohmic contact on the substrate; a drift layer formed on the first surface and including a cell region and a termination region enclosing the cell region; a plurality of first trenches with a first depth formed in the cell region; a plurality of second trenches with a second depth less than the first depth; a plurality of mesas formed in the substrate, each defined between neighboring ones of the trenches; an insulating layer formed on sidewalls and bottoms of the trenches; and a second contact metal formed on the mesas and the insulating layer, extending from the cell region to the termination region, and configured for forming a Schottky contact on the mesas of the substrate. | 06-26-2014 |
20140175458 | GRAPHENE STRUCTURE, GRAPHENE DEVICE INCLUDING SAME, AND METHOD OF MANUFACTURING GRAPHENE STRUCTURE - A method of manufacturing a graphene structure, the graphene structure, and a graphene device including the graphene structure, include depositing a metal layer over a silicon carbide substrate; and performing, at a first temperature, a heat treatment on the silicon carbide substrate over which the metal layer is deposited to form a composite layer and a graphene layer on the silicon carbide substrate. The composite layer includes a metal. | 06-26-2014 |
20140175459 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A SiC semiconductor device includes: a semiconductor switching element having: a substrate, a drift layer and a base region stacked in this order; a source region and a contact region in the base region; a trench extending from a surface of the source region to penetrate the base region; a gate electrode on a gate insulating film in the trench; a source electrode electrically coupled with the source region and the base region; a drain electrode on a back side of the substrate; and multiple deep layers in an upper portion of the drift layer deeper than the trench. Each deep layer has upper and lower portions. A width of the upper portion is smaller than the lower portion. | 06-26-2014 |
20140175460 | SEMICONDUCTOR DEVICES WITH MINIMIZED CURRENT FLOW DIFFERENCES AND METHODS OF SAME - A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device. | 06-26-2014 |
20140175461 | SIC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SAME - Provided are a SiC epitaxial wafer in which the surface density of stacking faults is reduced, and a manufacturing method thereof. The method for manufacturing such a SiC epitaxial wafer comprises a step of determining a ratio of basal plane dislocations (BPD), which causes stacking faults in a SiC epitaxial film of a prescribed thickness which is formed on a SiC single crystal substrate having an off angle, to basal plane dislocations which are present on a growth surface of the SiC single crystal substrate, a step of determining an upper limit of surface density of basal plane dislocations on the growth surface of a SiC single crystal substrate used based on the above ratio, and a step of preparing a SiC single crystal substrate which has surface density equal to or less than the above upper limit, and forming a SiC epitaxial film on the SiC single crystal substrate under the same conditions as the growth conditions of the epitaxial film used in the step of determining the ratio. | 06-26-2014 |
20140183551 | BLANKET EPI SUPER STEEP RETROGRADE WELL FORMATION WITHOUT Si RECESS - A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions. | 07-03-2014 |
20140183552 | TRANSISTOR STRUCTURES HAVING A DEEP RECESSED P+ JUNCTION AND METHODS FOR MAKING SAME - A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SIC) MOSFET device. | 07-03-2014 |
20140183553 | TRANSISTOR STRUCTURES HAVING REDUCED ELECTRICAL FIELD AT THE GATE OXIDE AND METHODS FOR MAKING SAME - A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide. | 07-03-2014 |
20140183554 | SCHOTTKY BARRIER DIODE AND METHOD OF MANUFACTURING THE SAME - A Schottky barrier diode includes: an n+ type silicon carbide substrate; an n− type epitaxial layer disposed on a first surface of the n+ type silicon carbide substrate and includes an electrode area and a terminal area positioned outside of the electrode area; a first trench and a second trench disposed on the n− type epitaxial layer in the terminal area; a p area disposed under the first trench and the second trench; a Schottky electrode disposed on the n− type epitaxial layer in the electrode area; and an ohmic electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein the first trench and the second trench are adjacently positioned to form a step. | 07-03-2014 |
20140183555 | ELECTRONIC COMPONENT - According to one embodiment, an electronic component includes a device having a plurality of electrodes; a lead electrically connected to each of the plurality of electrodes; a first resin body sealing the device and a portion of the lead; and a first conductive body connected to the leads and contactable with a second conductive body. | 07-03-2014 |
20140183556 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present inventive concept has been made in an effort to increase the width of a channel in a silicon carbide MOSFET using a trench gate. | 07-03-2014 |
20140183557 | SEMICONDUCTOR DEVICE STRUCTURE FOR OHMIC CONTACT AND METHOD FOR FABRICATING THE SAME - A semiconductor device structure for an ohmic contact is provided, including a silicon carbide substrate and an ohmic contact layer disposed on the silicon carbide substrate. A carbon layer is disposed on the ohmic contact layer. An anti-diffusion layer is disposed on the carbon layer, and a pad layer is disposed on the anti-diffusion layer. The anti-diffusion layer is made of any one of tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). | 07-03-2014 |
20140183558 | SCHOTTKY BARRIER DIODE AND METHOD OF MANUFACTURING THE SAME - A schottky barrier diode includes: an n− type epitaxial layer that is disposed at a first surface of an n+ type silicon carbide substrate; a plurality of n type pillar areas that are disposed at the inside of the n− type epitaxial layer and that are disposed at a first portion of the first surface of the n+ type silicon carbide substrate; a p type area that is disposed at the inside of the n− type epitaxial layer and that is extended in a direction perpendicular to the n type pillar areas; a plurality of p+ areas in which the n− type epitaxial layer is disposed at a surface thereof and that are separated from the n type pillar areas and the p type area; a schottky electrode that is disposed on the n− type epitaxial layer and the p+ areas; and an ohmic electrode that is disposed at a second surface of the n+ type silicon carbide substrate. | 07-03-2014 |
20140183559 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present inventive concept has been made in an effort to improve the breakdown voltage of a silicon carbide MOSFET using a trench gate. | 07-03-2014 |
20140183560 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an n+ type silicon carbide substrate; a plurality of n type pillar regions, a plurality of p type pillar regions, and an n− type epitaxial layer disposed on a first surface of the n+ type silicon carbide substrate; a p type epitaxial layer and an n+ region sequentially disposed on the n− type epitaxial layer; a trench penetrating the n+ region and the p type epitaxial layer and disposed on the n− type epitaxial layer; a gate insulating film disposed within the trench; a gate electrode disposed on the gate insulating film; an oxide film disposed on the gate electrode; a source electrode disposed on the p type epitaxial layer, the n+ region, and the oxide film; and a drain electrode positioned on a second surface of the n+ type silicon carbide substrate. | 07-03-2014 |
20140183561 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first semiconductor part and a conductive electrode. The first semiconductor part is made of SiC. The SiC contains a first element as an n-type or p-type impurity. The first semiconductor part has a first interface part. The first interface part is configured to have maximum area density of the first element. The c conductive electrode is electrically connected to the first interface part. | 07-03-2014 |
20140183562 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor layer | 07-03-2014 |
20140183563 | NITRIDE SEMICONDUCTOR DEVICE WITH LIMITED INSTANTANEOUS CURRENT REDUCTION - A GaN device suppressing the instantaneous current reduction after the shut-off of a high frequency signal is disclosed. The GaN device provides, on a SiC substrate, an AlN layer, a GaN layer, and an AlGaN layer. The SiC substrate has an energy difference greater than 0.67 eV but less than 1.43 eV; the AlN layer has a thickness less than 50 nm; and the GaN layer has a thickness less than 1.5 μm, | 07-03-2014 |
20140191247 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a gate electrode, a first semiconductor region, a second semiconductor region of a first conductivity type, a third semiconductor region of a second conductivity type and a fourth semiconductor region of the first conductivity type. The first semiconductor region includes a silicon carbide crystal of 4H—SiC. The second semiconductor region includes a first portion opposing the gate electrode and is provided between the gate electrode and the first semiconductor region. The third semiconductor region has a lattice spacing different from a lattice spacing of the silicon carbide crystal of 4H—SiC and is provided between the gate electrode and the second semiconductor region. The fourth semiconductor region is selectively provided on the third semiconductor region. | 07-10-2014 |
20140191248 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate that has an element region and a peripheral region that surrounds the element region; and a gate pad that is disposed in an area that is on a surface side of the semiconductor substrate. The element region is formed with an insulated gate semiconductor element that has a gate electrode. The peripheral region is formed with a first withstand voltage retaining structure that surrounds the element region and a second withstand voltage retaining structure that is located in a position on the first withstand voltage retaining structure side from an outer edge of the element region and on the element region side from a boundary of the first withstand voltage retaining structure on the element region side. The gate pad is electrically connected to the gate electrode and is disposed in an area in which the second withstand voltage retaining structure is formed. | 07-10-2014 |
20140191249 | ACTIVE LED MODULE WITH LED AND TRANSISTOR FORMED ON SAME SUBSTRATE - An LED module is disclosed containing an integrated driver transistor (e.g, a MOSFET) in series with an LED. In one embodiment, LED layers are grown over a substrate. The transistor regions are formed over the same substrate. After the LED layers, such as GaN layers, are grown to form the LED portion, a central area of the LED is etched away to expose a semiconductor surface in which the transistor regions are formed. A conductor connects the transistor in series with the LED. Another node of the transistor is electrically coupled to an electrode on the bottom surface of the substrate. In one embodiment, an anode of the LED is connected to one terminal of the module, one current carrying node of the transistor is connected to a second terminal of the module, and the control terminal of the transistor is connected to a third terminal of the module. | 07-10-2014 |
20140191250 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is carried out by readying each of a semiconductor element, a substrate having Cu as a principal element at least on a surface, and a ZnAl solder chip having a smaller shape than that of the semiconductor element; disposing the semiconductor element and the substrate so that respective bonding surfaces face each other, and sandwiching the ZnAl eutectic solder chip between the substrate and the semiconductor element; increasing the temperature of the ZnAl solder chip sandwiched between the substrate and the semiconductor element while applying a load to the ZnAl solder chip such that the ZnAl solder chip melts to form a ZnAl solder layer; and reducing the temperature of the ZnAl solder layer while applying a load to the ZnAl solder layer. | 07-10-2014 |
20140191251 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - It is expected that both reduction of the resistance of a source region and reduction of a leakage current in a gate oxide film be achieved in an MOSFET in a silicon carbide semiconductor device. A leakage current to occur in a gate oxide film of the MOSFET is suppressed by reducing roughness at an interface between a source region and the gate oxide film. If an impurity concentration is to become high at a surface portion of the source region, the gate oxide film is formed by dry oxidation or CVD process. If the gate oxide film is formed by wet oxidation, the impurity concentration at the surface portion of the source region is controlled at a low level. | 07-10-2014 |
20140197422 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a silicon carbide substrate. The silicon carbide substrate is composed of an element region provided with a semiconductor element portion and a termination region surrounding the element region as viewed in a plan view. The semiconductor element portion includes a drift region having a first conductivity type. The termination region includes a first electric field relaxing region contacting the element region and having a second conductivity type different from the first conductivity type, and a second electric field relaxing region arranged outside the first electric field relaxing region as viewed in the plan view, having the second conductivity type, and spaced from the first electric field relaxing region. A ratio calculated by dividing a width of the first electric field relaxing region by a thickness of the drift region is not less than 0.5 and not more than 1.83. | 07-17-2014 |
20140203297 | Method of Manufacturing Substrates Having Improved Carrier Lifetimes - This invention relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a chlorosilane gas, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C. but less than 2000° C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr. This invention also relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a non-chlorinated silicon-containing gas, hydrogen chloride, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C. but less than 2000° C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr. | 07-24-2014 |
20140203298 | STRAINED SILICON CARBIDE CHANNEL FOR ELECTRON MOBILITY OF NMOS - A semiconductor is formed on a (110) silicon (Si) substrate, with improved electron mobility. Embodiments include semiconductor devices having a silicon carbide (SiC) portion in the nFET channel region. An embodiment includes forming an nFET channel region and a pFET channel region in a Si substrate, such as a (110) Si substrate, and forming a silicon carbide (SiC) portion on the nFET channel region. The SiC portion may be formed by ion implantation of C followed by a recrystallization anneal or by epitaxial growth of SiC in a recess formed in the substrate. The use of SiC in the nFET channel region improves electron mobility without introducing topographical differences between NMOS and PMOS transistors. | 07-24-2014 |
20140203299 | SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage V | 07-24-2014 |
20140203300 | SiC SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF - Provided are a technology that simply forms a particular crystal surface such as a {03-38} surface having high carrier mobility in trench sidewalls and a SiC semiconductor element where most of the trench sidewalls appropriate for a channel member are formed from {03-38} surfaces. A trench structure formed in a (0001) surface or an off-oriented surface of a (0001) surface with an offset angle 8° or lower of SiC is provided. The channel member is in the trench structure. At least 90% of the area of the channel member is a {03-38} surface or a surface that a {03-38} surface offset by an angle from −8° to 8° in the <1-100> direction. Specifically, the trench sidewalls are finished to {03-38} surfaces by applying a thermal etching to a trench with (0001) surfaces of SiC. Thermal etching is conducted in a chlorine atmosphere above 800° C. with nitrogen gas as the carrier. | 07-24-2014 |
20140209926 | SEMICONDUCTOR INTEGRATED CIRCUIT - A compound semiconductor integrated circuit chip has a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extend over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other. | 07-31-2014 |
20140209927 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME AND SEMICONDUCTOR SUBSTRATE - According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type made of silicon carbide; and a second semiconductor layer of a second conductivity type made of silicon carbide, placed in junction with the first semiconductor layer, and containing an electrically inactive element. | 07-31-2014 |
20140217421 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a semiconductor structure comprising a substrate, a gate stack, a sidewall, a base region, source/drain regions, and a support structure, wherein: the base region is located above the substrate, and is separated from the substrate by the void; said support structure is located on both sides of the void, in which part of the support isolation structure is connected with the substrate; the gate stack is located above the base region, said sidewall surrounding the gate stack; said source/drain regions are located on both sides of the gate stack, the base region and the support isolation structure, in which the stress in the source/drain regions first gradually increases and then gradually decreases along the height direction from the bottom. The present invention also provides a manufacturing method for the semiconductor structure. The present invention is beneficial to suppress the short channel effect, as well as to provide an optimum stress to the channel. | 08-07-2014 |
20140217422 | FIELD EFFECT SILICON CARBIDE TRANSISTOR - In a SiC-MOSFET power device for which a SiC substrate is used, a laminated insulating film having a charge-trapping characteristic is employed as a gate insulating film of the SiC-DiMOSFET, and charges are injected into the laminated insulating film, thereby suppressing a change in the gate threshold voltage. | 08-07-2014 |
20140217423 | SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD FOR FORMING RECESSES OF THE SAME, AND LIGHT SOURCE APPARATUS USING THE SAME - A semiconductor light-emitting device made of a nitride-based semiconductor includes a semiconductor stacked structure having a nonpolar plane or a semipolar plane as a principal plane, and including an active layer for emitting polarized light. The semiconductor light-emitting device includes a striped structure which is provided in a position intersecting an exit path of the polarized light and includes a plurality of recesses. An angle formed between the extension direction of the recesses and the polarization direction of the polarized light is from 0° to 45°. The recesses have a minute uneven structure (texture) at at least part of a surface of each recess, the minute uneven structure being shallower than the depth of each recess. | 08-07-2014 |
20140217424 | SEMICONDUCTOR DEVICE, ELECTRO-OPTIC DEVICE, POWER CONVERSION DEVICE, AND ELECTRONIC APPARATUS - A semiconductor device includes a silicon substrate, a silicon carbide film formed on the silicon substrate, a mask member formed on a surface of the silicon carbide film, and having an opening section, single-crystal silicon carbide films each having grown epitaxially from the silicon carbide film exposed in the opening section as a base point, and covering the silicon carbide film and the mask member, and a semiconductor element formed on surfaces of the single-crystal silicon carbide films, an assembly section formed of the single-crystal silicon carbide films assembled to each other exists above the mask member, the semiconductor element has a body contact region, and the body contact region is disposed at a position overlapping the assembly section viewed from a direction perpendicular to the surface of the silicon substrate. | 08-07-2014 |
20140231825 | DIAMOND GaN DEVICES AND ASSOCIATED METHODS - Semiconductor devices and methods of making thereof are provided. In one aspect, for example, a method for making a semiconductor device can include polishing a working surface of a diamond layer to a substantially flat surface, depositing a buffer layer on the working surface of the diamond layer, and depositing a semiconductor layer on the buffer layer. In one specific aspect, the c-axis of the buffer layer is oriented perpendicular to the working surface of the diamond layer. | 08-21-2014 |
20140231826 | Methods of Growing a Silicon Carbide Epitaxial Layer on a Substrate to Increase and Control Carrier Lifetime - A method of growing an epitaxial layer on a substrate is generally provided. According to the method, the substrate is heated in a chemical vapor deposition chamber to a growth temperature in the presence of a carbon source gas, then the epitaxial layer is grown on the substrate at the growth temperature, and finally the substrate is cooled in a chemical vapor deposition chamber to at least about 80% of the growth temperature in the presence of a carbon source gas. Substrates formed from this method can have a carrier lifetime between about 0.25 μs and about 9.9 μs. | 08-21-2014 |
20140231827 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed. | 08-21-2014 |
20140231828 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first cell and a second cell. Each of the first cell and the second cell includes a first silicon carbide semiconductor layer including a first region and a second region provided in the first region, a second silicon carbide semiconductor layer provided on and in contact with the first silicon carbide semiconductor layer, a first ohmic electrode in ohmic contact with the second region, and an insulating film provided on the second silicon carbide semiconductor layer. The first cell includes a gate electrode, and the second cell includes no electrode configured to control the electric potential of the second silicon carbide semiconductor layer independently of the electric potential of the first ohmic electrode. | 08-21-2014 |
20140231829 | SEMICONDUCTOR DEVICE - Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP | 08-21-2014 |
20140231830 | CRYSTAL LAYERED STRUCTURE AND METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR ELEMENT - Provided is a crystal layered structure having a low dislocation density on the upper surface of a nitride semiconductor layer on a Ga | 08-21-2014 |
20140246680 | JFET Devices with Increased Barrier Height and Methods of Making Same - Devices for providing transistors with improved operating characteristics are provided. In one example, a system includes a processor and a memory device. A transistor of the processor or the memory device includes a channel in a semiconductor substrate that is undoped or intrinsic. A metal gate is disposed directly on top of the channel, and the bandgap of the semiconductor substrate and the work function of the metal form a Schottky barrier. | 09-04-2014 |
20140246681 | HIGH CURRENT, LOW SWITCHING LOSS SiC POWER MODULE - A power module includes a housing with an interior chamber and multiple switch modules mounted within the interior chamber of the housing. The switch modules are interconnected and configured to facilitate switching power to a load. Each one of the switch modules includes at least one transistor and at least one diode. The at least one transistor and the at least one diode may be formed from a wide band-gap material system, such as silicon carbide (SiC), thereby allowing the power module to operate at high frequencies with lower switching losses when compared to conventional power modules. | 09-04-2014 |
20140246682 | SEMICONDUCTOR ELEMENT - In a semiconductor element, a body region of a second conductivity type includes a first body region in contact with a surface of a first silicon carbide semiconductor layer, and a second body region in contact with a bottom surface of the body region of the second conductivity type. The impurity concentration of the first body region is twice or more the impurity concentration of the second body region. A second silicon carbide semiconductor layer of a first conductivity type, which is a channel layer, has an impurity concentration distribution in a direction perpendicular to a semiconductor substrate, and an impurity concentration on a side in contact with the gate insulating film is lower than an impurity concentration on a side in contact with the first body region. | 09-04-2014 |
20140252373 | Semiconductor Device and Method for Producing the Same - A method for producing a semiconductor device is provided. The method includes providing a semiconductor substrate, providing at least one semiconductor device on the substrate, having a back face opposite the semiconductor substrate and a front face towards the semiconductor substrate, providing a contact layer on the back face of the semiconductor device, bonding the contact layer to an auxiliary carrier, and separating the at least one semiconductor device from the substrate. Further, a semiconductor device produced according to the method and an intermediate product are provided. | 09-11-2014 |
20140252374 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A first drift layer has a first surface facing a first electrode and electrically connected to a first electrode, and a second surface opposite to the first surface. The first drift layer has an impurity concentration N | 09-11-2014 |
20140252375 | Delamination and Crack Prevention in III-Nitride Wafers - In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches. | 09-11-2014 |
20140252376 | SILICON CARBIDE SUBSTRATE, METHOD FOR MANUFACTURING SAME AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide substrate includes the following steps. A silicon carbide single-crystal substrate is prepared. A silicon carbide epitaxial layer is formed in contact with the silicon carbide single-crystal substrate. A silicon layer is formed in contact with a second surface of the silicon carbide epitaxial layer opposite to a first surface thereof that makes contact with the silicon carbide single-crystal substrate. Accordingly, there are provided a silicon carbide substrate, a method for manufacturing the silicon carbide substrate, and a method for manufacturing a silicon carbide semiconductor device so as to achieve prevention of contamination of a silicon carbide epitaxial layer in a simple manner. | 09-11-2014 |
20140252377 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - The semiconductor device includes a SiC substrate; an aluminum nitride layer provided on the substrate and having an island-shaped pattern consisting of plural islands: a channel layer provided on the AlN layer and comprising a nitride semiconductor; an electron supplying layer provided on the channel layer and having a band gap larger than that of the channel layer; and a gate, source and drain electrodes on the electron supply layer. The AlN layer has an area-averaged circularity Y/X of greater than 0.2. Y is a sum of values obtained by multiplying circularities of the plural islands by areas of the plural islands respectively, X is a sum of the areas of the plural islands. The circularity are calculated by a formula of (4π×area)/(length of periphery) | 09-11-2014 |
20140252378 | SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor substrate includes a substrate and a semiconductor layer. The substrate has a first surface and containing a silicon carbide. The semiconductor layer is provided on the first surface. The semiconductor layer has a thickness of H centimeters in a perpendicular direction to the first surface. The semiconductor layer contains an epitaxially grown silicon carbide with an off angle θ provided relative to a (0001) face of the substrate. The semiconductor layer includes k pieces of basal plane dislocation per one square centimeter viewed in the perpendicular direction. When S=(½)×H | 09-11-2014 |
20140264374 | METHOD FOR MANUFACTURING A SILICON CARBIDE SUBSTRATE FOR AN ELECTRICAL SILICON CARBIDE DEVICE, A SILICON CARBIDE SUBSTRATE AND AN ELECTRICAL SILICON CARBIDE DEVICE - A method for manufacturing a silicon carbide substrate for an electrical silicon carbide device includes providing a silicon carbide dispenser wafer including a silicon face and a carbon face and depositing a silicon carbide epitaxial layer on the silicon face. Further, the method includes implanting ions with a predefined energy characteristic forming an implant zone within the epitaxial layer, so that the ions are implanted with an average depth within the epitaxial layer corresponding to a designated thickness of an epitaxial layer of the silicon carbide substrate to be manufactured. Furthermore, the method comprises bonding an acceptor wafer onto the epitaxial layer so that the epitaxial layer is arranged between the dispenser wafer and the acceptor wafer. Further, the epitaxial layer is split along the implant zone so that a silicon carbide substrate represented by the acceptor wafer with an epitaxial layer with the designated thickness is obtained. | 09-18-2014 |
20140264375 | LATTICE MISMATCHED HETEROJUNCTION STRUCTURES AND DEVICES MADE THEREFROM - Semiconductor heterojunction structures comprising lattice mismatched, single-crystalline semiconductor materials and methods of fabricating the heterojunction structures are provided. The heterojunction structures comprise at least one three-layer junction comprising two layers of single-crystalline semiconductor and a current tunneling layer sandwiched between and separating the two layers of single-crystalline semiconductor material. Also provided are devices incorporating the heterojunction structures, methods of making the devices and method of using the devices. | 09-18-2014 |
20140264376 | Power Switching Module with Reduced Oscillation and Method for Manufacturing a Power Switching Module Circuit - A power switching module includes a three-terminal power semiconductor device designed for a rated current and a freewheeling unit. The freewheeling unit includes a pn-diode integrated in a first semiconductor material having a first band-gap, and a Schottky-diode integrated in a second semiconductor material having a second band-gap that is larger than the first band-gap. The Schottky-diode is electrically connected in parallel to the pn-diode. | 09-18-2014 |
20140264377 | SOL-GEL PROCESS FOR THE MANUFACTURE OF HIGH POWER SWITCHES - According to one embodiment, a photoconductive semiconductor switch includes a structure of nanopowder of a high band gap material, where the nanopowder is optically transparent, and where the nanopowder has a physical characteristic of formation from a sol-gel process. According to another embodiment, a method includes mixing a sol-gel precursor compound, a hydroxy benzene and an aldehyde in a solvent thereby creating a mixture, causing the mixture to gel thereby forming a wet gel, drying the wet gel to form a nanopowder, and applying a thermal treatment to form a SiC nanopowder. | 09-18-2014 |
20140264378 | SEMICONDUCTOR STRUCTURE - A semiconductor structure has a MOSFET and a substrate to accommodate the MOSFET. The MOSFET has a gate, a source, and a drain in the substrate. A first substrate region surrounding the MOSFET is doped with a stress enhancer, wherein the stress enhancer is configured to generate a tensile stress in the MOSFET's channel and the tensile stress is along the channel's widthwise direction. | 09-18-2014 |
20140264379 | III-Nitride P-Channel Field Effect Transistor with Hole Carriers in the Channel - A non-inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a nitrogen-polar III-Nitride first material, a barrier material layer, a two-dimensional hole gas in the barrier layer, and wherein the nitrogen-polar III-Nitride material comprises one or more III-Nitride epitaxial material layers grown in such a manner that when GaN is epitaxially grown the top surface of the epitaxial layer is nitrogen-polar. A method of making a P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face or offcut orientation of a substrate so that the nitrogen-polar (001) face is the dominant face, growing a nucleation layer, growing a GaN epitaxial layer, doping the epitaxial layer, growing a barrier layer, etching the GaN, forming contacts, performing device isolation, defining a gate opening, depositing and defining gate metal, making a contact window, depositing and defining a thick metal. | 09-18-2014 |
20140264380 | Complementary Field Effect Transistors Using Gallium Polar and Nitrogen Polar III-Nitride Material - A device with N-Channel and P-Channel III-Nitride field effect transistors comprising a non-inverted P-channel III-Nitride field effect transistor on a first nitrogen-polar nitrogen face III-Nitride material, a non-inverted N-channel III-Nitride field effect transistor, epitaxially grown, a first III-Nitride barrier layer, two-dimensional hole gas, second III-Nitride barrier layer, and a two-dimensional hole gas. A method of making complementary non-inverted P-channel and non-inverted N-channel III-Nitride FET comprising growing epitaxial layers, depositing oxide, defining opening, growing epitaxially a first nitrogen-polar III-Nitride material, buffer, back barrier, channel, spacer, barrier, and cap layer, and carrier enhancement layer, depositing oxide, growing AlN nucleation layer/polarity inversion layer, growing gallium-polar III-Nitride, including epitaxial layers, depositing dielectric, fabricating P-channel III-Nitride FET, and fabricating N-channel III-Nitride FET. | 09-18-2014 |
20140264381 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED OHMIC CONTACTS - A method of fabricating a semiconductor device includes providing one or more semiconductor layers, providing a gate contact on a first surface of the one or more semiconductor layers, then using the gate contact as a mask to deposit a source contact and a drain contact on the first surface of the one or more semiconductor layers, such that the source contact and the drain contact include an interior edge that is laterally aligned with a different lateral edge of the gate contact. | 09-18-2014 |
20140264382 | SILICON CARBIDE SEMICONDUCTOR DEVICES - Methods, systems, and devices are disclosed for thermal processing of silicon carbide semiconductor devices. In one aspect, a method for fabricating a silicon carbide semiconductor device includes forming a thin epitaxial layer of a nitrogen and phosphorous co-doped SiC material on a SiC epitaxial layer formed on a SiC substrate, and thermally growing an oxide layer to form an insulator material on the nitrogen and phosphorous co-doped SiC epitaxial layer, in which the thermally growing the oxide layer results in at least partially consuming the nitrogen and phosphorous co-doped SiC epitaxial layer in the oxide layer to produce an interface including nitrogen and phosphorous between the SiC epitaxial layer and the oxide layer. | 09-18-2014 |
20140264383 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a die pad, an SiC chip mounted on the die pad, a porous first sintered Ag layer bonding the die pad and the SiC chip, and a reinforcing resin portion covering a surface of the first sintered Ag layer and formed in a fillet shape. The semiconductor device further includes a source lead electrically connected to a source electrode of the SiC chip, a gate lead electrically connected to a gate electrode, a drain lead electrically connected to a drain electrode, and a sealing body which covers the SiC chip, the first sintered Ag layer, and a part of the die pad, and the reinforcing resin portion covers a part of a side surface of the SiC chip. | 09-18-2014 |
20140264384 | SiC SUBSTRATE WITH SiC EPITAXIAL FILM - A method of forming an epitaxial SiC film on SiC substrates in a warm wall CVD system, wherein the susceptor is actively heated and the ceiling and sidewall are not actively heated, but are allowed to be indirectly heated by the susceptor. The method includes a first process of reaction cell preparation and a second process of epitaxial film growth. The epitaxial growth is performed by flowing parallel to the surface of the wafers a gas mixture of hydrogen, silicon and carbon gases, at total gas velocity in a range 120 to 250 cm/sec. | 09-18-2014 |
20140264385 | Manufacture of wafers of wide energy gap semiconductor material for the integration of electronic and/or optical and/or optoelectronic devices - A method is provided for fabricating a wafer of semiconductor material intended for use for the integration of electronic and/or optical and/or optoelectronic devices. The method comprises: providing a starting wafer of crystalline silicon ( | 09-18-2014 |
20140264386 | PERFORMANCE ENHANCEMENT IN PMOS AND NMOS TRANSISTORS ON THE BASIS OF SILICON/CARBON MATERIAL - A semiconductor device includes a first transistor having first drain and source regions and a first channel region and a second transistor having second drain and source regions and a second channel region. A first silicon/carbon alloy material is embedded in the first drain and source regions, the first silicon/carbon alloy material inducing a first strain component along a first channel length direction of the first channel region. A second silicon/carbon alloy material is embedded in the second drain and source regions, the second silicon/carbon alloy material inducing a second strain component along a second channel length direction of the second channel region, wherein the second strain component is of an opposite type of the first strain component. | 09-18-2014 |
20140264387 | FIN FIELD EFFECT TRANSISTORS HAVING A NITRIDE CONTAINING SPACER TO REDUCE LATERAL GROWTH OF EPITAXIALLY DEPOSITED SEMICONDUCTOR MATERIALS - A fin field effect transistor including a plurality of fin structures on a substrate, and a shared gate structure on a channel portion of the plurality of fin structures. The fin field effect transistor further includes an epitaxial semiconductor material having a first portion between adjacent fin structures in the plurality of fin structures and a second portion present on outermost sidewalls of end fin structures of the plurality of fin structures. The epitaxial semiconductor material provides a source region and at drain region to each fin structure of the plurality of fin structures. A nitride containing spacer is present on the outermost sidewalls of the second portion of the epitaxial semiconductor material. | 09-18-2014 |
20140284615 | METHOD FOR MANUFACTURING A SILICON CARBIDE DEVICE AND A SILICON CARBIDE DEVICE - A method for manufacturing a silicon carbide device includes providing a silicon carbide wafer and manufacturing a mask layer on top of the silicon carbide wafer. Further, the method includes structuring the mask layer at an edge of a silicon carbide device to be manufactured, so that the mask layer includes a bevel at the edge of the silicon carbide device to be manufactured. Additionally, the method includes etching the mask layer and the silicon carbide wafer by a mutual etching process, so that the bevel of the mask layer is reproduced at the edge of the silicon carbide device. | 09-25-2014 |
20140284616 | SELF-FORMATION OF HIGH-DENSITY ARRAYS OF NANOSTRUCTURES - A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer. | 09-25-2014 |
20140284617 | SEMICONDUCTOR DEVICE - According to embodiments, a semiconductor device includes an insulating substrate, a first electrode plate disposed on the insulating substrate, a second electrode plate disposed on the insulating substrate, a third electrode plate disposed on the insulating substrate, a first semiconductor element disposed on the first electrode plate, a first electrode of the first semiconductor element being electrically connected to the first electrode plate, a second semiconductor element disposed on the second electrode plate, a first electrode of the second semiconductor element being electrically connected to the second electrode plate, a first bonding wire electrically connecting a second electrode of the first semiconductor element to the third electrode plate, and a second bonding wire electrically connecting a second electrode of the second semiconductor element to the third electrode plate. | 09-25-2014 |
20140284618 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - An aspect of the present embodiment, there is provided a semiconductor device, including a first electrode, a first semiconductor layer having a first conductive type connected to the first electrode, a second semiconductor layer having a second conductive type contacted to the first semiconductor layer, a third semiconductor layer having the first conductive type, an impurity concentration of the third semiconductor layer being smaller than an impurity concentration of the second semiconductor layer, the third semiconductor layer contacting to the second semiconductor layer to be separated from the first semiconductor layer by the second semiconductor layer, a gate insulator provided on the second semiconductor layer, and the first semiconductor layer and the third semiconductor layer arranged at both sides of the second semiconductor layer, respectively, a gate electrode on the gate insulator; and a second electrode connected to the third semiconductor layer. | 09-25-2014 |
20140284619 | SIC EPITAXIAL WAFER AND SEMICONDUCTOR DEVICE - An SiC epitaxial wafer of an embodiment includes, an SiC substrate, and a p-type first SiC epitaxial layer that is formed on the SiC substrate and contains a p-type impurity and an n-type impurity. An element A and an element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus) when the p-type impurity is the element A and the n-type impurity is the element D. The ratio of the concentration of the element D to the concentration of the element A in the combination(s) is higher than 0.33 but lower than 1.0. | 09-25-2014 |
20140284620 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes an n-type SiC substrate, an n-type SiC layer formed on the SiC substrate; a p-type first SiC region formed in the surface of the SiC layer and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the concentration of the element A in the combination(s) being higher than 0.33 but lower than 0.995, the concentration of the element A forming part of the combination(s) being not lower than 1×10 | 09-25-2014 |
20140284621 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes an n-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element A to the concentration of the element D in the above combination is higher than 0.40 but lower than 0.95, and the concentration of the element D forming the above combination is not lower than 1×10 | 09-25-2014 |
20140284622 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes a p-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element D to the concentration of the element A in the above combination is higher than 0.33 but lower than 0.995, and the concentration of the element A forming part of the above combination is not lower than 1×10 | 09-25-2014 |
20140284623 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes, an n-type SiC substrate that has first and second faces, and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus), the ratio of the concentration of the element A to the concentration of the element D in the combination(s) being higher than 0.40 but lower than 0.95, the concentration of the element D forming the combination(s) being not lower than 1×10 | 09-25-2014 |
20140284624 | Semiconductor Component, Semiconductor Module and Methods for Producing a Semiconductor Component and a Semiconductor Module - A semiconductor component includes a semiconductor body having a top side and a bottom side opposite the top side. A top metallization is applied to the top side and a bottom metallization is applied to the bottom side. A moisture barrier completely seals the semiconductor body in cooperation with the top metallization and the bottom metallization. | 09-25-2014 |
20140284625 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n | 09-25-2014 |
20140284626 | ENHANCED DISLOCATION STRESS TRANSISTOR - A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation. | 09-25-2014 |
20140284627 | WAFER AND METHOD OF FABRICATING THE SAME - Disclosed is a method of manufacturing a thin film, the method including: growing an epitaxial layer on a surface of a wafer at a growth temperature, wherein the growing of the epitaxial layer comprises controlling a defect present on a surface of the wafer. Also, disclosed is a wafer including: a substrate; and an epitaxial layer located on the substrate, wherein a basal dislocation density of the epitaxial layer is equal to or less than 1/cm2. | 09-25-2014 |
20140284628 | WAFER AND METHOD OF FABRICATING THE SAME - Disclosed is a method of manufacturing a thin film, the method including: growing an epitaxial layer on a surface of a wafer at a growth pressure, wherein the growing of the epitaxial layer comprises controlling a defect present on a surface of the wafer. Also, disclosed is a wafer including: a substrate; and a buffer layer and an epitaxial layer located on the substrate, wherein a surface dislocation density of the epitaxial layer is equal to or less than 1/cm2. | 09-25-2014 |
20140291695 | Silicon Carbide Device and a Method for Manufacturing a Silicon Carbide Device - A silicon carbide device includes an epitaxial silicon carbide layer including a first conductivity type and a buried lateral silicon carbide edge termination region located within the epitaxial silicon carbide layer including a second conductivity type. The buried lateral silicon carbide edge termination region is covered by a silicon carbide surface layer including the first conductivity type. | 10-02-2014 |
20140291696 | POWER ELECTRONICS MODULES WITH SOLDER LAYERS HAVING REDUCED THERMAL STRESS - Power electronics modules having solder layers with reduced thermal-stress are disclosed. In one embodiment, a power electronics module includes a power electronics device having a first surface, a second surface, a first edge, and a second edge opposite the first edge. The power electronics device has a device length measured from the first edge to the second edge. A first solder layer is adjacent to the first surface of the power electronics device, and a second solder layer is adjacent to the second surface. The first solder layer and the second solder layer have a maximum thickness T along a length that is less than the device length of the power electronics device. A first thermally conductive layer is adjacent to the first solder layer, and a second thermally conductive layer is adjacent to the second solder layer. In some embodiments, the first and second solder layers have tapered portions. | 10-02-2014 |
20140291697 | SILICON CARBIDE DEVICE AND A METHOD FOR FORMING A SILICON CARBIDE DEVICE - A silicon carbide device includes a silicon carbide substrate, an inorganic passivation layer structure and a molding material layer. The inorganic passivation layer structure laterally covers at least partly a main surface of the silicon carbide substrate and the molding material layer is arranged adjacent to the inorganic passivation layer structure. | 10-02-2014 |
20140291698 | LOW MICROPIPE 100 MM SILICON CARBIDE WAFER - A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 100 mm and a micropipe density of less than about 25 cm | 10-02-2014 |
20140291699 | CERAMIC/COPPER CIRCUIT BOARD AND SEMICONDUCTOR DEVICE - A ceramic/copper circuit board of an embodiment includes a ceramic substrate and first and second copper plates bonded to surfaces of the ceramic substrate via bonding layers containing active metal elements. In cross sections of end portions of the first and second copper plates, a ratio (C/D) of an area C in relation to an area D is from 0.2 to 0.6. The area C is a cross section area of a portion protruded toward an outer side direction of the copper plate from a line AB, and the area D is a cross section area of a portion corresponding to a right-angled triangle whose hypotenuse is the line AB. R-shape sections are provided at edges of upper surfaces of the first and second copper plates, and lengths F of the R-shape sections are 100 μm or less. | 10-02-2014 |
20140291700 | SIC SINGLE CRYSTAL, SIC WAFER, AND SEMICONDUCTOR DEVICE - An SiC single crystal includes a low dislocation density region (A) where the density of dislocations each of which has a Burgers vector in a {0001} in-plane direction (mainly a direction parallel to a <11-20> direction) is not more than 3,700 cm/cm | 10-02-2014 |
20140291701 | SEMICONDUCTOR DEVICE - An object of the present invention is to provide a semiconductor device that allows the life of solder joint parts of electronic components to be increased. The semiconductor device according to the present invention includes ceramic, an upper pattern formed on the ceramic, and a resistor connected onto the upper pattern via solder. The upper pattern has a portion formed in a recess shape, the portion being connected to the resistor via the solder. | 10-02-2014 |
20140299886 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A silicon carbide semiconductor device includes: a semiconductor substrate made of silicon carbide single crystal and having a principal surface and a backside; and an ohmic electrode contacting one of the principal surface and the backside of the semiconductor substrate in an ohmic manner. A boundary between the ohmic electrode and the one of the principal surface and the backside of the semiconductor substrate is terminated with an element, which has a Pauling electronegativity larger than silicon and a binding energy with silicon larger than a binding energy of Si—H. | 10-09-2014 |
20140299887 | SEMICONDUCTOR DEVICES COMPRISING GETTER LAYERS AND METHODS OF MAKING AND USING THE SAME - Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. | 10-09-2014 |
20140299888 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer. | 10-09-2014 |
20140299889 | SEMICONDUCTOR DEVICES - A semiconductor device includes a first gate structure on a first region of a substrate and a second gate structure on a second region of the substrate, a first impurity region on an upper portion of the substrate adjacent to the first gate structure and a second impurity region on an upper portion of the substrate adjacent to the second gate structure, a first metal silicide layer on the first impurity region, a Fermi level pinning layer on the second impurity region, a second metal silicide layer on the Fermi level pinning layer, and a first contact plug on the first metal silicide layer and a second contact plug on the second metal silicide layer. The Fermi level pinning layer pins a Fermi level of the second metal silicide layer to a given energy level. | 10-09-2014 |
20140299890 | SEMICONDUCTOR DEVICES COMPRISING GETTER LAYERS AND METHODS OF MAKING AND USING THE SAME - Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. | 10-09-2014 |
20140299891 | SEMICONDUCTOR DEVICE - A semiconductor device that can improve reliability while suppressing increase of a conduction loss or a switching loss. In the semiconductor device, when a two-dimensional shape on a main surface of the semiconductor substrate is an unit cell, the shape being a repeating unit of a plurality of well regions periodically disposed in a surface layer of a drift layer, one unit cell and another unit cell adjacent in an x-axis direction are disposed misaligned in a y-axis direction, and one unit cell and another unit cell adjacent in the y-axis direction are disposed misaligned in the x-axis direction. | 10-09-2014 |
20140306239 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first conduction type semiconductor substrate, a first conduction type semiconductor deposition layer, a trench, second conduction type wells, a JFET region, a first conduction type first source region, a first source region, a trench-type source electrode, a gate insulator film, a gate electrode, and a drain electrode. The trench is formed substantially perpendicularly to the semiconductor deposition layer so that the semiconductor deposition layer exposes to a bottom of the trench. The second conduction type second source region are formed in the first conduction type first source region. The trench-type source electrode is in contact with the first source region, the second source region, and the first conduction type semiconductor deposition layer to configure a Schottky junction. | 10-16-2014 |
20140312360 | Semiconductor Power Device Having a Heat Sink - A semiconductor device includes an electrically conducting carrier having a mounting surface. The semiconductor device further includes a metal block having a first surface facing the electrically conducting carrier and a second surface facing away from the electrically conducting carrier. A semiconductor power chip is disposed over the second surface of the metal block. | 10-23-2014 |
20140312361 | SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT - The semiconductor element has an electrode including: a Ni-inclusion metal layer containing nickel formed on a side of at least one surface of the semiconductor-element constituting part; a Ni-barrier metal layer formed outwardly on a side of the Ni-inclusion metal layer opposite to the side toward the semiconductor-element constituting part; and a surface metal layer outwardly formed on a side of the Ni-barrier metal layer opposite to the side toward the semiconductor-element constituting part, to be connected to the metal nanoparticles sintered layer; wherein the Ni-barrier metal layer contains a metal for suppressing diffusion of nickel toward the surface metal layer. | 10-23-2014 |
20140312362 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: a substrate; a compound semiconductor stacked structure of nitride over the substrate; a passivation film that covers the compound semiconductor stacked structure; a gate electrode, a source electrode, and a drain electrode at a level above the compound semiconductor stacked structure; and an Si—C bond containing film that contains an Si—C bond and includes a part between the source electrode and the drain electrode. The part contacts at least a part of an upper surface of the compound semiconductor stacked structure or at least a part of an upper surface of the passivation film. | 10-23-2014 |
20140319538 | FORCE DETECTION DEVICE, AND FORCE TRANSDUCER DEVICE - A force detection device includes a diamond piezoresistor including a highly orientated diamond into which boron is introduced as an impurity. The absolute value of the piezoresistance coefficient of the diamond piezoresistor is greater than the absolute value of a piezoresistance coefficient π11 or π12 in a case in which a major axis is in the <100> direction. | 10-30-2014 |
20140319539 | SEMICONDUCTOR WAFER MANUFACTURING METHOD, AND SEMICONDUCTOR WAFER - A method for manufacturing a semiconductor wafer includes a carbon layer formation step, a through hole formation step, a feed layer formation step, and an epitaxial layer formation step. In the carbon layer formation step, a carbon layer ( | 10-30-2014 |
20140319540 | SEMICONDUCTOR DEVICE - A semiconductor device is provided with a semiconductor substrate in which a power semiconductor element part and a temperature sensing diode part are provided. The temperature sensing diode part includes a first semiconductor region, a second semiconductor region, a first base region, and a first drift region. In the semiconductor substrate, an isolation trench is formed, which passes through the first base region, extends to the first drift region, and surrounds an outer periphery of the temperature sensing diode part. At least a part of one of side walls of the isolation trench is in contact with the power semiconductor element part, and the other side wall of the isolation trench is in contact with the temperature sensing diode part. | 10-30-2014 |
20140319541 | VOIDLESSLY ENCAPSULATED SEMICONDUCTOR DIE PACKAGE - A system can include a semiconductor die having a first side and a second side opposite the first side. The system can also include a first slug coupled to a portion of the first side of the die. The system can further include a second slug coupled to a portion of the second side of the die. The system can additionally include an insulating material voidlessly encapsulating the die. The first slug can include a first portion having a first width in proximity to the die and a second portion having a second width. The first portion can be closer than the second portion to the die and the first width can be smaller than the second width. | 10-30-2014 |
20140319542 | MOLYBDENUM TRIOXIDE-COATED HYDROGEN-TERMINATED DIAMOND SURFACE AND USES THEREOF - The present invention provides a conducting material comprising a carbon-based material selected from a diamond or an insulating diamond-like carbon, having a hydrogen-terminated surface and a layer of MoO | 10-30-2014 |
20140319543 | FIN FIELD-EFFECT TRANSISTORS - A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate; and forming a plurality of fins on top of the semiconductor substrate. The method also includes forming isolation structures between adjacent fins; and forming doping sidewall spacers in top portions of the isolation structures near the fins. Further, the method includes forming a punch-through stop layer at the bottom of each of the fins by thermal annealing the doping sidewall spacers; and forming a high-K metal gate on each of the fins. | 10-30-2014 |
20140319544 | APPARATUS AND METHOD FOR FABRICATING EPI WAFER AND EPI WAFER - A method for fabricating an epi wafer according to the embodiment comprises depositing an epi layer on a wafer in a first chamber; transferring the wafer to a second chamber connected to the first chamber; forming a protective layer on the wafer in the second chamber; and cooling the wafer in the second chamber. | 10-30-2014 |
20140319545 | METHOD FOR DEPOSITION OF SILICON CARBIDE AND SILICON CARBIDE EPITAXIAL WAFER - A method for deposition of silicon carbide according to an embodiment includes preparing a wafer in a susceptor; introducing first etching gas into the susceptor; introducing second etching gas into the susceptor; producing an intermediate compound by introducing a reactive raw material into the susceptor; and forming a silicon carbide epitaxial layer on the wafer by reacting the intermediate compound with the wafer. | 10-30-2014 |
20140327017 | SILICON CARBIDE BARRIER DIODE - Improved semiconductor devices are fabricated utilizing nickel gallide and refractory borides deposited onto a silicon carbide semiconductor substrate. Varying the deposition and annealing parameters of fabrication can provide a more thermally stable device that has greater barrier height and a low ideality. This improvement in the electrical properties allows use of Schottky barrier diodes in high power and high temperature applications. In one embodiment, a refractory metal boride layer is joined to a surface of a silicon carbide semiconductor substrate. The refractory metal boride layer is deposited on the silicon carbon semiconductor substrate at a temperature greater than 200° C. In another embodiment, a Schottky barrier diode is fabricated via deposition of nickel gallide on a SiC substrate. | 11-06-2014 |
20140327018 | POWER SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE DEVICE AND BONDING WIRE - It is an object of the present invention to provide a power semiconductor device, which is capable of being operable regardless of thermal stress generation, reducing a heat generation from wire, securing the reliability of bonding portion when the device is used for dealing with a large amount current and/or under a high temperature atmosphere, a method of manufacturing the device and a bonding wire. In a power semiconductor device in which a metal electrode (die electrode | 11-06-2014 |
20140327019 | WIDE BANDGAP SEMICONDUCTOR DEVICE - A wide bandgap semiconductor device includes a first conductive type high-concentration wide bandgap semiconductor substrate, a first conductive type low-concentration wide bandgap semiconductor deposited film which is formed on the semiconductor substrate, a metal film which is formed on the semiconductor deposited film so that a Schottoky interface region is formed between the metal film and the semiconductor deposited film, and a second conductive type region which is formed in a region of the semiconductor deposited film corresponding to a peripheral portion of the metal film, wherein the Schottoky interface region in the semiconductor deposited film is surrounded by the second conductive type region so that periodic island regions are formed in the Schottoky interface region. | 11-06-2014 |
20140332824 | SEMICONDUCTOR STRUCTURE WITH DIFFERENT FINS OF FINFETS - A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the FinFETs are defined from the substrate. The even fins of the FinFETs are different from the odd fins of the FinFETs in at least one of the width and the material, and may be further different from the odd fins of the FinFETs in the height. | 11-13-2014 |
20140339568 | SEMICONDUCTOR DEVICE WITH SUBSTRATE VIA HOLE AND METHOD TO FORM THE SAME - A process to form a substrate via hole is disclosed. The process includes steps of (1) forming a semiconductor layer on a substrate; (2) forming a gate and an auxiliary electrode simultaneously on a semiconductor layer; and (3) etching the substrate and the semiconductor layer from the back surface of the substrate to the auxiliary electrode to form a substrate via hole. A feature of the process is that the gate and the auxiliary electrode include a nickel or a metal primarily containing nickel in contact with the semiconductor layer. The nickel operates as an etching stopper for drilling the substrate and the semiconductor layer. | 11-20-2014 |
20140339569 | SEMICONDUCTOR DEVICE - A semiconductor device formed on a silicon carbide substrate that has a front surface on which an electrode is provided and a back surface on which an electrode is provided includes a drain layer, a drift layer, a base layer, a gate electrode that is located in a trench that extends from the front surface into the drift layer and is insulated by an insulating film, a some layer, a buried layer that is provided between the drift layer and the base layer and is formed such that the depth from the front surface to an end thereof on the side of the drift layer is greater than the depth from the front surface to a distal end of the trench, and a first epitaxial layer that is provided between the buried layer and the base layer and has a higher impurity concentration than the buried layer. | 11-20-2014 |
20140339570 | ACCESS-RESISTANT DIODE ARRAY DEVICE HAVING ENHANCED STABILITY - A device includes a substrate carrying an array of diodes, organized in rows and columns, and a peripheral substrate contact is arranged on at least one side of the array. The substrate includes one or more buried conducting lines electrically connected to the peripheral substrate contact and being positioned between at least two neighbouring columns of diodes and/or between at least two neighbouring rows of diodes. | 11-20-2014 |
20140339571 | SILICON CARBIDE EPITAXIAL WAFER AND MANUFACTURING METHOD THEREFOR - A SiC epitaxial wafer obtained by forming a SiC epitaxial layer on a 4H—SiC single-crystal substrate that is tilted at an off-angle of 0.4° to 5°, wherein linear density of step bunchings, which are connected to shallow pits which are due to screw dislocation in the SiC epitaxial wafer, is 5 mm | 11-20-2014 |
20140339572 | MEMORY WITH CARBON-CONTAINING SILICON CHANNEL - A memory includes a first memory cell and a second memory cell formed over the first memory cell. Each of the first memory cell and the second memory cell includes a channel region comprising silicon and carbon, a control gate, and a dielectric stack between the channel region and the control gate. A carbon content of the channel region of the second memory cell is less than a carbon content of the channel region of the first memory cell. | 11-20-2014 |
20140346528 | VERTICAL-CHANNEL TYPE JUNCTION SIC POWER FET AND METHOD OF MANUFACTURING SAME - In order to secure the performance of a SiC-based JFET having an impurity diffusion rate lower than silicon-based one, a gate depth is secured while precisely controlling a distance between gate regions, instead of forming gate regions by ion implantation into the side wall of a trench. This means that a channel region defined by a gate distance and a gate depth should have a high aspect ratio. Further, due to limitations of process, a gate region is formed within a source region. Formation of a highly doped PN junction between source and gate regions causes various problems such as inevitable increase in junction current. In addition, a markedly high energy ion implantation becomes necessary for the formation of a termination structure. In the invention, provided is a vertical channel type SiC power JFET having a floating gate region below and separated from a source region and between gate regions. | 11-27-2014 |
20140346529 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor-device manufacturing method of the present invention includes a step of selectively implanting impurity ions into a surface of an SiC semiconductor layer and forming impurity regions and a step of activating the impurity ions by annealing the SiC semiconductor layer at a temperature of 1400° C. or more when the surface of the SiC semiconductor layer is covered with an insulating film. | 11-27-2014 |
20140346530 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention includes a SiC substrate, an AlN layer provided on the SiC substrate and having a maximum valley depth Rv of 5 nm or less in an upper surface, a channel layer provided on the AlN layer and composed of a nitride semiconductor, an electron supply layer provided on the channel layer and having a greater band gap than the channel layer, and a gate electrode, a source electrode and a drain electrode provided on the electron supply layer. | 11-27-2014 |
20140346531 | SiC SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a method which heats a layer including nickel and titanium on a SiC substrate ( | 11-27-2014 |
20140353682 | Wide Band Gap Semiconductor Wafers Grown and processed in a Microgravity Environment and Method of Production - Wide band gap semiconductor wafers with previously unattainable characteristics and the method of processing and producing the same are disclosed and claimed herein. Specifically, the application discloses and claims a method to process silicon carbide and other similar wide band gap semiconductors in a microgravity environment. The wafers are placed onto stackable containment systems that create an appropriate gap between each wafer to allow for homogeneous heating and processing. The resulting wide band gap semiconductors have unique molecular structures not attainable when wide band gap semiconductors with the identical chemical composition are produced in a standard 1 gravity environment. | 12-04-2014 |
20140353683 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor substrate preparation step, a semiconductor substrate which is made of SiC and in which a first semiconductor region of a first conductivity type is formed is prepared. In a second semiconductor region forming step, a second semiconductor region is formed by implanting an impurity of a second conductivity type into a first semiconductor region through multiple ion implantation steps while varying implantation depths of the respective multiple ion implantation steps. In the second semiconductor region forming step, a dose amount of the impurity when an implantation energy of multiple ion implantation steps is the largest is smaller than a dose amount of impurity when the implantation energy is not the largest. | 12-04-2014 |
20140353684 | SILICON CARBIDE EPITAXIAL WAFER AND METHOD FOR FABRICATING THE SAME - A method for fabricating a silicon carbide epitaxial wafer according to the embodiment includes introducing a carbon source and a silicon source into a reactor in which a silicon carbide wafer is provided; heating the reactor; and adjusting an amount of the silicon source or the carbon source introduced into the reactor. A silicon carbide epitaxial wafer according to the embodiment includes a silicon carbide epitaxial layer having a surface roughness of 0.3 nm or less. | 12-04-2014 |
20140353685 | Semi-Polar III-Nitride Films and Materials and Method for Making the Same - A method has been developed to overcome deficiencies in the prior art in the properties and fabrication of semi-polar group III-nitride templates, films, and materials. A novel variant of hydride vapor phase epitaxy has been developed that provides for controlled growth of nanometer-scale periodic structures. The growth method has been utilized to grow multi-period stacks of alternating AlGaN layers of distinct compositions. The application of such periodic structures to semi-polar III-nitrides yielded superior structural and morphological properties of the material, including reduced threading dislocation density and surface roughness at the free surface of the as-grown material. Such enhancements enable to fabrication of superior quality semi-polar III-nitride electronic and optoelectronic devices, including but not limited to transistors, light emitting diodes, and laser diodes. | 12-04-2014 |
20140353686 | SEMICONDUCTOR DEVICE - A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another. | 12-04-2014 |
20140361313 | SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench. | 12-11-2014 |
20140361314 | SEMICONDUCTOR ALLOY FIN FIELD EFFECT TRANSISTOR - Semiconductor alloy fin structures can be formed by recessing a semiconductor material layer including a first semiconductor material to form a trench, and epitaxially depositing a semiconductor alloy material of the first semiconductor material and a second semiconductor material within the trench. The semiconductor alloy material is epitaxially aligned to the first semiconductor material in the semiconductor material layer. First semiconductor fins including the first semiconductor material and second semiconductor fins including the semiconductor alloy material can be simultaneously formed. In one embodiment, the first and second semiconductor fins can be formed on an insulator layer, which prevents diffusion of the second semiconductor material to the first semiconductor fins. In another embodiment, shallow trench isolation structures and reverse biased wells can be employed to provide electrical insulation among neighboring semiconductor fins. | 12-11-2014 |
20140361315 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to one embodiment having a first region comprising a first dopant type, a second region adjacent the first region haivng a second dopant type and a channel region. There is a third region segregated from the channel region having a second dopant type, wherein the third region substantially coincides with the second region. | 12-11-2014 |
20140367700 | High-Voltage Cascaded Diode with HEMT and Monolithically Integrated Semiconductor Diode - An embodiment of a cascaded diode having a breakdown voltage exceeding 300V includes an HEMT and a Si Schottky diode. The HEMT includes a gate, a drain, a source, and a two-dimensional electron gas channel region connecting the source and the drain and controlled by the gate. The HEMT has a breakdown voltage exceeding 300V. The Si Schottky diode is monolithically integrated with the HEMT. The Si Schottky diode includes a cathode connected to the source of the HEMT and an anode connected to the gate of the HEMT. The Si Schottky diode has a breakdown voltage less than 300V and a forward voltage less than or equal to 0.4V. The anode of the Si Schottky diode forms the anode of the cascaded diode and the drain of the HEMT forms the cathode of the cascaded diode. | 12-18-2014 |
20140367701 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device includes; a semiconductor element in which a metallization layer is formed on the backside side; a metallic lead frame that is arranged in parallel, with a distance spaced apart from the semiconductor element; a first bonding layer that is provided between the semiconductor element and the lead frame, and is bonded to the metallization layer; and a second bonding layer that is provided between the semiconductor element and the lead frame, and bonds the first bonding layer to the lead frame. The first bonding layer is expanded at a central portion toward the lead frame. | 12-18-2014 |
20140367702 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An object is to provide a fin integrated type semiconductor device and a method of manufacturing the same, which are provided with a simple structure and good heat dissipation characteristics. The semiconductor device includes: a base plate on which fins arranged in a standing condition are formed on a first main face; an insulating layer formed on a second main face of the base plate, the second main face being opposite to the first main face of the base plate; a circuit pattern fixed to the insulating layer; and a semiconductor element joined to the circuit pattern. The fins are formed with slits that pass through in the thickness direction of the fins. | 12-18-2014 |
20140367703 | SOLID STATE LIGHT SOURCES BASED ON THERMALLY CONDUCTIVE LUMINESCENT ELEMENTS CONTAINING INTERCONNECTS - Solid state light sources based on LEDs mounted on or within thermally conductive luminescent elements provide both convective and radiative cooling. Low cost self-cooling solid state light sources can integrate the electrical interconnect of the LEDs and other semiconductor devices. The thermally conductive luminescent element can completely or partially eliminate the need for any additional heatsinking means by efficiently transferring and spreading out the heat generated in LED and luminescent element itself over an area sufficiently large enough such that convective and radiative means can be used to cool the device. | 12-18-2014 |
20140374773 | VERTICAL POWER TRANSISTOR WITH BUILT-IN GATE BUFFER - A vertical power transistor is monolithically packaged on a semiconductor die with gate buffer circuitry. The gate buffer circuitry is adapted to deliver a biasing voltage to a gate contact of the vertical power transistor for switching the device between an ON state and an OFF state. By monolithically packaging the gate buffer circuitry together with the vertical power transistor, parasitic inductance between the gate buffer circuitry and the gate of the vertical power transistor is minimized, thereby decreasing the switching time of the vertical power transistor and reducing switching noise. | 12-25-2014 |
20140374774 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - This semiconductor device includes a silicon carbide layer of a first conductivity type having first and second principal surfaces and including an element region and a terminal region surrounding the element region on the first principal surface. The silicon carbide layer includes a first dopant layer of the first conductivity type contacting with the first principal surface and a second dopant layer of the first conductivity type located closer to the second principal surface than the first dopant layer is. The terminal region has, in its surface portion with a predetermined depth under the first principal surface, a terminal structure including respective portions of the first and second dopant layers and a ring region of a second conductivity type running through the first dopant layer to reach the second dopant layer. The dopant concentration of the first dopant layer is twice to five times as high as that of the second dopant layer | 12-25-2014 |
20140374775 | ELECTRONIC COMPONENT AND MANUFACTURING METHOD FOR ELECTRONIC COMPONENT - A first metal film, of which major component is copper, is formed on a surface of a conductive portion which becomes a front surface electrode of a semiconductor element. A second metal film of which major component is silver is formed on a surface of the first metal film. A metal plate, which electrically connects the conductive portion and the other members (e.g. a circuit pattern of an insulated substrate) is bonded with a surface of the second metal film via a bonding layer containing silver particles. The second metal film does not contain nickel which decreases the bonding strength between the second metal film and the bonding layer containing silver particles. With the above configuration, an electronic component having a high bonding strength, excellent heat resistance and radiation performance, and a manufacturing method for the electronic component can be provided. | 12-25-2014 |
20150008446 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE - A method of manufacturing a semiconductor device is presented. The method includes providing a semiconductor layer comprising silicon carbide, wherein the semiconductor layer comprises a first region doped with a first dopant type. The method further includes implanting the semiconductor layer with a second dopant type using a single implantation mask and a substantially similar implantation dose to form a second region and a junction termination extension (JTE) in the semiconductor layer, wherein the implantation dose is in a range from about 2×10 | 01-08-2015 |
20150008447 | Silicon Carbide Device and a Method for Manufacturing A Silicon Carbide Device - A silicon carbide device includes an epitaxial silicon carbide layer having a first conductivity type and a buried lateral silicon carbide edge termination region within the epitaxial silicon carbide layer and having a second conductivity type. The buried lateral silicon carbide edge termination region is covered by a silicon carbide surface layer including a doping of ions of a transition metal or including an increased density of intrinsic point defects in comparison to a density of intrinsic point defects of the buried lateral silicon carbide edge termination region. | 01-08-2015 |
20150008448 | METAL-OXIDE-SEMICONDUCTOR (MOS) DEVICES WITH INCREASED CHANNEL PERIPHERY AND METHODS OF MANUFACTURE - A semiconductor device includes a drift layer disposed on a substrate. The drift layer has a non-planar surface having a plurality of repeating features oriented parallel to a length of a channel of the semiconductor device. Further, each the repeating features have a dopant concentration higher than a remainder of the drift layer. | 01-08-2015 |
20150008449 | METAL-OXIDE-SEMICONDUCTOR (MOS) DEVICES WITH INCREASED CHANNEL PERIPHERY AND METHODS OF MANUFACTURE - A semiconductor device includes a silicon carbide (SiC) drift layer disposed on a (0001) oriented SiC substrate. The SiC drift layer has a non-planar surface including a plurality of repeating features that are oriented parallel to a length of a channel of the semiconductor device. Further, the channel region is disposed in a particular crystallographic plane of the SiC drift layer. | 01-08-2015 |
20150008450 | WIDE BAND GAP SEMICONDUCTOR DEVICE - The present invention includes a second source layer formed on a surface layer of a p base layer in the same step as that of forming a n | 01-08-2015 |
20150008451 | Formation Of Self-Aligned Source For Split-Gate Non-volatile Memory Cell - A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type. | 01-08-2015 |
20150008452 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region. | 01-08-2015 |
20150008453 | SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation σ of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation σ of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm. | 01-08-2015 |
20150008454 | SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation σ of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation σ of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm. | 01-08-2015 |
20150014704 | Bipolar Transistor and a Method for Manufacturing a Bipolar Transistor - A bipolar transistor includes a semiconductor structure including an emitter area, a base area and a collector area. The emitter area is electrically connected to an emitter contact of the bipolar transistor. Further, the emitter area has a first conductivity type. The base area is electrically connected to a base contact of the bipolar transistor. Further, the base area has at least mainly a second conductivity type. The collector area is electrically connected to a collector contact of the bipolar transistor and has at least mainly the first conductivity type. Further, the collector area includes a plurality of enclosed sub areas having the second conductivity type or the base area includes a plurality of enclosed sub areas having the first conductivity type. | 01-15-2015 |
20150014705 | SEMICONDUCTOR DEVICE - An optical fiber is provided between a photodiode and a semiconductor active portion of a wide gap semiconductor element forming portion such that emitted light at the time of light emission of the semiconductor active portion of the wide gap semiconductor element forming portion is incident from an incident surface of the optical fiber, and is received from an emitting surface to the photodiode through the optical fiber. Specifically, the incident surface of the optical fiber is arranged so as to be opposed to a side surface portion of the wide gap semiconductor element forming portion, so that the emitted light at the time of light emission of the wide gap semiconductor element is incident on the incident surface. | 01-15-2015 |
20150014706 | Vertical Hetero Wide Bandgap Transistor - A vertical hetero transistor provides a wide bandgap, increases the breakdown voltage or reduces the on resistance of the switching transistor or both. | 01-15-2015 |
20150014707 | METHOD FOR PRODUCING A MOS STACK ON A DIAMOND SUBSTRATE - The invention relates to a method for producing a component comprising a conductive grid insulated from a semiconductor monocrystalline diamond substrate by an insulating region, comprising the following steps: a) oxygenating the surface of the substrate so as to replace the hydrogen surface terminations of the substrate with oxygen surface terminations; and b) forming the insulating region on the surface of the substrate by repeated monatomic layer deposition. | 01-15-2015 |
20150021623 | ENHANCED GATE DIELECTRIC FOR A FIELD EFFECT DEVICE WITH A TRENCHED GATE - The present disclosure relates to a silicon carbide (SiC) field effect device that has a gate assembly formed in a trench. The gate assembly includes a gate dielectric that is an dielectric layer, which is deposited along the inside surface of the trench and a gate dielectric formed over the gate dielectric. The trench extends into the body of the device from a top surface and has a bottom and side walls that extend from the top surface of the body to the bottom of the trench. The thickness of the dielectric layer on the bottom of the trench is approximately equal to or greater than the thickness of the dielectric layer on the side walls of the trench. | 01-22-2015 |
20150021624 | LIFT-OFF OF EPITAXIAL LAYERS FROM SILICON CARBIDE OR COMPOUND SEMICONDUCTOR SUBSTRATES - A method to remove epitaxial semiconductor layers from a substrate by growing an epitaxial sacrificial layer on the substrate where the sacrificial layer is a transition metal nitride (TMN) or a TMN ternary compound, growing one or more epitaxial device layers on the sacrificial layer, and separating the device layers from the substrate by etching the sacrificial layer to completely remove the sacrificial layer without damaging or consuming the substrate or any device layer. Also disclosed are the related semiconductor materials made by this method. | 01-22-2015 |
20150021625 | SEMICONDUCTOR FIN ISOLATION BY A WELL TRAPPING FIN PORTION - A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer. | 01-22-2015 |
20150028348 | FORMING EMBEDDED SOURCE AND DRAIN REGIONS TO PREVENT BOTTOM LEAKAGE IN A DIELECTRICALLY ISOLATED FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE - Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a fin field effect transistor (finFET)) are provided. Specifically, the FinFET device comprises a gate structure formed over a finned substrate; an isolation oxide beneath an active fin channel of the gate structure; an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and an epitaxial (epi) bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D. The device further includes a set of implanted regions implanted beneath the epi bottom region, wherein the set of implanted regions may be doped and the epi bottom region undoped. In one approach, the embedded S/D comprises P++ doped Silicon Germanium (SiGe) for a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) and N++ Silicon Nitride (SiN) for a n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET). | 01-29-2015 |
20150028349 | METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES - Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height. | 01-29-2015 |
20150028350 | Controlled Ion Implantation Into Silicon Carbide Using Channeling And Devices Fabricated Using Controlled Ion Implantation Into Silicon Carbide Using Channeling - Methods of forming a semiconductor structure include the use of channeled implants into silicon carbide crystals. Some methods include providing a silicon carbide layer having a crystallographic axis, heating the silicon carbide layer to a temperature of about 300° C. or more, implanting dopant ions into the heated silicon carbide layer at an implant angle between a direction of implantation and the crystallographic axis of less than about 2°, and annealing the silicon carbide layer at a time-temperature product of less than about 30,000° C.-hours to activate the implanted ions. | 01-29-2015 |
20150028351 | Methods of Forming Buried Junction Devices in Silicon Carbide Using Ion Implant Channeling and Silicon Carbide Devices Including Buried Junctions - A semiconductor device structure according to some embodiments includes a silicon carbide substrate having a first conductivity type, a silicon carbide drift layer having the first conductivity type on the silicon carbide substrate and having an upper surface opposite the silicon carbide substrate, and a buried junction structure in the silicon carbide drift layer. The buried junction structure has a second conductivity type opposite the first conductivity type and has a junction depth that is greater than about one micron. | 01-29-2015 |
20150028352 | SEMICONDUCTOR DEVICE - [Object] To provide a semiconductor device with which an increase in on-resistance can be suppressed even if a voltage is continuously applied for a long period of time across a source and a drain in a gate-off state. | 01-29-2015 |
20150028353 | Schottky Barrier Detection Devices Having a 4H-SiC n-Type Epitaxial Layer - A detection device, along with methods of its manufacture and use, is provided. The detection device can include: a SiC substrate defining a substrate surface cut from planar to about 12°; a buffer epitaxial layer on the substrate surface; a n-type epitaxial layer on the buffer epitaxial layer; and a top contact on the n-type epitaxial layer. The buffer epitaxial layer can include a n-type 4H—SiC epitaxial layer doped at a concentration of about 1×10 | 01-29-2015 |
20150028354 | Silicon Carbide Devices Having Smooth Channels - Methods of forming silicon carbide power devices are provided. An n | 01-29-2015 |
20150028355 | Method of Forming A Semiconductor Device - A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film. | 01-29-2015 |
20150034969 | METHOD AND SYSTEM FOR A SEMICONDUCTOR DEVICE WITH INTEGRATED TRANSIENT VOLTAGE SUPPRESSION - A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value. | 02-05-2015 |
20150034970 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor device of the present invention includes a semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode being in contact with a surface of the semiconductor layer. The semiconductor layer includes a drift layer that forms the surface of the semiconductor layer and a high-resistance layer that is formed on a surface layer portion of the drift layer and that has higher resistance than the drift layer. The high-resistance layer is formed by implanting impurity ions from the surface of the semiconductor layer and then undergoing annealing treatment at less than 1500° C. | 02-05-2015 |
20150034971 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - [Problem] To provide an SiC semiconductor device, with which stabilization of high-temperature operation can be achieved by decreasing mobile ions in a gate insulating film, and a method for manufacturing the SiC semiconductor device. | 02-05-2015 |
20150034972 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes, a first conductivity type semiconductor substrate including one of Si and SiC; a second conductivity type semiconductor region at a surface of the semiconductor substrate, a GaN-based semiconductor layer on the semiconductor substrate, and a lateral semiconductor element at the GaN-based semiconductor layer and above the semiconductor region, the lateral semiconductor element having a first electrode and a second electrode electrically connected to the semiconductor region. | 02-05-2015 |
20150034973 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes: an n-type first SiC epitaxial layer; a p-type second SiC epitaxial layer provided on the first SiC epitaxial layer and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the concentration of the element A in the combination(s) being higher than 0.33 but lower than 1.0; n-type first and second SiC regions provided in the surface of the second SiC epitaxial layer; a gate insulating film; a gate electrode; a first electrode provided on the second SiC region; and a second electrode provided on the opposite side from the first electrode. | 02-05-2015 |
20150034974 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes: an n-type first SiC epitaxial layer; a p-type second SiC epitaxial layer on the first SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the element A being higher than 0.33 but lower than 1.0; a surface region at the surface of the second SiC epitaxial layer containing the element A at a lower concentration than in the second SiC epitaxial layer, the ratio being higher than in the second SiC epitaxial layer; n-type first and second SiC regions; a gate insulating film; a gate electrode; a first electrode; and a second electrode. | 02-05-2015 |
20150041824 | TRANSISTOR WITH BONDED GATE DIELECTRIC - A method for forming a semiconductor device includes forming a dielectric layer on a first substrate and wafer bonding the dielectric layer of the first substrate to a second substrate including SiC with a passivating layer formed on the SiC. A portion of the first substrate is removed from a side opposite the dielectric layer. The dielectric layer is patterned to form a gate dielectric for a field effect transistor formed on the second substrate. | 02-12-2015 |
20150041825 | SEMICONDUCTOR DEVICE, HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) AND METHOD OF MANUFACTURING - A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, and a barrier structure between the substrate and the channel layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The barrier structure is configured to block diffusion of at least one of a material of the substrate or a dopant toward the channel layer. | 02-12-2015 |
20150041826 | TRANSISTOR WITH BONDED GATE DIELECTRIC - A method for forming a semiconductor device includes forming a dielectric layer on a first substrate and wafer bonding the dielectric layer of the first substrate to a second substrate including SiC with a passivating layer formed on the SiC. A portion of the first substrate is removed from a side opposite the dielectric layer. The dielectric layer is patterned to form a gate dielectric for a field effect transistor formed on the second substrate. | 02-12-2015 |
20150041827 | BONDING STRUCTURE INCLUDING METAL NANO PARTICLES AND BONDING METHOD USING METAL NANO PARTICLES - A bonding structure including metal nano particles includes a first member having a metal surface on at least one side, a second member having a metal surface on at least one side, the second member being disposed such that the metal surface of the second member faces the metal surface of the first member, and a bonding material bonding the first member and the second member by sinter-bonding the metal nano particles. At least one of the metal surfaces of the first member and the second member is formed to be a rough surface having a surface roughness within the range from 0.5 μm to 2.0 μm. | 02-12-2015 |
20150041828 | SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - [Object] To provide a semiconductor device capable of improving a discharge starting voltage when measuring electric characteristics, and widening a pad area of a surface electrode or increasing the number of semiconductor devices (number of chips) to be obtained from one wafer, and a method for manufacturing the same. | 02-12-2015 |
20150041829 | ELECTRONIC CIRCUIT DEVICE - A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET. | 02-12-2015 |
20150041830 | SCHOTTKY DIODE - A semiconductor system of a Schottky diode is described having an integrated PN diode as a clamping element, which is suitable in particular as a Zener diode having a breakdown voltage of approximately 20 V for use in motor vehicle generator systems. The semiconductor system of the Schottky diode includes a combination of a Schottky diode and a PN diode. The breakdown voltage of the PN diode is much lower than the breakdown voltage of the Schottky diode, the semiconductor system being able to be operated using high currents during breakdown operation. | 02-12-2015 |
20150041831 | PRODUCTION OF AN INTEGRATED CIRCUIT INCLUDING ELECTRICAL CONTACT ON SiC - Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate. | 02-12-2015 |
20150048382 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a silicon carbide semiconductor device, a p-type SiC layer is disposed in a corner of a bottom of a trench. Thus, even if an electric field is applied between a drain and a gate when a MOSFET is turned off, a depletion layer in a pn junction between the p-type SiC layer and an n | 02-19-2015 |
20150048383 | SILICON CARBIDE SEMICONDUCTOR ELEMENT AND FABRICATION METHOD THEREOF | 02-19-2015 |
20150048384 | SEMICONDUCTOR DEVICE - In a JBS diode using a wide band gap semiconductor, the wide band gap semiconductor has a large built-in voltage, which sometimes causes difficulties for the pn diode portion to turn on, resulting in a problem that resistance to surge currents is not sufficiently ensured. In order to solve this problem, in the wide-band-gap JBS diode, a pn junction of the pn diode is formed away from the Schottky electrode, and well regions are formed so as to have a width narrowed at a portion away from the Schottky electrode. | 02-19-2015 |
20150053998 | SEMICONDUCTOR DEVICE - A base layer is used that has an N-type SiC layer formed in a surface layer on the front surface side of an N-type SiC substrate, and a P-type region is formed on a surface of the N-type SiC layer with an N-type source region selectively formed in a surface layer of the P-type region. A source electrode is formed on a surface of the N-type source region and a drain electrode is formed on the back surface side of the N-type SiC substrate. Additionally, the gate electrode is formed via a gate insulation film only on a surface of the P-type region. In this way, high electric field is no longer applied to the gate insulation film on the surface of the N-type SiC layer due to stoppage of voltage application to the gate electrode. | 02-26-2015 |
20150053999 | WIDE BANDGAP INSULATED GATE SEMICONDUCTOR DEVICE - A wide bandgap insulated gate semiconductor device includes a semiconductor substrate made of semiconductor having a bandgap wider than silicon; n | 02-26-2015 |
20150054000 | METHOD FOR TREATING SURFACE OF DIAMOND THIN FILM, METHOD FOR FORMING TRANSISTOR, AND SENSOR DEVICE - A method for treating a surface of a diamond thin film according to one aspect of the present invention performs one of a first substitution process for substituting part of hydrogen-terminals of a diamond thin film with fluorine-terminals in the absence of a fluorocarbon deposition on the surface of diamond thin film and a second substitution process for substituting part of hydrogen-terminals of a diamond thin film with fluorine-terminals in the presence of the fluorocarbon deposition on the surface of diamond thin film based on required surface properties of the diamond thin film. | 02-26-2015 |
20150060881 | SEMICONDUCTOR COMPONENT - A semiconductor component ( | 03-05-2015 |
20150060882 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes: a drift layer of the a first conduction type; a guard ring region of a second conduction type formed in annular form in a portion of one surface of the drift layer; a field insulating film formed on the one surface of the drift layer and surrounding the guard ring region; a Schottky electrode covering the guard ring region and the drift layer exposed inside the guard ring region and having an outer peripheral end existing on the field insulating film; and a surface electrode pad on the Schottky electrode, wherein an outer peripheral end of the surface electrode pad comes into contact with the field insulating film over the outer peripheral end of the Schottky electrode. | 03-05-2015 |
20150060883 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first electrode, a first insulating section, and a second insulating section. The first semiconductor region includes silicon carbide, is of a first conductivity type and includes first and second parts. The second semiconductor region includes silicon carbide, is of a second conductivity type and is provided on the second part. The third semiconductor region includes silicon carbide, is of the first conductivity type and is provided on the second semiconductor region. The first electrode is provided on the first part and the third semiconductor region. The first insulating section is provided on the third semiconductor region and juxtaposed with the first electrode. The second insulating section is provided between the first electrode and the first part and between the first electrode and the first insulating section. | 03-05-2015 |
20150060884 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, and a first electrode. The first semiconductor region is of a first conductivity type. The second semiconductor region is provided on the first semiconductor region, and is of a second conductivity type. The third semiconductor region is provided on the second semiconductor region, and is of the second conductivity type. The third semiconductor region contains a first impurity of the first conductivity type and a second impurity of the second conductivity type, and satisfies 103-05-2015 | |
20150060885 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes an i-type or a p-type first diamond semiconductor layer, an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer, a mesa structure and an n-type first diamond semiconductor region provided on the side surface. The mesa structure includes the first diamond semiconductor layer, the second diamond semiconductor layer, a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane. The first diamond semiconductor region is in contact with the second diamond semiconductor layer and has an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer. | 03-05-2015 |
20150060886 | SEMICONDUCTOR SUBSTRATE - A semiconductor substrate has a main surface and formed of single crystal silicon carbide. The main surface includes a central area, which is an area other than the area within 5 mm from the outer circumference. When the central area is divided into square areas of 1 mm×1 mm, in any square area, density of dislocations of which Burgers vector is parallel to <0001> direction is at most 1×10 | 03-05-2015 |
20150060887 | NORMALLY-OFF POWER JFET AND MANUFACTURING METHOD THEREOF - In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times. | 03-05-2015 |
20150069411 | SEMICONDUCTOR DEVICE, JUNCTION FIELD EFFECT TRANSISTOR AND VERTICAL FIELD EFFECT TRANSISTOR - A semiconductor device according to an embodiment is at least partially arranged in or on a substrate and includes a recess forming a mesa, wherein the mesa extends along a direction into the substrate to a bottom plane of the recess and includes a semiconducting material of a first conductivity type, the semiconducting material of the mesa including at least locally a first doping concentration not extending further into the substrate than the bottom plane. The semiconductor device further includes an electrically conductive structure arranged at least partially along a sidewall of the mesa, the electrically conductive structure forming a Schottky or Schottky-like electrical contact with the semiconducting material of the mesa, wherein the substrate comprises the semiconducting material of the first conductivity type comprising at least locally a second doping concentration different from the first doping concentration along a projection of the mesa into the substrate. | 03-12-2015 |
20150069412 | SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING SCHOTTKY BARRIER DIODE - A Schottky barrier diode and a method of manufacturing the Schottky barrier diode are provided. The diode includes an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate and having an upper surface, a lower surface, and an inclined surface that connects the upper surface and the lower surface. A p region is disposed on the inclined surface of the n− type epitaxial layer and a Schottky electrode is disposed on the upper surface of the n− type epitaxial layer and the p region. In addition, an ohmic electrode is disposed on a second surface of the n+ type silicon carbide substrate. | 03-12-2015 |
20150069413 | SEMICONDUCTOR DEVICE - According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer of a first conductivity type provided between the first electrode and the second electrode, the first semiconductor layer including silicon carbide; a second semiconductor layer of the first conductivity type provided between the first semiconductor layer and the second electrode, the second semiconductor layer having a lower impurity concentration than the first semiconductor layer, and the second semiconductor layer including silicon carbide; a third semiconductor layer of a second conductivity type provided between the second semiconductor layer and the second electrode, and the third semiconductor layer including silicon carbide; and a plurality of insulating layers provided between the third semiconductor layer and the second electrode. | 03-12-2015 |
20150069414 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes first and second electrodes, and first, second, and third semiconductor regions. The first semiconductor region has a first conductivity type. The first electrode is provided above the first semiconductor region. The second semiconductor region has a second conductivity type and is provided between the first semiconductor region and the first electrode. The third semiconductor region is provided between the first semiconductor region and the first electrode, and has the second conductivity type. The third semiconductor region has an impurity concentration substantially equal to an impurity concentration of the second semiconductor region, and has first and second portions. The first and second portions constitute a concave-convex form on a side of the first semiconductor region of the third semiconductor region. The second electrode is provided above an opposite side of the first semiconductor region from the first electrode. | 03-12-2015 |
20150069415 | SEMICONDUCTOR DEVICE - An n-type SiC layer is formed on a front face of an n | 03-12-2015 |
20150069416 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The first semiconductor region includes silicon carbide. A conductivity type of the first semiconductor region is a first conductivity type. The second semiconductor region includes silicon carbide. A conductivity type of the second semiconductor region is a second conductivity type. The third semiconductor region includes silicon carbide. A conductivity type of the third semiconductor is the second conductivity type. The third semiconductor region is provided between the first semiconductor region and the second semiconductor region. As viewed in a direction connecting the first semiconductor region and the second semiconductor region, an area of an overlapping region of the second semiconductor region and the third semiconductor region is smaller than an area of an overlapping region of the first semiconductor region and the second semiconductor region. | 03-12-2015 |
20150069417 | Monolithic Bidirectional Silicon Carbide Switching Devices - A monolithic bidirectional switching device includes a drift layer having a first conductivity type and having an upper surface, and first and second vertical metal-oxide semiconductor (MOS) structures at the upper surface of the drift layer. The drift layer provides a common drain for the first and second vertical MOS structures. The first and second vertical MOS structures are protected by respective first and second edge termination structures at the upper surface of the drift layer. A monolithic bidirectional switching device according to further embodiments includes a vertical MOS structure at the upper surface of the drift layer, and a diode at the upper surface of the drift layer. The drift layer provides a drain for the vertical MOS structure and a cathode for the diode, and the vertical MOS structure and the diode are protected by respective first and second edge termination structures. | 03-12-2015 |
20150076514 | METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION - Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures. | 03-19-2015 |
20150076515 | SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING SCHOTTKY BARRIER DIODE - A Schottky barrier diode and a method of manufacturing the diode are provided. The diode includes an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate and a plurality of p+ regions disposed within the n− type epitaxial layer. An n+ type epitaxial layer is disposed on the n− type epitaxial layer, a Schottky electrode is disposed on the n+ type epitaxial layer, and an ohmic electrode is disposed on a second surface of the n+ type silicon carbide substrate. The n+ type epitaxial layer includes a plurality of pillar parts disposed on the n− type epitaxial layer and a plurality of openings disposed between the pillar parts and that expose the p+ regions. Each of the pillar parts includes substantially straight parts that contact the n− type epitaxial layer and substantially curved parts that extend from the substantially straight parts. | 03-19-2015 |
20150076516 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - According to one embodiment, a semiconductor device includes a semiconductor element and a metal film. The semiconductor element has a first surface and a second surface opposite to the first surface. The metal film is provided above the second surface of the semiconductor element. The metal film includes Cr. | 03-19-2015 |
20150076517 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device is provided with a semiconductor-element substrate in which a front-surface electrode pattern is formed on a surface of an insulating substrate; semiconductor elements for electric power which are affixed to the surface of the front-surface electrode pattern; a partition wall which is provided on the front-surface electrode pattern so as to enclose the semiconductor elements for electric power; a first sealing resin member which is filled inside the partition wall; a second sealing resin member which covers the first sealing resin member and a part of the semiconductor-element substrate which is exposed from the partition wall, wherein an electrode for a relay terminal is provided on a surface of the partition wall, and a wiring from inside of the partition wall to outside of the partition wall is led out via the electrode for a relay terminal. | 03-19-2015 |
20150076518 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention aims at providing a semiconductor device having a conductive film formed on a semiconducting substrate so that heating of the substrate and contamination by impurities can be suppressed and Schottky resistance can be reduced, and at providing a method of manufacturing the same. The metal film formation method used in manufacturing the semiconductor device according to an embodiment of the present invention includes the steps of: irradiating one surface of the substrate with a femtosecond laser having energy in the vicinity of the processing threshold value to form a nano-periodic structure in the form of minute irregularities; and forming a metal film on the nano-periodic structure of the substrate. It is thereby possible to reduce the Schottky resistance at the interface between the substrate and the metal film and obtain an ohmic contact while suppressing heating of the substrate and contamination by impurities. | 03-19-2015 |
20150076519 | VERTICAL HIGH VOLTAGE SEMICONDUCTOR APPARATUS AND FABRICATION METHOD OF VERTICAL HIGH VOLTAGE SEMICONDUCTOR APPARATUS - A silicon carbide vertical MOSFET includes an N-counter layer of a first conductivity type formed in a surface layer other than a second semiconductor layer base layer selectively formed in a low concentration layer on a surface of the substrate, a gate electrode layer formed through a gate insulating film in at least a portion of an exposed portion of a surface of a third semiconductor layer of a second conductivity type between a source region of the first conductivity type and the N-counter layer of the first conductivity type, and a source electrode in contact commonly with surfaces of the source region and the third semiconductor layer. Portions of the second conductivity type semiconductor layer are connected with each other in a region beneath the N-counter layer. | 03-19-2015 |
20150076520 | SILICON CARBIDE SEMICONDUCTOR ELEMENT AND FABRICATION METHOD THEREOF - In a fabrication method of a silicon carbide semiconductor element including a drift layer playing a role of retaining a high withstand voltage on a front side of a semiconductor substrate of silicon carbide and including an ohmic electrode on a backside, dicing is added to form at least one dicing line in an element active region on a surface of the semiconductor substrate on a side opposite of the drift layer before forming the ohmic electrode on the backside of the semiconductor substrate. Thus, a silicon carbide semiconductor element and fabrication method thereof is provided such that even if the semiconductor substrate is made thinner to reduce the on-resistance, the strength of the substrate can be maintained and cracking of the wafer during wafer processing can be reduced. | 03-19-2015 |
20150076521 | VERTICAL HIGH-VOLTAGE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - To provide a vertical SIC-MOSFET and IGBT capable of having low ON-resistance without destruction of gate oxide films or degradation of reliability even when a high voltage is applied, and a fabrication method thereof, a vertical mosfet has a semiconductor layer and a base layer joined instead of a well region | 03-19-2015 |
20150076522 | SEMICONDUCTOR DEVICES WITH HETEROJUNCTION BARRIER REGIONS AND METHODS OF FABRICATING SAME - An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a junction, such as a Schottky junction, with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. Related methods are also disclosed. | 03-19-2015 |
20150076523 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first and a second transistor. The first transistor includes a first and a second region of a first conductivity type and a third region of a second conductivity type. The first region is disposed along a first crystal face of a silicon carbide region. The silicon carbide region has the first crystal face and a second crystal face. The second and the third region are disposed along the first face. The third region is provided between the first and the second region. The second transistor includes a fourth and fifth region of the second type and a sixth region of the first type. The fourth, the fifth and the sixth region are disposed along the second face of the silicon carbide region. The sixth region is provided between the fourth and the fifth region. | 03-19-2015 |
20150084062 | MONOLITHICALLY INTEGRATED VERTICAL POWER TRANSISTOR AND BYPASS DIODE - A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer. | 03-26-2015 |
20150084063 | SEMICONDUCTOR DEVICE WITH A CURRENT SPREADING LAYER - A semiconductor device includes a substrate, a drift layer over the substrate, a spreading layer over the drift layer, and a pair of junction implants in a surface of the spreading layer opposite the drift layer. An anode covers the surface of the spreading layer opposite the drift layer, and a cathode covers a surface of the substrate opposite the drift layer. By including the spreading layer, a better balance can be struck between the on state resistance of the semiconductor device and the peak electric field in the device, thereby improving the performance thereof. | 03-26-2015 |
20150084064 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP | 03-26-2015 |
20150084065 | SiC SINGLE CRYSTAL SUBSTRATE - A single crystal SiC substrate capable of forming a good epitaxial thin film thereon to give a high-quality epitaxial substrate is provided. The single crystal SiC substrate has a CMP-treated surface and has 5 or fewer lattice defects measuring 30 nm or more in a direction parallel to the polished surface and 50 nm or more in a direction perpendicular to the polished surface as counted within a depth of 100 nm from the polished surface in a direction perpendicular to the polished surface and a length of 10 μm in a direction parallel to the polished surface when observed in cross-section using a transmission electron microscope under the 00L reflection or the h-h0 reflection, where L and h are each an integer other than 0. | 03-26-2015 |
20150084066 | HIGH VOLTAGE MOSFET DEVICES AND METHODS OF MAKING THE DEVICES - A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described. | 03-26-2015 |
20150084067 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device of this embodiment includes: a first region of a first conductivity type SiC; a second region of a first conductivity type SiC, impurity concentration of first conductivity type of the second region being lower than impurity concentration of first conductivity type of the first region; a third region of a second conductivity type SiC provided between the first region and the second region; a Si layer provided on surfaces of the first, second, and third regions, a thickness of-the Si layer on the third region being thicker than a thickness of the Si layer on the second region; a gate insulating film provided on the Si layer; and a date electrode provided on the gate insulating film. | 03-26-2015 |
20150084068 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device of an embodiment includes: an SiC layer; a gate insulating film provided on a surface of the SiC layer, the gate insulating film including an oxide film or an oxynitride film in contact with the surface of the SiC layer, the oxide film or the oxynitride film containing at least one element selected from B, Al, Ga (gallium), In, Sc, Y, La, Mg, Ca, Sr, and Ba, a concentration peak of the element in the gate insulating film being on the SiC side of the gate insulating film, the concentration peak of the element being in the oxide film or the oxynitride film, the gate insulating film having a region with a concentration of the element being not higher than 1×10 | 03-26-2015 |
20150091019 | WHITE LED CHIP AND WHITE LED PACKAGING DEVICE - A white LED chip includes a P-type layer, a tunneling structure, an N-type layer, an N-type electrode, and a P-type electrode. The tunneling structure is disposed over the P-type layer. The tunneling structure includes a first barrier layer, an active layer and a second barrier layer. The first barrier layer includes a first material layer, the active layer includes a second material layer, and the second barrier layer includes a third material layer. The N-type layer is disposed over the tunneling structure. An energy gap of the second material layer is lower than an energy gap of the first material layer and an energy gap of the third material layer. Each of the first material layer, the second material layer and the third material layer is a metal oxide layer, a metal nitride layer or a metal oxynitride layer. | 04-02-2015 |
20150091020 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device includes: a gate oxide film formed on a surface of a semiconductor substrate; a gate electrode formed on the gate oxide film; and a high concentration impurity layer connected to a main electrode and formed on the surface of the semiconductor substrate, wherein an impurity species doped in the high concentration impurity layer comprises a first impurity species of phosphorous and a second impurity species of at least one of argon and nitrogen, a concentration of the second impurity species is higher than a concentration of the first impurity species in a surface of the high concentration impurity layer, and a peak position of a concentration distribution of the first impurity species in a depth direction in the high concentration impurity layer is deeper than a peak position of a concentration distribution of the second impurity species in the depth direction. | 04-02-2015 |
20150091021 | Method of Manufacturing Semiconductor Device and the Semiconductor Device - A method of manufacturing a semiconductor device includes: forming a gate electrode material layer made of a material configuring a gate electrode and a barrier material layer made of a silicon nitride film; forming an upper barrier layer configured to an upper surface of the gate electrode with the barrier material layer and forming the gate electrode from the gate electrode material later by etching the barrier material layer and the gate electrode material layer with a same mask pattern; forming a sidewall barrier layer configured to cover a side surface of the gate electrode by forming again the barrier material layer after the forming of the gate electrode; forming an interlayer insulation layer configured to cover a surface-side of the semiconductor substrate including the upper surface barrier layer and the sidewall barrier layer; and opening the interlayer insulation layer and forming the silicide electrode. | 04-02-2015 |
20150091022 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device having a main electrode connected to a first semiconductor region and a second semiconductor layer on a semiconductor substrate so that a pn-junction diode is formed with the first semiconductor region being interposed and a Schottky barrier diode is formed with the second semiconductor layer being interposed on a surface of the semiconductor substrate, the semiconductor device includes a first electrode configured to ohmic-contact the first semiconductor region; a second electrode configured to Schottky-contact the second semiconductor layer and not having a portion directly contacting the first electrode; and a conductive reaction suppression layer to suppress a reaction between a material configuring the first electrode and a material configuring the second electrode are provided on the surface of the semiconductor substrate, and the main electrode is electrically connected to the first electrode and the second electrode. | 04-02-2015 |
20150091023 | Semiconductor Device and Method of Manufacturing - A diode comprising a reduced surface field effect trench structure, the reduced surface field effect trench structure comprising at least two trenches formed in a substrate and separated from one another by a joining region of the substrate, the joining region comprising an electrical contact and a layer of p-doped semiconductor material. | 04-02-2015 |
20150097197 | FINFET WITH SIGMA CAVITY WITH MULTIPLE EPITAXIAL MATERIAL REGIONS - Embodiments of the present invention provide an improved finFET and methods of fabrication. A sigma cavity is used with an n-type finFET to allow multiple epitaxial layers to be disposed adjacent to a finFET gate. In some embodiments, stacking faults may be formed in the epitaxial layers using a stress memorization technique. | 04-09-2015 |
20150102361 | SEMICONDUCTOR DEVICES IN SIC USING VIAS THROUGH N-TYPE SUBSTRATE FOR BACKSIDE CONTACT TO P-TYPE LAYER - A Silicon Carbide (SiC) semiconductor device having back-side contacts to a P-type region and methods of fabrication thereof are disclosed. In one embodiment, an SiC semiconductor device includes an N-type substrate and an epitaxial structure on a front-side of the N-type substrate. The epitaxial substrate includes a P-type layer adjacent to the N-type substrate and one or more additional SiC layers on the P-type layer opposite the N-type substrate. The semiconductor device also includes one or more openings through the N-type substrate that extend from a back-side of the N-type substrate to the P-type layer and a back-side contact on the back-side of the N-type substrate and within the one or more openings such that the back-side contact is in physical and electrical contact with the P-type layer. The semiconductor device further includes front-side contacts on the epitaxial structure opposite the N-type substrate. | 04-16-2015 |
20150102362 | SILICON CARBIDE POWER DEVICE EQUIPPED WITH TERMINATION STRUCTURE - A silicon carbide power device equipped with termination structure comprises a silicon carbide substrate, a power element structure and a termination structure. The silicon carbide substrate contains a drift layer which has a first conductivity and includes an active zone and a termination zone. The power element structure is located in the active zone. The termination structure is located in the termination zone and has a second conductivity, and includes at least one first doped ring abutting and surrounding the power element structure and at least one second doped ring surrounding the first doped ring. The first doped ring has a first doping concentration smaller than that of the second doped ring and a first doping depth greater than that of the second doped ring, thereby can increase the breakdown voltage of the silicon carbide power device. | 04-16-2015 |
20150102363 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A silicon carbide semiconductor device has a first-conductivity-type semiconductor layer having a lower impurity concentration and formed on a first-conductivity-type semiconductor substrate, a second-conductivity-type semiconductor layer having a higher impurity concentration and selectively formed in the first-conductivity-type semiconductor layer, a second-conductivity-type base layer having a lower impurity concentration formed on a surface of the second-conductivity-type semiconductor layer, a first-conductivity-type source region selectively formed in a surface layer of the base layer, a first-conductivity-type well region formed to penetrate the base layer from a surface to the first-conductivity-type semiconductor layer, and a gate electrode formed via a gate insulation film on a surface of the base layer interposed between the source region and the well region. Portions of the respective second-conductivity-type semiconductor layers of different cells can be connected to each other by a connecting portion in a region under the well region. | 04-16-2015 |
20150102364 | Semiconductor Device with Low-Conducting Buried and/or Surface Layers - A device including one or more low-conducting layers is provided. A low-conducting layer can be located below the channel and one or more attributes of the low-conducting layer can be configured based on a minimum target operating frequency of the device and a charge-discharge time of a trapped charge targeted for removal by the low-conducting layer or a maximum interfering frequency targeted for suppression using the low-conducting layer. For example, a product of the lateral resistance and a capacitance between the low-conducting layer and the channel can be configured to be larger than an inverse of the minimum target operating frequency and the product can be smaller than at least one of: the charge-discharge time or an inverse of the maximum interfering frequency. | 04-16-2015 |
20150108499 | SEMICONDUCTOR DEVICES WITH GRAPHENE NANORIBBONS - Semiconductor devices with graphene nanoribbons and methods of manufacture are disclosed. The method includes forming at least one layer of Si material on a substrate. The method further includes forming at least one layer of carbon based material adjacent to the at least one layer of Si. The method further includes patterning at least one of the at least one layer of Si material and the at least one layer of carbon based material. The method further includes forming graphene on the patterned carbon based material. | 04-23-2015 |
20150108500 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device comprises a semiconductor body of a first semiconductor material, wherein at least a part of the semiconductor body constitutes a drift zone of a first conductivity type. The semiconductor device further comprises a channel layer structure comprising a semiconductor heterojunction between first and second semiconductor layers electrically coupled to the drift zone. The first and second semiconductor layers include semiconductor materials that are different to the first semiconductor material. | 04-23-2015 |
20150108501 | SEMICONDUCTOR DEVICE - In an active region, p | 04-23-2015 |
20150108502 | HEAT DISSIPATION SUBSTRATE AND METHOD FOR PRODUCING SAME - The present invention relates to a heat dissipation substrate, which is a composite substrate composed of two layers, and which is characterized in that a surface layer (first layer) ( | 04-23-2015 |
20150108503 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device of the present disclosure includes a semiconductor layer provided on a main surface of a substrate. A cell region is provided with a gate insulating film disposed on the semiconductor layer and a gate electrode disposed on the gate insulating film, and a wiring region is provided with a field insulating film disposed on the semiconductor layer and a gate wire disposed on the field insulating film. An end of the field insulating film has a convex shape in a cross section perpendicular to the main surface of the substrate, and an upper surface of the field insulating film is rougher than an upper surface of a portion of the gate wire below which the field insulating film is not disposed. | 04-23-2015 |
20150108504 | METHOD FOR PRODUCING 3C-SIC EPITAXIAL LAYER, 3C-SIC EPITAXIAL SUBSTRATE, AND SEMICONDUCTOR DEVICE - A 3C-SiC epitaxial layer is produced by a production method including: epitaxially growing a first 3C-SiC layer on a Si substrate; oxidizing the first 3C-SiC layer; removing an oxide film on a surface of the 3C-SiC layer; and epitaxially growing a second 3C-SiC layer on the 3C-SiC layer after the oxide film is removed. | 04-23-2015 |
20150108505 | Diamond Semiconductor System and Method - Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond material having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice. | 04-23-2015 |
20150115282 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating substrate, a semiconductor element secured to a top surface of the insulating substrate, a case formed of a resin and having a frame portion surrounding the semiconductor element, a metal support located above the insulating substrate and having an end secured to the frame portion, a holding-down portion extending downward from the metal support so as to prevent upwardly convex bending of the insulating substrate, and an adhesive bonding the insulating substrate and the case together. | 04-30-2015 |
20150115283 | SIC BIPOLAR JUNCTION TRANSISTOR WITH REDUCED CARRIER LIFETIME IN COLLECTOR AND A DEFECT TERMINATION LAYER - A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT ( | 04-30-2015 |
20150115284 | SEMICONDUCTOR DEVICE WITH JUNCTION TERMINATION EXTENSION - A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×10 | 04-30-2015 |
20150115285 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF SEMICONDUCTOR DEVICE | 04-30-2015 |
20150115286 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p | 04-30-2015 |
20150115287 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF SILICON CARBIDE SEMICONDUCTOR DEVICE | 04-30-2015 |
20150115288 | POWER SEMICONDUCTOR MODULE - A power semiconductor module includes a base plate as a metallic heat dissipating body, a first insulating layer on the base plate, and a first wiring pattern on the first insulating layer. On a predetermined region that is a part of the first wiring pattern, a second wiring pattern for a second layer is laminated via only a second insulating layer made of resin, thereby forming a pattern laminated region. A power semiconductor element is mounted in a region other than the pattern laminated region on the first wiring pattern. The base plate, the first insulating layer, the first wiring pattern, the second insulating layer, the second wiring pattern, and the power semiconductor element are integrally sealed with a transfer mold resin, thus obtaining the power semiconductor module. | 04-30-2015 |
20150115289 | HYBRID WIDE-BANDGAP SEMICONDUCTOR BIPOLAR SWITCHES - A hybrid semiconductor bipolar switch in which a normally-on high-voltage wide-bandgap semiconductor bipolar switch and a normally-off field effect transistor are connected in a cascode (Baliga-pair) configuration. The switch may be constructed as a stacked hybrid device where a discrete transistor is bonded on top of a bipolar switch. Power systems may use plural switches paired with anti-parallel diodes. | 04-30-2015 |
20150123145 | Semiconductor Device and Method for Producing the Same - A semiconductor device includes a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, including amorphous molybdenum nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided. | 05-07-2015 |
20150123146 | INCREASED SPACE BETWEEN EPITAXY ON ADJACENT FINS OF FINFET - A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxy is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxy on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume. | 05-07-2015 |
20150123147 | SEMICONDUCTOR DEVICES AND FABRICATION METHOD THEREOF - A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate; and forming a first gate structure on the semiconductor substrate. The method also includes forming offset spacers doped with a certain type of ions to increase an anti-corrosion ability of the offset spacers on both sides of the first gate structure by a stability doping process; and forming trenches in the semiconductor substrate at both sides of the first gate structures. Further, the method includes forming stress layers in the trenches. | 05-07-2015 |
20150123148 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - [Problem] To provide a semiconductor device in which the surface of a metal electrode arranged on the outermost surface can be made flat or smooth, and a method for producing said semiconductor device. | 05-07-2015 |
20150123149 | Semiconductor Device and Method for Producing the Same - A semiconductor device comprises a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, comprising amorphous metal nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided. | 05-07-2015 |
20150129891 | MULTI-LAYER SEMICONDUCTOR DEVICE STRUCTURES WITH DIFFERENT CHANNEL MATERIALS - Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer and a second device layer formed on a first device layer. The first device layer is formed on a substrate and includes a first channel structure configured to conduct a first current, the first channel structure including a first material capable of sustaining a first processing temperature. The second device layer includes a second channel structure configured to conduct a second current, the second channel structure including a second material capable of sustaining a second processing temperature, the second processing temperature being equal to or lower than the first processing temperature. | 05-14-2015 |
20150129892 | Wafer-Level Chip Scale Package - A wafer-level chip scale package is disclosed, including a chip including a substrate and a GaN transistor disposed on the substrate. The GaN transistor includes a first electrode, a dielectric layer disposed on the chip, and a redistribution trace disposed on the first dielectric layer and electrically connected with the first electrode, wherein the redistribution trace has a linear side and a curved side on opposite sides along its longitudinal direction. | 05-14-2015 |
20150129893 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device that can achieve both low on-resistance and high withstand voltage, while reducing the device size, improving the manufacturing yield, and reducing the cost. The semiconductor device | 05-14-2015 |
20150129894 | WIDE BAND GAP SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF - A silicon carbide epitaxial layer formed by a low concentration wide band gap semiconductor of a first conductivity type is formed on the surface of a silicon carbide substrate formed by a high concentration wide band gap semiconductor of the first conductivity type. A Schottky electrode is formed on the silicon carbide epitaxial layer. The interface between the Schottky electrode and the silicon carbide epitaxial layer is used as a Schottky interface. Plural impurity regions of a second conductivity type are disposed at predetermined intervals in a lateral direction, in the silicon carbide epitaxial layer, at a position in the lower portion of the Schottky electrode in the depth direction. Because of the shape of the impurity regions, any leak current can be suppressed without raising the ON-resistance. | 05-14-2015 |
20150129895 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer. Thus, the p type SiC layer can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer from remaining on the side surface of the trench. | 05-14-2015 |
20150129896 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm. A method for manufacturing a semiconductor device according to the present invention includes: a step of forming a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, on the surface of a first conductive-type SiC semiconductor layer; and a step for heat treating the Schottky metal whilst the surface thereof is exposed, and structuring the junction of the SiC semiconductor layer to the Schottky metal to be planar, or to have recesses and protrusions of equal to or less than 5 nm. | 05-14-2015 |
20150129897 | Pretreatment Method for Reduction and/or Elimination of Basal Plane Dislocations Close to Epilayer/Substrate Interface in Growth of SiC Epitaxial Films - Non-destructive pretreatment methods are generally provided for a surface of a SiC substrate with substantially no degradation of surface morphology thereon. In one particular embodiment, a molten mixture (e.g., including KOH and a buffering agent) is applied directly onto the surface of the SiC substrate to form a treated surface thereon. An epitaxial film (e.g., SiC) can then be grown on the treated surface to achieve very high (e.g., up to and including 100%) BPD to TED conversion rate close to the epilayer/substrate interface. | 05-14-2015 |
20150137142 | Junction Field Effect Transistor Cell with Lateral Channel Region - A semiconductor device includes a junction field effect transistor cell with a top gate region, a lateral channel region and a buried gate region. The lateral channel region is arranged between the top gate region and the buried gate region along a vertical direction with respect to a first surface of a semiconductor body. The lateral channel region comprises at least two first zones of a first conductivity type and at least one second zone of a second conductivity type, wherein the first and second zones alternate along the vertical direction. The embodiments provide well-defined channel widths and facilitate the adjustment of pinch-off voltages as well as the manufacture of normally-off junction field effect transistor cells. | 05-21-2015 |
20150137143 | Junction Field Effect Transistor Cell with Lateral Channel Region - A junction field effect transistor cell of a semiconductor device includes a top gate region, a lateral channel region and a buried gate region arranged along a vertical direction. The lateral channel region includes first zones of a first conductivity type and second zones of a second conductivity type which alternate along a lateral direction perpendicular to the vertical direction. A pinch-off voltage of the junction field effect transistor cell does not depend, or only to a low degree depends, on a vertical extension of the lateral channel region. | 05-21-2015 |
20150137144 | Predetermined Kerf Regions and Methods of Fabrication Thereof - In one embodiment, the semiconductor die includes a selective epitaxial layer including device regions, and a masking structure disposed around sidewalls of the epitaxial layer. The masking structure is part of an exposed surface of the semiconductor die. | 05-21-2015 |
20150137145 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method. A semiconductor device includes: a silicon carbide substrate; a first-conductive-type first silicon carbide layer provided on a first principal surface of the silicon carbide substrate; a second-conductive-type first silicon carbide region formed at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region formed at a surface of the first silicon carbide region; a second-conductive-type third silicon carbide region formed below the second silicon carbide region; a trench piercing through the second silicon carbide region to reach the third silicon carbide region; a gate insulating film; a gate electrode; an interlayer insulating film with which the gate electrode is covered; a first electrode that is formed on the second silicon carbide region and the interlayer insulating film in a side surface of the trench while containing a metallic element selected from a group consisting of Ni, Ti, Ta, Mo, and W; a second electrode that is formed on the third silicon carbide region in a bottom portion of the trench and the first electrode while containing Al; a first main electrode formed on the second electrode; and a second main electrode formed on a second principal surface of the silicon carbide substrate. | 05-21-2015 |
20150137146 | TRANSISTOR DEVICE - Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate. | 05-21-2015 |
20150137147 | CMOS WITH DUAL RAISED SOURCE AND DRAIN FOR NMOS AND PMOS - An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material. | 05-21-2015 |
20150144960 | TAPERED GATE ELECTRODE FOR SEMICONDUCTOR DEVICES - The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer. | 05-28-2015 |
20150144961 | HIGH FREQUENCY DEVICE AND METHOD OF MANUFACTURING THE SAME - A high frequency device includes: a capping layer formed on an epitaxial structure; source and drain electrodes formed on the capping layer; a multilayer insulating pattern formed on entire surfaces of the source and drain electrodes and the capping layer in a step shape; a T-shaped gate passing through the multilayer insulating pattern and the capping layer to be in contact with the epitaxial structure; and a passivation layer formed along entire surfaces of the T-shaped gate and the multilayer insulating pattern. | 05-28-2015 |
20150144962 | COMPLEMENTARILY STRAINED FINFET STRUCTURE - A complementary fin field-effect transistor (FinFET) includes a p-type device having a p-channel fin. The p-channel fin may include a first material that is lattice mismatched relative to a semiconductor substrate. The first material may have a compressive strain. The FinFET device also includes an n-type device having an re-channel fin. The n-channel fin may include a second material having a tensile strain that is lattice mismatched relative to the semiconductor substrate. The p-type device and the n-type device cooperate to form the complementary FinFET device. | 05-28-2015 |
20150144963 | SILICON CARBIDE EPI-WAFER AND METHOD OF FABRICATING THE SAME - A method of fabricating an epi-wafer includes providing a wafer in a susceptor, and growing an epi-layer on the wafer. The growing of the epi-layer on the wafer includes a first process of supplying a first input quantity of a raw material to the susceptor, and a second process of supplying a second input quantity of the raw material to the susceptor. The first input quantity is smaller than the second input quantity. An epi-wafer includes a wafer and an epi-layer formed on the wafer. Surface defects of the wafer are 1 ea/cm | 05-28-2015 |
20150144964 | SILICON CARBIDE EPI-WAFER AND METHOD OF FABRICATING THE SAME - A method of fabricating an epi-wafer includes providing a wafer in a susceptor, performing a surface treatment on the wafer by heating the susceptor and supplying a surface treatment gas, and growing an epi-layer on the wafer. An epi-wafer includes a wafer, and an epi-layer formed on the wafer. Surface defects of the wafer are 0.5 ea/cm | 05-28-2015 |
20150144965 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF SILICON CARBIDE SEMICONDUCTOR DEVICE - A p-type region, a p | 05-28-2015 |
20150144966 | SCHOTTKY DIODE WITH REDUCED FORWARD VOLTAGE - A semiconductor component includes a semiconductor body of a first conduction type and a metal layer on the semiconductor body, wherein the metal layer forms with the semiconductor body a Schottky contact along a contact surface. A doping concentration of the first conduction type on the contact surface varies along a direction of the contact surface. | 05-28-2015 |
20150144967 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer made of first conductivity type SiC; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film. | 05-28-2015 |
20150295023 | SCHOTTKY-BARRIER DEVICE AND RELATED SEMICONDUCTOR PRODUCT - In one general aspect, a power rectifier device can include a drift layer including silicon carbide of n-type conductivity, and a Schottky electrode disposed on the drift layer where the Schottky electrode and a surface of the drift layer can provide a Schottky contact. The power rectifier device can also include an array of p-type regions disposed underneath the Schottky electrode. | 10-15-2015 |
20150295048 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a silicon carbide layer, a body region, a source region, a gate insulating film, a gate electrode, a source electrode, a first impurity region, and a second impurity region. The second impurity region is disposed within the silicon carbide layer so as to connect the body region and the first impurity region to each other, and has a second conductivity type. An impurity concentration in the second impurity region is equal to or higher than an impurity concentration in the silicon carbide layer and equal to or lower than a lower limit of an impurity concentration in the body region. | 10-15-2015 |
20150295049 | EPITAXIAL WAFER AND SWITCH ELEMENT AND LIGHT-EMITTING ELEMENT USING SAME - An epitaxial wafer includes an epitaxial layer disposed on a substrate. The epitaxial layer includes a first semiconductor layer disposed on the substrate and a second semiconductor layer disposed on the first semiconductor layer and having a thickness that is thicker than that of the first semiconductor layer. A surface defect density of the second semiconductor layer is 0.1/cm | 10-15-2015 |
20150295050 | SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE AND METHODS FOR MANUFACTURING THEM - A silicon carbide substrate capable of reducing on-resistance and improving yield of semiconductor devices is made of single-crystal silicon carbide, and sulfur atoms are present in one main surface at a ratio of not less than 60×10 | 10-15-2015 |
20150295059 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A MOSFET includes an SiC layer including main surfaces. The SiC layer includes an a type drift region, a p type body region, and an n type source region. The MOSFET further includes a gate insulating film formed to be located on a channel region, a gate electrode formed to be located above the channel region, the gate insulating film being sandwiched between said gate electrode and said channel region, and a connection electrode which includes a contact portion having a width smaller than a width of the gate electrode, has electric resistance lower than electric resistance of the gate electrode, and is formed on the gate electrode. | 10-15-2015 |
20150295095 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A first main surface of a silicon carbide substrate has a flat surface located in an element portion and a side wall surface located in a termination portion. The silicon carbide substrate has an impurity layer having a portion located at each of the flat surface of the first main surface and a second main surface. On the flat surface, a Schottky electrode is in contact with the impurity layer. On the second main surface, a counter electrode is in contact with the impurity layer. An insulating film covers the side wall surface. The side wall surface is inclined by not less than 50° and not more than 80° relative to a {000-1} plane. This suppresses the leakage current of a silicon carbide semiconductor device. | 10-15-2015 |
20150295134 | TRANSPARENT ELECTRONIC SYSTEM AND METHOD - A system and method for transparent diamond semiconductor electronics are provided. The system may include a transparent substrate, a diamond active layer, a conductive layer, and an application that incorporates the transparent layer, the diamond layer, and the conductive layer. The method may include selecting a transparent substrate, creating a diamond material having a diamond lattice on the substrate, introducing acceptor dopant atoms to the diamond lattice to create ion tracks, introducing substitutional dopant atoms, annealing the diamond lattice, adding a conductive layer to the diamond lattice, and incorporating the substrate, and the diamond lattice, and the conductive layer into an application. | 10-15-2015 |
20150303126 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating substrate including a substrate, a metal pattern formed on an upper surface of the substrate, and a metal film formed on a lower surface of the substrate, a semiconductor element fixed on the metal pattern, a case surrounding the metal pattern and having a contact portion maintained in contact with the upper surface of the substrate, and an adhesive with which the case and a portion of the upper surface of the substrate outside a portion maintained in contact with the contact portion are bonded together, wherein a plurality of through holes are formed in a peripheral portion of the case, the through holes extending vertically through the case, and wherein the metal film exists in at least part of a place right below the contact portion. | 10-22-2015 |
20150303218 | METHOD TO CO-INTEGRATE OPPOSITELY STRAINED SEMICONDUCTOR DEVICES ON A SAME SUBSTRATE - Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differently-strained regions may have opposite types of strain. The strains in the different regions may be formed independently. | 10-22-2015 |
20150303266 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device has a silicon carbide substrate, a gate insulating film, and a gate electrode. Silicon carbide substrate includes a first impurity region having a first conductivity type, a well region being in contact with the first impurity region and having a second conductivity type which is different from the first conductivity type, and a second impurity region separated from the first impurity region by the well region and having the first conductivity type. The gate insulating film is in contact with the first impurity region and the well region. The gate electrode is in contact with the gate insulating film and is arranged opposite to the well region with respect to the gate insulating film. A specific on-resistance at a voltage which is half a gate driving voltage applied to the gate electrode is smaller than twice the specific on-resistance at the gate driving voltage. | 10-22-2015 |
20150303267 | SILICON CARBIDE SEMICONDUCTOR DEVICE - First and second ranges of a silicon carbide film have an interface. The first range includes: a first breakdown voltage holding layer having a first conductivity type; and an outer edge embedded region provided at an interface in the outer edge portion and having a second conductivity type. The second range includes a second breakdown voltage holding layer having the first conductivity type. A semiconductor element is formed in the second range. The first range includes: a central section facing the semiconductor element in the central portion in a thickness direction; and an outer edge section facing the semiconductor element in the outer edge portion in the thickness direction. At the interface, the outer edge section includes a portion having an impurity concentration different from the impurity concentration of the central section. | 10-22-2015 |
20150303271 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - This silicon carbide semiconductor device includes: a silicon carbide semiconductor layer; a gate insulating layer which is arranged over the silicon carbide semiconductor layer and which includes a silicon oxide film; a gate electrode which is arranged on the gate insulating layer; and a carbon transition layer which is interposed between the silicon carbide semiconductor layer and the silicon oxide film and which has a carbon atom concentration is 10% to 90% of a carbon atom concentration of the silicon carbide semiconductor layer. In a region of the carbon transition layer which is located closer to the silicon oxide film than a position where a nitrogen atom concentration becomes the highest is, a ratio of an integral of nitrogen atom concentrations to an integral of carbon atom concentrations is equal to or greater than 0.11. | 10-22-2015 |
20150303287 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element with a plurality of gates, an emitter pattern insulated from the plurality of gates and an emitter electrode formed on the emitter pattern, the semiconductor element being formed such that a main current flows into the emitter electrode via the emitter pattern, a first solder formed on a part of the emitter electrode, a second solder formed on a part of the emitter electrode apart from the first solder, and a terminal connected to the emitter electrode by means of the first solder and the second solder, wherein the semiconductor element includes a first solder region, a second solder region and an intermediate region, a density of the gates in each of the solder regions are equal, and a current density of the main current in the intermediate region is lower than current densities of the main currents in the other solder regions. | 10-22-2015 |
20150303297 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is on the field oxide film, going around a periphery of the cell region, and electrically connected to the second gate electrode. The gate wiring is a silicide of a constituting substance of the second gate electrode. | 10-22-2015 |
20150311076 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A silicon carbide substrate including a first impurity region, a well region, and a second impurity region separated from the first impurity region by the well region is prepared. A silicon dioxide layer is formed in contact with the first impurity region and the well region. A gate electrode is formed on the silicon dioxide layer. A silicon-containing material is formed on the first impurity region. The silicon-containing material is oxidized. The silicon dioxide layer includes a first silicon dioxide region on the first impurity region and a second silicon dioxide region on the well region. The thickness of the first silicon dioxide region is greater than the thickness of the second silicon dioxide region. Consequently, a silicon carbide semiconductor device capable of achieving improved switching characteristics while suppressing a decrease in drain current, and a method of manufacturing the same can be provided. | 10-29-2015 |
20150311203 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, and a core device and a dummy device disposed on the semiconductor substrate. The core device includes a first gate disposed on the semiconductor substrate and a first stress layer disposed on opposing sides of the first gate. The dummy device includes a second gate disposed on the semiconductor substrate and a second stress layer disposed on opposing sides of the second gate. | 10-29-2015 |
20150311278 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor device of the present invention includes a semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode being in contact with a surface of the semiconductor layer. The semiconductor layer includes a drift layer that forms the surface of the semiconductor layer and a high-resistance layer that is formed on a surface layer portion of the drift layer and that has higher resistance than the drift layer. The high-resistance layer is formed by implanting impurity ions from the surface of the semiconductor layer and then undergoing annealing treatment at less than 1500° C. | 10-29-2015 |
20150311290 | EPITAXIAL WAFER AND SWITCH ELEMENT AND LIGHT-EMITTING ELEMENT USING SAME - An epitaxial wafer comprises an epitaxial layer disposed on a substrate. The epitaxial layer comprises first to third semiconductor layers. The third semiconductor layer has a thickness that is thicker than that of the first semiconductor layer. A second doping density of the second semiconductor layer is between a first doping density of the first semiconductor layer and a third doping density of the third semiconductor layer. | 10-29-2015 |
20150311325 | IGBT STRUCTURE ON SIC FOR HIGH PERFORMANCE - An IGBT device includes an IGBT stack including a first surface and a second surface opposite the first surface, a collector contact over the first surface of the IGBT stack, a gate contact on the second surface of the IGBT stack, and an emitter contact on the second surface of the IGBT stack. The IGBT stack includes an injector region, which provides the first surface of the IGBT stack, a drift region over the injector region opposite the first surface, a pair of junction implants in the IGBT stack along the second surface of the IGBT stack, and a field termination region between the pair of junction implants in the IGBT stack along the second surface of the IGBT stack. | 10-29-2015 |
20150311328 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes semiconductor layers of a first conductivity-type and a second conductivity-type stacked on a silicon carbide semiconductor and having differing impurity concentrations. Trenches disposed penetrating the semiconductor layer of the second conductivity-type form a planar striped pattern; and a gate electrode is disposed therein through a gate insulation film. First and second semiconductor regions respectively of the first and the second conductivity-types have impurity concentrations exceeding that of the semiconductor layer of the second conductivity-type and are selectively disposed therein. The depth of the second semiconductor region exceeds that of the semiconductor layer of the second conductivity-type, but not that of the trenches. The second semiconductor region is arranged at given intervals along the length of the trenches. In the silicon carbide semiconductor below the trench bottoms, a third semiconductor region of the second conductivity-type and having a floating potential is disposed covering the trench bottoms. | 10-29-2015 |
20150311375 | VARIABLE RANGE PHOTODETECTOR AND METHOD THEREOF - A method of making and a photodetector comprising a substrate; a p-type or n-type layer; first and second region each having polarizations, a first interface therebetween, the magnitudes and directions of the first and second polarizations being such that a scalar projection of second polarization on the growth direction relative to the scalar projection of the first polarization projected onto the growth direction is sufficient to create a first interface charge; and a third region suitable for forming one of an n-metal or p-metal contact thereon having a third polarization, a second interface between the second and third regions, the third polarization having a scalar projection on the growth direction that, relative to scalar projection of the second polarization onto the growth direction, is sufficient to create a second interface charge; the first and second interface charges creating an electrostatic potential barrier to carriers defining a predetermined wavelength range. | 10-29-2015 |
20150318279 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - Semiconductor devices and fabrication methods are provided. A semiconductor substrate is provided having dummy gate structures formed thereon. A stress layer is formed in the semiconductor substrate between adjacent dummy gate structures. A first dielectric layer is formed on the semiconductor substrate, the stress layers, and the sidewall spacers of the dummy gate structures, exposing dummy gate electrode layers. Gate structures are formed in the dielectric layer to replace the dummy gate structures. The gate structures include functional gate structures and at least one non-functional gate structure. The at least one non-functional gate structure is removed to form at least one second opening in the first dielectric layer. At least one third opening is formed in the semiconductor substrate at a bottom of the at least one second opening. A second dielectric layer is formed in the at least one second opening and the at least one third opening. | 11-05-2015 |
20150318357 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer of a first conductivity type; a field insulating film formed on a surface of the silicon carbide semiconductor layer; a Schottky electrode formed on the surface of the silicon carbide semiconductor layer on an inner periphery side relative to the field insulating film, the Schottky electrode being formed to overlap onto the field insulating film; a front-surface electrode that covers the Schottky electrode and extends on the field insulating film beyond a peripheral edge of the Schottky electrode; and a terminal well region of a second conductivity type that is formed to be in contact with a part of the Schottky electrode in an upper part of the silicon carbide semiconductor layer and extends in the silicon carbide semiconductor layer on an outer periphery side relative to a peripheral edge of the front-surface electrode. | 11-05-2015 |
20150318358 | Semiconductor Devices Including Polar Insulation Layer Capped by Non-Polar Insulation Layer - Illustrative embodiments of semiconductor devices including a polar insulation layer capped by a non-polar insulation layer, and methods of fabrication of such semiconductor devices, are disclosed. In at least one illustrative embodiment, a semiconductor device may comprise a semiconductor substrate, a polar insulation layer disposed on the semiconductor substrate and comprising a Group V element configured to increase a carrier mobility in at least a portion of the semiconductor substrate, and a non-polar insulation layer disposed above the polar insulation layer. | 11-05-2015 |
20150318372 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention has a MIS structure that includes a semiconductor layer, a gate insulating film in contact with the semiconductor layer, and a gate electrode formed on the gate insulating film, and the gate insulating film includes an AlON layer with a nitrogen composition of 5% to 40%. A semiconductor device is thereby provided with which electron trapping in the gate insulating film can be reduced and shifting of a threshold voltage V | 11-05-2015 |
20150318389 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - When a gate length is reduced for the purpose of reducing on-resistance in a SiC DOMSFET, it is difficult to achieve both of the reduction of on-resistance by the reduction of gate length and the high element withstand voltage at the same time. In the present invention, a body layer is formed after the source diffusion layer region is formed and then a portion of the source diffusion layer region is recessed. Because of the presence of the body layer, the distances between the source diffusion region and respective end portions can be increased, a depletion layer is effectively expanded, and electric field concentration at the end portions can be suppressed, thereby improving withstand voltage characteristics. Consequently, the present invention can provide a silicon carbide semiconductor device that achieves both of the reduction of channel resistance by the reduction of gate length and the high element withstand voltage at the same time. | 11-05-2015 |
20150325571 | SWITCHING DEVICE - A switching device according to the present invention is a switching device for switching a load by on-off control of voltage, and includes an SiC semiconductor layer where a current path is formed by on-control of the voltage, a first electrode arranged to be in contact with the SiC semiconductor layer, and a second electrode arranged to be in contact with the SiC semiconductor layer fo |