| Entries |
| Document | Title | Date |
|---|
| 20080197358 | WIDE-BANDGAP SEMICONDUCTOR DEVICES | 08-21-2008 |
| 20080197359 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device has a buffer layer formed on a conductive SiC substrate, an AlxGa1-xN layer formed on the buffer layer in which an impurity for reducing carrier concentration from an unintentionally doped donor impurity is added and in which the Al composition x is 0| 08-21-2008 | |
| 20080210948 | High-Heat-Resistive Semiconductor Device - The outer surface of a wide-gap semiconductor device is coated with a synthetic polymer compound containing one or more silicon-containing polymer having a bridged structure formed by a siloxane (Si—O—Si bond structure). The synthetic polymer compound may include, for example, a silicon-containing polymer which has one or more reactive groups (A′) selected from Si—R | 09-04-2008 |
| 20080210949 | SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE USING THE SAME - A semiconductor substrate includes: an AlN layer provided on a silicon substrate; an AlGaN layer that is provided on the AlN layer and has an Al composition ratio of 0.3 to 0.6; and a GaN layer provided on the AlGaN layer. | 09-04-2008 |
| 20080217625 | NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type Al | 09-11-2008 |
| 20080224148 | SEMICONDUCTOR SENSING DEVICE - A semiconductor sensing device in which a sensing layer is exposed to a medium being tested in an area below and/or adjacent to a contact. In one embodiment, the device comprises a field effect transistor in which the sensing layer is disposed below a gate contact. The sensing layer is exposed to the medium by one or more perforations that are included in the gate contact and/or one or more layers disposed above the sensing layer. The sensing layer can comprise a dielectric layer, a semiconductor layer, or the like. | 09-18-2008 |
| 20080230784 | Cascode circuit employing a depletion-mode, GaN-based fet - A circuit includes an input drain, source and gate nodes. The circuit also includes a group III nitride depletion mode FET having a source, drain and gate, wherein the gate of the depletion mode FET is coupled to a potential that maintains the depletion mode FET in its on-state. In addition, the circuit further includes an enhancement mode FET having a source, drain and gate. The source of the depletion mode FET is serially coupled to the drain of the enhancement mode FET. The drain of the depletion mode FET serves as the input drain node, the source of the enhancement mode FET serves as the input source node and the gate of the enhancement mode FET serves as the input gate node. | 09-25-2008 |
| 20080230785 | Termination and contact structures for a high voltage GaN-based heterojunction transistor - A semiconductor device is provided that includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A termination layer, which is disposed on the second active layer, includes InGaN. Source, gate and drain contacts are disposed on the termination layer. | 09-25-2008 |
| 20080230786 | High temperature performance capable gallium nitride transistor - A transistor device capable of high performance at high temperatures. The transistor comprises a gate having a contact layer that contacts the active region. The gate contact layer is made of a material that has a high Schottky barrier when used in conjunction with a particular semiconductor system (e.g., Group-III nitrides) and exhibits decreased degradation when operating at high temperatures. The device may also incorporate a field plate to further increase the operating lifetime of the device. | 09-25-2008 |
| 20080237605 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes: a first semiconductor layer which is made of a first group III nitride semiconductor; a cap layer which is formed on the first semiconductor layer, which is made of a second group III nitride semiconductor, and which has an opening for exposing the first semiconductor layer; and a source electrode and a drain electrode which are formed on the cap layer so as to oppose to each other with the opening interposed. A gate electrode is formed on the bottom face of the opening with an insulating film interposed. The insulating film is formed on at least a part of the first semiconductor layer which is exposed through the opening. | 10-02-2008 |
| 20080237606 | COMPOUND SEMICONDUCTOR DEVICE - A compound semiconductor device having a transistor structure, includes a substrate, a first layer formed on the substrate and comprising GaN, a second layer formed over the first layer and containing InN whose lattice constant is larger than the first layer, a third layer formed over the second layer and comprising GaN whose energy bandgap is smaller than the second layer, and a channel region layer formed on the third layer. | 10-02-2008 |
| 20080237607 | LIGHT EMITTING ELEMENT AND METHOD OF MAKING SAME - A light emitting element has a substrate of gallium oxides and a pn-junction formed on the substrate. The substrate is of gallium oxides represented by: (Al | 10-02-2008 |
| 20080246040 | LIGHT EMITTING DEVICE HAVING LIGHT EMITTING ELEMENTS - A light-emitting device operating on a high drive voltage and a small drive current. LEDs ( | 10-09-2008 |
| 20080258150 | METHOD TO FABRICATE III-N FIELD EFFECT TRANSISTORS USING ION IMPLANTATION WITH REDUCED DOPANT ACTIVATION AND DAMAGE RECOVERY TEMPERATURE - Structures to reduce dopant activation temperatures for ion implantation in III-N transistors, using low aluminum content layers in proximity to the conducting channel, are disclosed. A method to increase the temperature at which structures can be annealed by annealing in an active nitrogen ambient, for example, in NH | 10-23-2008 |
| 20080258151 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are a light emitting device and a method for manufacturing the same. A light emitting diode comprises a plurality of Un-GaN layers and a plurality of N-type semiconductor layers, an active layer on the N-type semiconductor layer, and a P-type semiconductor layer on the active layer, wherein at least two of the Un-GaN layers and at least two of the N-type semiconductor layers are alternatively stacked on each other. | 10-23-2008 |
| 20080265258 | Group III Nitride Semiconductor Device and Epitaxial Substrate - Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be decreased. In a high electron mobility transistor | 10-30-2008 |
| 20080265259 | GaN-BASED PERMEABLE BASE TRANSISTOR AND METHOD OF FABRICATION - An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same. | 10-30-2008 |
| 20080272377 | Gallium Nitride Substrate and Gallium Nitride Film Deposition Method - Affords high-carrier-concentration, low-cracking-incidence gallium nitride substrates and methods of forming gallium nitride films. A gallium nitride film | 11-06-2008 |
| 20080272378 | METHOD FOR FORMING A NITRIDE SEMICONDUCTOR LAYER AND METHOD FOR SEPARATING THE NITRIDE SEMICONDUCTOR LAYER FROM THE SUBSTRATE - There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point. | 11-06-2008 |
| 20080277667 | Method of producing III-nitride substrate | 11-13-2008 |
| 20080283844 | Method for manufacturing a field effect transistor having a field plate - An opening for forming a gate electrode is provided by a first photoresist pattern formed on an insulating film. Reactive ion etching by inductively coupled plasma is applied to the insulating film through the first photoresist pattern as a mask to thereby expose the surface of a GaN semiconductor layer, evaporating thereon a gate metal such as NiAu, thereby forming the gate electrode by self-aligned process. This prevents an oxidized film from being formed on the surface of the semiconductor layer. After the gate electrode is formed, a second photoresist pattern is formed to form a field plate on the gate electrode and the insulating film through the second photoresist pattern as a mask. Thereby, Ti having a high adhesiveness with an insulating film made of SiN or the like can be used as a field plate metal. | 11-20-2008 |
| 20080290346 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a light emitting device and a manufacturing method thereof. The light emitting device comprises a first conductive semiconductor layer with a lower surface being uneven in height, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer. | 11-27-2008 |
| 20080290347 | Gallium Nitride Semiconductor and Method of Manufacturing the Same - The present invention provides to a gallium nitride (GaN) semiconductor and a method of manufacturing the same, capable of reducing crystal defects caused by a difference in lattice parameters, and minimizing internal residual stress. In particular, since a high-quality GaN thin film is formed on a silicon wafer, manufacturing costs can be reduced by securing high-quality wafers with a large diameter at a low price, and applicability to a variety of devices and circuit can also be improved. | 11-27-2008 |
| 20080296584 | III-V Nitride Semiconductor Layer-Bonded Substrate and Semiconductor Device - Affords III-V nitride semiconductor layer-bonded substrates from which semiconductor device of enhanced properties can be manufactured, and semiconductor devices incorporating the III-V nitride semiconductor layer-bonded substrates. The III-V nitride semiconductor layer-bonded substrate, in which a III-V nitride semiconductor layer and a base substrate are bonded together, is characterized in that thermal expansion coefficient difference between the III-V nitride semiconductor layer and the base substrate is 4.5×10 | 12-04-2008 |
| 20080296585 | GROWTH METHOD OF GaN CRYSTAL, AND GaN CRYSTAL SUBSTRATE - A method of producing a GaN crystal is directed to growing a GaN crystal on a GaN seed crystal substrate. The method includes the steps of preparing a GaN seed crystal substrate including a first dopant such that the thermal expansion coefficient of the GaN seed crystal substrate becomes greater than that of the GaN crystal, and growing the GaN crystal to a thickness of at least 1 mm on the GaN seed crystal substrate. Accordingly, there can be provided a method of producing a GaN crystal that can suppress generation of a crack and grow a thick GaN crystal, and a GaN crystal substrate. | 12-04-2008 |
| 20080303032 | Bulk Mono-Crystalline Gallium-Containing Nitride and Its Application - Bulk monocrystalline gallium-containing nitride, grown on the seed at least in the direction essentially perpendicular to the direction of the seed growth, essentially without propagation of crystalline defects as present in the seed, having the dislocation density not exceeding 10 | 12-11-2008 |
| 20080303033 | FORMATION OF NITRIDE-BASED OPTOELECTRONIC AND ELECTRONIC DEVICE STRUCTURES ON LATTICE-MATCHED SUBSTRATES - A method of forming an AlInGaN alloy-based electronic or optoelectronic device structure on a nitride substrate and subsequent removal of the substrate. An AlInGaN alloy-based electronic or optoelectronic device structure formed on a nitride substrate is freed from the substrate on which it was grown. | 12-11-2008 |
| 20080303034 | Light-emitting gallium nitride-based III-V group compound semiconductor device and manufacturing method thereof - A light-emitting gallium nitride-based III-V group compound semiconductor device and a manufacturing method thereof are disclosed. The light emitting device includes a substrate, a n-type semiconductor layer over the substrate, an active layer over the n-type semiconductor layer, a p-type semiconductor layer over the active layer, a conductive layer over the p-type semiconductor layer, a first electrode disposed on the conductive layer and a second electrode arranged on exposed part of the n-type semiconductor layer. A resistant reflective layer or a contact window is disposed on the p-type semiconductor layer, corresponding to the first electrode so that current passes beside the resistant reflective layer or by the contact window to the active layer for generating light. When the light is transmitted to the conductive layer for being emitted, it is not absorbed or shielded by the first electrode. Thus the current is distributed efficiently over the conductive layer. Therefore, both LED brightness and efficiency are improved. Moreover, adhesion between the conductive layer and the p-type semiconductor layer is improved so that metal peel-off problem during manufacturing processes can be improved. | 12-11-2008 |
| 20080303035 | COMPOUND SEMICONDUCTOR FILM, LIGHT EMITTING FILM, AND MANUFACTURING METHOD THEREOF - Provided are a compound semiconductor film which is manufactured at a low temperature and exhibits excellent p-type conductivity, and a light emitting film in which the compound semiconductor film and a light emitting material are laminated and with which high-intensity light emission can be realized. The compound semiconductor film has a composition represented by a Cu | 12-11-2008 |
| 20080308812 | Ga-Containing Nitride Semiconductor Single Crystal, Production Method Thereof, and Substrate and Device Using the Crystal - A Ga-containing nitride semiconductor single crystal characterized in that (a) the maximum reflectance measured by irradiating the Ga-containing nitride semiconductor single crystal with light at a wavelength of 450 nm is 20% or less and the difference between the maximum reflectance and the minimum reflectance is within 10%, (b) the ratio of maximum value to minimum value (maximum value/minimum value) of the dislocation density measured by a cathode luminescence method is 10 or less, and/or (c) the lifetime measured by a time-resolved photoluminescence method is 95 ps or more. | 12-18-2008 |
| 20080308813 | HIGH BREAKDOWN ENHANCEMENT MODE GALLIUM NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTORS WITH INTEGRATED SLANT FIELD PLATE - High breakdown enhancement mode gallium nitride (GaN) based high electron mobility transistors (HEMTs) with integrated slant field plates. These HEMTs have an epilayer structure comprised of AlGaN/GaN buffer. Before the formation of the gate electrode, a passivation layer is deposited, and then the opening for the gate is patterned. The passivation layer below the gate is etched using an etch condition that creates a slanted sidewalls. Then, the charge below the channel is removed either by Fluorine-based plasma treatment and/or by a recess etch. The gate metal is deposited with an angled rotation to form a gate structure with an inherent field plate with rounded edges. | 12-18-2008 |
| 20080308814 | GALLIUM NITRIDE SUBSTRATE AND GALLIUM NITRIDE LAYER FORMATION METHOD - There is disclosed a method for forming a gallium nitride layer of which resistivity is 1×10 | 12-18-2008 |
| 20080308815 | GaN Substrate, Substrate with an Epitaxial Layer, Semiconductor Device, and GaN Substrate Manufacturing Method - Affords a GaN substrate from which enhanced-emission-efficiency light-emitting and like semiconductor devices can be produced, an epi-substrate in which an epitaxial layer has been formed on the GaN substrate principal surface, a semiconductor device, and a method of manufacturing the GaN substrate. The GaN substrate is a substrate having a principal surface with respect to whose normal vector the [0001] plane orientation is inclined in two different off-axis directions. | 12-18-2008 |
| 20080308816 | TRANSISTORS FOR REPLACING METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTORS IN NANOELECTRONICS - Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET) logic cells substituted for existing MOSFET-based logic cells to produce revised integrated circuit designs. Integrated circuits can include JFETS where the channel comprises a wide bandgap semiconductor material and the gate comprises a narrow bandgap semiconductor material. Mixtures of JFET and MOSFET transistors can be included on an integrated circuit design. | 12-18-2008 |
| 20080315209 | Group III Nitride Semiconductor Device and Epitaxial Substrate - Affords a Group III nitride semiconductor device having a structure that can improve the breakdown voltage. A Schottky diode ( | 12-25-2008 |
| 20080315210 | High electron mobility transistor - A GaN-based semiconductor layer is stacked on a GaN-based single-crystal substrate. The GaN-based single-crystal substrate forms an electron transit layer, and the GaN-based semiconductor layer forms an electron supply layer. A principal growth plane of the GaN-based single-crystal substrate is an m-plane, and a principal growth plane of the GaN-based semiconductor layer formed on the GaN-based single-crystal substrate is also an m-plane. With such a layer structure, no piezoelectric field is generated since the m-plane is a nonpolar plane. This suppresses generation of a two-dimensional electron gas layer at the time when no gate voltage is applied and consequently enables achievement of a normally-off configuration. | 12-25-2008 |
| 20090001381 | Semiconductor device - A semiconductor device includes a substrate, laminated layers provided on the substrate. The laminated layers include an AlGaN barrier layer as an uppermost layer. A gate electrode is provided in a channel region of the laminated layers. A source electrode and a drain electrode are provided so as to face each other via the channel region interposed therebetween. A silicon nitride film is formed to cover an exposed surface of the laminated layers exposed via the gate electrode, the source electrode and the drain electrode. The silicon nitride film has characteristics that an etching rate thereof is in a range from 1 nm per/min to 2 nm/min for an etchant in which hydrofluoric acid having a concentration of 50 weight percent and ammonium fluoride having a concentration of 40 weight percent are mixed at a mixing ratio of 1:9. | 01-01-2009 |
| 20090008647 | Gallium nitride-on-silicon interface using multiple aluminum compound buffer layers - A thermal expansion interface between silicon (Si) and gallium nitride (GaN) films using multiple buffer layers of aluminum compounds has been provided, along with an associated fabrication method. The method provides a (111) Si substrate and deposits a first layer of AlN overlying the substrate by heating the substrate to a relatively high temperature of 1000 to 1200° C. A second layer of AlN is deposited overlying the first layer of AlN at a lower temperature of 500 to 800° C. A third layer of AlN is deposited overlying the second layer of AlN by heating the substrate to the higher temperature range. Then, a grading Al | 01-08-2009 |
| 20090008648 | GALLIUM NITRIDE-BASED SEMICONDUCTOR ELEMENT, OPTICAL DEVICE USING THE SAME, AND IMAGE DISPLAY APPARATUS USING OPTICAL DEVICE - A GaN-based semiconductor element which can suppress a leakage current generated during reverse bias application, an optical device using the same, and an image display apparatus using the optical device are provided. The GaN-based semiconductor element has a first GaN-based compound layer including an n-type conductive layer; a second GaN-based compound layer including a p-type conductive layer; and an active layer provided between the first GaN-based compound layer and the second GaN-based compound layer. In this GaN-based semiconductor element, the first GaN-based compound layer includes an underlayer having an n-type impurity concentration in the range of 3×10 | 01-08-2009 |
| 20090014728 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer and a first semiconductor element located in the first semiconductor layer. The semiconductor device also includes a second semiconductor layer of a transparent semiconductor material. The second semiconductor layer is disposed on the first semiconductor layer covering the first semiconductor element. The semiconductor device also includes a second semiconductor element located in the second semiconductor layer. The semiconductor device also includes a wire extending within the second semiconductor layer and electrically connecting the first and second semiconductor elements. | 01-15-2009 |
| 20090014729 | Semiconductor light emitting device including group III nitride semiconductor - A semiconductor light emitting device comprises: a substrate; a semiconductor stack formed on one of surfaces of the substrate, the semiconductor stack including an active layer composed of a group III nitride semiconductor having a substantially nonpolar or substantially semipolar plane as a main surface; a first electrode formed in a part of a first electrode surface which is the other surface of the substrate; and a second electrode formed on a second electrode surface opposite to the first electrode surface across the substrate and semiconductor stack. | 01-15-2009 |
| 20090032820 | Reliable Normally-Off III-Nitride Active Device Structures, and Related Methods and Systems - A field-effect transistor includes a first gate, a second gate held at a substantially fixed potential in a cascode configuration, and a semiconductor channel. The semiconductor channel has an enhancement mode portion and a depletion mode portion. The enhancement mode portion is gated to be turned on and off by the first gate, and has been modified to operate in enhancement mode. The depletion mode portion is gated by the second gate, and has been modified to operate in depletion mode and that is operative to shield the first gate from voltage stress. | 02-05-2009 |
| 20090039356 | PLANAR NONPOLAR M-PLANE GROUP III-NITRIDE FILMS GROWN ON MISCUT SUBSTRATES - A nonpolar III-nitride film grown on a miscut angle of a substrate. The miscut angle towards the <000-1> direction is 0.75° or greater miscut and less than 27° miscut towards the <000-1> direction. Surface undulations are suppressed and may comprise faceted pyramids. A device fabricated using the film is also disclosed. A nonpolar III-nitride film having a smooth surface morphology fabricated using a method comprising selecting a miscut angle of a substrate upon which the nonpolar III-nitride films are grown in order to suppress surface undulations of the nonpolar III-nitride films. A nonpolar III-nitride-based device grown on a film having a smooth surface morphology grown on a miscut angle of a substrate which the nonpolar III-nitride films are grown. The miscut angle may also be selected to achieve long wavelength light emission from the nonpolar film. | 02-12-2009 |
| 20090045410 | GaN SUBSTRATE AND SEMICONDUCTOR DEVICE PREPARED BY USING METHOD AND APPARATUS OF POLISHING GaN SUBSTRATE - In a polishing method of a GaN substrate according to this invention, first, while supplying a polishing solution | 02-19-2009 |
| 20090057684 | Nitride semiconductor device and method for producing nitride semiconductor device - A nitride semiconductor device includes: a semiconductor base layer made of a conductive group III nitride semiconductor having a principal plane defined by a nonpolar plane or a semipolar plane; an insulating layer formed on the principal plane of the semiconductor base layer with an aperture partially exposing the principal plane; a nitride semiconductor multilayer structure portion, formed on a region extending onto the insulating layer from the aperture, having a parallel surface parallel to the principal plane of the semiconductor base layer as well as a +c-axis side first inclined surface and a −c-axis side second inclined surface inclined with respect to the principal plane of the semiconductor base layer and including two types of group III nitride semiconductor layers at least having different lattice constants; a gate electrode formed to be opposed to the second inclined surface; a source electrode arranged to be electrically connected with the group III nitride semiconductor layers; and a drain electrode formed on a back surface of the semiconductor base layer opposite to the principal plane. | 03-05-2009 |
| 20090065785 | III-nitride power semiconductor device - A power semiconductor device that includes common conduction regions, charge compensation regions, each adjacent a respective common conduction region, and a stand off region over the common conduction regions and charge compensation regions. | 03-12-2009 |
| 20090065786 | PROCESS FOR PRODUCING THIN NITRIDE FILM ON SAPPHIRE SUBSTRATE AND THIN NITRIDE FILM PRODUCING APPARATUS - A method for growing a nitride thin film on a sapphire substrate, in which using no resists, miniaturization can be accomplished while relieving vexatious complication of the process; and a relevant device using nitride thin film. There is provided a method for growing a nitride thin film on a sapphire substrate, comprising irradiating a sapphire substrate having undergone high temperature hydrogen treatment with electron beams and depositing a nitride thin film on the substrate having undergone the electron beam irradiation by using the metal-organic chemical vapor deposition technique to thereby accomplish patterning of nitride thin film. | 03-12-2009 |
| 20090065787 | COMPOUND SEMICONDUCTOR STRUCTURE - A method for manufacturing a compound semiconductor structure, includes (a) selecting a conductive SiC substrate in accordance with color and resistivity and (b) epitaxially growing a GaN series compound semiconductor layer on the selected conductive SiC substrate. The step (a) preferably selects a conductive SiC substrate whose main color is green, whose conductivity type is n-type and whose resistivity is 0.08 Ωcm to 1×10 | 03-12-2009 |
| 20090072239 | Gallium oxide single crystal composite, process for producing the same, and process for producing nitride semiconductor film utilizing gallium oxide single crystal composite - Provided are: a gallium oxide single crystal composite, which can provide, for example, upon a crystal growth of a nitride semiconductor, a high-quality cubic crystal in which mixing of a hexagonal crystal is reduced to thereby realize dominant growth of a cubic crystal over hexagonal crystal, and which can be utilized as a substrate particularly suitable for epitaxial growth of cubic GaN; a process for producing the same; and a process for producing a nitride semiconductor film. The gallium oxide single crystal composite has a gallium nitride layer formed of cubic gallium nitride on a surface of the gallium oxide single crystal; the process for producing the gallium oxide single crystal composite includes subjecting the surface of gallium oxide single crystal to nitriding treatment using ECR plasma or RF plasma to form the gallium nitride layer formed of cubic gallium nitride on the surface of the gallium oxide single crystal; and further, the process for producing the nitride semiconductor film includes growing the nitride semiconductor film on the surface of the gallium oxide single crystal composite by an RF-MBE method. | 03-19-2009 |
| 20090072240 | III-Nitride Devices with Recessed Gates - III-nitride devices are described with recessed gates. In some embodiments, the material around the gates is formed by epitaxially depositing different III-nitride layers on a substrate and etching through at least the top two layers in the gate region. Because adjacent layers in the top three layers of the structure have different compositions, some of the layers act as etch stops to allow for precision etching. In some embodiments, a regrowth mask is used to prevent growth of material in the gate region. A gate electrode is deposited in the recess. | 03-19-2009 |
| 20090085043 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are a semiconductor light emitting device, which can improve characteristics of the semiconductor light emitting device such as a forward voltage characteristic and a turn-on voltage characteristic, increase light emission efficiency by lowering an input voltage, and increase reliability of the semiconductor light emitting device by a low-voltage operation, and a method of manufacturing the same. The semiconductor light emitting device includes: an n-type GaN semiconductor layer; an active layer formed on a gallium face of the n-type GaN semiconductor layer; a p-type semiconductor layer formed on the active layer; and an n-type electrode formed on a nitrogen face of the n-type GaN semiconductor layer and including a lanthanum (La)-nickel (Ni) alloy. | 04-02-2009 |
| 20090090917 | GaN single-crystal substrate and method for producing GaN single crystal - A GaN single-crystal substrate has a substrate surface in which polarity inversion zones are included. The number density of the polarity inversion zones in the substrate surface is not more than 20 cm | 04-09-2009 |
| 20090127564 | GaN Substrate Manufacturing Method, GaN Substrate, and Semiconductor Device - A GaN substrate manufacturing method characterized in including a step of processing the surface of a substrate composed of a GaN single crystal into a concavely spherical form, based on differences in orientation of the crystallographic axis across the substrate surface. Processing the GaN substrate surface into a concavely spherical form reduces, in the post-process GaN substrate surface, differences in orientation of the crystallographic axis with respect to a normal. Furthermore, employing to manufacture semiconductor devices a GaN substrate in which differences in orientation of the crystallographic axis have been reduced makes it possible to uniformize in device characteristics a plurality of semiconductor devices fabricated from a single GaN substrate, which contributes to improving yields in manufacturing the semiconductor devices. | 05-21-2009 |
| 20090140262 | FIELD-EFFECT TRANSISTOR - A field-effect transistor includes a carrier transport layer made of nitride semiconductor, a gate electrode having first and second sidewall surfaces on first and second sides, respectively, an insulating film formed directly on the gate electrode to cover at least one of the first and second sidewall surfaces, first and second ohmic electrodes formed on the first and second sides, respectively, a passivation film including a first portion extending from the first ohmic electrode toward the gate electrode to cover a surface area between the first ohmic electrode and the gate electrode and a second portion extending from the second ohmic electrode toward the gate electrode to cover a surface area between the second ohmic electrode and the gate electrode, wherein the insulating film is in direct contact with at least the first and second passivation film portions, and has a composition different from that of the passivation film. | 06-04-2009 |
| 20090152565 | PENDEO EPITAXIAL STRUCTURES AND DEVICES - A substrate comprising a trench lateral epitaxial overgrowth structure including a trench cavity, wherein the trench cavity includes a growth-blocking layer or patterned material supportive of a coalescent Pendeo layer thereon, on at least a portion of an inside surface of the trench. Such substrate is suitable for carrying out lateral epitaxial overgrowth to form a bridged lateral overgrowth formation overlying the trench cavity. The bridged lateral overgrowth formation provides a substrate surface on which epitaxial layers can be grown in the fabrication of microelectronic devices such as laser diodes, high electron mobility transistors, ultraviolet light emitting diodes, and other devices in which low dislocation density is critical. The epitaxial substrate structures of the invention can be formed without the necessity for deep trenches, such as are required in conventional Pendeo epitaxial overgrowth structures. | 06-18-2009 |
| 20090218578 | SEMICONDUCTOR DEVICE - A semiconductor device comprises an AlN layer, a GaN layer, and an AlGaN layer sequentially formed on a semiconductor substrate. A first opening extends through said GaN layer and said AlGaN layer and exposes part of an upper surface of the AlN layer. A second opening extends through the semiconductor substrate and exposes a part of a lower surface of the AlN layer, in a location facing the first opening. A upper electrode is exposed on an upper surface of the AlN layer in the first opening; and a lower electrode is disposed on a lower surface of the AlN layer in the second opening. | 09-03-2009 |
| 20090242897 | INDIUM GALLIUM NITRIDE-BASED OHMIC CONTACT LAYERS FOR GALLIUM NITRIDE-BASED DEVICES - Light emitting devices include a gallium nitride-based epitaxial structure that includes an active light emitting region and a gallium nitride-based outer layer, for example gallium nitride. A indium nitride-based layer, such as indium gallium nitride, is provided directly on the outer layer. A reflective metal layer or a transparent conductive oxide layer is provided directly on the indium gallium nitride layer opposite the outer layer. The indium gallium nitride layer forms a direct ohmic contact with the outer layer. An ohmic metal layer need not be used. Related fabrication methods are also disclosed. | 10-01-2009 |
| 20090242898 | METHOD OF CONTROLLING STRESS IN GALLIUM NITRIDE FILMS DEPOSITED ON SUBSTRATES - Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. | 10-01-2009 |
| 20090256159 | GaN semiconductor device - This invention discloses a GaN semiconductor device comprising a substrate; a metal-rich nitride compound thin film on the substrate; a buffer layer formed on the metal-rich nitride compound thin film, and a semiconductor stack layer on the buffer layer wherein the metal-dominated nitride compound thin film covers a partial upper surface of the substrate. Because metal-rich nitride compound is amorphous, the epitaxial growth direction of the buffer layer grows upwards in the beginning and then turns laterally, and the epitaxy defects of the buffer layer also bend with the epitaxial growth direction of the buffer layer. Therefore, the probability of the epitaxial defects extending to the semiconductor stack layer is reduced and the reliability of the GaN semiconductor device is improved. | 10-15-2009 |
| 20090261345 | METHOD FOR MANUFACTURING COMPLIANT SUBSTRATE, COMPLIANT SUBSTRATE MANUFACTURED THEREBY, GALLIUM NITRIDE BASED COMPOUND SEMICONDUCTOR DEVICE HAVING THE COMPLIANT SUBSTRATE AND MANUFACTURING METHOD THEREOF - A compliant substrate having a reduced stress, a method for manufacturing the same having a reduced manufacturing time, a gallium nitride based compound semiconductor device including the compliant substrate and a method for manufacturing the same are disclosed. The compliant substrate is manufactured by heating a substrate and a group III metal including at least one of an aluminum, a gallium and an indium, and a chloride based compound generated by introducing a HCl gas to the melted group III metal reacts with a NH | 10-22-2009 |
| 20090261346 | Integrating CMOS and Optical Devices on a Same Chip - An integrated circuit structure includes a semiconductor substrate having a first surface region and a second surface region, wherein the first surface region and the second surface region have different surface orientations; a semiconductor device formed at a surface of the first surface region; and a group-III nitride layer over the second surface region, wherein the group-III nitride layer does not extend over the first surface region. | 10-22-2009 |
| 20090267078 | Enhancement Mode III-N HEMTs - A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate. | 10-29-2009 |
| 20090267079 | EXTERNALLY CONFIGURABLE INTEGRATED CIRCUITS - A die comprising two or more active electronic components is provided. The active electronic components are capable of being interconnected using interconnections external to the die. The die may be encased within a package, and the active electronic components may be interconnected using interconnections external to the package. By interconnecting the active electronic components, either directly or through one or more additional components, a desired circuit may be formed. In some examples, the desired circuit may be a monolithic microwave integrated circuit (MMIC). Methods of forming the circuit are also disclosed. | 10-29-2009 |
| 20090267080 | SEMICONDUCTOR DEVICE - In a semiconductor device by which peripheral circuit sections, such as a semiconductor element, a matching circuit section, a bias circuit section, a capacitor element, are placed on and connected to a substrate, the semiconductor element can be grounded, and the semiconductor device which can make heat radiation characteristics of the semiconductor element satisfactory is provided, without providing a via hole into a semiconductor substrate. | 10-29-2009 |
| 20090278136 | Process for Growth of Low Dislocation Density Gan - High quality free standing GaN is obtained using a new modification of the Epitaxial Lateral Overgrowth technology in which 3D islands or features are created only by tuning the growth parameters. Smoothing these islands (2D growth) is achieved thereafter by setting growth conditions producing enhanced lateral growth. The repetition of 3D-2D growth results in multiple bending of the threading dislocations thus producing thick layers or free standing GaN with threading dislocation density below 10 | 11-12-2009 |
| 20090283776 | WIDE BAND GAP SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A wide band gap semiconductor device is disclosed. A first trench in a gate electrode part and a second trench in a source electrode part (Schottky diode part) are disposed so that the first and second trenches are close to each other while and the second trench is deeper than the first trench. A metal electrode is formed in the second trench to form a Schottky junction on a surface of an n-type drift layer in the bottom of the second trench. Further, a p+-type region is provided in part of the built-in Schottky diode part being in contact with the surface of the n-type drift layer, preferably in the bottom of the second trench. The result is a wide band gap semiconductor device which is small in size and low in on-resistance and loss, and in which electric field concentration applied on a gate insulating film is relaxed to suppress lowering of withstand voltage to thereby increase avalanche breakdown tolerance at turning-off time. | 11-19-2009 |
| 20090289261 | GALLIUM NITRIDE CRYSTAL SUBSTRATE AND METHOD OF PRODUCING SAME - A low-distortion gallium nitride crystal substrate including low dislocation single crystal regions (Z) having a definite c-axis and a definite a-axis, C-plane growth regions (Y) having a c-axis and a-axis parallel to the c-axis and a-axis of the low dislocation single crystal regions (Z), voluminous defect accumulating regions (H) having a c-axis inverse to the c-axis of the low dislocation single crystal regions (Z) and an a-axis parallel with the a-axis of the low dislocation single crystal regions (Z), and 0.1/cm | 11-26-2009 |
| 20090294774 | MANUFACTURING METHOD OF GaN THIN FILM TEMPLATE SUBSTRATE, GaN THIN FILM TEMPLATE SUBSTRATE AND GaN THICK FILM SINGLE CRYSTAL - Provided are a manufacturing method of a GaN single crystal in which the film thickness of the GaN single crystal can be controlled accurately, even when a hydride vapor phase epitaxy is applied; a GaN thin film template substrate which is suitable for growing a GaN thick film with a fine property; and a GaN single crystal growing apparatus. Provided is a manufacturing method of a GaN single crystal by a hydride vapor phase epitaxy, wherein the hydride vapor phase epitaxy comprises: spraying HCl (hydrogen chloride) onto Ga (gallium) which is heated and fused in a predetermined temperature to generate GaCl (gallium chloride); and forming a GaN thin film by a reaction of the generated GaCl (gallium chloride) with NH | 12-03-2009 |
| 20090294775 | HEXAGONAL WURTZITE TYPE EPITAXIAL LAYER POSSESSING A LOW ALKALI-METAL CONCENTRATION AND METHOD OF CREATING THE SAME - A method of obtaining a hexagonal würtzite type epitaxial layer with a low impurity concentration of alkali-metal by using a hexagonal würtzite substrate possessing a higher impurity concentration of alkali-metal, wherein a surface of the substrate upon which the epitaxial layer is grown has a crystal plane which is different from the c-plane. | 12-03-2009 |
| 20090309105 | Methods for producing improved crystallinity group III-nitride crystals from initial group III-Nitride seed by ammonothermal Growth - The present invention discloses methods to create higher quality group III-nitride wafers that then generate improvements in the crystalline properties of ingots produced by ammonothermal growth from an initial defective seed. By obtaining future seeds from carefully chosen regions of an ingot produced on a bowed seed crystal, future ingot crystalline properties can be improved. Specifically, the future seeds are optimized if chosen from an area of relieved stress on a cracked ingot or from a carefully chosen N-polar compressed area. When the seeds are sliced out, miscut of 3-10° helps to improve structural quality of successive growth. Additionally a method is proposed to improve crystal quality by using the ammonothermal method to produce a series of ingots, each using a specifically oriented seed from the previous ingot. When employed, these methods enhance the quality of Group III nitride wafers and thus improve the efficiency of any subsequent device. | 12-17-2009 |
| 20090315036 | SEMICONDUCTOR DEVICES INCLUDING SCHOTTKY DIODES HAVING DOPED REGIONS ARRANGED AS ISLANDS AND METHODS OF FABRICATING SAME - A semiconductor device according to some embodiments includes a semiconductor layer having a first conductivity type and a surface in which an active region of the semiconductor device is defined. A plurality of spaced apart first doped regions are arranged within the active region. The plurality of first doped regions have a second conductivity type that is opposite the first conductivity type, have a first dopant concentration, and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of first doped regions are arranged as islands in the semiconductor layer. A second doped region in the semiconductor layer has the second conductivity type and has a second dopant concentration that is greater than the first dopant concentration. | 12-24-2009 |
| 20090315037 | COMPOUND SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD - A vertical type GaN series field effect transistor having excellent pinch-off characteristics is provided. A compound semiconductor device includes a conductive semiconductor substrate, a drain electrode formed on a bottom surface of the conductive semiconductor substrate, a current blocking layer formed on a top surface of the conductive semiconductor substrate, made of high resistance compound semiconductor or insulator, and having openings, an active layer of compound semiconductor burying the openings and extending on an upper surface of the current blocking layer, a gate electrode formed above the openings and above the active layer, and a source electrode formed laterally spaced from the gate electrode and formed above the active layer. | 12-24-2009 |
| 20090315038 | COMPOUND SEMICONDUCTOR ELEMENT RESISTIBLE TO HIGH VOLTAGE - A compound semiconductor element is provided which electrically connects an electrode | 12-24-2009 |
| 20090321745 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes: a substrate; a first conductivity type layer formed on the substrate and including a plurality of group III-V nitride semiconductor layers of a first conductivity type; an active layer formed on the first conductivity type layer; and a second conductivity type layer formed on the active layer and including a group III-V nitride semiconductor layer of a second conductivity type. The first conductivity type layer includes an intermediate layer made of Al | 12-31-2009 |
| 20100001289 | PROCESS FOR PRODUCING AN EPITAXIAL LAYER OF GALIUM NITRIDE - A method of manufacturing a low defect density GaN material comprising at least two steps of growing epitaxial layers of GaN with differences in growing conditions, (a.) a first step of growing an epitaxial layer GaN on an epitaxially competent layer under first growing conditions selected to induce island features formation, followed by (b.) a second step of growing an epitaxial layer of GaN under second growing conditions selected to enhance lateral growth until coalescence. | 01-07-2010 |
| 20100006857 | MULTILAYER STRUCTURE AND FABRICATION THEREOF - A process for fabricating a multilayer structure is provided as well as the structure itself. In accordance with one embodiment, the process includes growing a growth layer on a silicon substrate by epitaxial growth, forming at least one pattern from the growth layer, depositing an oxide layer on the silicon substrate, transferring a silicon active layer onto the oxide layer, forming a cavity in the silicon active layer oxide layer above the pattern, and growing a III-V material in the cavity. | 01-14-2010 |
| 20100012947 | PROCESS FOR MAKING A GaN SUBSTRATE - The invention relates to a process for making a GaN substrate ( | 01-21-2010 |
| 20100012948 | Growth of Planar Non-Polar M-Plane and Semi-Polar Gallium Nitride with Hydride Vapor Phase Epitaxy (HVPE) - A method of growing planar non-polar m-plane or semi-polar III-Nitride material, such as an m-plane gallium nitride (GaN) epitaxial layer, wherein the III-Nitride material is grown on a suitable substrate, such as an m-plane Sapphire substrate, using hydride vapor phase epitaxy (HVPE). The method includes in-situ pretreatment of the substrate at elevated temperatures in the ambient of ammonia and argon, growing an intermediate layer such as an aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN) on the annealed substrate, and growing the non-polar m-plane III-Nitride epitaxial layer on the intermediate layer using HVPE. | 01-21-2010 |
| 20100019247 | Light emitting device using gan led chip - A light emitting device is constituted by flip-chip mounting a GaN-based LED chip | 01-28-2010 |
| 20100019248 | GALLIUM NITRIDE MATERIAL DEVICES INCLUDING CONDUCTIVE REGIONS AND METHODS ASSOCIATED WITH THE SAME - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. | 01-28-2010 |
| 20100025693 | Wide band gap semiconductor device including junction field effect transistor - A wide band gap semiconductor device has a transistor cell region, a diode forming region, an electric field relaxation region located between the transistor cell region and the diode forming region, and an outer peripheral region surrounding the transistor cell region and the diode forming region. In the transistor cell region, a junction field effect transistor is disposed. In the diode forming region, a diode is disposed. In the electric field relaxation region, an isolating part is provided. The isolating part includes a trench dividing the transistor cell region and the diode forming region, a first conductivity-type layer disposed on an inner wall of the trench, and a second conductivity-type layer disposed on a surface of the first conductivity-type layer so as to fill the trench. The first conductivity-type layer and the second conductivity-type layer provide a PN junction. | 02-04-2010 |
| 20100025694 | Apparatus and method for transformation of substrate - A method is disclosed for forming a layer of a wide bandgap material in a non-wide bandgap material. The method comprises providing a substrate of a non-wide bandgap material and converting a layer of the non-wide bandgap material into a layer of a wide bandgap material. An improved component such as wide bandgap semiconductor device may be formed within the wide bandgap material through a further conversion process. | 02-04-2010 |
| 20100032682 | Large area thin freestanding nitride layers and their use as circuit layers - Thin flat crack-free freestanding nitride layers are fabricated by laser patterning of the interface and/or opposing surface of the nitride layer. The nitride layer is substantially flat once removed from the non-native substrate. The thin flat crack free nitride layers are between 3 and 250 microns thick and can have areas greater than 1 cm | 02-11-2010 |
| 20100032683 | GaN-BASED SEMICONDUCTOR ELEMENT - The GaN-based semiconductor element | 02-11-2010 |
| 20100032684 | ION IMPLANTATION FOR SUPPRESSION OF DEFECTS IN ANNEALED SiGe LAYERS - A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form a substantially relaxed SiGe alloy layer that has a reduced planar defect density. A substantially relaxed SiGe-on-insulator substrate material having a SiGe layer with a reduced planar defect density as well as heterostructures containing the same are also provided. | 02-11-2010 |
| 20100038652 | LIGHT EMITTING ELEMENT AND METHOD OF MAKING SAME - A light emitting element has a substrate of gallium oxides and a pn-junction formed on the substrate. The substrate is of gallium oxides represented by: (Al | 02-18-2010 |
| 20100044718 | Group III Nitride Articles and Methods for Making Same - Group III (Al, Ga, In)N single crystals, articles and films useful for producing optoelectronic devices (such as light emitting diodes (LEDs), laser diodes (LDs) and photodetectors) and electronic devices (such as high electron mobility transistors (HEMTs)) composed of III-V nitride compounds, and methods for fabricating such crystals, articles and films. | 02-25-2010 |
| 20100044719 | III-V Compound Semiconductor Epitaxy Using Lateral Overgrowth - A circuit structure includes a substrate; a patterned mask layer over the substrate, wherein the patterned mask layer includes a plurality of gaps; and a group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layer includes a first portion over the mask layer and second portions in the gaps, wherein the III-V compound semiconductor layer overlies a buffer/nucleation layer. | 02-25-2010 |
| 20100051960 | DEVICE AND PROCESS OF FORMING DEVICE WITH PRE-PATTERNED TRENCH AND GRAPHENE-BASED DEVICE STRUCTURE FORMED THEREIN - A graphene-based device is formed with a trench in one or more layers of material, a graphene layer within the trench, and a device structure on the graphene layer and within the trench. Fabrication techniques includes forming a trench defined by one or more layers of material, forming a graphene layer within the trench, and forming a device structure on the graphene layer and within the trench. | 03-04-2010 |
| 20100051961 | EPITAXIAL SUBSTRATE, SEMICONDUCTOR DEVICE SUBSTRATE, AND HEMT DEVICE - A buffer layer formed of In | 03-04-2010 |
| 20100051962 | Compound semiconductor device and the fabricating method of the same - A GaN layer functions as an electron transit layer and is formed to exhibit, at least at a portion thereof, A/B ratio of 0.2 or less obtained by a photoluminescence measurement, where “A” is the light-emission intensity in the 500-600 nm band, and “B” is the light-emission intensity at the GaN band-edge. | 03-04-2010 |
| 20100059759 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR FORMING THE SAME - An active layer | 03-11-2010 |
| 20100059760 | GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR LIGHT EMITTING DEVICE AND PROCESS FOR ITS PRODUCTION - It is an object of the present invention to provide a gallium nitride-based compound semiconductor light emitting device with high light emission output and low driving voltage. | 03-11-2010 |
| 20100059761 | SCHOTTKY BARRIER DIODE - A Schottky barrier diode includes a GaN freestanding substrate having a front surface, a GaN epitaxial layer deposited on the front surface, and an insulation layer deposited on the GaN epitaxial layer at a front surface and having an opening. Furthermore, the Schottky barrier diode also includes an electrode. The electrode is configured by a Schottky electrode provided in the opening in contact with the GaN epitaxial layer, and a field plate electrode connected to the Schottky electrode and also overlapping the insulation layer. The GaN freestanding substrate has a dislocation density of at most 1×10 | 03-11-2010 |
| 20100065854 | GROWTH AND MANUFACTURE OF REDUCED DISLOCATION DENSITY AND FREE-STANDING ALUMINUM NITRIDE FILMS BY HYDRIDE VAPOR PHASE EPITAXY - A Group III-nitride semiconductor film containing aluminum, and methods for growing this film. A film is grown by patterning a substrate, and growing the Group III-nitride semi-conductor film containing aluminum on the substrate at a temperature designed to increase the mobility of aluminum atoms to increase a lateral growth rate of the Group III-nitride semiconductor film. The film optionally includes a substrate patterned with elevated stripes separated by trench regions, wherein the stripes have a height chosen to allow the Group III-nitride semiconductor film to coalesce prior to growth from the bottom of the trenches reaching the top of the stripes, the temperature being greater than 1075° C., the Group III-nitride semiconductor film being grown using hydride vapor phase epitaxy, the stripes being oriented along a (1-100) direction of the substrate or the growing film, and a dislocation density of the grown film being less than 10 | 03-18-2010 |
| 20100065855 | METHOD OF MANUFACTURING GROUP-III NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE, GROUP-III NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND LAMP - The object of the present invention is to provide a method of manufacturing a Group-III nitride semiconductor light-emitting device that is highly productive and that enables production of a device having excellent light-emitting properties; a Group-III nitride semiconductor light-emitting device; and a lamp using the light emitting device. The present invention provides a method of manufacturing a Group-III nitride semiconductor light-emitting device, comprising the steps of: activating a gas including a Group-V element and a metal material with plasma, thereby reacting the gas with the metal material; forming on a substrate an intermediate layer that is made of a Group-III nitride compound; and stacking an n-type semiconductor layer that is made of a Group-III nitride semiconductor, a light-emitting layer, and a p-type semiconductor layer, sequentially on the intermediate layer, wherein the Group-V element is nitrogen, the gas fraction of nitrogen in the gas is within a range of more than 20% to less than 99% during forming of the intermediate layer, and the intermediate layer is formed into a single crystal structure. | 03-18-2010 |
| 20100065856 | Semiconductor package with integrated passives and method for fabricating same - According to one disclosed embodiment, a semiconductor package for integrated passives and a semiconductor device comprises a high permeability structure formed over a surface of the semiconductor package and surrounding a contact body of the semiconductor package, the contact body being connected to an output of the semiconductor device. The contact body can be, for example, a solder bump. The high permeability structure causes a substantial increase in inductance of the contact body so as to form an increased inductance inductor coupled to the output of the semiconductor device. In one embodiment, the semiconductor package further comprises a blanket insulator formed over the high permeability structure, and a capacitor stack formed over the blanket insulator. In one embodiment, the semiconductor device comprises a group III-V power semiconductor device. | 03-18-2010 |
| 20100078648 | GALLIUM NITRIDE-BASED EPITAXIAL WAFER AND METHOD OF FABRICATING EPITAXIAL WAFER - A gallium nitride-based epitaxial wafer for a nitride light-emitting device comprises a gallium nitride substrate having a primary surface, a gallium nitride-based semiconductor film provided on the primary surface of the gallium nitride substrate, and, an active layer provided on the gallium nitride-based semiconductor film, the active layer having a quantum well structure. The active layer includes a well layer of a gallium nitride-based semiconductor. The gallium nitride-based semiconductor contains indium as a Group III element. A normal line of the primary surface and a C-axis of the gallium nitride substrate form an off angle with each other. The off angle is distributed on the primary surface, and the off angle monotonically increases on the line that extends from one point to another point through a center point of the primary surface of the gallium nitride substrate. The one point and the other point are on an edge of the primary surface, and indium contents of the well layer defined at n points (n: integer) on the line monotonically decrease in a direction from the one point to the other point. The thickness values of the well layer defined at the n points monotonically increase in the direction. | 04-01-2010 |
| 20100078649 | Light emitting element and light emitting device - A light emitting element which emits light of a wavelength, includes a substrate which is transparent to the wavelength of emitted light and includes a first surface and a second surface; a semiconductor layer stacked on the first surface; a first electrode which is reflective to the wavelength of emitted light and formed on a surface of the semiconductor layer, wherein electrical resistance of the first electrode in a farthest distance is equal to or smaller than 1Ω; and a second electrode which is reflective to the wavelength of emitted light and formed on the second surface, wherein electrical resistance of the second electrode in a farthest distance is equal to or smaller than 1Ω. | 04-01-2010 |
| 20100090225 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a main semiconductor region comprising a first nitride semiconductor layer having a first band gap, and a second nitride semiconductor layer having a second band gap larger than the first band gap, a heterojunction being formed between the first nitride semiconductor layer and a the second nitride semiconductor layer such that two-dimensional electron gas layer can be caused inside the first nitride semiconductor layer based on the heterojunction; a source electrode formed on the main semiconductor region; a drain electrode formed on the main semiconductor region and separated from the source electrode; a third nitride semiconductor layer formed on the first nitride semiconductor layer and between the source electrode and the drain electrode; and a gate electrode formed on the third nitride semiconductor layer. The third nitride semiconductor layer has a third band gap smaller than the first band gap. | 04-15-2010 |
| 20100102326 | GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE - An object of the present invention is to provide a gallium nitride-based compound semiconductor light-emitting device having a positive electrode which comprises a first electrode and an over-coating layer covering the side surfaces and upper surface of the first electrode provided on a p-type semiconductor layer, the over-coating layer tending not to be exfoliated from the p-type semiconductor layer. The inventive gallium nitride-based compound semiconductor light-emitting device comprises an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer of gallium nitride-based compound semiconductors which are formed in this order on a substrate, the negative electrode and the positive electrode being provided in contact with the n-type semiconductor layer and the p-type semiconductor layer, respectively, wherein the positive electrode comprises at least a first electrode and an over-coating layer covering the side surfaces and upper surface of the first electrode, and the area where the over-coating layer comes into contact with the p-type semiconductor layer is greater at the corner portions of the positive electrode than at the side portions thereof, per unit length of the outer edge of the first electrode. | 04-29-2010 |
| 20100102327 | Semiconductor device and passive component integration in a semiconductor package - According to one exemplary embodiment, a semiconductor package includes a substrate having lower and upper surfaces. The semiconductor package further includes at least one passive component coupled to first and second conductive pads on the upper surface of the substrate. The semiconductor package further includes at least one semiconductor device coupled to a first conductive pad on the lower surface of the substrate. The at least one semiconductor device has a first electrode for electrical and mechanical connection to a conductive pad external to the semiconductor package. The at least one semiconductor device can have a second electrode electrically and mechanically coupled to the first conductive pad on the lower surface of the substrate. | 04-29-2010 |
| 20100102328 | NITRIDE SEMICONDUCTOR SUBSTRATE - A nitride semiconductor substrate is featured in comprising: a GaN semiconductor layer grown on a base layer, which has a substantially triangular cross-section along the thickness direction thereof, a periodic stripe shapes, and uneven surfaces arranged on the stripes inclined surfaces; and an overgrown layer composed of AlGaN or InAlGaN on the GaN semiconductor layer. | 04-29-2010 |
| 20100102329 | LIGHT-EMITTING DEVICE HAVING LIGHT-EMITTING ELEMENTS WITH A SHARED ELECTRODE - A light-emitting device operating on a high drive voltage and a small drive current. LEDs ( | 04-29-2010 |
| 20100102330 | NITRIDE SEMICONDUCTOR DEVICE HAVING OXYGEN-DOPED N-TYPE GALLIUM NITRIDE FREESTANDING SINGLE CRYSTAL SUBSTRATE - Oxygen can be doped into a gallium nitride crystal by preparing a non-C-plane gallium nitride seed crystal, supplying material gases including gallium, nitrogen and oxygen to the non-C-plane gallium nitride seed crystal, growing a non-C-plane gallium nitride crystal on the non-C-plane gallium nitride seed crystal and allowing oxygen to infiltrating via a non-C-plane surface to the growing gallium nitride crystal. | 04-29-2010 |
| 20100109015 | GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - An insulating layer, an undoped first GaN layer and an AlGaN layer are laminated in this order on a surface of a semiconductor substrate. A surface barrier layer formed by a two-dimensional electron gas is provided in an interface between the first GaN layer and the AlGaN layer. A recess (first recess) which reaches the first GaN layer but does not pierce the first GaN layer is formed in a surface layer of the AlGaN layer. A first high withstand voltage transistor and a control circuit are formed integrally on the aforementioned semiconductor substrate. The first high withstand voltage transistor is formed in the first recess and on a surface of the AlGaN layer. The control circuit includes an n-channel MOSFET formed in part of the first recess, and a depression type n-channel MOSFET formed on a surface of the AlGaN layer. In this manner, there are provided a gallium nitride semiconductor device which can be used under a high temperature environment while reduction in total circuit size can be attained, and a method for producing the gallium nitride semiconductor device. | 05-06-2010 |
| 20100109016 | POWER SEMICONDUCTOR MODULE - Provided is a power semiconductor module in which two components are bonded by a Bi based solder material. A Cu layer is provided on the surfaces thereof to be bonded by the Bi based solder material on the two-component. Two components, i.e., the components to be bonded, are a combination of a semiconductor element and an insulating part, or a combination of an insulating part and a radiator plate. The insulating part is composed of a Cu/SiNx/Cu laminated body. | 05-06-2010 |
| 20100109017 | GaN-BASED COMPOUND SEMICONDUCTOR DEVICE - A gallium nitride (GaN)-based compound semiconductor device having a structure improving a surface characteristic of a thin film growing on a substrate is provided. The GaN-based compound semiconductor device includes an Al | 05-06-2010 |
| 20100109018 | METHOD OF FABRICATING SEMI-INSULATING GALLIUM NITRIDE USING AN ALUMINUM GALLIUM NITRIDE BLOCKING LAYER - A method for fabricating a single crystal, high quality, semi-insulating (SI) gallium nitride (GaN) layer using an Al | 05-06-2010 |
| 20100109019 | FORMING METHOD OF GALLIUM NITRIDE SYSTEM COMPOUND SEMICONDUCTOR LAYER, TRANSFER METHOD OF THE SAME, AND SUBSTRATE STRUCTURE WITH THE SAME BONDED THERETO - A method includes: forming a first layer containing silicon oxide on a first substrate; partially removing the first layer to form an exposure portion on the first substrate; depositing amorphous gallium nitride system compound semiconductor on the first substrate with the exposure portion; evaporating the semiconductor on the first layer to form cores of the semiconductor on the exposure portion of the first substrate; forming an epitaxial layer of the semiconductor on the first substrate through increase in a size of the core, combination of the cores, crystal growth, formation of facets, bending of dislocation lines, transverse crystal growth onto the first layer, collision between adjoining crystal grains, combination of the transversely grown crystals, formation of dislocation networks, and formation of a flat surface of the semiconductor; and removing the epitaxial layer of the semiconductor on the exposure portion on the first substrate to form a separating groove. | 05-06-2010 |
| 20100109020 | Diode having vertical structure and method of manufacturing the same - A light emitting diode includes a conductive layer, an n-GaN layer on the conductive layer, an active layer on the n-GaN layer, a p-GaN layer on the active layer, and a p-electrode on the p-GaN layer. The conductive layer is an n-electrode. | 05-06-2010 |
| 20100117094 | GALLIUM NITRIDE EPITAXIAL CRYSTAL, METHOD FOR PRODUCTION THEREOF, AND FIELD EFFECT TRANSISTOR - The present invention provides a gallium nitride type epitaxial crystal, a method for producing the crystal, and a field effect transistor using the crystal. The gallium nitride type epitaxial crystal comprises a base substrate and the following (a) to (e), wherein a connection layer comprising a gallium nitride type crystal is arranged in an opening of the non-gallium nitride type insulating layer to electrically connect the first buffer layer and the p-conductive type semiconductor crystal layer. (a) a gate layer, (b) a high purity first buffer layer containing a channel layer contacting an interface on the base substrate side of the gate layer, (c) a second buffer layer arranged on the base substrate side of the first buffer layer, (d) a non-gallium nitride type insulating layer arranged on the base substrate side of the second buffer layer, and having the opening at a part thereof, and (e) a p-conductive type semiconductor crystal layer arranged on the base substrate side of the insulating layer. | 05-13-2010 |
| 20100117095 | GaN-Based Device Cascoded with an Integrated FET/Schottky Diode Device - A power semiconductor device is provided that includes a depletion mode (normally ON) main switching device cascoded with a higher speed switching device, resulting in an enhancement mode (normally OFF) FET device for switching power applications. The main switching device comprises a depletion mode GaN-based HEMT (High Electron Mobility Transistor) FET that does not include an intrinsic body diode. In one or more embodiments, the higher speed switching device comprises a high speed FET semiconductor switch arranged or connected in parallel with a Schottky diode. The high speed FET semiconductor switch may comprise a Si FET, GaN FET or any other type of FET which possesses higher speed switching capabilities and a lower voltage than that of the GaN-based HEMT FET. In some embodiments, the GaN-based HEMT FET and the higher speed switching device (i.e., the FET and Schottky diode) may be monolithically integrated on the same substrate. | 05-13-2010 |
| 20100117096 | VERTICAL STRUCTURE SEMICONDUCTOR DEVICES WITH IMPROVED LIGHT OUTPUT - The invention provides a reliable technique to fabricate a new vertical structure compound semiconductor devices with highly improved light output. An exemplary embodiment of a method of fabricating light emitting semiconductor devices comprising the steps of forming a light emitting layer, and forming an undulated surface over light emitting layer to improve light output. In one embodiment, the method further comprises the step of forming a lens over the undulated surface of each of the semiconductor devices. In one embodiment, the method of claim further comprises the steps of forming a contact pad over the semiconductor structure to contact with the light emitting layer, and packaging each of the semiconductor devices in a package including an upper lead frame and lower lead frame. Advantages of the invention include an improved technique for fabricating semiconductor devices with great yield, reliability and light output. | 05-13-2010 |
| 20100123139 | SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - An aspect of the present invention inheres in a semiconductor wafer includes a support substrate, a first nitride semiconductor layer, at least an upper surface of which has become monocrystalline, the first semiconductor layer being provided on the support substrate, and a second nitride semiconductor layer containing nitrogen and gallium, the second nitride semiconductor layer being provided on the upper surface of the first nitride semiconductor layer. | 05-20-2010 |
| 20100127274 | Thin film light emitting diode - Light emitting LEDs devices comprised of LED chips that emit light at a first wavelength, and a thin film layer over the LED chip that changes the color of the emitted light. For example, a blue LED chip can be used to produce white light. The thin film layer beneficially consists of a florescent material, such as a phosphor, and/or includes tin. The thin film layer is beneficially deposited using chemical vapor deposition. | 05-27-2010 |
| 20100127275 | GAN-BASED FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A GaN-based field effect transistor | 05-27-2010 |
| 20100127276 | GaN Based LED with Improved Light Extraction Efficiency and Method for Making the Same - A light-emitting device and the method for making the same are disclosed. The device includes a substrate, a light-emitting structure and a light scattering layer. The light-emitting structure includes an active layer sandwiched between a p-type GaN layer and an n-type GaN layer, the active layer emitting light of a predetermined wavelength when electrons and holes from the n-type GaN layer and the p-type GaN layer, respectively, combine therein. The light scattering layer includes a GaN crystalline layer characterized by an N-face surface. The N-face surface includes features that scatter light of the predetermined wavelength. The light-emitting structure is between the N-face surface and the substrate. | 05-27-2010 |
| 20100133547 | Semiconductor Sensor - A semiconductor sensor determines physical and/or chemical properties of a medium, in particular a pH sensor. The semiconductor sensor has an electronic component with a sensitive surface, said component being constructed for its part on the basis of semiconductors with a large band gap (wide-gap semiconductor). The sensitive surface is provided at least in regions with a functional layer sequence which has an ion-sensitive surface. The functional layer sequence has at least one layer which is impermeable at least for the medium and/or the materials or ions to be determined. | 06-03-2010 |
| 20100133548 | METHODS FOR IMPROVING THE QUALITY OF EPITAXIALLY-GROWN SEMICONDUCTOR MATERIALS - The invention provides methods which can be applied during the epitaxial growth of two or more layers of semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects present in one epitaxial layer are capped with a masking material. A following layer is then grown so it extends laterally above the caps according to the known phenomena of epitaxial lateral overgrowth. The methods of the invention can be repeated by capping surface defects in the following layer and then epitaxially growing a second following layer according to ELO. The invention also includes semiconductor structures fabricated by these methods. | 06-03-2010 |
| 20100140627 | Package for Semiconductor Devices - A packaged semiconductor device including a semiconductor die mounted on a header of a leadframe. A plurality of spaced external conductors extends from the header and at least one of the external conductors has a bond wire post at one end thereof such that a bonding wire extends between the bond wire post and the semiconductor die. The package device also includes a housing, which encloses the semiconductor die, the header, the bonding wire and the bonding wire post resulting in an insulated packaged device. | 06-10-2010 |
| 20100148183 | Method of Forming a Carbon Nanotube-Based Contact to Semiconductor - Manufacturers encounter limitations in forming low resistance ohmic electrical contact to semiconductor material P-type Gallium Nitride (p-GaN), commonly used in photonic applications, such that the contact is highly transparent to the light emission of the device. Carbon nanotubes (CNTs) can address this problem due to their combined metallic and semiconducting characteristics in conjunction with the fact that a fabric of CNTs has high optical transparency. The physical structure of the contact scheme is broken down into three components, a) the GaN, b) an interface material and c) the metallic conductor. The role of the interface material is to make suitable contact to both the GaN and the metal so that the GaN, in turn, will make good electrical contact to the metallic conductor that interfaces the device to external circuitry. A method of fabricating contact to GaN using CNTs and metal while maintaining protection of the GaN surface is provided. | 06-17-2010 |
| 20100148184 | GAN-BASED FIELD EFFECT TRANSISTOR - A GaN-based field effect transistor (MOSFET) is comprised of a channel layer comprised of p-type GaN, an electron supply layer, a surface layer having band gap energy smaller than that of said electron supply layer, sequentially laminated on a substrate, and recess section is formed by removing a part of the drift layer, the electron supply layer, and the surface layer down to a depth that reaches to the channel layer. A source electrode and a drain electrode are formed so that the recess section positions between them, a gate insulation film is formed on the surface layer and on inner-surface of the recess section including the channel layer, and a gate electrode is formed on the gate insulating film in the recess section. | 06-17-2010 |
| 20100148185 | FLIP-CHIP LIGHT-EMITTING DIODE DEVICE - A flip-chip light-emitting diode (LED) device is provided. The flip-chip LED device includes a substrate, an n-GaN layer, an epitaxy layer, a p-GaN layer, a first electrode, and a second electrode. The n-GaN layer is formed on a surface of the substrate. The epitaxy layer is formed on the n-GaN layer. The p-GaN layer is formed on the epitaxy layer. The first electrode has a first polarity and is formed on the p-GaN layer. The first electrode substantially covers the p-GaN layer. The second electrode is formed on the n-GaN layer and has a second polarity opposite to the first polarity. | 06-17-2010 |
| 20100155738 | Light Emitting Diode and Method for Manufacturing Same - This invention provides a light emitting diode in which a thick transparent conductive electrode is formed on an emitting side of GaN based semiconductor light emitting element, and a light emitting efficiency of the GaN semiconductor light emitting element is improved. Further, it provides a manufacturing method of the light emitting diode by which a thick transparent electrode film of the light emitting diode is effectively formed. A light emitting diode which emits light in a blue or an ultraviolet region comprising a substrate and a light emitting layer thereon comprising at least an n-type GaN based semiconductor layer, a p-type GaN based semiconductor layer, and a GaN based semiconductor sandwiched between them, wherein a transparent conductive film having a thickness of 1-100 μm is provided on the light emitting layer. | 06-24-2010 |
| 20100155739 | LIGHT-EMITTING DEVICE, METHOD FOR MANUFACTURING SAME, MOLDED BODY AND SEALING MEMBER - Disclosed is a light-emitting device comprising a light-emitting element ( | 06-24-2010 |
| 20100155740 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A cavity-containing layer having a plurality of cavities is formed on a growth substrate by carrying out in alternating fashion a plurality of cycles of a first and second growth steps of growing a group III nitride at growth rates different from each other. The semiconductor epitaxial layer is subsequently formed on the cavity-containing layer, after which a support substrate is bonded to the semiconductor epitaxial layer. The growth substrate is separated from the cavity-containing layer. | 06-24-2010 |
| 20100155741 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A compound semiconductor device includes a carrier transit layer including GaN formed over a substrate; a carrier supply layer including GaN formed over the carrier transit layer; a source electrode and a drain electrode formed over the carrier supply layer; a first compound semiconductor layer including N in which a first opening is formed and that is located between the source electrode and the drain electrode over the carrier supply layer; a gate electrode extending from within the first opening to above the first compound semiconductor layer; and an insulator layer having a second opening that is smaller than the first opening, and insulating the gate electrode and the first compound semiconductor layer within the first opening. The gate electrode extends from within the second opening to above the first compound semiconductor layer. | 06-24-2010 |
| 20100163886 | GALLIUM NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME, AND LAMP INCLUDING THE SAME - The present invention provides a gallium nitride compound semiconductor light-emitting device that prevents an increase in the specific resistance of a p-type semiconductor layer due to hydrogen annealing and reduces the specific resistance of a translucent conductive oxide film to lower a driving voltage Vf, a method of manufacturing the same, and a lamp including the same. The method of manufacturing the gallium nitride compound semiconductor light-emitting device includes: forming a positive electrode | 07-01-2010 |
| 20100163887 | LIGHT EMITTING DEVICE HAVING A PLURALITY OF NON-POLAR LIGHT EMITTING CELLS AND A METHOD OF FABRICATING THE SAME - The present invention relates to a light emitting device having a plurality of non-polar light emitting cells and a method of fabricating the same. Nitride semiconductor layers are disposed on a Gallium Nitride substrate having an upper surface. The upper surface is a non-polar or semi-polar crystal and forms an intersection angle with respect to a c-plane. The nitride semiconductor layers may be patterned to form light emitting cells separated from one another. When patterning the light emitting cells, the substrate may be partially removed in separation regions between the light emitting cells to form recess regions. The recess regions are filled with an insulating layer, and the substrate is at least partially removed by using the insulating layer. | 07-01-2010 |
| 20100163888 | MANUFACTURING PROCESS OF A POWER ELECTRONIC DEVICE INTEGRATED IN A SEMICONDUCTOR SUBSTRATE WITH WIDE BAND GAP AND ELECTRONIC DEVICE THUS OBTAINED - An embodiment of a process for manufacturing an electronic device on a semiconductor body of a material with wide forbidden bandgap having a first conductivity type. The process comprises the steps of: forming, on the semiconductor body, a first mask having a first window and a second window above a first surface portion and a second surface portion of the semiconductor body; forming, within the first and second surface portions of the semiconductor body underneath the first and second windows, at least one first conductive region and one second conductive region having a second conductivity type, the first conductive region and the second conductive region facing one another; forming a second mask on the semiconductor body, the second mask having a plurality of windows above surface portions of the first conductive region and the second conductive region; forming, within the first conductive region and the second conductive region and underneath the plurality of windows, a plurality of third conductive regions having the first conductivity type; removing completely the first and second masks; performing an activation thermal process of the first, second, and third conductive regions at a high temperature; and forming body and source regions. | 07-01-2010 |
| 20100171124 | Low-defect density gallium nitride semiconductor structures and fabrication methods - A low-defect gallium nitride structure including a first gallium nitride layer comprising a plurality of gallium nitride columns etched into the first gallium nitride layer and a first dislocation density; and a second gallium nitride layer that extends over the gallium nitride columns and comprises a second dislocation density, wherein the second dislocation density may be lower than the first dislocation density. In addition, a method for fabricating a gallium nitride semiconductor layer that includes masking an underlying gallium nitride layer with a mask that comprises an array of columns and growing the underlying gallium nitride layer through the columns and onto said mask using metal-organic chemical vapor deposition pendeo-epitaxy to thereby form a pendeo-epitaxial gallium nitride layer coalesced on said mask to form a continuous pendeo-epitaxial monocrystalline gallium nitride semiconductor layer. | 07-08-2010 |
| 20100171125 | Thin film light emitting diode - Light emitting LEDs devices comprised of LED chips that emit light at a first wavelength, and a thin film layer over the LED chip that changes the color of the emitted light. For example, a blue LED chip can be used to produce white light. The thin film layer beneficially consists of a florescent material, such as a phosphor, and/or includes tin. The thin film layer is beneficially deposited using chemical vapor deposition. | 07-08-2010 |
| 20100171126 | In situ dopant implantation and growth of a Ill-nitride semiconductor body - In one embodiment a method enabling in situ dopant implantation during growth of a III-nitride semiconductor body, comprises establishing a growth environment for the III-nitride semiconductor body in a composite III-nitride chamber having a dopant implanter and a growth chamber, growing the III-nitride semiconductor body in the growth chamber, and implanting the III-nitride semiconductor body in situ in the growth chamber using the dopant implanter. A semiconductor device produced using the disclosed method comprises a III-nitride semiconductor body having a first conductivity type formed over a support substrate, and at least one doped region produced by in situ dopant implantation of the III-nitride semiconductor body during its growth, that at least one doped region having a second conductivity type. | 07-08-2010 |
| 20100181576 | Epitaxial Structure Having Low Defect Density - An epitaxial structure having a low defect density includes: a base layer; a first epitaxial layer having a plurality of concentrated defect groups, and an epitaxial surface that has a plurality of first recesses corresponding in position to the concentrated defect groups, the sizes of the first recesses being close to each other; and a plurality of defect-termination blocks respectively and filling the first recesses and having polished surfaces. The defect-termination blocks are made of a material which is different in removal rate from that of the first epitaxial layer. The polished surfaces are substantially flush with the epitaxial surface so that the first epitaxial layer has a substantially planarized crystal growth surface | 07-22-2010 |
| 20100181577 | NITRIDE SEMICONDUCTOR SUBSTRATE - There is provided a nitride semiconductor substrate. The nitride semiconductor substrate comprises a substrate, a patterned epitaxy layer, a protective layer and a gallium nitride semiconductor layer. The patterned epitaxy layer is disposed on the substrate, wherein the patterned epitaxy layer comprises a pier structure and the patterned epitaxy layer has an upper surface and a lower surface opposite to the upper surface and the lower surface faces to the substrate. The protective layer covers a portion of the upper surface of the patterned epitaxy layer to expose a top surface of the pier structure. The gallium nitride (GaN) semiconductor layer extends substantially across an entire area above the patterned epitaxy layer and connected to the exposed top surface of the pier structure. | 07-22-2010 |
| 20100187540 | GROUP III NITRIDE SUBSTRATE, EPITAXIAL LAYER-PROVIDED SUBSTRATE, METHODS OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate is one of the following: a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface is not more than 2×10 | 07-29-2010 |
| 20100187541 | Doped Aluminum Nitride Crystals and Methods of Making Them - Fabrication of doped AlN crystals and/or AlGaN epitaxial layers with high conductivity and mobility is accomplished by, for example, forming mixed crystals including a plurality of impurity species and electrically activating at least a portion of the crystal. | 07-29-2010 |
| 20100187542 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor light emitting element from a wafer in which a gallium nitride compound semiconductor has been laminated on a sapphire substrate having an orientation flat, comprises of: laminating a semiconductor layer on a first main face of the sapphire substrate having an off angle θ in a direction Xo parallel to the orientation flat; forming a first break groove that extends in a direction Y substantially perpendicular to the direction Xo, on the semiconductor layer side; forming a second break line that is shifted by a predetermined distance in the ±Xo direction from a predicted split line within the first break groove and parallel to the first break groove in the interior of the sapphire substrate and corresponding to the inclination of the off angle θ; and splitting the wafer along the first and/or second break line. | 07-29-2010 |
| 20100200863 | ELECTRODE STRUCTURE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING THOSE - A first layer containing Ti as a constituent element, a second layer containing Nb as a constituent element, and a third layer containing Au as a constituent element are formed on a GaN substrate 11. Thereafter, the GaN substrate 11 and the first to third layers are kept at 700° C. or higher and at 1300° C. or lower. This allows a metal oxide of Ti to be distributed to extend from the interface between the GaN substrate 11 and the electrode 14 over to the inside of the electrode 14. Further, a metal nitride of Nb is formed in the inside of the GaN substrate 11. The metal nitride of Nb will be distributed to extend from the inside of the electrode 14 over to the inside of the GaN substrate 11. | 08-12-2010 |
| 20100200864 | Method for Fabricating a Semiconductor Component Based on GaN - A semiconductor component has a plurality of GaN-based layers, which are preferably used to generate radiation, produced in a fabrication process. In the process, the plurality of GaN-based layers are applied to a composite substrate that includes a substrate body and an interlayer. A coefficient of thermal expansion of the substrate body is similar to or preferably greater than the coefficient of thermal expansion of the GaN-based layers, and the GaN-based layers are deposited on the interlayer. The interlayer and the substrate body are preferably joined by a wafer bonding process. | 08-12-2010 |
| 20100200865 | GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD FOR CLEANING THE SAME - A Group-III nitride semiconductor substrate having a flat surface with a dangling bond density of higher than 14.0 nm | 08-12-2010 |
| 20100207123 | LIGHT EMITTING DEVICE - A light emitting device is provided. The light emitting device may include a plurality of light emitting elements formed on a first common electrode, each light emitting element having a first conductive layer formed over the first common electrode. The light emitting device may also include an active layer formed over the first conductive layer, a second conductive layer formed over the active layer, and an insulator formed between adjacent light emitting elements. A plurality of electrodes may be respectively formed on the plurality of light emitting elements, and a second common electrode may couple the plurality electrodes. Such a light emitting structure may improve emission characteristics, heat dissipation and high temperature reliability. | 08-19-2010 |
| 20100207124 | COMPOUND SEMICONDUCTOR DEVICE INCLUDING AIN LAYER OF CONTROLLED SKEWNESS - A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AlN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive. | 08-19-2010 |
| 20100213468 | LIGHT EMITTING DEVICE HAVING A PLURALITY OF LIGHT EMITTING CELLS AND METHOD OF FABRICATING THE SAME - Disclosed is a light emitting device having a plurality of light emitting cells. The light emitting device comprises a thermally conductive substrate, such as a SiC substrate, having a thermal conductivity higher than that of a sapphire substrate. The plurality of light emitting cells are connected in series on the thermally conductive substrate. Meanwhile, a semi-insulating buffer layer is interposed between the thermally conductive substrate and the light emitting cells. For example, the semi-insulating buffer layer may be formed of AlN or semi-insulating GaN. Since the thermally conductive substrate having a thermal conductivity higher than that of a sapphire substrate is employed, heat-dissipating performance can be enhanced as compared with a conventional sapphire substrate, thereby increasing the maximum light output of a light emitting device that is driven under a high voltage AC power source. In addition, since the semi-insulating buffer layer is employed, it is possible to prevent an increase in a leakage current through the thermally conductive substrate and between the light emitting cells. | 08-26-2010 |
| 20100219416 | METHOD OF IMPROVING SURFACE MORPHOLOGY OF (GA,AL,IN,B)N THIN FILMS AND DEVICES GROWN ON NONPOLAR OR SEMIPOLAR (GA,AL,IN,B)N SUBSTRATES - A method for improving the growth morphology of (Ga,Al,In,B)N thin films on nonpolar or semipolar (Ga,Al,In,B)N substrates, wherein a (Ga,Al,In,B)N thin film is grown directly on a nonpolar or semipolar (Ga,Al,In,B)N substrate or template and a portion of the carrier gas used during growth is comprised of an inert gas. Nonpolar or semipolar nitride LEDs and diode lasers may be grown on the smooth (Ga,Al,In,B)N thin films grown by the present invention. | 09-02-2010 |
| 20100230684 | SEMICONDUCTOR DEVICE - A semiconductor device includes a channel layer, an electron-supplying layer provided on the channel layer, a cap layer provided on the electron-supplying layer and creating lattice match with the channel layer, and ohmic electrodes provided on the cap layer. The cap layer has a composition of (In | 09-16-2010 |
| 20100230685 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM INCLUDING THE SAME - Provided are a light emitting device, a light emitting device package and a lighting system including the same. The light emitting device (LED) comprises a light emitting structure comprising a second conductive type semiconductor layer, an active layer, and a first conductive type semiconductor layer and a first electrode over the light emitting structure. A portion of the light emitting structure is sloped at a predetermined angle. | 09-16-2010 |
| 20100230686 | LIGHT EMITTING DEVICE - Disclosed are a light emitting device and a method of manufacturing the same. The light emitting device includes a plurality of compound semiconductor layers that includes a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer. An electrode is formed on the compound semiconductor layers. A groove is formed at an upper portion of the compound semiconductor layers. An electrode layer is formed under the compound semiconductor layers. | 09-16-2010 |
| 20100230687 | III NITRIDE ELECTRONIC DEVICE AND III NITRIDE SEMICONDUCTOR EPITAXIAL SUBSTRATE - In a group III nitride hetero junction transistor | 09-16-2010 |
| 20100244040 | GROUP-III NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD OF MANUFACTURING GROUP-III NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND LAMP - A group-III nitride compound semiconductor light-emitting device, a method of manufacturing the group-III nitride compound semiconductor light-emitting device, and a lamp. The method includes the steps of: forming an intermediate layer ( | 09-30-2010 |
| 20100244041 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An isolation layer for suppressing a leakage current is provided at least between a channel layer and a buffer layer formed under the channel layer in the buffer layer. | 09-30-2010 |
| 20100244042 | Group III nitride compound semiconductor light emitting element and manufacturing method thereof - A group III nitride compound semiconductor light emitting element comprising: a first layer which is a single crystal layer of a group III nitride compound semiconductor, the first layer formed on the buffer layer and including a threading dislocation; a second layer of a group III nitride compound semiconductor formed on the first layer, the second layer including a pit and a flat portion, wherein the pit continuing from the threading dislocations and having a cross section parallel to the substrate expanding in a growth direction of the second layer; a luminescent layer including a flat portion and a pit corresponding to those of the second layer. The indium concentration in the pit of the luminescent layer is smaller than that in the flat portion of the luminescent layer. A luminescent spectrum width of thereof is expanded as compared to a case where the pit does not exist. | 09-30-2010 |
| 20100244043 | ELECTRICAL DEVICES HAVING IMPROVED TRANSFER CHARACTERISTICS AND METHOD FOR TAILORING THE TRANSFER CHARACTERISTICS OF AN ELECTRICAL DEVICE - The invention concerns about electrical devices having improved transfer characteristics and a corresponding method of tailoring the transfer characteristics of such electrical devices. According to one aspect of the invention, there is provided an electrical device including at least two transistor segments or at least two transistors connected in parallel or in series characterized in that the at least two segments of the transistor or the at least two of the transistors have a different single transfer characteristic due to at least one of different topology and different material properties. | 09-30-2010 |
| 20100244044 | GaN-BASED FIELD EFFECT TRANSISTOR - The invention provides a GaN-based compound semiconductor device that is operable with low ON-resistance and high withstanding voltage. The GaN-based field effect transistor includes a buffer layer formed on a substrate, a channel layer, a drift layer formed on the channel layer, source and drain electrodes formed on the drift layer, an insulating film formed on the inner surface of a recess form in the drift layer and on the surface of the drift layer and a gate electrode formed on the insulating film and having a field plate portion. The drift layer has a reducing surface field region composed of n-type GaN-based compound semiconductor whose sheet carrier density is more than 5×10 | 09-30-2010 |
| 20100244045 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with the Schottky electrode and the ohmic electrode exposed. The second semiconductor layer has a larger band gap than that of the first semiconductor layer. | 09-30-2010 |
| 20100244046 | NITRIDE SEMICONDUCTOR DEVICE - On a processed substrate having an engraved region as a depressed portion formed thereon, a nitride semiconductor thin film is laid. The sectional area occupied by the nitride semiconductor thin film filling the depressed portion is 0.8 times the sectional area of the depressed portion or less. | 09-30-2010 |
| 20100252834 | METHOD FOR GROWING GROUP III-V NITRIDE FILM AND STRUCTURE THEREOF - A method for growing a Group III-V nitride film and a structure thereof are presented. The method is carried out by hydride vapor phase epitaxy (HVPE). The method includes the steps of, inter alia, slowly epitaxially growing a temperature ramping nitride layer on a substrate by rising a first growth temperature of 900-950° C. to a second growth temperature of 1000-1050° C. at a temperature-rising rate of 0.5-10° C./min. The lattice quality of the temperature ramping nitride layer is slowly transformed with the layer height, so that a stress induced by lattice mismatch between a sapphire substrate and a gallium nitride (GaN) layer is relieved. | 10-07-2010 |
| 20100252835 | NITRIDE SEMICONDUCTOR AND NITRIDE SEMICONDUCTOR CRYSTAL GROWTH METHOD - A base at least one principal plane of which is a nitride is prepared for use in epitaxial growth. The base is placed on a susceptor in an epitaxial growth reactor and heated to a predetermined temperature (step A). The heating is started with inactive, nitrogen gas being supplied into the reactor. Then, active, NH | 10-07-2010 |
| 20100252836 | GROUP-III NITRIDE STRUCTURE AND METHOD FOR PRODUCING A GROUP-III NITRIDE STRUCTURE - A group-III nitride structure includes a substrate | 10-07-2010 |
| 20100258812 | GROUP-III NITRIDE SEMICONDUCTOR FREESTANDING SUBSTRATE AND MANUFACTURING METHOD OF THE SAME - To provide a group-III nitride semiconductor freestanding substrate, with carrier concentration of a peripheral part of a n-type group-III nitride semiconductor freestanding substrate set to be lower than the carrier concentration inside of the peripheral part. In this freestanding substrate, preferably value Δσ obtained by dividing a difference between a maximum value of the carrier concentration and a minimum value of the carrier concentration in a surface of the freestanding substrate by the maximum value of the carrier concentration is greater than 0.05, and the carrier concentration in any place in the surface of the freestanding substrate exceeds 5.0×10 | 10-14-2010 |
| 20100258813 | Light Emitting Device and Fabrication Thereof - A light emitting diode of the invention via laser scribing method is used to build up the mesh texture on the backside of the sapphire of light emitting diodes. Then high reflectivity and thermal conductivity metals are deposited onto the mesh structure. Since the multiple-reflection from the texture, the light extraction efficiency will be increased. Meanwhile, the high thermal conductivity metal filled into the sapphire also lead to the better heat dissipation within the light emitting diodes, it will decrease the junction temperature and avoid the thermal effect to reduce light efficiency and the lifetime. | 10-14-2010 |
| 20100258814 | Light emitting diode and method of fabrication thereof - There is provided a light emitting diode fabricating method including: a) forming, on a substrate and via a buffer layer, an epitaxial growth layer that includes a light emitting layer, and forming one electrode on a surface of the epitaxial growth layer; b) joining a supporting substrate to the one electrode; c) removing, by etching, the substrate and the buffer layer; and d) forming another electrode at a region, other than a region where output light is taken-out, at a reverse surface opposite the surface of the epitaxial growth layer on which the one electrode is formed. | 10-14-2010 |
| 20100264424 | GaN LAYER CONTAINING MULTILAYER SUBSTRATE, PROCESS FOR PRODUCING SAME, AND DEVICE - A GaN layer-containing multilayer substrate employing as a substrate a single crystal that can be made to have a large diameter, a process for producing same, and a device employing the multilayer substrate. The process for producing a multilayer substrate of the present invention includes a germanium growing step of heteroepitaxially growing a germanium layer above a (111) silicon substrate by chemical vapor deposition, a heat treatment step of carrying out a heat treatment of the obtained germanium layer above the silicon substrate in a temperature range of 700° C. to 900° C., and subsequently a GaN growing step of heteroepitaxially growing a GaN layer above the germanium layer. | 10-21-2010 |
| 20100264425 | TRANSISTORS FOR REPLACING METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS IN NANOELECTRONICS - Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET) logic cells substituted for existing MOSFET-based logic cells to produce revised integrated circuit designs. Integrated circuits can include JFETS where the channel comprises a wide bandgap semiconductor material and the gate comprises a narrow bandgap semiconductor material. Mixtures of JFET and MOSFET transistors can be included on an integrated circuit design. | 10-21-2010 |
| 20100270559 | FIELD EFFECT TRANSISTOR AND PROCESS FOR MANUFACTURING SAME - A field effect transistor includes: a channel layer | 10-28-2010 |
| 20100270560 | SYSTEM AND METHOD FOR EMITTER LAYER SHAPING - Embodiments of an LED disclosed has an emitter layer shaped to a controlled depth or height relative to a substrate of the LED to maximize the light output of the LED and to achieve a desired intensity distribution. In some embodiments, the exit face of the LED may be selected to conserve radiance. In some embodiments, shaping the entire LED, including the substrate and sidewalls, or shaping the substrate alone can extract 100% or approximately 100% of the light generated at the emitter layers from the emitter layers. In some embodiments, the total efficiency is at least 90% or above. In some embodiments, the emitter layer can be shaped by etching, mechanical shaping, or a combination of various shaping methods. In some embodiments, only a portion of the emitter layer is shaped to form the tiny emitters. The unshaped portion forms a continuous electrical connection for the LED. | 10-28-2010 |
| 20100276697 | SEMICONDUCTOR DEVICE - Semiconductor devices having strong excitonic binding are disclosed. In some embodiments, a semiconductor device includes at least one active layer composed of a first compound, and at least one barrier layer composed of a second compound and disposed on at least one surface of the at least one active layer. An energy band gap of the at least one barrier layer is wider than energy band gap of the at least one active layer, and the first and/or second compounds are selected to strengthen an excitonic binding between an electron and a hole in the at least one active layer. | 11-04-2010 |
| 20100276698 | GATE ELECTRODES FOR MILLIMETER-WAVE OPERATION AND METHODS OF FABRICATION - A transistor device having a tiered gate electrode fabricated with methods using a triple layer resist structure. The triple layer resist stack is deposited on a semiconductor structure. An exposure pattern is written onto the resist stack using an e-beam writer, for example. The exposure dose is non-uniform across the device. Portions of the three resist layers are removed with a sequential development process, resulting in tiered resist structure. A conductive material is deposited to form the gate electrode. The resulting “Air-T” gate also has a three-tiered structure. The fabrication process is well-suited for the production of gates small enough for use in millimeter wave devices. | 11-04-2010 |
| 20100276699 | Silicon Carbide and Related Wide Bandgap Semiconductor Based Optically-Controlled Power Switching Devices - An optically-controlled power switch for use as an electrical switch is generally provided. The device can include a wide bandgap semiconducting material defining a stack having a p-n junction, a metal mask overlying the top surface of the stack and defining at least one opening to allow light to pass through the metal mask; a first lead wire connected to the metal stack; and a second lead wire connected to the bottom surface of the stack. | 11-04-2010 |
| 20100276700 | EXTERNAL EXTRACTION LIGHT EMITTING DIODE BASED UPON CRYSTALLOGRAPHIC FACETED SURFACES - A light emitting diode is disclosed that includes a support structure and a Group III nitride light emitting active structure mesa on the support structure. The mesa has its sidewalls along an indexed crystal plane of the Group III nitride. A method of forming the diode is also disclosed that includes the steps of removing a substrate from a Group III nitride light emitting structure that includes a sub-mount structure on the Group III nitride light emitting structure opposite the substrate, and thereafter etching the surface of the Group III nitride from which the substrate has been removed with an anisotropic etch to develop crystal facets on the surface in which the facets are along an index plane of the Group III nitride. The method can also include etching the light emitting structure with an anisotropic etch to form a mesa with edges along an index plane of the Group III nitride. | 11-04-2010 |
| 20100283060 | Field effect transistor - A material of a gate electrode is a conductive oxide having a higher work function than that of conventionally used Pd and so on, thereby achieving a normally-off transistor without reducing the sheet carrier concentration of a heterojunction. It is thus possible to achieve a normally-off operation while reducing an increase in the specific on-state resistance. | 11-11-2010 |
| 20100289029 | EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE - An epitaxial substrate having preferable two dimensional electron gas characteristic and contact characteristic is provided in the present invention. A channel layer is formed on a base substrate with GaN. A spacer layer is formed on the channel layer with AlN. A barrier layer is formed on the spacer layer with group III nitride having a composition of In | 11-18-2010 |
| 20100295054 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD FOR FABRICATING THE SAME - The semiconductor light-emitting element includes a group III nitride semiconductor multilayer structure having an active layer containing In as well as a p-type layer and an n-type layer stacked to hold the active layer therebetween. The group III nitride semiconductor multilayer structure is made of a group III nitride semiconductor having a major surface defined by a nonpolar plane whose offset angle in a c-axis direction is negative. A remarkable effect is attained when the emission wavelength of the active layer is not less than 450 nm. In the group III nitride semiconductor constituting the group III nitride semiconductor multilayer structure, the offset angle θ in the c-axis direction preferably satisfies −1°<θ<0°. | 11-25-2010 |
| 20100295055 | NITRIDE SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME - To improve an adhesion to a substrate holder, and improve a device production yield by uniformizing a temperature distribution in a surface of a substrate and uniformizing characteristics such as a film thickness. When a concave warpage is set to be negative on a substrate front side, and a convex warpage is set to be positive on the substrate front side, then a line segment is drawn from one end of a substrate rear surface to the other end of the substrate rear surface, passing through a substrate center line, and a substrate is sliced by this line segment in a substrate thickness direction, a maximum value of shortest values of a distance from an arbitrary point on the drawn line segment to a rear side outline in a sliced surface, is defined as warpage H in a diameter direction, and when the warpage H in the diameter direction is obtained in a substrate peripheral direction, with its maximum value set to be Hmax, and its minimum value set to be Hmin, the warpage H in the diameter direction is defined to satisfy Hmax−Hmin≦30 μm. | 11-25-2010 |
| 20100295056 | III-NITRIDE MATERIALS INCLUDING LOW DISLOCATION DENSITIES AND METHODS ASSOCIATED WITH THE SAME - Semiconductor structures including one, or more, III-nitride material regions (e.g., gallium nitride material region) and methods associated with such structures are provided. The III-nitride material region(s) advantageously have a low dislocation density and, in particular, a low screw dislocation density. In some embodiments, the presence of screw dislocations in the III-nitride material region(s) may be essentially eliminated. The presence of a strain-absorbing layer underlying the III-nitride material region(s) and/or processing conditions can contribute to achieving the low screw dislocation densities. In some embodiments, the III-nitride material region(s) having low dislocation densities include a gallium nitride material region which functions as the active region of the device. The low screw dislocation densities of the active device region (e.g., gallium nitride material region) can lead to improved properties (e.g., electrical and optical) by increasing electron transport, limiting non-radiative recombination, and increasing compositional/growth uniformity, amongst other effects. | 11-25-2010 |
| 20100295057 | DOWN-CONVERTED LIGHT SOURCE WITH UNIFORM WAVELENGTH EMISSION - An arrangement of light sources is attached to a semiconductor wavelength converter. Each light source emits light at a respective peak wavelength, and the arrangement of light sources is characterized by a first range of peak wavelengths. The semiconductor wavelength converter is characterized by a second range of peak wavelengths when pumped by the arrangement of light sources. The second range of peak wavelengths is narrower than the first range of peak wavelengths. The semiconductor wavelength converter is characterized by an absorption edge having a wavelength longer than the longest peak wavelength of the light sources. The wavelength converter may also be used for reducing the wavelength variation in the output from an extended light source. | 11-25-2010 |
| 20100301347 | WAFER BONDING TECHNIQUE IN NITRIDE SEMICONDUCTORS - A semiconductor arrangement is provided that includes one or more substrate structures. One or more nitride-based material structures are used in fabricating nitride-based devices. One or more intermediary layers are interposed between the one or more substrate structures and the one or more nitride-based material structures. The one or more intermediary layers support the lattice mismatch and thermal expansion coefficients between the one or more nitride-based material structure and the one or more substrate structures. Several new electronic devices based on this arrangement are described. | 12-02-2010 |
| 20100301348 | Nitride semiconductor wafer, nitride semiconductor chip, and method of manufacture of nitride semiconductor chip - A nitride semiconductor chip is provided that offers enhanced luminous efficacy as a result of an improved EL emission pattern. The nitride semiconductor laser chip (nitride semiconductor chip) has an n-type GaN substrate having as a principal growth plane a plane having an off-angle in the a-axis direction relative to the m plane, and a nitride semiconductor layer formed on the principal growth plane of the n-type GaN substrate. The n-type GaN substrate includes a depressed portion (carved region), which is carved from the principal growth plane in the thickness direction, and an uncarved region, which is a region not carved. The nitride semiconductor layer formed on the n-type GaN substrate has a gradient thickness region whose thickness decreases in a gradient fashion toward the depressed portion (carved region) and an emission portion formation region whose thickness varies very little. In the emission portion formation region | 12-02-2010 |
| 20100301349 | WAFER LEVEL LED PACKAGE STRUCTURE FOR INCREASING LIGHT-EMITTING EFFICIENCY AND HEAT-DISSIPATING EFFECT AND METHOD FOR MANUFACTURING THE SAME - A wafer level LED package structure includes a light-emitting unit, a reflecting unit, a first conductive unit and a second conductive unit. The light-emitting unit has a substrate body, a light-emitting body disposed on the substrate body, a positive and a negative conductive layers formed on the light-emitting body, and a light-emitting area formed in the light-emitting body. The reflecting unit has a reflecting layer formed between the positive and the negative conductive layers and on the substrate body for covering external sides of the light-emitting body. The first conductive unit has a first positive conductive layer formed on the positive conductive layer and a first negative conductive layer formed on the negative conductive layer. The second conductive unit has a second positive conductive structure formed on the first positive conductive layer and a second negative conductive structure formed on the first negative conductive layer. | 12-02-2010 |
| 20100308339 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM INCLUDING THE SAME - Provided are a light emitting device (LED), a light emitting device package and a lighting system including the same. The LED includes a light emitting structure having a second semiconductor layer of a second conductivity type, an active layer on the second semiconductor layer, and a first semiconductor layer of a first conductivity type on the active layer, a current blocking layer below the second semiconductor layer, a second electrode below the second semiconductor layer, and a first electrode on the first semiconductor layer. The current blocking layer includes a non second conductive region. | 12-09-2010 |
| 20100314625 | GaN Single-Crystal Mass and Method of Its Manufacture, and Semiconductor Device and Method of Its Manufacture - Affords a GaN single-crystal mass, a method of its manufacture, and a semiconductor device and method of its manufacture, whereby when the GaN single-crystal mass is being grown, and when the grown GaN single-crystal mass is being processed into a substrate or like form, as well as when an at least single-lamina semiconductor layer is being formed onto a single-crystal GaN mass in substrate form to manufacture semiconductor devices, cracking is controlled to a minimum. The GaN single-crystal mass | 12-16-2010 |
| 20100320474 | GALLIUM NITRIDE FOR LIQUID CRYSTAL ELECTRODES - Described herein is a liquid crystal (LC) device having Gallium Nitride HEMT electrodes. The Gallium Nitride HEMT electrodes can be grown on a variety of substrates, including but not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer), and spinel. Also described is a structure provided from GaN HEMT grown on large area silicon substrates and transferred to another substrate with appropriate properties for OPA devices. Such substrates include, but are not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer), and spinel. The GaN HEMT structure includes an AlN interlayer for improving the mobility of the structure. | 12-23-2010 |
| 20100320475 | ETCHING TECHNIQUE FOR THE FABRICATION OF THIN (Al, In, Ga)N LAYERS - An etching technique for the fabrication of thin (Al, In, Ga)N layers. A suitable template or substrate is selected and implanted with foreign ions over a desired area to create ion implanted material. A regrowth of a device structure is then performed on the implanted template or substrate. The top growth surface of the template is bonded to a carrier wafer to created a bonded template/carrier wafer structure. The substrate is removed, as is any residual material, to expose the ion implanted material. The ion implanted material on the bonded template/carrier wafer structure is then exposed to a suitable etchant for a sufficient time to remove the ion implanted material. | 12-23-2010 |
| 20100327291 | Single crystal group III nitride articles and method of producing same by HVPE method incorporating a polycrystalline layer for yield enhancement - In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article. | 12-30-2010 |
| 20100327292 | METHOD OF OBTAINING BULK MONO-CRYSTALLINE GALLIUM-CONTAINING NITRIDE, BULK MONO-CRYSTALLINE GALLIUM-CONTAINING NITRIDE, SUBSTRATES MANUFACTURED THEREOF AND DEVICES MANUFACTURED ON SUCH SUBSTRATES - The invention is related to a method of obtaining bulk mono-crystalline gallium-containing nitride, comprising a step of seeded crystallization of mono-crystalline gallium-containing nitride from supercritical ammonia-containing solution, containing ions of Group I metals and ions of acceptor dopant, wherein at process conditions the molar ratio of acceptor dopant ions to supercritical ammonia-containing solvent is at least 0.0001. According to said method, after said step of seeded crystallization the method further comprises a step of annealing said nitride at the temperature between 950° C. and 1200° C., preferably between 950° C. and 1150° C. | 12-30-2010 |
| 20100327293 | FIELD-EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased. | 12-30-2010 |
| 20110001142 | METHOD FOR MANUFACTURING ELECTRONIC DEVICE, METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE, III NITRIDE SEMICONDUCTOR ELEMENT AND GALLIUM NITRIDE EPITAXIAL SUBSTRATE | 01-06-2011 |
| 20110006307 | Group III-Nitride Semiconductor Schottky Diode and Its Fabrication Method - A group III-nitride semiconductor Schottky diode comprises a conducting substrate having a first surface, a stack of multiple layers including a buffer layer and a semiconductor layer sequentially formed on the first surface, wherein the semiconductor layer comprises a group III nitride compound, a first electrode on the semiconductor layer, and a second electrode formed in contact with the first surface at a position adjacent to the stack of multiple layers. In other embodiments, the application also describes a method of fabricating the group III-nitride semiconductor Schottky diode. | 01-13-2011 |
| 20110006308 | SEMICONDUCTOR DEVICE - To obtain a device in which a buffer leak on a GaN substrate is reduced. | 01-13-2011 |
| 20110012126 | NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE - An object is to provide a nitride-based semiconductor light emitting device capable of preventing a Schottky barrier from being formed at an interface between a contact layer and an electrode. LD | 01-20-2011 |
| 20110012127 | GaN CRYSTAL SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a GaN crystal substrate, a rear surface opposite to a crystal growth surface can have a warpage w | 01-20-2011 |
| 20110012128 | METHOD FOR MANUFACTURING A LAYER OF GALLIUM NITRIDE OR GALLIUM AND ALUMINUM NITRIDE - The present invention relates to a method for manufacturing a crack free monocrystalline nitride layer having the composition Al | 01-20-2011 |
| 20110018002 | TRANSISTORS AND RECTIFIERS UTILIZING HYBRID ELECTRODES AND METHODS OF FABRICATING THE SAME - Systems, methods, and apparatus described herein are associated with devices including hybrid electrodes. A heterostructure semiconductor transistor can include a III-N-type semiconductor heterostructure including a barrier layer overlying an active layer and a hybrid electrode region including a hybrid drain electrode region. Further, a heterostructure semiconductor rectifier can include a III-N-type semiconductor heterostructure and a hybrid electrode region including a hybrid cathode electrode region. Furthermore, the hybrid electrode region of the transistor and rectifier can include permanently trapped charge located under a Schottky contact of the hybrid electrode region. | 01-27-2011 |
| 20110018003 | GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a group III nitride semiconductor substrate includes the growth step of epitaxially growing a first group III nitride semiconductor layer on an underlying substrate, and the process step of forming a first group III nitride semiconductor substrate by cutting and/or surface-polishing the first group III nitride semiconductor layer. In the growth step, at least one element selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb is added as an impurity element by at least 1×10 | 01-27-2011 |
| 20110037075 | PROCESS FOR FABRICATING A STRUCTURE FOR EPITAXY WITHOUT AN EXCLUSION ZONE - A process for fabricating a composite structure for epitaxy, including at least one crystalline growth seed layer of semiconductor material on a support substrate, with the support substrate and the crystalline growth seed layer each having, on the periphery of their bonding face, a chamfer or an edge rounding zone. The process includes at least one step of wafer bonding the crystalline growth seed layer directly onto the support substrate and at least one step of thinning the crystalline growth seed layer. After thinning, the crystalline growth seed layer has a diameter identical to its initial diameter. | 02-17-2011 |
| 20110042680 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A light emitting device includes: a conductive substrate; a metal film provided above the conductive substrate; a light emitting layer provided above the metal film; an electrode provided partly above the light emitting layer; and a current suppression layer being in contact with the metal film, provided in a region including at least part of an immediately underlying region of the electrode, and configured to suppress current, a first portion of the metal film including at least part of a portion located between the current suppression layer and the electrode, being separated from an portion other than the first portion. | 02-24-2011 |
| 20110042681 | N-SIDE ELECTRODE, NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT - An n-side electrode that can inhibit the reduction in ohmic properties is provided. The n-side electrode is an n-side electrode for a nitride semiconductor light-emitting element, and includes an Al layer forming an ohmic contact to an n-type nitride semiconductor layer and having a thickness of 30 nm or greater. | 02-24-2011 |
| 20110042682 | INCLUSION-FREE UNIFORM SEMI-INSULATING GROUP III NITRIDE SUBSTRATES AND METHODS FOR MAKING SAME - In a method for making an inclusion-free uniformly semi-insulating GaN crystal, an epitaxial nitride layer is deposited on a substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode, wherein a surface of the nucleation layer is substantially covered with pits and the aspect ratio of the pits is essentially the same. A GaN transitional layer is grown on the nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. After growing the transitional layer, a surface of the transitional layer is substantially pit-free. A bulk GaN layer is grown on the transitional layer by HVPE. After growing the bulk layer, a surface of the bulk layer is smooth and substantially pit-free. The GaN is doped with a transition metal during at least one of the foregoing GaN growth steps. | 02-24-2011 |
| 20110042683 | CRACK FREE MULTILAYERED DEVICES, METHODS OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME - Disclosed herein is an article comprising a substrate; an interlayer comprising aluminum nitride, gallium nitride, boron nitride, indium nitride or a solid solution of aluminum nitride, gallium nitride, boron nitride and/or indium nitride; the interlayer being directly disposed upon the substrate and in contact with the substrate; where the interlayer comprises a columnar film and/or nanorods and/or nanotubes; and a group-III nitride layer disposed upon the interlayer; where the group-III nitride layer completely covers a surface of the interlayer that is opposed to a surface in contact with the substrate; the group-III nitride layer being free from cracks. | 02-24-2011 |
| 20110042684 | Method of Growing AlN Crystals, and AlN Laminate - Affords an AlN crystal growth method, and an AlN laminate, wherein AlN of favorable crystalline quality is grown. The AlN crystal growth method is provided with the following steps. To begin with, a source material ( | 02-24-2011 |
| 20110049526 | Semiconductor Devices with Field Plates - A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer. | 03-03-2011 |
| 20110049527 | SEMICONDUCTOR DEVICE - A semiconductor device comprising: an active layer, which has a composition represented by the formula: Al | 03-03-2011 |
| 20110049528 | METHODS FOR FABRICATING COMPOUND MATERIAL WAFERS - Reconditioned donor substrates that include a remainder substrate from a donor substrate wherein the remainder substrate has a detachment surface where a transfer layer was detached and an opposite surface; and an additional layer deposited upon the opposite surface of the remainder substrate to increase its thickness and to form the reconditioned substrate. The reconditioned substrate is recycled as a donor substrate for fabricating compound material wafers and is typically made from gallium nitride donor substrates. | 03-03-2011 |
| 20110049529 | GaN-BASED SEMICONDUCTOR ELEMENT AND METHOD OF MANUFACTURING THE SAME - Provided is a GaN series semiconductor element, which is capable of obtaining an adequate normally-off characteristic, and a manufacturing method thereof. | 03-03-2011 |
| 20110057196 | GaN HEMT with Nitrogen-Rich Tungsten Nitride Schottky Gate and Method of Forming the Same - A GaN HEMT with Schottky gate is disclosed. The GaN HEMT sequentially has a GaN layer, an AlGaN layer, and a Schottky gate on a substrate, and a source and a drain on two sides of the Schottky gate. The Schottky gate is made by a material of nitrogen-rich tungsten nitride, which has a nitrogen content of about 0.5 molar ratio. | 03-10-2011 |
| 20110057197 | GaN SINGLE CRYSTAL SUBSTRATE AND METHOD OF MANUFACTURING THEREOF AND GaN-BASED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A GaN single crystal substrate has a main surface with an area of not less than 10 cm | 03-10-2011 |
| 20110057198 | TECHNIQUE FOR DEVELOPMENT OF HIGH CURRENT DENSITY HETEROJUNCTION FIELD EFFECT TRANSISTORS BASED ON (10-10)-PLANE GaN BY DELTA-DOPING - A delta (δ)-doped (10-10)-plane GaN transistor is disclosed. Delta doping can achieve a transistor having at least 10 times higher current density than a conventional (10-10)-plane GaN transistor. | 03-10-2011 |
| 20110057199 | Antistatic Gallium Nitride Based Light Emitting Device and Method for Fabricating the Same - The invention provides an antistatic gallium nitride based light emitting device and a method for fabricating the same. The method includes: growing an n-type GaN-based epitaxial layer, an active layer, a p-type GaN-based epitaxial layer and an undoped GaN-based epitaxial layer sequentially on a substrate; etching to remove parts of the layers above, to expose a part of the n-type GaN-based epitaxial layer, with the unetched part defined as an emitting area; etching to remove a part of the undoped GaN-based epitaxial layer; forming an ohmic contact electrode on an exposed part of p-type GaN-based epitaxial layer, and forming a Schottky contact electrode on another part; forming a p-electrode on a transparent conducting layer such that the p-electrode is electrically connected with the ohmic contact electrode; forming an n-electrode on the exposed n-type GaN-based epitaxial layer; and forming a connecting conductor on an insulation layer such that the connecting conductor is electrically connected with the n-electrode and the Schottky contact electrode. By forming a GaN Schottky diode directly on a p-type GaN-based epitaxial layer, the fabrication process is simplified while providing antistatic ability at the same time, and the emitting area is made the maximum use of so as to avoid the drop in the luminous efficiency of the GaN-based LED. | 03-10-2011 |
| 20110057200 | GROUP III NITRIDE SEMICONDUCTOR DEVICE, EPITAXIAL SUBSTRATE, AND METHOD OF FABRICATING GROUP III NITRIDE SEMICONDUCTOR DEVICE - A group III nitride semiconductor device having a gallium nitride based semiconductor film with an excellent surface morphology is provided. A group III nitride optical semiconductor device | 03-10-2011 |
| 20110057201 | LED Element with a Thin-layer Semiconductor Element Made of Gallium Nitride - An LED module comprising an LED chip, with an active gallium nitride layer and a silicon platform on which the LED chip is arranged, wherein the silicon platform has two electrodes on the side facing away from the LED chip which are electrically connected to the LED chip and wherein the thickness of the gallium nitride layer of the LED chip is between 2 μm and 10 μm, preferably 1 μm to 5 μm. | 03-10-2011 |
| 20110062448 | Field effect semiconductor devices and methods of manufacturing field effect semiconductor devices - Field effect semiconductor devices and methods of manufacturing the same are provided, the field effect semiconductor devices include a second semiconductor layer on a first surface of a first semiconductor layer, a first and a second third semiconductor layer respectively on two sides of the second semiconductor layer, a source and a drain respectively on the first and second third semiconductor layer, and a gate electrode on a second surface of the first semiconductor layer. | 03-17-2011 |
| 20110062449 | TECHNIQUE FOR THE GROWTH AND FABRICATION OF SEMIPOLAR (GA,AL,IN,B)N THIN FILMS, HETEROSTRUCTURES, AND DEVICES - A method for growth and fabrication of semipolar (Ga, Al, In, B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga, Al, In, B)N template or nucleation layer on the substrate, and growing the semipolar (Ga, Al, In, B)N thin films, heterostructures or devices on the planar semipolar (Ga, Al, In, B)N template or nucleation layer. The method results in a large area of the semipolar (Ga, Al, In, B)N thin films, heterostructures, and devices being parallel to the substrate surface. | 03-17-2011 |
| 20110068347 | Nitride Semiconductor Structure and Method of Making Same - A structure method for producing same provides suppressed lattice defects when epitaxially forming nitride layers over non-c-plane oriented layers, such as a semi-polar oriented template layer or substrate. A patterned mask with “window” openings, or trenches formed in the substrate with appropriate vertical dimensions, such as the product of the window width times the cotangent of the angle between the surface normal and the c-axis direction, provides significant blocking of all diagonally running defects during growth. In addition, inclined posts of appropriate height and spacing provide a blocking barrier to vertically running defects is created. When used in conjunction with the aforementioned aspects of mask windows or trenches, the post structure provides significant blocking of both vertically and diagonally running defects during growth. | 03-24-2011 |
| 20110068348 | THIN BODY MOSFET WITH CONDUCTING SURFACE CHANNEL EXTENSIONS AND GATE-CONTROLLED CHANNEL SIDEWALLS - A thin body MOSFET with conducting surface channel extensions and gate-controlled channel sidewalls is described. One embodiment is a MOSFET comprising a semiconductor substrate; a channel layer disposed on a top surface of the substrate; a gate dielectric layer interposed between a gate electrode and the channel layer; and dielectric extension layers disposed on top of the channel layer and interposed between the gate electrode and Ohmic contacts. The gate dielectric layer comprises a first material, the first material forming an interface of low defectivity with the channel layer. In contrast, the dielectric extensions comprise a second material different than the first material, the second material forming a conducting surface channel with the channel layer. | 03-24-2011 |
| 20110068349 | SEMICONDUCTOR LIGHT EMITTING ELEMENT, METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENT, AND LAMP - A semiconductor light-emitting device ( | 03-24-2011 |
| 20110073870 | III-NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - The present III-nitride semiconductor light-emitting device comprises: a first III-nitride semiconductor layer having a first conductivity type; a second III-nitride semiconductor layer having a second conductivity type different from the first conductivity type; an active layer disposed between the first III-nitride semiconductor layer and the second III-nitride semiconductor layer and generating light by recombination of electrons and holes; and a depletion barrier layer brought into contact with the active layer and having a first conductivity type. | 03-31-2011 |
| 20110073871 | GALLIUM NITRIDE SUBSTRATE - A gallium nitride substrate comprising a primary surface, the primary surface being tilted at an angle in a range of 20 to 160 degrees with respect to a C-plane of the substrate, and the substrate having a fracture toughness of more than or equal to 1.36 MN/m | 03-31-2011 |
| 20110079790 | GROUP III NITRIDE SEMICONDUCTOR ELEMENT AND EPITAXIAL WAFER - A primary surface | 04-07-2011 |
| 20110089430 | Compound semiconductor device and method for fabricating the same - The compound semiconductor device comprises an i-GaN buffer layer | 04-21-2011 |
| 20110101369 | Gallium nitride semiconductor device with improved termination scheme - This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area disposed at a peripheral area of the semiconductor power device comprises a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein. | 05-05-2011 |
| 20110101370 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device and method of manufacturing the device is disclosed. In one aspect, the device includes a semiconductor substrate and a GaN-type layer stack on top of the semiconductor substrate. The GaN-type layer stack has at least one buffer layer, a first active layer and a second active layer. Active device regions are definable at an interface of the first and second active layer. The semiconductor substrate is present on an insulating layer and is patterned to define trenches according to a predefined pattern, which includes at least one trench underlying the active device region. The trenches extend from the insulating layer into at least one buffer layer of the GaN-type layer stack and are overgrown within the at least one buffer layer, so as to obtain that the first and the second active layer are continuous at least within the active device regions. | 05-05-2011 |
| 20110101371 | Gallium nitride semiconductor - A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts. | 05-05-2011 |
| 20110101372 | NITRIDE SEMICONDUCTOR ELEMENT AND METHOD FOR PRODUCING THE SAME - A nitride-based semiconductor light-emitting device | 05-05-2011 |
| 20110101373 | METHOD OF FORMING A COMPOSITE LASER SUBSTRATE - A composite substrate for laser devices is disclosed having improved wave guiding properties, improved lattice matching, improved thermal expansion matching, and improved thermal conductivity. The composite substrate has an intermediate layer ( | 05-05-2011 |
| 20110108850 | METHOD OF MANUFACTURING AN INTEGRATED SEMICONDUCTOR SUBSTRATE STRUCTURE - An integrated semiconductor substrate structure is disclosed. In one aspect, the structure includes a substrate, a GaN-heterostructure and a semiconductor substrate layer. The GaN heterostructure is present in a first device area for definition of GaN-based devices, and is covered at least partially with a protection layer. The semiconductor substrate layer is present in a second device area for definition of CMOS devices. At least one of the GaN heterostructure and the semiconductor substrate layer is provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed. | 05-12-2011 |
| 20110108851 | VERTICAL LIGHT EMITTING DIODE HAVING AN OUTWARDLY DISPOSED ELECTRODE - The invention relates to a vertical light emitting diode (VLED) having an outwardly disposed electrode, the vertical light emitting diode comprises a conductive base, a semiconductor epitaxial structure formed on the conductive base, a passivation layer formed at the periphery of the semiconductor epitaxial structure, and a conductive frame formed on the passivation layer and contacting with the edge of the upper surface of the semiconductor epitaxial structure such that the conductive frame is electrically connected to the semiconductor epitaxial structure. | 05-12-2011 |
| 20110108852 | GaN SUBSTRATE AND LIGHT-EMITTING DEVICE - The present GaN substrate can have an absorption coefficient not lower than 7 cm | 05-12-2011 |
| 20110114965 | METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES AND DEVICES USING GLASS BONDING LAYERS, AND SEMICONDUCTOR STRUCTURES AND DEVICES FORMED BY SUCH METHODS - Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to a substrate using a glass may be utilized to control the strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control the strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material. | 05-19-2011 |
| 20110114966 | LIGHT EMITTING DIODE DEVICE - A high-brightness vertical light emitting diode (LED) device having an outwardly located metal electrode. The LED device is formed by: forming the metal electrode on an edge of a surface of a LED epitaxy structure using a deposition method, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), evaporation, electro-plating, or any combination thereof; and then performing a packaging process. The composition of the LED may be a nitride, a phosphide or an arsenide. The LED of the invention has the following advantages: improving current spreading performance, reducing light-absorption of the metal electrode, increasing brightness, increasing efficiency, and thereby improving energy efficiency. The metal electrode is located on the edge of the device and on the light emitting side. The metal electrode has two side walls, among which one side wall can receive more emission light from the device in comparison with the other one. | 05-19-2011 |
| 20110114967 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode. | 05-19-2011 |
| 20110121310 | SOLID STATE LIGHTING DEVICES WITH SELECTED THERMAL EXPANSION AND/OR SURFACE CHARACTERISTICS, AND ASSOCIATED METHODS - Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods are disclosed. A method in accordance with a particular embodiment includes forming an SSL (solid state lighting) formation structure having a formation structure coefficient of thermal expansion (CTE), selecting a first material of an interlayer structure to have a first material CTE greater than the substrate CTE, and selecting a second material of the interlayer structure based at least in part on the second material having a second material CTE less than the first material CTE. The method can further include forming the interlayer structure over the SSL formation structure by disposing (at least) a first layer of the first material over the SSL formation structure, a portion of the second material over the first material, and a second layer of the first material over the second material. The SSL formation structure supports an SSL emitter material, and the method further includes counteracting a force placed on the formation structure by the first material, by virtue of the difference between the second material CTE and the first material CTE. In other embodiments, the SSL formation structure can have an off-cut angle with a non-zero value of up to about 4.5 degrees. | 05-26-2011 |
| 20110121311 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE - The present invention provides a method for manufacturing a semiconductor substrate including a low-resistance nitride layer laminated on a substrate, a method for manufacturing a semiconductor device, a semiconductor substrate, and a semiconductor device. A method for manufacturing a semiconductor substrate of the present invention includes the following steps: A nitride substrate having a principal surface and a back surface opposite to the principal surface is prepared. Vapor-phase ions are implanted into the back surface of the nitride substrate. The back surface of the nitride substrate is bonded to a dissimilar substrate to form a bonded substrate. The nitride substrate is partially separated from the bonded substrate to form a laminated substrate including the dissimilar substrate and a nitride layer. The laminated substrate is heat-treated at a temperature over 700° C. | 05-26-2011 |
| 20110121312 | OPTICAL SEMICONDUCTOR DEVICE HAVING UNEVEN SEMICONDUCTOR LAYER WITH NON-UNIFORM CARRIER DENSITY - In an optical semiconductor device including a first semiconductor layer of a first conductivity type, an active layer provided on the first semiconductor layer, a second semiconductor layer of a second conductivity type provided on the active layer, an insulating layer provided on a part of the second semiconductor layer, an uneven semiconductor layer of the second conductivity type provided on another part of the second semiconductor layer, and an electrode layer provided on the insulating layer and the uneven semiconductor layer, a density of carriers of the second conductivity type being larger at a tip portion of the uneven semiconductor layer than at a bottom portion of the uneven semiconductor layer. | 05-26-2011 |
| 20110121313 | Enhancement Mode III-Nitride Transistors with Single Gate Dielectric Structure - According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge. | 05-26-2011 |
| 20110121314 | ENHANCEMENT MODE GALLIUM NITRIDE POWER DEVICES - Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices. | 05-26-2011 |
| 20110127539 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A nitride semiconductor light-emitting device includes an n type nitride semiconductor layer, a light-emitting layer formed on the n type nitride semiconductor layer, a first p type nitride semiconductor layer formed on the light-emitting layer, an intermediate layer formed on the first p type nitride semiconductor layer to alternately cover and expose a surface of the first p type nitride semiconductor layer, and a second p type nitride semiconductor layer formed on the intermediate layer. The intermediate layer is made of a compound containing Si and N as constituent elements. | 06-02-2011 |
| 20110127540 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate on which a GaN channel layer, an AlGaN electron supply layer and a GaN cap layer are stacked in this order, a gate electrode formed on the GaN cap layer, and a source electrode and a drain electrode formed on the AlGaN electron supply layer so as to interpose the gate electrode. A first recess is formed in the GaN cap layer and being located between the gate electrode and the source electrode. A thickness of the GaN cap layer in a bottom of the first recess is less than that of the GaN cap layer located under the gate electrode. | 06-02-2011 |
| 20110127541 | SEMICONDUCTOR HETEROSTRUCTURE DIODES - Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG. | 06-02-2011 |
| 20110133203 | TRANSPARENT CERAMIC PHOTO-OPTICAL SEMICONDUCTOR HIGH POWER SWITCHES - A photoconductive semiconductor switch according to one embodiment includes a structure of sintered nanoparticles of a high band gap material exhibiting a lower electrical resistance when excited by light relative to an electrical resistance thereof when not exposed to the light. A method according to one embodiment includes creating a mixture comprising particles, at least one dopant, and at least one solvent; adding the mixture to a mold; forming a green structure in the mold; and sintering the green structure to form a transparent ceramic. Additional system, methods and products are also presented. | 06-09-2011 |
| 20110133204 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode includes a thermal conductive substrate, an p-type GaN layer, an active layer and an n-type GaN layer sequentially stacked above the substrate and an electrode pad deposited on the n-type GaN layer. A surface of n-type GaN layer away from the active layer has a first diffusing section and a second diffusing section. The first diffusing section is adjacent to the electrode pad and the second diffusing section is located at the other side of the first diffusing section opposite to the electrode pad, wherein the doping concentration of the first diffusing section is less than that of the second diffusing section. The n-type GaN layer has an electrical resistance larger than that of the first diffusing section which in turn is larger than that of the second diffusing section. | 06-09-2011 |
| 20110133205 | FIELD-EFFECT TRANSISTOR - A field-effect transistor provided with a channel layer, a carrier supply layer forming a heterojunction with the channel layer, a recessed portion recessed from a surface of the carrier supply layer, a first insulating layer formed at least along the recessed portion, a first gate electrode formed on the first insulating layer, a source electrode formed on one side of the recessed portion in a channel lengthwise direction, and a drain electrode formed on an opposite side of the recessed portion in the channel lengthwise direction. The recessed portion snakes in a direction intersecting the channel lengthwise direction, in the range of a channel length between the source electrode and the drain electrode. | 06-09-2011 |
| 20110133206 | Compound semiconductor device - At a gate electrode formed on a compound semiconductor layer with a Schottky junction, a diffusion preventing layer made of Ti | 06-09-2011 |
| 20110133207 | GROUP III NITRIDE SUBSTRATE, EPITAXIAL LAYER-PROVIDED SUBSTRATE, METHODS OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate ( | 06-09-2011 |
| 20110133208 | SEMICONDUCTOR ELEMENT - Light extraction efficiency of a semiconductor light-emitting element is improved. A buffer layer, an n-type GaN layer, an InGaN emission layer, and a p-type GaN layer are laminated on a sapphire substrate in a semiconductor light-emitting element. A ZnO layer functioning as a transparent electrode is provided on the p-type GaN layer and concave portions are formed on a surface of the ZnO layer at two-dimensional periodic intervals. If a wavelength of light from the InGaN emission layer in the air is λ, an index of refraction of the ZnO layer at the wavelength λ is n | 06-09-2011 |
| 20110133209 | GaN SUBSTRATE, EPITAXIAL LAYER-PROVIDED SUBSTRATE, METHODS OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A GaN substrate on which an epitaxially grown layer of good quality can be formed is obtained. A GaN substrate as a group III nitride substrate has a surface in which the number of chlorine atoms per square centimeter of the surface is not more than 2×10 | 06-09-2011 |
| 20110133210 | SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING SCHOTTKY BARRIER DIODE - A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×10 | 06-09-2011 |
| 20110140121 | ENHANCEMENT NORMALLY OFF NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to an enhancement normally off nitride semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buffer layer on a substrate; forming a first nitride semiconductor layer on the buffer layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer; etching a gate region above the second nitride semiconductor layer up to a predetermined depth of the first nitride semiconductor layer; forming an insulating film on the etched region and the second nitride semiconductor layer; patterning a source/drain region, etching the insulating film in the source/drain region, and forming electrodes in the source/drain region; and forming a gate electrode on the insulating film in the gate region. In this manner, the present invention provides a method of easily implementing a normally off enhancement semiconductor device by originally blocking 2DEG which is generated under a gate region. In addition, the present invention provides an enhancement normally off power semiconductor device with a simple and efficient driving circuit in a HEMT device. | 06-16-2011 |
| 20110140122 | LARGE AREA, UNIFORMLY LOW DISLOCATION DENSITY GaN SUBSTRATE AND PROCESS FOR MAKING THE SAME - Large area single crystal III-V nitride material having an area of at least 2 cm | 06-16-2011 |
| 20110140123 | Nitride-Based Transistors With a Protective Layer and a Low-Damage Recess - Transistors are fabricated by forming a nitride-based semiconductor barrier layer on a nitride-based semiconductor channel layer and forming a protective layer on a gate region of the nitride-based semiconductor barrier layer. Patterned ohmic contact metal regions are formed on the barrier layer and annealed to provide first and second ohmic contacts. The annealing is carried out with the protective layer on the gate region. A gate contact is also formed on the gate region of the barrier layer. Transistors having protective layer in the gate region are also provided as are transistors having a barrier layer with a sheet resistance substantially the same as an as-grown sheet resistance of the barrier layer. | 06-16-2011 |
| 20110140124 | PASSIVATION OF ALUMINUM NITRIDE SUBSTRATES - The present invention provides methods of protecting a surface of an aluminum nitride substrate. The substrate with the protected surface can be stored for a period of time and easily activated to be in a condition ready for thin film growth or other processing. In certain embodiments, the method of protecting the substrate surface comprises forming a passivating layer on at least a portion of the substrate surface by performing a wet etch, which can comprise the use of one or more organic compounds and one or more acids. The invention also provides aluminum nitride substrates having passivated surfaces. | 06-16-2011 |
| 20110140125 | LIGHT EMITTING DIODES WITH SMOOTH SURFACE FOR REFLECTIVE ELECTRODE - A light emitting diode comprising an epitaxial layer structure, a first electrode, and a second electrode. The first and second electrodes are disposed on one side of the epitaxial layer structure. The epitaxial layer structure includes a transparent ohmic contact layer having a root-means-square (RMS) roughness less than about 3 nm at a surface whereon the second electrode is formed. The epitaxial layer structure includes a p-type epitaxial layer and a n-type epitaxial layer, wherein the n-type epitaxial layer is coupled between the first electrode and the p-type epitaxial layer, and the p-type epitaxial layer is between the second electrode and the n-type epitaxial layer. The first electrode is located on the n-type epitaxial layer. | 06-16-2011 |
| 20110147759 | GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME - A Group III nitride semiconductor substrate is provided, with diameter of 25 mm or more and thickness of 250 μm or more, wherein in at least an outer edge side part of an outer edge part within 5 mm from an outer edge of the group III nitride semiconductor substrate, stress within a main surface of the group III nitride semiconductor substrate works as a tensile stress, with the tensile stress becoming relatively greater compared to that of a center side part from the outer edge side part of the group III nitride semiconductor substrate. | 06-23-2011 |
| 20110147760 | Semiconductor apparatus with thin semiconductor film - A semiconductor apparatus includes a substrate having at least one terminal, a thin semiconductor film including at least one semiconductor device, the thin semiconductor film being disposed and bonded on the substrate; and an individual interconnecting line formed as a thin conductive film extending from the semiconductor device in the thin semiconductor film to the terminal in the substrate, electrically connecting the semiconductor device to the terminal. Compared with conventional semiconductor apparatus, the invented apparatus is smaller and has a reduced material cost. | 06-23-2011 |
| 20110147761 | TWO-TERMINAL SWITCHING DEVICES AND THEIR METHODS OF FABRICATION - Two-terminal switching devices characterized by high on/off current ratios and by high breakdown voltage are provided. These devices can be employed as switches in the driving circuits of active matrix displays, e.g., in electrophoretic, rotating element and liquid crystal displays. The switching devices include two electrodes, and a layer of a broad band semiconducting material residing between the electrodes. According to one example, the cathode comprises a metal having a low work function, the anode comprises an organic material having a p+ or p++ type of conductivity, and the broad band semiconductor comprises a metal oxide. The work function difference between the cathode and the anode material is preferably at least about 0.6 eV. The on/off current ratios of at least 10,000 over a voltage range of about 15 V can be achieved. The devices can be formed, if desired, on flexible polymeric substrates having low melting points. | 06-23-2011 |
| 20110147762 | Integrated Nitride and Silicon Carbide-Based Devices - Monolithic electronic devices are providing including a high bandgap layer. A first type of nitride device is provided on a first portion of the high bandgap layer, the first nitride device including first and second implanted regions respectively defining source and drain regions of the first type of nitride device. A second type of nitride device, different from the first type of nitride device, is provided on a second portion of the high bandgap layer, the second type of nitride device including an implanted highly conductive region. At least a portion of the implanted highly conductive region of the second type of nitride device is coplanar with at least a portion of both the first and second implanted regions of the first type of nitride device. | 06-23-2011 |
| 20110147763 | GROUP III NITRIDE SEMICONDUCTOR MULTILAYER STRUCTURE AND PRODUCTION METHOD THEREOF - According to the present invention, an AlN crystal film seed layer having high crystallinity is combined with selective/lateral growth, whereby a Group III nitride semiconductor multilayer structure more enhanced in crystallinity can be obtained. The Group III nitride semiconductor multilayer structure of the present invention is a Group III nitride semiconductor multilayer structure where an AlN crystal film having a crystal grain boundary interval of 200 nm or more is formed as a seed layer on a C-plane sapphire substrate surface by a sputtering method and an underlying layer, an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer, each composed of a Group III nitride semiconductor, are further stacked, wherein regions in which the seed layer is present and is absent are formed on the C-plane sapphire substrate surface and/or regions capable of epitaxial growth and incapable of epitaxial growth are formed in the underlying layer. | 06-23-2011 |
| 20110156047 | NITRIDE SEMICONDUCTOR TEMPLATE AND METHOD OF MANUFACTURING THE SAME - A nitride semiconductor template and a manufacturing method thereof are provided. The nitride semiconductor template includes a carrier substrate with a first thermal expansion coefficient, a nitride semiconductor layer with a second thermal expansion coefficient different from the first thermal expansion coefficient, and a bonding layer. The nitride semiconductor layer disposed on the carrier substrate is at least 10 μm in thickness. A ratio of a dislocation density of the nitride semiconductor layer at a first surface to that at a second surface is from 0.1 to 10. The bonding layer is disposed between the carrier substrate and the nitride semiconductor layer to adhere the nitride semiconductor layer onto the carrier substrate. The second surface is near an interface between the nitride semiconductor layer and the bonding layer, and the first surface is 10 μm from the second surface. | 06-30-2011 |
| 20110156048 | NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride-based semiconductor light-emitting device | 06-30-2011 |
| 20110156049 | LED DEVICE AND FABRICATION METHOD THEREOF - A LED device includes a n-type first semiconductor layer, a p-type second semiconductor layer, an active layer between the first semiconductor layer and the second semiconductor layer, an electrode positioned on a surface of the second semiconductor layer away from the active layer, and an ohmic contacting layer positioned on a surface of the second semiconductor layer away from the active layer. The ohmic contacting layer includes a resistance region corresponding to the electrode and a conductive region surrounding the resistance region, in which the conductive region having less resistance than that of the resistance region. | 06-30-2011 |
| 20110156050 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - The semiconductor device includes a GaN-based layered body having an opening and including an n-type drift layer and a p-type layer located on the n-type drift layer, a regrown layer including a channel and located so as to cover the opening, and a gate electrode located on the regrown layer and formed along the regrown layer, wherein the opening reaches the n-type drift layer, and an edge of the gate electrode is not located outside a region of the p-type layer when viewed in plan. | 06-30-2011 |
| 20110156051 | SEMICONDUCTOR DEVICES WITH LOW LEAKAGE SCHOTTKY CONTACTS - Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced. | 06-30-2011 |
| 20110163322 | PHOSPHOR, PHOSPHOR MANUFACTURING METHOD, AND WHITE LIGHT EMITTING DEVICE - Provided are a phosphor, a phosphor manufacturing method, and a white light emitting device. The phosphor is represented as a chemical formula of M | 07-07-2011 |
| 20110163323 | GaN SINGLE CRYSTAL SUBSTRATE AND METHOD OF MAKING THE SAME - The method of making a GaN single crystal substrate comprises a mask layer forming step of forming on a GaAs substrate | 07-07-2011 |
| 20110163324 | LIGHT EMITTING DEVICE - A light emitting diode of one embodiment includes a light emitting device having a plurality of N-type semiconductor layers including a first N-type semiconductor layer and a second N-type semiconductor layer on the first N-type semiconductor layer, an active layer on an upper layer of the plurality of N-type semiconductor layers, and a P-type semiconductor layer on the active layer. The first N-type semiconductor layer includes a first Si doped Nitride layer and the second N-type semiconductor layer includes a second Si doped Nitride layer. The first and second N-type semiconductor layers have a Si impurity concentration different from each other. | 07-07-2011 |
| 20110163325 | METHOD OF MANUFACTURING GaN SUBSTRATE, METHOD OF MANUFACTURING EPITAXIALWAFER, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND EPITAXIALWAFER - Assuming that r (m) represents the radius of a GaN substrate, t | 07-07-2011 |
| 20110163326 | SUBSTRATE, EPITAXIAL LAYER PROVIDED SUBSTRATE, METHOD FOR PRODUCING SUBSTRATE, AND METHOD FOR PRODUCING EPITAXIAL LAYER PROVIDED SUBSTRATE - The present invention provides a substrate formed at a low cost and having a controlled plate shape, an epitaxial layer provided substrate obtained by forming an epitaxial layer on the substrate, and methods for producing them. The method for producing the substrate according to the present invention includes an ingot growing step serving as a step of preparing an ingot formed of gallium nitride (GaN); and a slicing step serving as a step of obtaining a substrate formed of gallium nitride, by slicing the ingot. In the slicing step, the substrate thus obtained by the slicing has a main surface with an arithmetic mean roughness Ra of not less than 0.05 μm and not more than 1 μm on a line of 10 mm. | 07-07-2011 |
| 20110169012 | NANOWIRE AND LARGER GaN BASED HEMTS - Nanowire and larger, post-based HEMTs, arrays of such HEMTs, and methods for their manufacture are provided. In one embodiment, a HEMT can include a III-N based core-shell structure including a core member (e.g., GaN), a shell member (e.g., AlGaN) surrounding a length of the core member and a two-dimensional electron gas (2-DEG) at the interface therebetween. The core member including a nanowire and/or a post can be disposed over a doped buffer layer and a gate material can be disposed around a portion of the shell member. Exemplary methods for making the nanowire HEMTs and arrays of nanowire HEMTs can include epitaxially forming nanowire(s) and epitaxially forming a shell member from each formed nanowire. Exemplary methods for making the post HEMTs and arrays of post HEMTs can include etching a III-N layer to form II-N post(s) followed by formation of the shell member(s). | 07-14-2011 |
| 20110175103 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device has a satisfactory ohmic contact on a p-type principal surface tilting from a c-plane. The principal surface | 07-21-2011 |
| 20110175104 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having a novel structure which includes a combination of semiconductor elements with different characteristics and is capable of realizing higher integration. A semiconductor device includes a first transistor, which includes a first channel formation region including a first semiconductor material, and a first gate electrode, and a second transistor, which includes one of a second source electrode and a second drain electrode combined with the first gate electrode, and a second channel formation region including a second semiconductor material and electrically connected to the second source electrode and the second drain electrode. | 07-21-2011 |
| 20110175105 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND FABRICATION METHOD THEREOF - A plurality of protrusions is formed on the C-plane substrate with a corundum structure. A base film made of a III-V compound semiconductor including Ga and N is formed on the surface of the substrate. The surface of the base film is flatter than the surface of the substrate. A light emitting structure including Ga and N is disposed on the base film. The protrusions are regularly arranged in a first direction that is tilted by less than 15 degrees with respect to the a-axis of the base film and in a second direction that is orthogonal to the first direction. Each protrusion has two first parallel sides tilted by less than 15 degrees relative to an m-axis and two second parallel sides tilted by less than 15 degrees relative to the a-axis. An interval between the two second sides is wider than an interval between the two first sides. | 07-21-2011 |
| 20110180804 | SOLID STATE LIGHT EMITTING DEVICE - A light emitting device comprises: an LED chip array comprising a plurality of LEDs formed on a single die (monolithic chip array) and at least one discrete LED that is separate from the LED chip array connected in series with the LED chip array. In an AC-drivable device the LED chip array is AC-drivable and two or more discrete LEDs are configured to be AC-drivable. The device can further comprise a package in which the LED chip array and discrete LED(s) are mounted. The discrete LEDs are configured such that positive and negative half wave periods of an AC drive voltage are mapped onto oppositely connected LED such that oppositely connected LED chips are alternately operable on a respective half wave period. | 07-28-2011 |
| 20110180805 | GROUP-III NITRIDE SEMICONDUCTOR DEVICE, EPITAXIAL SUBSTRATE, AND METHOD OF FABRICATING GROUP-III NITRIDE SEMICONDUCTOR DEVICE - A III-nitride semiconductor device has a support base comprised of a III-nitride semiconductor and having a primary surface extending along a first reference plane perpendicular to a reference axis inclined at a predetermined angle ALPHA with respect to the c-axis of the III-nitride semiconductor, and an epitaxial semiconductor region provided on the primary surface of the support base. The epitaxial semiconductor region includes a plurality of GaN-based semiconductor layers. The reference axis is inclined at a first angle ALPHA | 07-28-2011 |
| 20110180806 | MONOLITHIC INTEGRATION OF GALLIUM NITRIDE AND SILICON DEVICES AND CIRCUITS, STRUCTURE AND METHOD - A structure and method for a semiconductor device includes a silicon device layer and a gallium nitride (GaN) device layer. In an embodiment, the silicon device layer and the GaN device layer have upper surfaces which are coplanar with each other. In another embodiment, the GaN device layer does not directly underlie the silicon device layer, and the silicon device layer does not directly underlie the GaN device layer. The semiconductor device can further include a silicon-based semiconductor device formed on and/or within the silicon device layer, and a nitride-based semiconductor device formed on and/or within the GaN device layer. The GaN device layer can include a plurality of layers which can be formed as conformal blanket layers and then planarized, or which can be selectively formed then planarized. | 07-28-2011 |
| 20110186855 | Enhancement-Mode GaN MOSFET with Low Leakage Current and Improved Reliability - An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO | 08-04-2011 |
| 20110186856 | LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a light emitting element includes providing a substrate, forming a buffer layer on the substrate, forming a GaN layer on the buffer layer, forming a rough layer on the GaN layer at low temperature, and forming an epitaxial layer on the rough layer, wherein a refraction index of the epitaxial layer exceeds a refraction index of the rough layer. Thus, most light scatters at the rough layer, and then emits upwardly to a light emitting surface, enhancing light extraction efficiency thereof. An epitaxial process of the method is processed in situ in an MOCVD reactor. | 08-04-2011 |
| 20110186857 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, AND LIGHTING SYSTEM - Provided is a light emitting device according to one embodiment including: a substrate which has protrusions on the C-face, and of which unit cells are constructed in a hexagonal structure; a semiconductor layer which is formed on the substrate, in which empty spaces are formed in sides of the protrusions, and of which unit cells are constructed in a hexagonal structure; and a light emitting structure layer comprising a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer formed between the first conductive semiconductor layer and second conductive semiconductor layer which are formed on the semiconductor layer, wherein the A-face of the substrate and the A-face of the semiconductor layer form an angle of greater than zero degree, and the protrusions include the R-faces. | 08-04-2011 |
| 20110186858 | Gallium Nitride Power Devices Using Island Topography - A semiconductor device in provided having a substrate and a semiconductor layer formed on a main surface of the substrate. A plurality of first island electrodes and a plurality of second island electrodes are placed over the semiconductor layer. The plurality of first island electrodes and second island electrodes are spaced apart from each other so as to be alternatively arranged to produce two-dimensional active regions in all feasible areas of the semiconductor layer. Each side of the first island electrodes is opposite a side of the second island electrodes. The semiconductor device can also include a plurality of strip electrodes that are formed in the regions between the first island electrodes and the second island electrodes. The strip electrodes serve as the gate electrodes of a multi-island transistor. The first island electrodes serve as the source electrodes of the multi-island transistor. The second island electrodes serve as the drain electrodes of the multi-island transistor. A plurality of connections to the gate electrodes are provided at each interstice defined by corners of the first island electrodes and the second island electrodes. | 08-04-2011 |
| 20110186859 | High speed high power nitride semiconductor device - A nitride semiconductor device has: a substrate; a semiconductor lamination formed on the substrate, and including a channel layer of nitride semiconductor; source and drain electrodes formed on the semiconductor lamination in ohmic contact with the channel layer; an insulating layer formed on the semiconductor lamination, and having an opening in a gate electrode contact area, a total thickness portion having a flat surface and a total thickness in an area spaced apart from the opening, and a transient portion with monotonically changing thickness between the opening and the total thickness portion, a sidewall of the insulating layer facing the opening rising steeply to a partial thickness of the total thickness; and a T-shaped gate electrode contacting the semiconductor lamination layer in the opening and extending on the insulating film to portions with increased thickness thicker than the partial thickness. | 08-04-2011 |
| 20110186860 | NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE, METHOD FOR MANUFACTURING NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE, AND LIGHT EMITTING APPARATUS - Disclosed is a nitride-based semiconductor light emitting device with excellent light extraction efficiency. A light emitting device | 08-04-2011 |
| 20110193091 | DENSITY OF STATES ENGINEERED FIELD EFFECT TRANSISTOR - Layer structures for use in density of states (“DOS”) engineered FETs are described. One embodiment comprises a layer structure for use in fabricating an n-channel transistor. The layer structure includes a first semiconductor layer having a conduction band minimum E | 08-11-2011 |
| 20110193092 | FIELD EFFECT TRANSISTOR WITH CONDUCTION BAND ELECTRON CHANNEL AND UNI-TERMINAL RESPONSE - A uni-terminal transistor device is described. In one embodiment, an n-channel transistor comprises a first semiconductor layer having a discrete hole level H | 08-11-2011 |
| 20110193093 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - Provided is a light emitting device. A light emitting device includes: a conductive support member; a light emitting structure for generating a light on the conductive support member, the light emitting structure comprising a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer; an electrode on the light emitting structure; and an oxide layer between the electrode and the light emitting structure. The light emitting structure includes an oxygen-injected region where oxygen is injected on an upper portion of the light emitting structure. | 08-11-2011 |
| 20110193094 | GROWTH OF PLANAR REDUCED DISLOCATION DENSITY M-PLANE GALLIUM NITRIDE BY HYDRIDE VAPOR PHASE EPITAXY - A method of growing highly planar, fully transparent and specular m-plane gallium nitride (GaN) films. The method provides for a significant reduction in structural defect densities via a lateral overgrowth technique. High quality, uniform, thick m-plane GaN films are produced for use as substrates for polarization-free device growth. | 08-11-2011 |
| 20110193095 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a GaN-based semiconductor layer formed on a substrate, a gate insulating film that is formed on a surface of the GaN-based semiconductor layer and is made of aluminum oxide, and a gate electrode formed on the gate insulating film, the gate insulating film having a carbon concentration of 2×10 | 08-11-2011 |
| 20110193096 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An n-type GaN layer ( | 08-11-2011 |
| 20110198609 | Light-Emitting Devices with Through-Substrate Via Connections - Multiple through-substrate vias (TSVs) are used to make electrical connections for an LED formed over a substrate. A first TSV extends through the substrate from a back surface of the substrate to the front surface of the substrate and includes a first TSV conductor that electrically connects to a first cladding layer of the LED. A second TSV extends through the substrate and an active layer of the LED from the back surface of the substrate to a second cladding layer or an ITO layer. The second TSV includes an isolation layer that electrically isolates a second TSV conductor from the first cladding layer and the active layer. Additionally dummy TSVs may be formed to conduct heat away from the LED optionally through a package substrate. | 08-18-2011 |
| 20110198610 | NITRIDE SEMICONDUCTOR CRYSTAL, MANUFACTURING METHOD OF THE NITRIDE SEMICONDUCTOR FREESTANDING SUBSTRATE AND NITRIDE SEMICONDUCTOR DEVICE - To provide a nitride semiconductor crystal, comprising: laminated homogeneous nitride semiconductor layers, with a thickness of 2 mm or more, wherein the laminated homogeneous nitride semiconductor layers are constituted so that a nitride semiconductor layer with low dopant concentration and a nitride semiconductor layer with high dopant concentration are alternately laminated by two cycles or more. | 08-18-2011 |
| 20110198611 | III-Nitride Power Device with Solderable Front Metal - Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson. | 08-18-2011 |
| 20110204376 | GROWTH OF MULTI-JUNCTION LED FILM STACKS WITH MULTI-CHAMBERED EPITAXY SYSTEM - Apparatus and method for growth of non-p-type GaN layers over p-type GaN layers. Embodiments include multi-junction LED film stacks, multi-junction LED devices paired into units and multi-junction LED arrays of the paired units. Epitaxial growths of p-type and non-p-type material layers are split between epitaxial chambers clustered onto a single platform to reduce p-type dopant cross-contamination. Arrayed multi-junction LED devices provide improved packing density and reduced blinking during AC operation. | 08-25-2011 |
| 20110204377 | Methods of growing nitride semiconductors and methods of manufacturing nitride semiconductor substrates - Methods of growing nitride semiconductor layers including forming nitride semiconductor dots on a substrate and growing a nitride semiconductor layer on the nitride semiconductor dots. The nitride semiconductor layer may be separated from the substrate to be used as a nitride semiconductor substrate. | 08-25-2011 |
| 20110204378 | GROWTH OF GROUP III-V MATERIAL LAYERS BY SPATIALLY CONFINED EPITAXY - Techniques for crack-free growth of GaN, and related, films on larger-size substrates via spatially confined epitaxy are described. | 08-25-2011 |
| 20110204379 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A nitride semiconductor device including: a substrate; a nitride semiconductor layer formed on the substrate and having a heterojunction interface; and a recess portion formed on the nitride semiconductor layer, wherein the nitride semiconductor layer includes: a carrier transit layer, which has a composition represented by the formula: Al | 08-25-2011 |
| 20110204380 | NITRIDE-BASED FET - According to an embodiment, in a nitride-based FET, a protrusion portion is formed at an upper portion of an undoped GaN layer by second recess etching. On the protrusion portion, an undoped AlGaN layer is provided which is formed by first recess etching the upper portion of the undoped AlGaN layer. A multilayer portion is composed of the protrusion portion of the undoped GaN layer, the undoped AlGaN layer, and an insulating film. A trench portion is formed by recess etching the insulating film, the undoped AlGaN layer and a surface of the undoped GaN layer. A gate insulating film is formed on the multilayer portion and the trench portion. A gate electrode is formed on the gate insulating film so as to cover the trench portion. A film thickness of the insulting film is set larger than that of the gate insulating film. | 08-25-2011 |
| 20110204381 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - There are provided a semiconductor device that includes a bypass protection unit against surge voltage or the like, achieves good withstand voltage characteristics and low on-resistance (low On-state voltage), has a simple structure, and is used for large-current purpose and a method for producing the semiconductor device. | 08-25-2011 |
| 20110210337 | Monolithic integration of silicon and group III-V devices - Disclosed is a monolithically integrated silicon and group III-V device that includes a group III-V transistor formed in a III-V semiconductor body disposed over a silicon substrate. At least one via extends through the III-V semiconductor body to couple at least one terminal of the group III-V transistor to a silicon device formed in the silicon substrate. The silicon device can be a Schottky diode, and the group III-V transistor can be a GaN HEMT. In one embodiment an anode of the Schottky diode is formed in the silicon substrate. In another embodiment, the anode of the Schottky diode is formed in a lightly doped epitaxial silicon layer atop the silicon substrate. In one embodiment a parallel combination of the Schottky diode and the group III-V transistor is formed, while in another embodiment is series combination is formed. | 09-01-2011 |
| 20110210338 | Efficient High Voltage Switching Circuits and Monolithic Integration of Same - A high voltage switching circuit includes first and second group III-V transistors, the second group III-V transistor having a greater breakdown voltage than the first group III-V transistor. The circuit further includes a silicon diode in a parallel arrangement with the first group III-V transistor, the parallel arrangement being in cascade with the second group III-V transistor. The circuit is effectively a three-terminal device, where a first terminal is coupled to a gate of the second III-V transistor, a source of the first III-V transistor, and an anode of the silicon diode. A second terminal is coupled to a gate of the first group III-V transistor, and a third terminal is coupled to a drain of the second group III-V transistor. The first group III-V transistor might be an enhancement mode transistor. The second group III-V transistor might be a depletion mode transistor. The first and second group III-V transistors can be GaN HEMTs. | 09-01-2011 |
| 20110215339 | Termination and contact structures for a high voltage GaN-based heterojunction transistor - A semiconductor device is provided that includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A termination layer, which is disposed on the second active layer, includes InGaN. Source, gate and drain contacts are disposed on the termination layer. | 09-08-2011 |
| 20110220910 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, an insulating film, a first interconnection, a second interconnection, a barrier metal layer, a first metal pillar, a second metal pillar, and a resin. The semiconductor layer has a first major surface, a second major surface formed on an opposite side to the first major surface, and a light emitting layer. The first electrode is provided on the second major surface of the semiconductor layer. The second electrode is provided on the second major surface of the semiconductor layer and includes a silver layer. The insulating film is provided on the second major surface side of the semiconductor layer. The barrier metal layer is provided between the second electrode and the insulating film and between the second electrode and the second interconnection to cover the second electrode. | 09-15-2011 |
| 20110220911 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - According to one embodiment, a semiconductor light-emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a light-emitting layer, a third semiconductor layer and a first electrode. The light-emitting layer is provided between the first and second semiconductor layers. The third semiconductor layer is provided on opposite side of the first semiconductor layer from the light-emitting layer, has a lower impurity concentration than the first semiconductor layer, and includes an opening exposing part of the first semiconductor layer. The first electrode is in contact with the first semiconductor layer through the opening. The third semiconductor layer further includes a rough surface portion which is provided on opposite side from the first semiconductor layer and includes a surface asperity larger than wavelength in the third semiconductor layer of peak wavelength of emission light emitted from the light-emitting layer. | 09-15-2011 |
| 20110220912 | Semi-insulating Group III Metal Nitride and Method of Manufacture - A large-area, high-purity, low-cost single crystal semi-insulating gallium nitride that is useful as substrates for fabricating GaN devices for electronic and/or optoelectronic applications is provided. The gallium nitride is formed by doping gallium nitride material during ammonothermal growth with a deep acceptor dopant species, e.g., Mn, Fe, Co, Ni, Cu, etc., to compensate donor species in the gallium nitride, and impart semi-insulating character to the gallium nitride. | 09-15-2011 |
| 20110227089 | MULTILAYER DIFFUSION BARRIERS FOR WIDE BANDGAP SCHOTTKY BARRIER DEVICES - Semiconductor Schottky barrier devices include a wide bandgap semiconductor layer, a Schottky barrier metal layer on the wide bandgap semiconductor layer and forming a Schottky junction, a current spreading layer on the Schottky barrier metal layer remote from the wide bandgap semiconductor layer and two or more diffusion barrier layers between the current spreading layer and the Schottky barrier metal layer. The first diffusion barrier layer reduces mixing of the current spreading layer and the second diffusion barrier layer at temperatures of the Schottky junction above about 300° C. and the second diffusion barrier layer reduces mixing of the first diffusion barrier layer and the Schottky barrier metal layer at the temperatures of the Schottky junction above about 300° C. | 09-22-2011 |
| 20110227090 | Programmable III-Nitride Transistor with Aluminum-Doped Gate - Disclosed is a III-nitride heterojunction device that includes a conduction channel having a two dimensional electron gas formed at an interface between a first III-nitride material and a second III-nitride material. A modification including a contact insulator, for example, a gate insulator formed under a gate contact, is disposed over the conduction channel, wherein the contact insulator includes aluminum to alter formation of the two dimensional electron gas at the interface. The contact insulator can include AlSiN, or can be SiN doped with aluminum. The modification results in programming the threshold voltage of the III-nitride heterojunction device to, for example, make the device an enhancement mode device. The modification can further include a recess, an ion implanted region, a diffused region, an oxidation region, and/or a nitridation region. In one embodiment, the first III-nitride material comprises GaN and the second III-nitride material comprises AlGaN. | 09-22-2011 |
| 20110227091 | SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - A solid-state imaging device is provided with a pixel region in which a plurality of pixels including photoelectric conversion films are arrayed and pixel isolation portions are interposed between the plurality of pixels, wherein the photoelectric conversion film is a chalcopyrite-structure compound semiconductor composed of a copper-aluminum-gallium-indium-sulfur-selenium based mixed crystal or a copper-aluminum-gallium-indium-zinc-sulfur-selenium based mixed crystal and is disposed on a silicon substrate in such a way as to lattice-match the silicon substrate concerned, and the pixel isolation portion is formed from a compound semiconductor subjected to doping concentration control or composition control in such a way as to become a potential barrier between the photoelectric conversion films disposed in accordance with the plurality of pixels. | 09-22-2011 |
| 20110227092 | III-Nitride Semiconductor Device - A III-nitride heterojunction power semiconductor device having a barrier layer that includes a region of reduced nitrogen content. | 09-22-2011 |
| 20110227093 | FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - The present invention has an object to provide an FET and a method of manufacturing the FET that are capable of increasing the threshold voltage as well as decreasing the on-resistance. The FET of the present invention includes a first undoped GaN layer; a first undoped AlGaN layer formed on the first undoped GaN layer, having a band gap energy greater than that of the first undoped GaN layer; a second undoped GaN layer formed on the first undoped AlGaN layer; a second undoped AlGaN layer formed on the second undoped GaN layer, having a band gap energy greater than that of the second undoped GaN layer; a p-type GaN layer formed in the recess of the second undoped AlGaN layer; a gate electrode formed on the p-type GaN layer; and a source electrode and a drain electrode which are formed in both lateral regions of the gate electrode, wherein a channel is formed at the heterojunction interface between the first undoped GaN layer and the first undoped AlGaN layer. | 09-22-2011 |
| 20110233558 | LIGHT-EMITTING DEVICE, LIGHT-EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM - Disclosed is a light-emitting device including: a support member; and a light-emitting structure on the support member, the light-emitting structure including a first semiconductor layer, at least one intermediate layer, an active layer and a second semiconductor layer, wherein the intermediate layer is on at least one of upper and lower regions of the active layer and comprises at least four layers, wherein the layers have different band gaps, and wherein, among the layers, a layer having the largest band gap contacts a layer having the smallest band gap. Based on this configuration, it is possible to reduce crystal defects and improve brightness of the light-emitting device through effective diffusion of current. | 09-29-2011 |
| 20110233559 | FIELD-EFFECT TRANSISTOR - A field-effect transistor (FET) in which a gate electrode is located between a source electrode formed on one side of the gate electrode and a drain electrode formed on the other side, a source ohmic contact is formed under the source electrode and a drain ohmic contact is formed under the drain electrode. In the FET, the rise in the channel temperature is suppressed, the parasitic capacitance with a substrate is decreased, and the temperature dependence of drain efficiency is reduced, so that highly efficient operation can be achieved at high temperatures. The drain electrode is divided into a plurality of drain sub-electrodes spaced from each other and an insulating region is formed between the drain ohmic contacts formed under the drain sub-electrodes. | 09-29-2011 |
| 20110241016 | NITRIDE-BASED SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A nitride-based semiconductor light-emitting element LE | 10-06-2011 |
| 20110241017 | FIELD EFFECT TRANSISTOR - A field effect transistor includes: a buffer layer that is formed on a substrate; a high resistance layer or a foundation layer that is formed on the buffer layer; a carbon-containing carrier concentration controlling layer that is formed on the high resistance layer or the foundation layer; a carrier traveling layer that is formed on the carrier concentration controlling layer; a carrier supplying layer that is formed on the carrier traveling layer; a recess that is formed from the carrier supplying layer up to a predetermined depth; source/drain electrodes that are formed on the carrier supplying layer with the recess intervening therebetween; a gate insulating film that is formed on the carrier supplying layer so as to cover the recess; and a gate electrode that is formed on the gate insulating film in the recess | 10-06-2011 |
| 20110241018 | FABRICATING A GALLIUM NITRIDE DEVICE WITH A DIAMOND LAYER - In one aspect, a method includes fabricating a device. The device includes a gallium nitride (GaN) layer, a diamond layer disposed on the GaN layer and a gate structure disposed in contact with the GaN layer and the diamond layer. | 10-06-2011 |
| 20110241019 | III-Nitride Power Semiconductor Device - A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof. | 10-06-2011 |
| 20110248280 | TRANSISTOR HAVING THERMO ELECTRON COOLING - A semiconductor structure having a transistor and a thermo electronic structure. The transistor has a control electrode for controlling a flow of carriers through a semiconductor layer between a pair of electrodes. The thermo electronic structure has a first portion disposed on at least one of the pair of electrodes and a second portion disposed over a region of the semiconductor layer proximate the control electrode between the control electrode and said at least one of the pair of electrode. The thermo electronic structure extends from the first portion to the second portion for removing heat generated heat from said region in the semiconductor layer. | 10-13-2011 |
| 20110248281 | Nitride semiconductor substrate, production method therefor and nitride semiconductor device - A nitride semiconductor substrate includes two principal surfaces including an upper surface that is a growth face and a lower surface on its opposite side. An FWHM in a surface layer region at depths of from 0 to 250 nm from the upper surface is narrower than an FWHM in an inner region at depths exceeding 5 μm from the upper surface, where the FWHMs are obtained by X-ray rocking curve measurement using diffraction off a particular asymmetric plane inclined relative to the upper surface. | 10-13-2011 |
| 20110248282 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - The invention provides a semiconductor structure and a manufacturing method of the same, and relates to a field of semiconductor manufacture. The semiconductor structure comprises: a silicon substrate; a large bandgap semiconductor layer formed on the silicon substrates; and a silicon layer formed on the large bandgap semiconductor layer. The method comprises: growing a large bandgap semiconductor layer on a silicon substrate; and growing a silicon layer on the large bandgap semiconductor layer. The embodiments of the present invention can be applied to manufacture of semiconductor devices. | 10-13-2011 |
| 20110248283 | VIA STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Semiconductor devices, such as GaN HEMT and HFET devices, and methods of forming such devices, with a via that provides an electrical connection between a contact and a corresponding external contact pad. Embodiments include semiconductor devices with a via extending through a dielectric material to connect a gate to a corresponding external contact pad, and semiconductor devices with a via extending through a dielectric material to connect an Ohmic contact and a corresponding external contact pad. Embodiments also include semiconductor devices with a via connecting an external contact pad to a gate that is formed above a dielectric material. | 10-13-2011 |
| 20110254012 | Ultra high voltage GaN ESD protection device - In an ultra high voltage lateral GaN structure having a 2DEG region extending between two terminals, an isolation region is provided between the two terminals to provide for reversible snapback. | 10-20-2011 |
| 20110254013 | HYBRID ORIENTATION ACCUMULATION MODE GAA CMOSFET - A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased. | 10-20-2011 |
| 20110254014 | NITRIDE SEMICONDUCTOR WAFER AND NITRIDE SEMICONDUCTOR DEVICE - There is stably provided a nitride semiconductor wafer having a nitride semiconductor layer with high insulating properties, wherein a semi-insulating nitride semiconductor layer is provided on an insulating substrate, with a resistivity of 10 MΩcm or more and 100 MΩcm or less, and a film thickness of 0.1 μm or more and 1.5 μm or less. | 10-20-2011 |
| 20110260173 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure may comprise a substrate ( | 10-27-2011 |
| 20110266551 | HIGH BRIGHTNESS LIGHT EMITTING DIODE COVERED BY ZINC OXIDE LAYERS ON MULTIPLE SURFACES GROWN IN LOW TEMPERATURE AQUEOUS SOLUTION - A high brightness III-Nitride based Light Emitting Diode (LED), comprising multiple surfaces covered by Zinc Oxide (ZnO) layers, wherein the ZnO layers are grown in a low temperature aqueous solution and each have a (0001) c-orientation and a top surface that is a (0001) plane. | 11-03-2011 |
| 20110266552 | LIGHT EMITTING ELEMENT AND MANUFACTURING METHOD THEREOF - A light emitting element includes a substrate, a GaN layer formed on the substrate, a first low refractive index semiconductor layer formed on the GaN layer, and a lighting structure having a high refractive index formed on the first low refractive index semiconductor layer. A second low refractive index semiconductor layer is embedded in the first low refractive index semiconductor layer. The first low refractive index semiconductor layer and the GaN layer exhibit a lattice mismatch therebetween. | 11-03-2011 |
| 20110266553 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD OF MANUFACTURING THE SAME - An object of the present invention is to provide a nitride semiconductor light-emitting device in which contact resistance generated between an n-contact layer and an n-side electrode is effectively reduced while maintaining satisfactory external quantum efficiency, and a method of efficiently producing the nitride semiconductor light-emitting device. Specifically, the present invention characteristically provides a nitride semiconductor light-emitting device having a semiconductor laminated body including an n-type laminate, a light-emitting layer and a p-type laminate, and an n-side electrode and a p-side electrode, characterized in that: the n-type laminate includes an n-contact layer made of an Al | 11-03-2011 |
| 20110266554 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE DEVICE - In a manufacturing method of a semiconductor device, first, a first semiconductor layer, a second semiconductor layer, and a p-type third semiconductor layer are sequentially epitaxially grown on a substrate. After that, the third semiconductor layer is selectively removed. Then, a fourth semiconductor layer is epitaxially grown on the second semiconductor layer. Then, a gate electrode is formed on the third semiconductor layer. | 11-03-2011 |
| 20110266555 | METHOD OF GROWING SEMICONDUCTOR HETEROSTRUCTURES BASED ON GALLIUM NITRIDE - The method of growing non-polar epitaxial heterostructures for light-emitting diodes producing white emission and lasers, on the basis of compounds and alloys in AlGaInN system, comprising the step of vapor-phase deposition of one or multiple heterostructures layers described by the formula Al | 11-03-2011 |
| 20110272703 | SEMICONDUCTOR DEVICE, LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are a semiconductor device, a light emitting device and a method for manufacturing the same. The semiconductor device includes a substrate, a plurality of rods disposed on the substrate, a plurality of particles disposed between the rods and on the substrate, and a first semiconductor layer disposed on the rods. The method for manufacturing the semiconductor device includes preparing a substrate, disposing a plurality of first particles on the substrate, and forming a plurality of rods by etching a portion of the substrate by using the first particles as an etch mask. The semiconductor device effectively reflects in an upward direction light by the above particles, so that light efficiency is improved. The rods are easily formed by using the first particles. | 11-10-2011 |
| 20110272704 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An AlN layer ( | 11-10-2011 |
| 20110272705 | Interdigitated Conductive Support for GaN Semiconductor Die - A GaN die having a plurality of parallel alternating and closely spaced source and drain strips is contacted by parallel coplanar comb-shaped fingers of source and drain pads. A plurality of enlarged area coplanar spaced gate pads having respective fingers contacting the gate contact of the die. The pads may be elements of a lead frame, or conductive areas on an insulation substrate. Other semiconductor die can be mounted on the pads and connected in predetermined circuit arrangements with the GaN die. | 11-10-2011 |
| 20110272706 | LIGHT EMITTING DIODE AND METHOD FOR FABRICATING THE SAME - A light emitting diode and a method for fabricating the same are provided. The light emitting diode includes: a transparent substrate; a semiconductor material layer formed on the top surface of a substrate with an active layer generating light; and a fluorescent layer formed on the back surface of the substrate with controlled varied thicknesses. The ratio of light whose wavelength is shifted while propagating through the fluorescent layer and the original light generated in the active layer can be controlled by adjusting the thickness of the fluorescent layer, to emit desirable homogeneous white light from the light emitting diode. | 11-10-2011 |
| 20110278585 | GROWTH OF REDUCED DISLOCATION DENSITY NON-POLAR GALLIUM NITRIDE - Lateral epitaxial overgrowth (LEO) of non-polar gallium nitride (GaN) films results in significantly reduced defect density. | 11-17-2011 |
| 20110278586 | BIPOLAR TRANSISTOR - A bipolar transistor is provided with an emitter layer, a base layer and a collector layer. The emitter layer is formed above a substrate and is an n-type conductive layer including a first nitride semiconductor. The base layer is formed on the emitter layer and is a p-type conductive including a second nitride semiconductor. The collector layer is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed such that a crystal growth direction to the substrate surface is parallel to a substrate direction of [000-1]. The third nitride semiconductor contains In | 11-17-2011 |
| 20110278587 | Fast Annealing for GaN LEDs - Methods of performing fast thermal annealing in forming GaN light-emitting diodes (LEDs) are disclosed, as are GaN LEDs formed using fast thermal annealing. An exemplary method includes forming a GaN multilayer structure having a n-GaN layer and a p-GaN layer that sandwich an active layer. The method includes performing fast thermal annealing of the p-GaN layer using either a laser or a flash lamp. The method further includes forming a transparent conducting layer atop the GaN multilayer structure, and adding a p-contact to the transparent conducting layer and a n-contact to the n-GaN layer. The resultant GaN LEDs have enhanced output power, lower turn-on voltage and reduced series resistance. | 11-17-2011 |
| 20110278588 | Method of Preparing and Storing GaN Substrate, Prepared and Stored GaN Substrate, and Semiconductor Device and Method of Its Manufacture - A GaN substrate storage method of storing, within an atmosphere in which the oxygen concentration is not greater than 15 vol. % and the water-vapor concentration is not greater than 20 g/m | 11-17-2011 |
| 20110278589 | Gallium Nitride Semiconductor Device With Improved Forward Conduction - A gallium nitride based semiconductor diode includes a substrate, a semiconductor body including a first heavily doped GaN layer and a second lightly doped GaN layer. The semiconductor body includes mesas projecting upwardly from a lower surface where each of the mesas includes the second GaN layer and a portion of the first GaN layer. Schottky contacts are formed on the upper surface of the mesas and ohmic contacts are formed on the lower surface of the semiconductor body. An insulating layer is formed over the Schottky and ohmic contacts. Vias are formed in the insulating layer to the Schottky contacts and vias are formed in the semiconductor body to the Ohmic contacts. An anode electrode is formed in a first metal pad in electrical contact with the Schottky contacts. A cathode electrode is formed in a second metal pad in electrical contact with the ohmic contacts. | 11-17-2011 |
| 20110284862 | III-nitride switching device with an emulated diode - Some exemplary embodiments of a III-nitride switching device with an emulated diode have been disclosed. One exemplary embodiment comprises a GaN switching device fabricated on a substrate comprising a high threshold GaN transistor coupled across a low threshold GaN transistor, wherein a gate and a source of the low threshold GaN transistor are shorted with an interconnect metal to function as a parallel diode in a reverse mode. The high threshold GaN transistor is configured to provide noise immunity for the GaN switching device when in a forward mode. The high threshold GaN transistor and the low threshold GaN transistor are typically fabricated on the same substrate, and with significantly different thresholds. As a result, the superior switching characteristics of III-nitride devices may be leveraged while retaining the functionality and the monolithic structure of the inherent body diode in traditional silicon FETs. | 11-24-2011 |
| 20110284863 | III-V SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING THE SAME - Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation. | 11-24-2011 |
| 20110284864 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, AND LIGHTING DEVICE - A light emitting device includes a support member, a light emitting structure on the support member, the light emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the second conductive type semiconductor layer and the first conductive type semiconductor layer, a first nitride semiconductor layer disposed on the second conductive type semiconductor layer, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and including an uneven structure, and a first electrode pad disposed on the light emitting structure wherein the second nitride semiconductor layer has an opening, the first electrode pad is in contact with the first nitride semiconductor layer through the opening, and the first nitride semiconductor layer has a work function smaller than that of the second nitride semiconductor layer. | 11-24-2011 |
| 20110284865 | HETEROJUNCTION FIELD EFFECT TRANSISTOR, METHOD FOR PRODUCING HETEROJUNCTION FIELD EFFECT TRANSISTOR, AND ELECTRONIC DEVICE - A heterojunction filed effect transistor with a low access resistance, a low on resistance, and the like, a method for producing a heterojunction filed effect transistor and an electron device are provided. In the heterojunction field effect transistor, an electron transit layer | 11-24-2011 |
| 20110284866 | LIGHT-EMITTING DIODE (LED) STRUCTURE HAVING A WAVELENGTH-CONVERTING LAYER AND METHOD OF PRODUCING - A light emitting diode (LED) device having a substantially conformal wavelength-converting layer for producing uniform white light and a method of making said LED at both the wafer and individual die levels are provided. The LED device includes a metal substrate, a p-type semiconductor coupled to the metal substrate, an active region coupled to the p-type semiconductor, an n-type semiconductor coupled to the active region, and a wavelength converting layer coupled to the n-type semiconductor. | 11-24-2011 |
| 20110284867 | LIGHT-EMITTING DIODE WITH INCREASED LIGHT EXTRACTION - Methods are disclosed for forming a vertical semiconductor light-emitting diode (VLED) device having an active layer between an n-doped layer and a p-doped layer; and securing a plurality of balls on a surface of the n-doped layer of the VLED device. | 11-24-2011 |
| 20110284868 | High Voltage III-Nitride Transistor - A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer. The high voltage durability HEMT also comprises a III-nitride semiconductor body formed over the P type conductivity <111> silicon layer, the III-nitride semiconductor body forming a heterojunction of the HEMT. | 11-24-2011 |
| 20110284869 | High Voltage Durability III-Nitride HEMT - A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer. The high voltage durability HEMT also comprises a III-nitride semiconductor body formed over the P type conductivity <111> silicon layer, the III-nitride semiconductor body forming a heterojunction of the HEMT. | 11-24-2011 |
| 20110291103 | TRENCH SIDEWALL CONTACT SCHOTTKY PHOTODIODE AND RELATED METHOD OF FABRICATION - A Schottky photodiode may include a monocrystalline semiconductor substrate having a front surface, a rear surface, and a first dopant concentration and configured to define a cathode of the Schottky photodiode, a doped epitaxial layer over the front surface of the monocrystalline semiconductor substrate having a second dopant concentration less than the first dopant concentration, and parallel spaced apart trenches in the doped epitaxial layer and having of a depth less than a depth of the doped epitaxial layer. The Schottky photodiode may include a metal filler in the parallel spaced apart trenches to form a Schottky rectifying contact with the doped epitaxial layer, an anode current distributor metal layer on a surface of the doped epitaxial layer and in electrical contact with the metal filler of the parallel spaced apart trenches, a dielectric passivation layer on the anode current distributor metal layer, and a conductive metal layer over the rear surface of the monocrystalline semiconductor substrate and configured to provide an ohmic contact with the cathode. | 12-01-2011 |
| 20110297953 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - An exemplary light emitting diode includes a conductive base, an LED die, a transparent conductive layer and at least one pad. The LED die includes a p-type GaN layer connected to the base, an active layer on the p-type GaN layer, and an n-type GaN layer on the active layer. The transparent conductive layer is coated on an exposed side of the n-type GaN layer. The exposed side has an arched central portion, which in one embodiment is concave and in another embodiment is convex. The at least one n-side pad is mounted on the transparent conductive layer. The at least one n-side pad and the conductive base are for connecting with a power source. | 12-08-2011 |
| 20110297954 | SEMICONDUCTOR DEVICE, SCHOTTKY BARRIER DIODE, ELECTRONIC APPARATUS, AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - [Problem to be Solved] Provided is a semiconductor device in which the trade-off between the pressure resistance and the on-state resistance is improved and the performance is improved. | 12-08-2011 |
| 20110297955 | Semiconductor Light Emitting Diode - A highly-efficient semiconductor light emitting diode with improved light extraction efficiency comprising at least a substrate having a plurality of crystal planes, a first conductivity-type barrier layer, an active layer serving as a light emitting layer and a second conductivity-type barrier layer stacked on the substrate. The semiconductor light emitting diode comprises a ridge structure configured from one flat surface and at least two inclining surfaces in the in-plane direction. The width (W) of the flat surface of the ridge structure is 2λ (λ: light emission wavelength) or less. The active layer is positioned in the laminating direction so that the shortest length (L) between two points is λ (light emission wavelength) or less, wherewith the first point is the shortest point where the light emitted from the center (C) of the active layer begins total internal reflection at the interface between the inclining surfaces of the ridge structure and air, and the second point is a point where the flat surface begins. | 12-08-2011 |
| 20110297956 | METHOD FOR MANUFACTURING GALLIUM NITRIDE COMPOUND SEMICONDUCTOR, AND SEMICONDUCTOR LIGHT EMITTING ELEMENT - The present invention is a method of manufacturing a gallium nitride-based compound semiconductor, including growing an m-plane InGaN layer whose emission peak wavelength is not less than 500 nm by metalorganic chemical vapor deposition. Firstly, step (A) of heating a substrate in a reactor is performed. Then, step (B) of supplying into the reactor a gas which contains an In source gas, a Ga source gas, and a N source gas and growing an m-plane InGaN layer of an In | 12-08-2011 |
| 20110297957 | COMPOUND SEMINCONDUCTOR STRUCTURE - A method for manufacturing a compound semiconductor structure, includes (a) selecting a conductive SiC substrate in accordance with color and resistivity and (b) epitaxially growing a GaN series compound semiconductor layer on the selected conductive SiC substrate. The step (a) preferably selects a conductive SiC substrate whose main color is green, whose conductivity type is n-type and whose resistivity is 0.08 52 cm to 1×10 | 12-08-2011 |
| 20110297958 | Gate after Diamond Transistor - A gate after diamond transistor and method of making comprising the steps of depositing a first dielectric layer on a semiconductor substrate, depositing a diamond particle nucleation layer on the first dielectric layer, growing a diamond thin film layer on the first dielectric layer, defining an opening for the gate in the diamond thin film layer, patterning of the diamond thin film layer for a gate metal to first dielectric layer surface, etching the first dielectric layer, depositing and defining a gate metal, and forming a contact window opening in the diamond thin film layer and the first dielectric layer to the ohmic contact. | 12-08-2011 |
| 20110297959 | CHAMFERED FREESTANDING NITRIDE SEMICONDUCTOR WAFER AND METHOD OF CHAMFERING NITRIDE SEMICONDUCTOR WAFER - Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 μm to Ra 6 μm. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra 10 nm and Ra 5 μm at edges of wafers. | 12-08-2011 |
| 20110297960 | TRANSISTOR ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a transistor assembly includes the steps of: (a) forming a transistor; (b) polishing a base substrate; and (c) securing the transistor of which the base substrate is polished to a support substrate. The step (a) is a step of forming a first semiconductor layer and a second semiconductor layer on a principle surface of the base substrate. The step (b) is a step of polishing a surface of the base substrate opposite to the principle surface. The step (c) is a step of securing the transistor on the support substrate in the presence of a stress applied on the base substrate in such a direction that a warp of the base substrate is reduced. The base substrate is made of a material different from that of the first semiconductor layer and the second semiconductor layer, and a tensile stress is applied on the second semiconductor layer. | 12-08-2011 |
| 20110297961 | FIELD EFFECT POWER TRANSISTORS - A normally OFF field effect transistor (FET) comprising: a plurality of contiguous nitride semiconductor layers having different composition and heterojunction interfaces between contiguous layers, a Fermi level, and conduction and valence energy bands; a source and a drain overlying a top nitride layer of the plurality of nitride layers and having source and drain access regions respectively comprising regions of at least two of the heterojunctions near the source and drain; a first gate between the source and drain; wherein when there is no potential difference between the gates and a common ground voltage, a two dimensional electron gas (2DEG) is present in the access region at a plurality of heterojunctions in each of the source and drain access regions, and substantially no 2DEG is present adjacent any regions of the heterojunctions under the first gate. | 12-08-2011 |
| 20110303924 | LIGHT-EMITTING DEVICE AND PROJECTOR - A light-emitting device includes a first layer, a second layer, and a semiconductor body interposed between the first and second layers, wherein the semiconductor body has a first fine-wall-shape member, a second fine-wall-shape member, and a semiconductor member interposed between the first and second fine-wall-shape members, the first and second fine-wall-shape members have a third layer, a fourth layer, and a fifth layer interposed between the third and fourth layers, the fifth layer is a layer that generates light and guides the light, the third and fourth layers are layers that guide the light generated in the fifth layer, and the first and second layers are layers that suppress leakage of the light generated in the fifth layer. | 12-15-2011 |
| 20110309371 | SCHOTTKY DIODE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A Schottky diode structure and a method for fabricating the same, which are based on the principle of charge compensation, wherein a P-type gallium nitride layer is added to a Schottky diode structure, and wherein the PN junction of the P-type gallium nitride layer and the N-type gallium nitride layer decreases the non-uniformity of the surface electric field distribution, whereby the breakdown voltage of the element is raised. | 12-22-2011 |
| 20110309372 | ENHANCEMENT-MODE HFET CIRCUIT ARRANGEMENT HAVING HIGH POWER AND A HIGH THRESHOLD VOLTAGE - A circuit includes input drain, source and gate nodes. The circuit also includes a group III nitride enhancement-mode HFET having a source, drain and gate and a voltage shifter having a first terminal connected to the gate of the enhancement mode HFET at a common junction. The circuit also includes a load resistive element connected to the common junction. The drain of the enhancement-mode HFET serves as the input drain node, the source of the enhancement-mode HFET serves as the input source node and a second terminal of the voltage shifter serves as the input gate node. | 12-22-2011 |
| 20110309373 | Singulation Method and Resulting Device of Thick Gallium and Nitrogen Containing Substrates - A method for singulation of thick GaN wafers (e.g., 300-400 um) through the use of a double-side laser-scribe process. In a preferred embodiment, the patterned GaN substrate is processed using a laser-scribe on each side of the substrate to form scribe lines. The scribe lines are aligned to each other. In a preferred embodiment, the substrate has not been subjected to a thinning or polishing process for reducing its thickness. | 12-22-2011 |
| 20110309374 | Fast thermal annealing of GaN LEDs - Methods of performing fast thermal annealing in forming GaN light-emitting diodes (LEDs) are disclosed, as are GaN LEDs formed using fast thermal annealing having a time duration of 10 seconds or faster. An exemplary method includes forming a GaN multilayer structure having a n-GaN layer and a p-GaN layer that sandwich an active layer. The method includes performing fast thermal annealing of the p-GaN layer using either a laser or a flash lamp. The method further includes forming a transparent conducting layer atop the GaN multilayer structure, and adding a p-contact to the transparent conducting layer and a n-contact to the n-GaN layer. The resultant GaN LEDs have enhanced output power, lower turn-on voltage and reduced series resistance. | 12-22-2011 |
| 20110315996 | SEMICONDUCTOR DEVICE, LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING SAME - Disclosed are a semiconductor device, a light emitting device, and a method of manufacturing the same. The semiconductor device includes a substrate, a plurality of rods aligned on the substrate, a metal layer disposed on the substrate between the rods, and a semiconductor layer disposed on and between the rods. Electrical and optical characteristics of the semiconductor device are improved due to the metal layer. | 12-29-2011 |
| 20110315997 | GaN Substrate and Method of Its Manufacture, Method of Manufacturing GaN Layer-Bonded Substrate, and Method of Manufacturing Semiconductor Device - The present invention makes available a GaN substrate, and a method of its manufacture, that, with minimal machining allowances, facilitates consistent machining, and makes available a method of manufacturing a GaN layer-bonded substrate, and a semiconductor device, utilizing the GaN substrate. A GaN substrate ( | 12-29-2011 |
| 20110315998 | EPITAXIAL WAFER, METHOD FOR MANUFACTURING GALLIUM NITRIDE SEMICONDUCTOR DEVICE, GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND GALLIUM OXIDE WAFER - A gallium nitride based semiconductor device is provided which includes a gallium nitride based semiconductor film with a flat c-plane surface provided on a gallium oxide wafer. A light emitting diode LED includes a gallium oxide support base | 12-29-2011 |
| 20110315999 | Gallium and Nitrogen Containing Triangular or Diamond-shaped Configuration for Optical Devices - A gallium and nitrogen containing optical device has a base region and no more than three major planar side regions configured in a triangular arrangement provided from the base region. | 12-29-2011 |
| 20110316000 | MANUFACTURING OF LOW DEFECT DENSITY FREE-STANDING GALLIUM NITRIDE SUBSTRATES AND DEVICES FABRICATED THEREOF - The invention relates to a method for manufacturing a single crystal of nitride by epitaxial growth on a support ( | 12-29-2011 |
| 20110316001 | METHOD FOR GROWING GROUP III-V NITRIDE FILM AND STRUCTURE THEREOF - A method for growing a Group III-V nitride film and a structure thereof are presented. The method is carried out by hydride vapor phase epitaxy (HVPE). The method includes the steps of, inter alia, slowly epitaxially growing a temperature ramping nitride layer on a substrate by rising a first growth temperature of 900-950° C. to a second growth temperature of 1000-1050° C. at a temperature-rising rate of 0.5-10° C./min. The lattice quality of the temperature ramping nitride layer is slowly transformed with the layer height, so that a stress induced by lattice mismatch between a sapphire substrate and a gallium nitride (GaN) layer is relieved. | 12-29-2011 |
| 20120001193 | Polishing method, polishing apparatus and GaN wafer - A polishing method can process and flatten, in a practical processing time and with high surface accuracy, a surface of a substrate of a Ga element-containing compound semiconductor. The polishing method includes: bringing a Ga element-containing compound semiconductor substrate ( | 01-05-2012 |
| 20120001194 | SEMICONDUCTOR DEVICE - A semiconductor device includes a Si substrate having a principal plane that is a crystal surface inclined at an off angle of 0.1 degrees or less with respect to a (111) plane, an AlN layer that is provided so as to contact the principal plane of the Si substrate and is configured so that an FWHM of a rocking curve of a (002) plane by x-ray diffraction is not greater than 2000 seconds, and a GaN-based semiconductor layer formed on the AlN layer. | 01-05-2012 |
| 20120001195 | SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE - A semiconductor substrate inclu8des an AlN layer that is formed so as to contact a Si substrate and has an FWMH of a rocking curve of a (002) plane by x-ray diffraction, the FWMH being less than or equal to 1500 seconds, and a GaN-based semiconductor layer formed on the AlN layer. | 01-05-2012 |
| 20120001196 | LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME, LIGHT EMITTING DEVICE PACKAGE, AND LIGHTING SYSTEM - Provided are a light emitting device, a method of manufacturing the same, a light emitting device package, and a lighting system. The light emitting device includes: a light emitting structure layer including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; an oxide protrusion disposed on at least a portion of the second conducive semiconductor layer; and a current spreading layer on the second conductive semiconductor layer and the oxide protrusion. | 01-05-2012 |
| 20120007097 | SCHOTTKY DIODE WITH COMBINED FIELD PLATE AND GUARD RING - A Schottky diode comprising a merged guard ring and field plate defining a Schottky contact region is provided. A Schottky metal is formed over at least partially over the Schottky contact region and at least partially over the merged guard ring and field plate. | 01-12-2012 |
| 20120007098 | TRANSISTOR AND METHOD FOR PRODUCING TRANSISTOR - Certain embodiments provide a transistor including a semiconductor conductive layer, a drain electrode, a source electrode, and a gate electrode. The semiconductor device is III nitride-based semiconductor conductive layer including an active layer, formed on a surface of a substrate. The drain electrode and the source electrode have a titanium layer and an aluminum layer formed on the titanium layer and having a film thickness ratio of 12 to 15 with respect to the titanium layer, and the drain electrode and the source electrode come into ohmic contact with the semiconductor layer. The gate electrode is in Schottky junction with the semiconductor layer between the drain electrode and source electrode. | 01-12-2012 |
| 20120007099 | MULTI-GAS SENSOR AND METHOD OF FABRICATING THE SENSOR - The present invention is a multi-gas sensor and a method for fabricating the multi-gas sensor. | 01-12-2012 |
| 20120007100 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device including a substrate, a reflective layer provided on the substrate, and a light emitting structure, which includes a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer placed between the first and second conductive semiconductor layers, wherein the first conductive semiconductor layer is an n-type semiconductor layer including GaN and doped with an n-type dopant, wherein the first conductive semiconductor layer includes a first n-type semiconductor layer and a second n-type semiconductor layer between the first n-type semiconductor layer and the active layer, wherein one surface of the first n-type semiconductor layer contacts the second n-type semiconductor layer, and wherein the surface of the first n-type semiconductor layer contacting the second n-type semiconductor layer is formed in an N-phase. The disclosed light emitting device may have improved luminous efficacy while showing reduction in crystal defects. | 01-12-2012 |
| 20120007101 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor light-emitting device, and a method of manufacturing the same. The semiconductor light-emitting device includes a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked on a substrate, a first contact that passes through the substrate to be electrically connected to the first electrode layer, and a second contact that passes through the substrate, the first electrode layer, and the insulating layer to communicate with the second electrode layer. The first electrode layer is electrically connected to the first semiconductor layer by filling a contact hole that passes through the second electrode layer, the second semiconductor layer, and the active layer, and the insulating layer surrounds an inner circumferential surface of the contact hole to insulate the first electrode layer from the second electrode layer. | 01-12-2012 |
| 20120007102 | High Voltage Device and Method for Optical Devices - A light emitting device comprising a gallium and nitrogen containing substrate. The device also has an electrically isolating material grown between the substrate and an active region such that the light emitting device is operable at a voltage greater than 10V. | 01-12-2012 |
| 20120012855 | SOLID-STATE LIGHT EMITTERS HAVING SUBSTRATES WITH THERMAL AND ELECTRICAL CONDUCTIVITY ENHANCEMENTS AND METHOD OF MANUFACTURE - Solid-state lighting devices (SSLDs) including a carrier substrate with conductors and methods of manufacturing SSLDs. The conductors can provide (a) improved thermal conductivity between a solid-state light emitter (SSLE) and a package substrate and (b) improved electrical conductivity for the SSLE. In one embodiment, the conductors have higher thermal and electrical conductivities than the carrier substrate supporting the SSLE. | 01-19-2012 |
| 20120012856 | GaN Light Emitting Diode and Method for Increasing Light Extraction on GaN Light Emitting Diode Via Sapphire Shaping - A method for enhancing light extraction efficiency of GaN light emitting diodes is disclosed. By cutting off a portion from each end of bottom of a sapphire substrate or forming depressions on the bottom of the substrate and forming a reflector, light beams emitted to side walls of the substrate can be guided to the light emitting diodes. | 01-19-2012 |
| 20120012857 | WIDE-GAP SEMICONDUCTOR SUBSTRATE AND METHOD TO FABRICATE WIDE-GAP SEMICONDUCTOR DEVICE USING THE SAME - A wide-gap semiconductor substrate includes a narrow-gap semiconductor layer, a wide-gap semiconductor layer and an alignment mark. The narrow-gap semiconductor layer has a main surface. The wide-gap semiconductor layer is epitaxially grown on the narrow-gap semiconductor layer. The alignment mark is preliminarily carved in a prescribed position on the main surface so that the alignment mark is preliminarily buried in the wide-gap semiconductor substrate. | 01-19-2012 |
| 20120012858 | SEMICONDUCTOR DEVICE - A semiconductor device includes source fingers and drain fingers provided on an active region of a nitride semiconductor layer alternately, gate fingers having a side edge and a distal edge, a first insulation film provided on the nitride semiconductor layer and covers a top face, the side and distal edges of the gate fingers, field plates provided on the first insulation film between the gate fingers and the drain fingers, a minimum distance between the side face of the first insulation film located on the side edge of the gate fingers and the field plate being at least 100 nm, and field plate interconnections provided on the first insulation film and located outside of the active region and electrically connected with the source fingers and the field plates, a minimum distance between the side face of the first insulation film located on the distal edge of the gate fingers and the field plate interconnections being at least 100 nm. | 01-19-2012 |
| 20120012859 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a light emitting device and a method of manufacturing the same. A light emitting device includes an active layer; a first conductive semiconductor layer on the active layer; a second conductive semiconductor layer on the active layer so that the active layer is disposed between the first and second conductive semiconductor layers; and a photonic crystal structure comprising a first light extraction pattern on the first conductive semiconductor layer having a first period, and second light extraction pattern on the first conductive semiconductor layer having a second period, the first period being greater than λ/n, and the second period being identical to or smaller than λ/n, where n is a refractive index of the first conductive semiconductor layer, and λ is a wavelength of light emitted from the active layer. | 01-19-2012 |
| 20120018734 | Light-emitting devices and methods of manufacturing the same - Example embodiments are directed to light-emitting devices (LEDs) and methods of manufacturing the same. The LED includes a first semiconductor layer; a second semiconductor layer; an active layer formed between the first and second semiconductor layers; and an emission pattern layer including a plurality of layers on the first semiconductor layer, the emission pattern including an emission pattern for externally emitting light generated from the active layer. | 01-26-2012 |
| 20120018735 | SEMICONDUCTOR DEVICE - A semiconductor device includes a source electrode and a drain electrode formed on an active region of the semiconductor layer, a gate electrode formed on the active region of the semiconductor layer, a first insulating film formed on the semiconductor layer and covering the gate electrode, the first insulating film having a step portion following a shape of the gate electrode, a first field plate formed on the insulating film and located between the gate electrode and the drain electrode and separated from the step portion, a second insulating film formed on the first insulating film to cover the step portion and the first field plate, and a shield electrode formed on the second insulating film, the shield electrode extending from a portion located above the first field plate and a portion located above the gate electrode. | 01-26-2012 |
| 20120018736 | GROUP III NITRIDE SUBSTRATE, SEMICONDUCTOR DEVICE COMPRISING THE SAME, AND METHOD FOR PRODUCING SURFACE-TREATED GROUP III NITRIDE SUBSTRATE - A group III nitride substrate in one embodiment has a surface layer. The surface layer contains 3 at. % to 25 at. % of carbon and 5×10 | 01-26-2012 |
| 20120025201 | Inverted Trapezoidal Recess for Epitaxial Growth - A semiconductor device having an epitaxial layer a method of manufacture thereof is provided. The semiconductor device has a substrate with a trench formed therein and a recess formed below the trench. The recess has sidewalls with a (111) crystal orientation. The depth of the trench is such that the depth is greater than or equal to one-half a length of sidewalls of the recess. An epitaxial layer is formed in the recess and the trench. The depth of the trench is sufficient to cause dislocations formed between the interface of the semiconductor substrate and the epitaxial layer to terminate along sidewalls of the trench. | 02-02-2012 |
| 20120025202 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a silicon substrate; a buffer layer provided on the silicon substrate and has a band gap greater than GaN; a first GaN layer provided on the buffer layer; and a second GaN layer provided directly on the first GaN layer, a carbon concentration of the first GaN layer being higher than a carbon concentration of the second GaN layer. | 02-02-2012 |
| 20120025203 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first GaN layer formed on a substrate, the first GaN layer including a transition metal and an impurity under constant concentration, the impurity forming a deeper energy level in the first GaN layer than energy level formed by the transition metal, a second GaN layer formed on the first GaN layer, the second GaN layer including the transition metal and the impurity under inclined concentration, an inclined direction of the transition metal being same as an inclined direction of the impurity, and an electron supply layer formed on the second GaN layer. | 02-02-2012 |
| 20120032182 | SOLID STATE LIGHTS WITH THERMAL CONTROL ELEMENTS - A solid state light (“SSL”), a solid state emitter (“SSE”), and methods of manufacturing SSLs and SSEs. In one embodiment, an SSL comprises a packaging substrate having an electrical contact and a light emitting structure having a front side and a back side. The back side of the light emitting structure is superimposed with the electrical contact of the packaging substrate. The SSL can further include a temperature control element aligned with the light emitting structure and the electrical contact of the packaging substrate. | 02-09-2012 |
| 20120032183 | GaN Based LED having Reduced Thickness and Method for Making the Same - A device having a carrier, a light-emitting structure, and first and second electrodes is disclosed. The light-emitting structure includes an active layer sandwiched between a p-type GaN layer and an n-type GaN layer, the active layer emitting light of a predetermined wavelength in the active layer when electrons and holes from the n-type GaN layer and the p-type GaN layer, respectively, combine therein. The first and second electrodes are bonded to the surfaces of the p-type and n-type GaN layers that are not adjacent to the active layer. The n-type GaN layer has a thickness less than 1.25 μm. The carrier is bonded to the light emitting structure during the thinning of the n-type GaN layer. The thinned light-emitting structure can be transferred to a second carrier to provide a device that is analogous to conventional LEDs having contacts on the top surface of the LED. | 02-09-2012 |
| 20120032184 | SYSTEMS AND METHODS FOR PRODUCING WHITE-LIGHT LIGHT EMITTING DIODES - A vertical light-emitting diode (VLED) includes a metal substrate, a p-electrode coupled to the metal substrate, a p-contact coupled to the p-electrode, a p-GaN portion coupled to the p-electrode, an active region coupled to the p-GaN portion, an n-GaN portion coupled to the active region, and a phosphor layer coupled to the n-GaN portion. | 02-09-2012 |
| 20120032185 | LEAKAGE BARRIER FOR GaN BASED HEMT ACTIVE DEVICE - An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated. | 02-09-2012 |
| 20120032186 | WHITE ORGANIC LIGHT EMITTING DEVICE - Provided is a white organic light emitting device (OLED), including: a first electrode formed on a substrate; a hole transport layer formed on the first electrode; an emission layer formed on the hole transport layer; an electron transport layer formed on the emission layer; and an color control layer formed on at least one of the hole transport layer, the emission layer and the electron transport layer, and emitting green and/or red by energy transfer from the emission layer. The white OLED emits red, green and blue light with high efficiency, has excellent color reproducibility and a high color reproduction index. | 02-09-2012 |
| 20120032187 | Lattice-Mismatched GaInP LED Devices and Methods of Fabricating Same | 02-09-2012 |
| 20120032188 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output. | 02-09-2012 |
| 20120037917 | LOW INTERCONNECT RESISTANCE INTEGRATED SWITCHES - Circuits and systems comprising one or more switches are provided. A circuit includes a first switch formed on a substrate; and a second switch formed on the substrate, the second switch including a first terminal coupled to a third terminal of the first switch. A system includes a supply; a first switch formed on a substrate, the first switch coupled to the supply; a second switch formed on the substrate, the second switch coupled to the first switch; a third switch formed on the substrate, the third switch coupled to the supply; a fourth switch formed on the substrate, the fourth switch coupled to the third switch; and a driver coupled to respective second terminals of the first, second, third, and fourth switches. | 02-16-2012 |
| 20120037918 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SAME - A semiconductor device includes a semiconductor layer ( | 02-16-2012 |
| 20120037919 | NANOPORE ELECTRICAL SENSOR - A nanopore electrical sensor is provided. The sensor has layered structure, including a substrate ( | 02-16-2012 |
| 20120043550 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a stacked structural body, first and second electrodes, a high resistance layer and a transparent conductive layer. The stacked structural body includes first and second semiconductor layers and a light emitting layer. The first semiconductor layer is disposed between the first electrode and the second semiconductor layer. The second semiconductor layer is disposed between the second electrode and the first semiconductor layer. The second electrode has reflectivity with respect to luminescent light. The high resistance layer is in contact with the second semiconductor layer between the second semiconductor layer and the second electrode and includes a portion overlapping with the first electrode. The transparent conductive layer is in contact with the second semiconductor layer between the second semiconductor layer and the second electrode. The transparent conductive layer has a resistance lower than a resistance of the high resistance layer. | 02-23-2012 |
| 20120043551 | Second contact schottky metal layer to improve GaN schottky diode performance - A Schottky diode includes a first nitride-based semiconductor layer disposed atop a substrate. A second nitride-based semiconductor layer is disposed atop a portion of the first nitride-based semiconductor layer. The second layer has a doping concentration lower than that of the first layer. A first Schottky contact metal layer having a first metal work function is disposed on a top planar surface of the second layer, forming a first Schottky junction. A second Schottky contact metal layer having a second metal work function is disposed atop of and laterally surrounding the first Schottky contact metal layer, the metal work function of the second metal layer is higher than that of the first metal layer. A metal layer disposed on first and second planar surfaces forms an ohmic contact with the first nitride-based semiconductor layer. | 02-23-2012 |
| 20120043552 | System and Method for Selected Pump LEDs with Multiple Phosphors - An LED pump light with multiple phosphors is described. LEDs emitting radiation at violet and/or ultraviolet wavelengths are used to pump phosphor materials that emit other colors. The LEDs operating in different wavelength ranges are arranged to reduce light re-absorption and improve light output efficiency. | 02-23-2012 |
| 20120043553 | Hybrid Semiconductor Device Having a GaN Transistor and a Silicon MOSFET - A hybrid device including a silicon based MOSFET operatively connected with a GaN based device. | 02-23-2012 |
| 20120043554 | LIGHT-EMITTING DEVICES - Light-emitting devices, and related components, systems and methods are disclosed. | 02-23-2012 |
| 20120043555 | LIQUID FLUORESCENT COMPOSITION AND LIGHT EMITTING DEVICE - The invention provides a liquid fluorescent composition. The liquid fluorescent composition includes at least (a) 0.001-2 parts by weight of a fluorescent material; and (b) 100 parts by weight of a cyclic solvent having a boiling point above 100° C. The invention also provides a light emitting device containing the above liquid fluorescent composition. | 02-23-2012 |
| 20120056191 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND POWER SUPPLY APPARATUS - A semiconductor device includes a GaN electron transport layer provided over a substrate; a first AlGaN electron supply layer provided over the GaN electron transport layer; an AlN electron supply layer provided over the first AlGaN electron supply layer; a second AlGaN electron supply layer provided over the AlN electron supply layer; a gate recess provided in the second AlGaN electron supply layer and the AlN electron supply layer; and a gate electrode provided over the gate recess. | 03-08-2012 |
| 20120056192 | COMPOUND SEMICONDUCTOR IMAGE SENSOR - A stack-type image sensor using a compound semiconductor. The stack-type image sensor includes a stack of photoelectric conversion units which are sequentially arranged in a light incident direction and which absorb light in ascending order of a wavelength from shortest to longest. | 03-08-2012 |
| 20120056193 | Series Connected Segmented LED - A light source and method for making the same are disclosed. The light source includes a conducting substrate, and a light emitting structure that is divided into segments. The light emitting structure includes a first layer of semiconductor material of a first conductivity type deposited on the substrate, an active layer overlying the first layer, and a second layer of semiconductor material of an opposite conductivity type from the first conductivity type overlying the active layer. A barrier divides the light emitting structure into first and second segments that are electrically isolated from one another. A serial connection electrode connects the first layer in the first segment to the second layer in the second segment. A power contact is electrically connected to the second layer in the first segment, and a second power contact electrically connected to the first layer in the second segment. | 03-08-2012 |
| 20120061680 | GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heat dissipation substrate (that is, a thermal conductive substrate); a GaN-based multi-layer arranged on the heat dissipation substrate and having N-face polarity; and a heterostructure field effect transistor (HFET) or a Schottky electrode arranged on the GaN-based multi-layer. The HFET device may include a gate having a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used. | 03-15-2012 |
| 20120068186 | Electronic Device - An electronic device includes a carrier, a plurality of pins, and an electronic circuit that includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is attached to the carrier and the second semiconductor chip is attached to one of the plurality of pins. | 03-22-2012 |
| 20120068187 | SOLID STATE LIGHTING DEVICES WITH IMPROVED COLOR UNIFORMITY AND METHODS OF MANUFACTURING - Solid state lighting (SSL) devices with good color uniformity and methods of manufacturing are disclosed herein. In one embodiment, an SSL device includes a support structure, an SSL die in the support structure, and a converter material at least partially encapsulating the SSL die. The converter material is configured to emit under excitation. The converter material has a surface facing away from the SSL die, and the surface of the converter material has a generally convex shape. | 03-22-2012 |
| 20120068188 | Defects Annealing and Impurities Activation in III-Nitride Compound Semiconductors - A GaN sample in a sealed enclosure is heated very fast to a high temperature above the point where GaN is thermodynamically stable and is then cooled down very fast to a temperature where it is thermodynamically stable. The time of the GaN exposure to a high temperature range above its thermodynamic stability is sufficiently short, in a range of few seconds, to prevent the GaN from decomposing. This heating and cooling cycle is repeated multiple times without removing the sample from the enclosure. As a result, by accumulating the exposure time in each cycle, the GaN sample can be exposed to a high temperature above its point of thermodynamic stability for a long time but the GaN sample integrity is maintained (i.e., the GaN doesn't decompose) due to the extremely short heating duration of each single cycle. | 03-22-2012 |
| 20120068189 | Method for Vertical and Lateral Control of III-N Polarity - Disclosed herein is a method of: depositing a patterned mask layer on an N-polar GaN epitaxial layer of a sapphire, silicon, or silicon carbide substrate; depositing an AlN inversion layer on the open areas; removing any remaining mask; and depositing a III-N epitaxial layer to simultaneously produce N-polar material and III-polar material. Also disclosed herein is: depositing an AlN inversion layer on an N-polar bulk III-N substrate and depositing a III-N epitaxial layer to produce III-polar material. Also disclosed herein is: depositing an inversion layer on a III-polar bulk III-N substrate and depositing a III-N epitaxial layer to produce N-polar material. Also disclosed herein is a composition having: a bulk III-N substrate; an inversion layer on portions of the substrate; and a III-N epitaxial layer on the inversion layer. The III-N epitaxial layer is of the opposite polarity of the surface of the substrate. | 03-22-2012 |
| 20120068190 | Gallium Nitride Devices with Electrically Conductive Regions - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., PET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. | 03-22-2012 |
| 20120068191 | METHOD OF CONTROLLING STRESS IN GROUP-III NITRIDE FILMS DEPOSITED ON SUBSTRATES - Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. | 03-22-2012 |
| 20120068192 | CRYSTAL GROWTH OF M-PLANE AND SEMIPOLAR PLANES OF (Al, In, Ga, B)N ON VARIOUS SUBSTRATES - A method of reducing threading dislocation densities in non-polar such as a-{11-20} plane and m-{1-100} plane or semi-polar such as {10-1n} plane III-Nitrides by employing lateral epitaxial overgrowth from sidewalls of etched template material through a patterned mask. The method includes depositing a patterned mask on a template material such as a non-polar or semi polar GaN template, etching the template material down to various depths through openings in the mask, and growing non-polar or semi-polar III-Nitride by coalescing laterally from the tops of the sidewalls before the vertically growing material from the trench bottoms reaches the tops of the sidewalls. The coalesced features grow through the openings of the mask, and grow laterally over the dielectric mask until a fully coalesced continuous film is achieved. | 03-22-2012 |
| 20120074424 | GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a conductive heat dissipation substrate (that is, a thermal conductive substrate); an GaN-based multi-layer arranged on the heat dissipation substrate; and a Schottky electrode arranged on the GaN-based multi-layer. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used. | 03-29-2012 |
| 20120074425 | GROWTH OF REDUCED DISLOCATION DENSITY NON-POLAR GALLIUM NITRIDE - Lateral epitaxial overgrowth (LEO) of non-polar gallium nitride (GaN) films results in significantly reduced defect density. | 03-29-2012 |
| 20120074426 | FIELD-EFFECT TRANSISTOR - A field-effect transistor includes a carrier transport layer made of nitride semiconductor, a gate electrode having first and second sidewall surfaces on first and second sides, respectively, an insulating film formed directly on the gate electrode to cover at least one of the first and second sidewall surfaces, first and second ohmic electrodes formed on the first and second sides, respectively, a passivation film including a first portion extending from the first ohmic electrode toward the gate electrode to cover a surface area between the first ohmic electrode and the gate electrode and a second portion extending from the second ohmic electrode toward the gate electrode to cover a surface area between the second ohmic electrode and the gate electrode, wherein the insulating film is in direct contact with at least the first and second passivation film portions, and has a composition different from that of the passivation film. | 03-29-2012 |
| 20120074427 | METHOD FOR MANUFACTURING A LAYER OF GALLIUM NITRIDE OR GALLIUM AND ALUMINUM NITRIDE - The present invention relates to a crack-free monocrystalline nitride layer having the composition AlxGa | 03-29-2012 |
| 20120080686 | Semiconductor Devices and Methods of Manufacturing Thereof - In one embodiment, a method of forming a semiconductor device includes forming a first porous semiconductor layer over a top surface of a substrate. A first epitaxial layer is formed over the first porous semiconductor layer. A circuitry is formed within and over the first epitaxial layer. The circuitry is formed without completely oxidizing the first epitaxial layer. | 04-05-2012 |
| 20120080687 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device of an embodiment includes: a nitride semiconductor device, including: a nitride semiconductor substrate; a first anode electrode formed on the substrate; a recess structure formed on the substrate of an outer peripheral portion of the first anode electrode by engraving the substrate; a second anode electrode formed so as to cover the first anode electrode and so as to be embedded in the recess structure; and a cathode electrode formed on the substrate. | 04-05-2012 |
| 20120080688 | ULTRA-THIN OHMIC CONTACTS FOR P-TYPE NITRIDE LIGHT EMITTING DEVICES - A flip-chip semiconductor based Light Emitting Device (LED) can include an n-type semiconductor substrate and an n-type GaN epi-layer on the substrate. A p-type GaN epi-layer can be on the n-type GaN epi-layer and a metal ohmic contact p-electrode can be on the p-type GaN epi-layer, where the metal ohmic contact p-electrode can have an average thickness less than about 25 Å. A reflector can be on the metal ohmic contact p-electrode and a metal stack can be on the reflector. An n-electrode can be on the substrate opposite the n-type GaN epi-layer and a bonding pad can be on the n-electrode. | 04-05-2012 |
| 20120080689 | LIGHT EMITTING DIODE, LIGHT EMITTING DIODE LAMP, AND LIGHTING APPARATUS - A light-emitting diode having a high output, high efficiency, and a long service life under a high-humidity environment is provided. The light-emitting diode ( | 04-05-2012 |
| 20120086014 | Semiconductor Device Having Glue Layer And Supporter - A plurality of metal patterns are disposed on a substrate. A support structure is provided between the plurality of metal patterns. The support structure has a supporter and a glue layer. Each of the plurality of metal patterns has a greater vertical length than a horizontal length on the substrate when viewed from a cross-sectional view. The supporter has a band gap energy of at least 4.5eV. The glue layer is in contact with the plurality of metal patterns. The supporter and the glue layer are formed of different materials. | 04-12-2012 |
| 20120086015 | GROUP III NITRIDE SEMICONDUCTOR DEVICE, EPITAXIAL SUBSTRATE, AND METHOD OF FABRICATING GROUP III NITRIDE SEMICONDUCTOR DEVICE - A group III nitride semiconductor device having a gallium nitride based semiconductor film with an excellent surface morphology is provided. A group III nitride optical semiconductor device includes a group III nitride semiconductor supporting base, a GaN based semiconductor region, an active layer, and a GaN semiconductor region. The primary surface of the group III nitride semiconductor supporting base is not any polar plane, and forms a finite angle with a reference plane that is orthogonal to a reference axis extending in the direction of a c-axis of the group III nitride semiconductor. The GaN based semiconductor region, grown on the semipolar primary surface, includes a semiconductor layer of, for example, an n-type GaN based semiconductor doped with silicon. A GaN based semiconductor layer of an oxygen concentration of 5×10 | 04-12-2012 |
| 20120086016 | GROUP III NITRIDE SEMICONDUCTOR AND GROUP III NITRIDE SEMICONDUCTOR STRUCTURE - There is provided a surface treatment method of a group III nitride semiconductor including: providing a group III nitride semiconductor including a first surface having a group III polarity and a second surface opposing the first surface and having a nitrogen polarity; and irradiating a laser beam onto the second surface to change the nitrogen polarity of the second surface to the group III polarity. | 04-12-2012 |
| 20120086017 | HETEROGENEOUS SUBSTRATE, NITRIDE-BASED SEMICONDUCTOR DEVICE USING SAME, AND MANUFACTURING METHOD THEREOF - Provided are a heterogeneous substrate, a nitride-based semiconductor device using the same, and a manufacturing method thereof to form a high-quality non-polar or semi-polar nitride layer on a non-polar or semi-polar plane of the heterogeneous substrate by adjusting a crystal growth mode. A base substrate having one of a non-polar plane and a semi-polar plane is prepared, and a nitride-based nucleation layer is formed on the plane of the base substrate. A first buffer layer is grown faster in the vertical direction than in the lateral direction on the nucleation layer. A lateral growth layer is grown faster in the lateral direction than in the vertical direction on the first buffer layer. A second buffer layer is formed on the lateral growth layer. A silicon nitride layer having a plurality of holes may be formed between the lateral growth layer on the first buffer layer and the second buffer layer. | 04-12-2012 |
| 20120091463 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND MANUFACTURING METHOD THEREFOR - A nitride-based semiconductor light-emitting device according to the present invention has a nitride-based semiconductor multilayer structure | 04-19-2012 |
| 20120091464 | GaN LEDs with Improved Area and Method for Making the Same - Enlightening device and method for making the same are disclosed. Individual light emitting devices such as LEDs are separated to form individual dies by process in which a first narrow trench cuts the light emitting portion of the device and a second trench cuts the substrate to which the light emitting portion is attached. The first trench can be less than 10 μm. Hence, a semiconductor area that would normally be devoted to dicing streets on the wafer is substantially reduced thereby increasing the yield of devices. The devices generated by this method can also include base members that are electrically conducting as well as heat conducting in which the base member is directly bonded to the light emitting layers thereby providing improved heat conduction. | 04-19-2012 |
| 20120091465 | Method of Making Bulk InGaN Substrates and Devices Thereon - A relaxed epitaxial Al | 04-19-2012 |
| 20120091466 | Smart Integrated Semiconductor Light Emitting System Including Nitride Based Light Emitting Diodes (LED) And Application Specific Integrated Circuits (ASIC) - A light emitting diode (LED) system includes a substrate, an application specific integrated circuit (ASIC), and at least one light emitting diode (LED) that includes a Group-III nitride based material such as GaN, InGaN, AlGaN, AlInGaN or other (Ga, In or Al) N-based materials. The light emitting diode (LED) system can also include a polymer lens, and a phosphor layer on the lens or light emitting diode (LED) for producing white light. In addition, multiple light emitting diodes (LEDs) can be mounted on the substrate, and can have different colors for smart color control lighting. The substrate and the application specific integrated circuit (ASIC) are configured to provide an integrated LED circuit having smart functionality. In addition, the substrate is configured to compliment and expand the functions of the application specific integrated circuit (ASIC), and can also include built in integrated circuits for performing additional electrical functions. | 04-19-2012 |
| 20120091467 | IN-SITU DEFECT REDUCTION TECHNIQUES FOR NONPOLAR AND SEMIPOLAR (Al, Ga, In)N - A method for growing reduced defect density planar gallium nitride (GaN) films is disclosed. The method includes the steps of (a) growing at least one silicon nitride (SiN | 04-19-2012 |
| 20120097968 | MULTILAYER SUBSTRATE HAVING GALLIUM NITRIDE LAYER AND METHOD FOR FORMING THE SAME - The present invention provides a method for forming a multilayer substrate having a gallium nitride layer, wherein a mesh layer having a plurality of openings is formed on a substrate, and a buffer layer, three aluminum gallium nitride layers with different aluminum concentrations and a gallium nitride layer are formed in sequence on the substrate in the openings. The three aluminum gallium nitride layers with different aluminum concentrations are capable of releasing stress, decreasing cracks on the surface of the gallium nitride layer and controlling interior defects, such that the present invention provides a gallium nitride layer with larger area, greater thickness, no cracks and high quality for facilitating the formation of high performance electronic components in comparison with the prior art. The present invention further provides a multilayer substrate having a gallium nitride layer. | 04-26-2012 |
| 20120097969 | LIGHT EMITTING DIODE CHIP AND MANUFACTURING METHOD THEREOF - An exemplary LED chip includes a substrate, a buffer layer formed on the substrate and a light emitting layer formed on the buffer layer. The light emitting layer includes an n-type semiconductor layer and a p-type semiconductor layer. A first electrode is electrically connected with one of the n-type semiconductor layer and the p-type semiconductor layer. A second electrode is electrically connected with the other one of the n-type semiconductor layer and the p-type semiconductor layer. A bonding pad is formed on a top surface of the first electrode. A bonding wire is secured to the bonding pad. A ratio between a contacting area between the bonding pad and the top surface of the first electrode and an area of the top surface of the first electrode is no less than 6:10. | 04-26-2012 |
| 20120097970 | ATOMIC LAYER DEPOSITION ENCAPSULATION FOR POWER AMPLIFIERS IN RF CIRCUITS - Power amplifiers and methods of coating a protective film of alumina (Al | 04-26-2012 |
| 20120097971 | CONTIGUOUS AND VIRTUALLY CONTIGUOUS AREA EXPANSION OF SEMICONDUCTOR SUBSTRATES - Substrates are processed, with a high degree of topography, to produce a variety of semiconductors or other devices and are then stretched out, substantially flat, to achieve a significant increase in surface area. Devices made from a contiguous structure of a single, active crystalline material or from non-contiguous structures of multiple materials, such as a combination of dielectrics, thin film metals and active crystalline semiconductors, are fabricated by utilizing anisotropically etched, high aspect ratio configurations of the active material. The structure is then stretched out to achieve a significant increase in surface area, thereby enabling a substantial reduction in the cost of the substrate materials per unit area in the final product. | 04-26-2012 |
| 20120097972 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a light emitting device includes forming a multilayer body including a light emitting layer so that a first surface thereof is adjacent to a first surface side of a translucent substrate. A dielectric film on a second surface side opposite to the first surface of the multilayer body is formed having first and second openings on a p-side electrode and an n-side electrode. A seed metal on the dielectric film and an exposed surface of the first and second openings form a p-side metal interconnect layer and an n-side metal interconnect layer separating the seed metal into a p-side seed metal and an n-side seed metal by removing a part of the seed metal. A resin is formed in a space from which the seed metal is removed. | 04-26-2012 |
| 20120097973 | HIGH PERFORMANCE POWER SWITCH - In one example, we describe a new high performance AlGaN/GaN metal-insulator-semiconductor heterostructure field-effect transistor (MISHFET), which was fabricated using HfO2 as the surface passivation and gate insulator. The gate and drain leakage currents are drastically reduced to tens of nA, before breakdown. Without field plates, for 10 μm of gate-drain spacing, the off-state breakdown voltage is 1035V with a specific on-resistance of 0.9 mΩ-cm2. In addition, there is no current slump observed from the pulse measurements. This is the best performance reported on GaN-based, fast power-switching devices on sapphire, up to now, which efficiently combines excellent device forward, reverse, and switching characteristics. Other variations, features, and examples are also mentioned here. | 04-26-2012 |
| 20120104407 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - An LED includes a substrate, a first n-type GaN layer, a connecting layer, a second n-type GaN layer, a light emitting layer, and a p-type GaN layer. The first n-type GaN layer is formed on the substrate, the first n-type GaN layer has a first surface facing away from the substrate, and the first surface includes a first area and a second area. The connecting layer, the second n-type GaN layer, the light emitting layer, and the p-type GaN layer are formed on the first area in sequence. The connecting layer is etchable by alkaline solution; a bottom surface of the second n-type GaN layer facing towards the connecting layer has a roughened exposed portion; the GaN on the bottom surface of the second n-type GaN layer is N-face GaN. | 05-03-2012 |
| 20120104408 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In an aspect of a semiconductor device, there are provided a substrate, a transistor including an electron transit layer and an electron supply layer formed over the substrate, a nitride semiconductor layer formed over the substrate and connected to a gate of the transistor, and a controller controlling electric charges moving in the nitride semiconductor layer. | 05-03-2012 |
| 20120104409 | FORMING LIGHT-EMITTING DIODES USING SEED PARTICLES - A seed layer for growing a group III-V semiconductor structure is embedded in a dielectric material on a carrier substrate. After the group III-V semiconductor structure is grown, the dielectric material is removed by wet etch to detach the carrier substrate. The group III-V semiconductor structure includes a thick gallium nitride layer of at least 100 microns or a light-emitting structure. | 05-03-2012 |
| 20120104410 | Reflector, Manufacture Method Thereof And Light-Emitting Device Including The Reflector - A reflector for a GaN-based light-emitting device, method for manufacturing the reflector and GaN-haled light-emitting device including the reflector are provided. The reflector is formed on a p-type GaN-based epitaxial layer and includes: a whisker crystal of un-doped GaN, formed on a surface of the p-type GaN-based epitaxial layer with a predefined density distribution and at a position that corresponds to a dislocation defect of an epitaxial layer; and a metal reflective layer, formed on both the p-type GaN-based epitaxial layer and the whisker crystal. The whisker of un-doped GaN is positioned on the dislocation defect of the p-type GaN-based epitaxial layer, so that the Ag reflective layer can be separated from the dislocation defect of the p-type GaN-based epitaxial layer, thereby effectively preventing Ag from moving inside the dislocation defect via electromigration, and largely decreasing the possibility of current leakage of the light-emitting device including the Ag reflector. | 05-03-2012 |
| 20120104411 | TEXTURED III-V SEMICONDUCTOR - A method for fabricating a III-nitride semiconductor film, comprising depositing or growing a III-nitride semiconductor film in a semiconductor light absorbing or light emitting device structure; and growing a textured or structured surface of the III-nitride nitride semiconductor film in situ with the growing or the deposition of the III-nitride semiconductor film, by controlling the growing of the III-nitride semiconductor film to obtain a texture of the textured surface, or one or more structures of the structured surface, that increase output power of light from the light emitting device, or increase absorption of light in the light absorbing device. | 05-03-2012 |
| 20120104412 | HIGH LIGHT EXTRACTION EFFICIENCY NITRIDE BASED LIGHT EMITTING DIODE BY SURFACE ROUGHENING - A III-nitride light emitting diode (LED) and method of fabricating the same, wherein at least one surface of a semipolar or nonpolar plane of a III-nitride layer of the LED is textured, thereby forming a textured surface in order to increase light extraction. The texturing may be performed by plasma assisted chemical etching, photolithography followed by etching, or nano-imprinting followed by etching. | 05-03-2012 |
| 20120104413 | LIGHT EMITTING SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING - The light emitting semiconductor device ( | 05-03-2012 |
| 20120112201 | HIGH MELTING POINT SOLDERING LAYER AND FABRICATION METHOD FOR THE SAME, AND SEMICONDUCTOR DEVICE - A high melting point soldering layer includes a low melting point metal layer, a first high melting point metal layer disposed on a surface of the low melting point metal layer, and a second high melting point metal layer disposed at a back side of the low melting point metal layer. The low melting point metal layer, the first high melting point metal layer, and the second high melting point metal layer are mutually alloyed by transient liquid phase bonding, by annealing not less than a melting temperature of the low melting point metal layer, diffusing the metal of the low melting point metal layer into an alloy of the first high melting point metal layer and the second high melting point metal layer. The high melting point soldering layer has a higher melting point temperature than that of the low melting point metal layer. It is provided a binary based high melting point soldering layer having TLP bonding of a high melting point according to a low temperature processing, a fabrication method for the high melting point soldering layer and a semiconductor device to which the high melting point soldering layer is applied. | 05-10-2012 |
| 20120112202 | E-Mode High Electron Mobility Transistors And Methods Of Manufacturing The Same - An Enhancement-mode (E-mode) high electron mobility transistor (HEMT) includes a channel layer with a 2-Dimensional Electron Gas (2DEG), a barrier layer inducing the 2DEG in the channel layer, source and drain electrodes on the barrier layer, a depletion layer on the barrier layer between the source and drain electrodes, and a gate electrode on the depletion layer. The barrier layer is recessed below the gate electrode and the depletion layer covers a surface of the recess and extends onto the barrier layer around the recess. | 05-10-2012 |
| 20120112203 | GROUP-III NITRIDE SEMICONDUCTOR DEVICE, METHOD FOR FABRICATING GROUP-III NITRIDE SEMICONDUCTOR DEVICE, AND EPITAXIAL SUBSTRATE - Provided is a Group III nitride semiconductor device, which comprises an electrically conductive substrate including a primary surface comprised of a first gallium nitride based semiconductor, and a Group III nitride semiconductor region including a first p-type gallium nitride based semiconductor layer and provided on the primary surface. The primary surface of the substrate is inclined at an angle in the range of not less than 50 degrees, and less than 130 degrees from a plane perpendicular to a reference axis extending along the c-axis of the first gallium nitride based semiconductor, an oxygen concentration Noxg of the first p-type gallium nitride based semiconductor layer is not more than 5×10 | 05-10-2012 |
| 20120112204 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND EPITAXIAL SUBSTRATE - For a nitride semiconductor light emitting device, a c-axis vector of hexagonal GaN of a support substrate is inclined to an X-axis direction with respect to a normal axis Nx normal to a primary surface. In a semiconductor region an active layer, a first gallium nitride-based semiconductor layer, an electron block layer, and a second gallium nitride-based semiconductor layer are arranged along the normal axis on the primary surface of the support substrate. A p-type cladding layer is comprised of AlGaN, and the electron block layer is comprised of AlGaN. The electron block layer is subject to tensile strain in the X-axis direction. The first gallium nitride-based semiconductor layer is subject to compressive strain in the X-axis direction. The misfit dislocation density at an interface is smaller than that at an interface. A barrier to electrons at the interface is raised by piezoelectric polarization. | 05-10-2012 |
| 20120112205 | SEMICONDUCTOR STRUCTURES AND DEVICES INCLUDING SEMICONDUCTOR MATERIAL ON A NON-GLASSY BONDING LAYER - Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material. | 05-10-2012 |
| 20120119218 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE USING SELECTIVE EPITAXY OF GROUP III-NITRIDE - A method for forming a single crystalline Group-III Nitride film. A substrate is provided, having a first passivation layer, a monocrystalline layer, and a second passivation layer. The substrate is patterned to form a plurality of features with elongated sidewalls having a second crystal orientation. Group-III Nitride films are formed on the elongated sidewalls, but not on the first or second passivation layers. In one embodiment, the dimensions of the patterned features and the film deposition process result in a single crystalline Group-III Nitride film having a third crystal orientation normal to the substrate surface. In another embodiment, the dimensions and orientation of the patterned features and the film deposition process result in a plurality of single crystalline Group-III Nitride films. In other embodiments, additional layers are formed on the Group-III Nitride film or films to form semiconductor devices, for example, a light-emitting diode. | 05-17-2012 |
| 20120119219 | NITRIDE SEMICONDUCTOR ELEMENT AND NITRIDE SEMICONDUCTOR PACKAGE - A nitride semiconductor element capable of accommodating GaN electron transfer layers of a wide range of thickness, so as to allow greater freedom of device design, and a nitride semiconductor element package with excellent voltage tolerance performance and reliability are provided. On a substrate ( | 05-17-2012 |
| 20120119220 | NITRIDE SEMICONDUCTOR STRUCTURE - A nitride semiconductor substrate includes an epitaxy substrate, a patterned nitride semiconductor pillar layer, a nitride semiconductor layer, and a mask layer is provided. The nitride semiconductor pillar layer includes a plurality of first patterned arranged hollow structures and a plurality of second patterned arranged hollow structures formed among the first patterned arranged hollow structures. The second patterned arranged hollow structures have nano dimensions. The nitride semiconductor pillar layer is formed on the epitaxy substrate, and the nitride semiconductor layer is formed on the nitride semiconductor pillar layer. The mask layer covers surfaces of the nitride semiconductor pillar layer and the epitaxy substrate. | 05-17-2012 |
| 20120119221 | SEMICONDUCTOR LIGHT EMITTING DEVICES INCLUDING FLEXIBLE UNITARY FILM ON ALUMINUM NITRIDE SUBSTRATE - Semiconductor light emitting devices include an aluminum nitride substrate, a light emitting diode on a face of the substrate and flexible silicone film that includes a silicone lens on the face of the substrate. The light emitting diode emits light through the silicone lens. | 05-17-2012 |
| 20120119222 | TECHNIQUE FOR THE GROWTH OF PLANAR SEMI-POLAR GALLIUM NITRIDE - A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {10 | 05-17-2012 |
| 20120119223 | Gallium Nitride Semiconductor Structures with Compositionally-Graded Transition Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 05-17-2012 |
| 20120126239 | LAYER STRUCTURES FOR CONTROLLING STRESS OF HETEROEPITAXIALLY GROWN III-NITRIDE LAYERS - A III-N layer structure is described that includes a III-N buffer layer on a foreign substrate, an additional III-N layer, a first III-N structure, and a second III-N layer structure. The first III-N structure atop the III-N buffer layer includes at least two III-N layers, each having an aluminum composition, and the III-N layer of the two III-N layers that is closer to the III-N buffer layer having the larger aluminum composition. The second III-N structure includes a III-N superlattice, the III-N superlattice including at least two III-N well layers interleaved with at least two III-N barrier layer. The first III-N structure and the second III-N structure are between the additional III-N layer and the foreign substrate. | 05-24-2012 |
| 20120126240 | Wafer level packaged GaN power device and the manufacturing method thereof - Disclosed are a GaN-based compound power semiconductor device and a manufacturing method thereof, in which on a GaN power semiconductor element, a contact pad is formed for flip-chip bonding, and a bonding pad of a module substrate to be mounted with the GaN power semiconductor element is formed with a bump so as to modularize an individual semiconductor element. In the disclosed GaN-based compound power semiconductor device, an AlGaN HEMT element is flip-chip bonded to the substrate, so that heat generated from the element can be efficiently radiated. | 05-24-2012 |
| 20120126241 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND PRODUCTION METHOD THEREFOR - A Group III nitride semiconductor light-emitting device includes a sapphire substrate having an embossment on a surface thereof; and an n-type layer, a light-emitting layer, and a p-type layer, which are sequentially stacked on the embossed surface of the sapphire substrate via a buffer layer, and each of which is formed of a Group HI nitride semiconductor. The embossment has a structure including a first stripe-pattern embossment which is formed on a surface of the sapphire substrate, and whose stripe direction corresponds to the x-axis direction; and a second stripe-pattern embossment which is formed atop the first stripe-pattern embossment, and whose stripe direction corresponds to the y-axis direction, the y-axis direction being orthogonal to the x-axis direction. | 05-24-2012 |
| 20120126242 | LIGHT EMITTING DEVICE AND LIGHTING APPARATUS - Provided are a light emitting device, a light emitting device package, and a lighting apparatus. The light emitting device includes: an n-type semiconductor layer including a first area and a second area in a plane; an n-type contact layer disposed on the n-type semiconductor layer and has a first thickness in the first area and a second thickness in the second area; an undoped semiconductor layer disposed on the n-type contact layer having the first thickness in the first area; an active layer disposed on the undoped semiconductor layer in the first area; a p-type semiconductor layer disposed on the active layer in the first area; a first electrode disposed on the n-type contact layer having the second thickness in the second area; and a second electrode disposed on the p-type semiconductor layer. | 05-24-2012 |
| 20120132921 | REDUCING WAFER DISTORTION THROUGH A HIGH CTE LAYER - Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon ( | 05-31-2012 |
| 20120132922 | COMPOSITE SUBSTRATE WITH CRYSTALLINE SEED LAYER AND CARRIER LAYER WITH A COINCIDENT CLEAVAGE PLANE - A structure and a method can provide a crystalline seed layer material, such as GaN, on a crystalline carrier material, such as sapphire, aligned such that a common crystal plane exists between the two materials. The common crystal plane may provide for a fracture surface along a cleavage plane that may be oriented to be perpendicular to the top surface of an optoelectronic device as well as perpendicular to a light emission direction. | 05-31-2012 |
| 20120138945 | REDUCING WAFER DISTORTION THROUGH A LOW CTE LAYER - Provided is a method of fabricating a semiconductor device. The method includes forming a first layer on a first side of a first silicon wafer. The first silicon wafer has a second side opposite the first side. The first layer has a coefficient-of-thermal-expansion (CTE) that is lower than that of silicon. The method includes bonding the first wafer to a second silicon wafer in a manner so that the first layer is disposed in between the first and second silicon wafers. The method includes removing a portion of the first silicon wafer from the second side. The method includes forming a second layer over the second side of the first silicon wafer. The second layer has a CTE higher than that of silicon. | 06-07-2012 |
| 20120138946 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a cooler having a main surface constructed of a metal base, joined layers fixed on the metal base through joining layers, insulating layers fixed on the joined layers and which contain an organic resin as a base material, metal layers provided on the insulating layers, and semiconductor elements provided on the metal layers. A stacked structure with the joined layers, the insulating layers, and the metal layers is divided into parts containing one or the plurality of semiconductor elements, and is fixed through the joining layers on the metal base. | 06-07-2012 |
| 20120138947 | Epitaxial Structure With An Epitaxial Defect Barrier Layer And Methods Making The Same - An epitaxial structure for an LED is provided. The epitaxial structure includes a patterned epitaxial defect barrier layer disposed over a first portion of a substantially flat substrate to expose a second portion of the substrate. The epitaxial structure also includes a patterned buffer layer over the second portion of the substrate. The epitaxial structure further includes a first semiconductor layer over the patterned buffer layer and the patterned epitaxial defect barrier layer, an active layer over the first semiconductor layer, and a second semiconductor layer over the active layer. | 06-07-2012 |
| 20120138948 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device includes: an electron transport layer formed over a substrate; an electron supply layer formed over the electron transport layer; and a cap layer formed over the electron supply layer; the cap layer includes a first compound semiconductor layer containing GaN; a second compound semiconductor layer containing AlN, which is formed over the first compound semiconductor layer; a third compound semiconductor layer containing GaN, which is formed over the second compound semiconductor layer; and at least one of a first AlGaN-containing layer and a second AlGaN-containing layer, with the first AlGaN-containing layer formed between the first compound semiconductor layer and the second compound semiconductor layer and the Al content increases toward the second compound semiconductor layer, and the second AlGaN-containing layer formed between the second compound semiconductor layer and the third compound semiconductor layer and the Al content increases toward the second compound semiconductor layer. | 06-07-2012 |
| 20120138949 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device including a substrate, a first buffer layer disposed on the substrate, the first buffer layer comprising aluminum nitride (AlN), an insertion layer disposed on the first buffer layer, the insertion layer comprising aluminum (Al), and a light emitting structure disposed on the insertion layer, the light emitting structure comprising a first semiconductor layer, a second semiconductor layer, and an active layer interposed between the first semiconductor layer and the second semiconductor layer. | 06-07-2012 |
| 20120138950 | ISLAND MATRIXED GALLIUM NITRIDE MICROWAVE AND POWER SWITCHING TRANSISTORS - A gallium nitride (GaN) device that has greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The layout scheme, which uses island electrodes rather than finger electrodes, is shown to increase the active area density over that of conventional interdigitated structures. Ultra low on resistance transistors can be built using the island topology. Specifically, the present invention, which uses conventional GaN lateral technology and electrode spacing, provides a means to enhance cost/effective performance of all lateral GaN structures. | 06-07-2012 |
| 20120138951 | SEMICONDUCTOR CHIP AND PROCESS FOR PRODUCTION THEREOF - A semiconductor chip of the present invention is a semiconductor device that includes a hexagonal semiconductor layer having anisotropic mechanical properties. A semiconductor chip ( | 06-07-2012 |
| 20120138952 | HIGH PRESSURE CHEMICAL VAPOR DEPOSITION APPARATUSES, METHODS, AND COMPOSITIONS PRODUCED THEREWITH - A composition, reactor apparatus, method, and control system for growing epitaxial layers of group III-nitride alloys. Super-atmospheric pressure is used as a process parameter to control the epitaxial layer growth where the identity of alloy layers differ within a heterostructure stack of two or more layers. | 06-07-2012 |
| 20120146044 | Optoelectronic Semiconductor Chip and Method for Producing an Optoelectronic Semiconductor Chip - In at least one embodiment of the optoelectronic semiconductor chip ( | 06-14-2012 |
| 20120146045 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a light emitting layer, a light transmitting layer and a first semiconductor layer. The light transmitting layer is transmittable with respect to light emitted from the light emitting layer. The first semiconductor layer contacts the light transmitting layer between the light emitting layer and the light transmitting layer. The light transmitting layer has a thermal expansion coefficient larger than a thermal expansion coefficient of the light transmitting layer, has a lattice constant smaller than a lattice constant of the active layer, and has a tensile stress in an in-plane direction. | 06-14-2012 |
| 20120146046 | SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a gate recess formed by removing at least a portion of the second semiconductor layer, an insulation film formed on the gate recess and the second semiconductor layer, a gate electrode formed on the gate recess via the insulation film, source and drain electrodes formed on one of the first and the second semiconductor layers, and a fluorine containing region formed in at least one of a part of the first semiconductor layer corresponding to a region in which the gate recess is formed and a part of the second semiconductor layer corresponding to the region in which the gate recess is formed. | 06-14-2012 |
| 20120146047 | P-CONTACT AND LIGHT-EMITTING DIODE FOR THE ULTRAVIOLET SPECTRAL RANGE - The present invention relates to a p-doped contact for use in a light-emitting diode for the ultraviolet spectral range, comprising a p-contact layer having a first surface for contacting a radiation zone and a second surface comprising, on the side facing away from the first surface: a) a coating, which directly contacts 5%-99.99% of the second surface of the p-contact layer and contains or consists of a material having a maximum reflectivity of at least 60% for light with a wavelength of 200 nm to 400 nm; b) a plurality of p-injectors, which are disposed directly on the second surface of the p-contact layer. | 06-14-2012 |
| 20120146048 | GALLIUM NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE - Provided is a gallium nitride-based compound semiconductor light-emitting element, in which the concentration of Mg which is a p-type dopant in a p-GaN layer in which the (10-10) m-plane of a hexagonal wurtzite structure grows is adjusted in a range from 1.0×10 | 06-14-2012 |
| 20120146049 | JFET DEVICES WITH INCREASED BARRIER HEIGHT AND METHODS OF MAKING THE SAME - Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET. | 06-14-2012 |
| 20120153294 | Semiconductor Structures Having Directly Bonded Diamond Heat Sinks and Methods for Making Such Structures - A semiconductor structure is bonded directly to a diamond substrate by Van der Waal forces. The diamond substrate is formed by polishing a surface of diamond to a first degree of smoothness; forming a material, such as diamond, BeO, GaN, MgO, or SiO | 06-21-2012 |
| 20120153295 | IONIC JUNCTION FOR RADIATION DETECTORS - Radiation detector. The detector includes an ionic junction having an ionically bonded wide band gap material having a first region dominated by positively charged ionic defects in intimate contact with a second region dominated by negatively charged ionic defects forming depleted regions on both sides of the junction resulting in a built-in electric field. The detector also includes an ionic junction having a first ionically bonded wide band gap material dominated by positively charged ionic defects in intimate contact with a second ionically bonded wide band gap material dominated by negatively charged ionic defects forming depleted regions on both sides of the junction resulting in a built-in electric field. Circuit means are provided to establish a voltage across the junction so that radiation impinging upon the junction will cause a current to flow in the circuit. | 06-21-2012 |
| 20120153296 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE SEMICONDUCTOR DEVICE - A semiconductor device, a method of manufacturing the semiconductor device, and an electronic device including the semiconductor device are provided. The semiconductor device includes a silicon substrate; a plurality of nanorods formed on the silicon substrate; and a nitride semiconductor layer formed on the silicon substrate and the plurality of nanorods, wherein a plurality of voids are formed between the silicon substrate and the nitride semiconductor in regions between the plurality of nanorods. | 06-21-2012 |
| 20120153297 | OHMIC CATHODE ELECTRODE ON THE BACKSIDE OF NONPOLAR M-PLANE (1-100) AND SEMIPOLAR (20-21) BULK GALLIUM NITRIDE SUBSTRATES - Ohmic cathode electrodes are formed on the backside of nonpolar m-plane (1-100) and semipolar (20-21) bulk gallium nitride (GaN) substrates. The GaN substrates are thinned using a mechanical polishing process. For m-plane GaN, after the thinning process, dry etching is performed, followed by metal deposition, resulting in ohmic I-V characteristics for the contact. For (20-21) GaN, after the thinning process, dry etching is performed, followed by metal deposition, followed by annealing, resulting in ohmic I-V characteristics for the contact as well. | 06-21-2012 |
| 20120161146 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention includes a semiconductor substrate, a gate electrode which is provided on the semiconductor substrate, a source electrode and a drain elect rode which are provided on the semiconductor substrate to sandwich the gate electrode, and a recess provided below edges of the gate electrode at least on a drain electrode side. | 06-28-2012 |
| 20120161147 | HIGH TEMPERATURE STRAIN SENSOR - An example sensor that includes a first Schottky diode, a second Schottky diode and an integrated circuit. The sensor further includes a voltage generator that generates a first voltage across the first Schottky diode and a second voltage across the second Schottky diode. When the first Schottky diode and the second Schottky diode are subjected to different strain, the integrated circuit measures the values of the currents flowing through the first Schottky diode and the second Schottky diode to determine the strain on an element where the first Schottky diode and the second Schottky diode are attached. | 06-28-2012 |
| 20120161148 | NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes a base material, a patterned nitride semiconductor, a protection layer, and a nitride semiconductor layer. The patterned nitride semiconductor layer is located on the base material and includes a plurality of nanorod structures and a plurality of block patterns, and an upper surface of the nanorod structures is substantially coplanar with an upper surface of the block patterns. The protection layer covers a side wall of the nanorod structure sand a side wall of the block patterns. The nitride semiconductor layer is located on the patterned nitride semiconductor layer, and a plurality of nanopores are located between the nitride semiconductor layer and the patterned nitride semiconductor layer. | 06-28-2012 |
| 20120161149 | INTERMEDIATE EPITAXIAL STRUCTURE AND METHOD FOR FABRICATING AN EPITAXIAL STRUCTURE - A method for fabricating an epitaxial structure includes: (a) forming over a temporary substrate a patterned sacrificial layer that partially exposes the temporary substrate; (b) growing laterally and epitaxially a temporary epitaxial film over the patterned sacrificial layer and the temporary substrate; (c) forming over the temporary epitaxial film an etching-stop layer; (d) forming an epitaxial layer unit over the etching-stop layer; (e) removing the patterned sacrificial layer using a first etchant; and (f) removing the temporary epitaxial film using a second etchant. | 06-28-2012 |
| 20120161150 | METHOD FOR DETERMINING THE STRUCTURE OF A TRANSISTOR - A method for determining the structure of a transistor having at least one first layer including GaN, one second layer including Al | 06-28-2012 |
| 20120161151 | SOLID STATE LIGHTING DEVICES AND ASSOCIATED METHODS OF MANUFACTURING - Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (GaN) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (InGaN) material directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN, and P-type GaN materials has a non-planar surface. | 06-28-2012 |
| 20120161152 | EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE - Provided is a crack-free epitaxial substrate having a small amount of warping, in which a silicon substrate is used as a base substrate. The epitaxial substrate includes a (111) single crystal Si substrate, a buffer layer, and a crystal layer. The buffer layer is formed of a first lamination unit and a second lamination unit being alternately laminated. The first lamination unit includes a composition modulation layer and a first intermediate layer. The composition modulation layer is formed of a first unit layer and a second unit layer having different compositions being alternately and repeatedly laminated so that a compressive strain exists therein. The first intermediate layer enhances the compressive strain existing in the composition modulation layer. The second lamination unit is a second intermediate layer that is substantially strain-free. | 06-28-2012 |
| 20120161153 | SEMICONDUCTOR DEVICE - A semiconductor device of one embodiment, including the semiconductor layer including a III-V group nitride semiconductor; a groove portion formed in the semiconductor layer; the gate insulating film formed at least on a bottom surface of the groove portion, the gate insulating film being a stacked film of a first insulating film and a second insulating film of which dielectric constant is higher than that of the first insulating film; the gate electrode formed on the gate insulating film; and a source electrode and a drain electrode formed on the semiconductor layer across the gate electrode, in which the second insulating film is selectively formed only under the gate electrode. | 06-28-2012 |
| 20120168766 | LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) WITH TAPERED DIELECTRIC PLATES TO ACHIEVE A HIGH DRAIN-TO-BODY BREAKDOWN VOLTAGE, A METHOD OF FORMING THE TRANSISTOR AND A PROGRAM STORAGE DEVICE FOR DESIGNING THE TRANSISTOR - A lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) with a high drain-to-body breakdown voltage (Vb) incorporates gate structure extensions on opposing sides of a drain drift region. The extensions are tapered such that a distance between each extension and the drift region increases linearly from one end adjacent to the channel region to another end adjacent to the drain region. In one embodiment, these extensions can extend vertically through the isolation region that surrounds the LEDMOSFET. In another embodiment, the extensions can sit atop the isolation region. In either case, the extensions create a strong essentially uniform horizontal electric field profile within the drain drift. Also disclosed are a method for forming the LEDMOSFET with a specific Vb by defining the dimensions of the extensions and a program storage device for designing the LEDMOSFET to have a specific Vb. | 07-05-2012 |
| 20120168767 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of floating regions, an insulating layer and a capacitance forming portion. The plurality of floating regions are arranged on a surface of a semiconductor substrate in a row, wherein the plurality of floating regions are provided with insulating regions therebetween. The plurality of floating regions include a first floating region and a second floating region. The second floating region is located farther than the first floating region from an island region of a predetermined potential on the semiconductor substrate. The insulating layer is interposed between each of the plurality of floating regions and a semiconductor material layer of the semiconductor substrate. The capacitance forming portion forms an external capacitance in parallel with the capacitance of the insulating region between the first floating region and the island region of the predetermined potential. | 07-05-2012 |
| 20120168768 | SEMICONDUCTOR STRUCTURES AND METHOD FOR FABRICATING THE SAME - A semiconductor structure is provided. The semiconductor structure includes: a substrate; one or more semiconductor device layers formed on the substrate; and one or more lattice breaking areas formed on the surface of the substrate between the semiconductor device layers. The invention also provides a method for fabricating a semiconductor structure. | 07-05-2012 |
| 20120168769 | METHOD OF MANUFACTURING LIGHT EMITTING DIODE AND LIGHT EMITTING DIODE MANUFACTURED THEREBY - There is provided a method of manufacturing a light emitting diode and a light emitting diode manufactured by the same. The method includes growing a first conductivity type nitride semiconductor layer and an undoped nitride semiconductor layer on a substrate sequentially in a first reaction chamber; transferring the substrate having the first conductivity type nitride semiconductor layer and the undoped nitride semiconductor layer grown thereon to a second reaction chamber; growing an additional first conductivity type nitride semiconductor layer on the undoped nitride semiconductor layer in the second reaction chamber; growing an active layer on the additional first conductivity type nitride semiconductor layer; and growing a second conductivity type nitride semiconductor layer on the active layer. | 07-05-2012 |
| 20120168770 | HEAT DISSIPATION STRUCTURE OF CHIP - A heat dissipation structure of a chip in the field of microelectronics is provided. The heat dissipation structure includes a P-type superlattice layer and an N-type superlattice layer formed over an upper surface of the chip by oxidation isolation. The P-type superlattice and the N-type superlattice are isolated by silicon oxide. Through a contact hole the P-type superlattice is electrically connected to a metal layer that is applied with a low potential in the chip, and a metal layer to be connected with an external power source is formed over the P-type superlattice. Through a contact hole the N-type superlattice is electrically connected to a metal layer that is applied with a high-potential power source in the chip, and a metal layer to be connected with an external power source is formed over the N-type superlattice. The potential of the external power source connected with the P-type superlattice is lower than that of the external power source connected with the N-type superlattice. The present invention can achieve heat dissipation of the chip and meanwhile prevent the ambient heat from transferring into the chip, by using the feature that the superlattice has a low thermal conductivity and phonon-localization-like behavior. | 07-05-2012 |
| 20120168771 | SEMICONDUCTOR ELEMENT, HEMT ELEMENT, AND METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT - A semiconductor device is provided such that a reverse leak current is suppressed, and a Schottky junction is reinforced. The semiconductor device includes an epitaxial substrate formed by laminating a group of group-III nitride layers on a base substrate in such a manner that (0001) surfaces of said group-III nitride layers are substantially parallel to a substrate surface, and a Schottky electrode, in which the epitaxial substrate includes a channel layer formed of a first group-III nitride having a composition of In | 07-05-2012 |
| 20120168772 | PASSIVATION OF ALUMINUM NITRIDE SUBSTRATES - The present invention provides methods of protecting a surface of an aluminum nitride substrate. The substrate with the protected surface can be stored for a period of time and easily activated to be in a condition ready for thin film growth or other processing. In certain embodiments, the method of protecting the substrate surface comprises forming a passivating layer on at least a portion of the substrate surface by performing a wet etch, which can comprise the use of one or more organic compounds and one or more acids. The invention also provides aluminum nitride substrates having passivated surfaces. | 07-05-2012 |
| 20120175628 | LIGHT EMITTING DIODES AND METHOD FOR MANUFACTURING THE SAME - An exemplary LED includes an electrode layer, an LED die, a transparent electrically conductive layer, and an electrically insulating layer. The electrode layer includes a first section and a second section electrically insulated from the first section. The LED die is arranged on and electrically connected to the second section of the electrode layer. The transparent electrically conductive layer is formed on the LED die and electrically connects the LED die to the first section of the electrode layer. The electrically insulating layer is located between the LED die and the transparent electrically conductive layer to insulate the transparent electrically conductive layer from the second section of the electrode layer. | 07-12-2012 |
| 20120175629 | SEMICONDUCTOR EPITAXIAL STRUCTURE - A semiconductor epitaxial structure is provided. The semiconductor epitaxial structure includes a substrate, a doped semiconductor epitaxial layer, and a carbon nanotube layer. The doped semiconductor epitaxial layer is located on the substrate. The carbon nanotube layer is located between the substrate and the doped semiconductor epitaxial layer. The carbon nanotube layer can be a carbon nanotube film drawn from a carbon nanotube array and including a plurality of successive and oriented carbon nanotubes joined end-to-end by van der Waals attractive force therebetween. | 07-12-2012 |
| 20120175630 | LIGHT EMITTING DIODES AND METHOD FOR MANUFACTURING THE SAME - An LED comprises an electrode layer comprising a first a second sections electrically insulated from each other; an electrically conductive layer on the second section, an electrically conductive pole protruding from the electrically conductive layer; an LED die comprising an electrically insulating substrate on the electrically conductive layer, and a P-N junction on the electrically insulating substrate, the P-N junction comprising a first electrode and a second electrode, the electrically conductive pole extending through the electrically insulating substrate to electrically connect the first electrode to the second section; a transparent electrically conducting layer on the LED die, the transparent electrically conducting layer electrically connecting the second electrode to the first section; and an electrically insulating layer between the LED die, the electrically conductive layer, and the transparent electrically conducting layer, wherein the electrically insulating layer insulates the transparent electrically conducting layer from the electrically conductive layer and the second section. | 07-12-2012 |
| 20120175631 | ENHANCEMENT MODE GaN HEMT DEVICE WITH GATE SPACER AND METHOD FOR FABRICATING THE SAME - Enhancement-mode GaN devices having a gate spacer, a gate metal material and a gate compound that are self-aligned, and a methods of forming the same. The materials are patterned and etched using a single photo mask, which reduces manufacturing costs. An interface of the gate spacer and the gate compound has lower leakage than the interface of a dielectric film and the gate compound, thereby reducing gate leakage. In addition, an ohmic contact metal layer is used as a field plate to relieve the electric field at a doped III-V gate compound corner towards the drain contact, which leads to lower gate leakage current and improved gate reliability. | 07-12-2012 |
| 20120175632 | LIGHT EMITTING DEVICE - The light emitting device, and corresponding method of manufacture, the light emitting device including a second electrode layer; a second conductive type semiconductor layer formed on the second electrode layer; an active layer formed on the second conductive type semiconductor layer; a first conductive type semiconductor layer formed with a first photonic crystal that includes a mask layer and an air gap formed on the active layer; and a first electrode layer formed on the first conductive type semiconductor layer. | 07-12-2012 |
| 20120175633 | NITRIDE SEMICONDUCTOR SUBSTRATE - A nitride semiconductor substrate is featured in comprising: a GaN semiconductor layer grown on a base layer, which has a substantially triangular cross-section along the thickness direction thereof, a periodic stripe shapes, and uneven surfaces arranged on the stripes inclined surfaces; and an overgrown layer composed of AlGaN or InAlGaN on the GaN semiconductor layer. | 07-12-2012 |
| 20120181546 | LIGHT-EMITTING DIODE - A light-emitting diode includes a first electrode, a conductive substrate layer, a reflective layer, a first electrical semiconductor layer, a active layer, a second electrical semiconductor layer, and at least one second electrode. The conductive substrate layer is formed on the first electrode. The reflective layer is formed on the conductive substrate layer. The first electrical semiconductor layer is formed on the reflective layer. The active layer is formed on the first electrical semiconductor layer. The second electrical semiconductor layer is formed on the active layer. The at least one second electrode is formed on the second electrical semiconductor layer. At least one third electrode is additionally disposed under the second electrical semiconductor layer. At least one connection channel is disposed between the second electrode and the third electrode, so that the second electrode and the third electrode are electrically connected. | 07-19-2012 |
| 20120181547 | HIGH VOLTAGE SWITCHING DEVICES AND PROCESS FOR FORMING SAME - The present invention relates to various switching device structures including Schottky diode, P-N diode, and P-I-N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm | 07-19-2012 |
| 20120181548 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - There are provided a high current semiconductor device that has low on-resistance, high mobility, and good pinch-off characteristics and in which a kink phenomenon is not easily caused even if a drain voltage is increased, and a method for producing the semiconductor device. The semiconductor device of the present invention includes a GaN-based layered body | 07-19-2012 |
| 20120187412 | Gallium-Nitride-on-Handle Substrate Materials and Devices and Method of Manufacture - A gallium and nitrogen containing substrate structure includes a handle substrate member having a first surface and a second surface and a transferred thickness of gallium and nitrogen material. The structure has a gallium and nitrogen containing active region grown overlying the transferred thickness and a recessed region formed within a portion of the handle substrate member. The substrate structure has a conductive material formed within the recessed region configured to transfer thermal energy from at least the transferred thickness of gallium and nitrogen material. | 07-26-2012 |
| 20120187413 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nitride semiconductor device includes a first semiconductor, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a first electrode, a second electrode and a third electrode. The first, second and fourth semiconductor layers include a nitride semiconductor. The second semiconductor layer is provided on the first semiconductor layer, has a band gap not less than that of the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer. The third semiconductor layer is GaN. The fourth semiconductor layer is provided on the third semiconductor layer to have an interspace on a part of the third semiconductor layer, has a band gap not less than that of the second semiconductor layer. The first electrode is provided on a portion of the third semiconductor layer. The fourth semiconductor layer is not provided on the portion. | 07-26-2012 |
| 20120187414 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND PROCESS FOR PRODUCTION THEREOF - One aspect of the present invention provides a semiconductor light-emitting device improved in luminance, and also provides a process for production thereof. The process comprises a procedure of forming a relief structure on the light-extraction surface of the device by use of a self-assembled film. In that procedure, the light-extraction surface is partly covered with a protective film so as to protect an area for an electrode to be formed therein. The electrode is then finally formed there after the procedure. The process thus reduces the area incapable, due to thickness of the electrode, of being provided with the relief structure. Between the electrode and the light-extraction surface, a contact layer is formed so as to establish ohmic contact between them. | 07-26-2012 |
| 20120187415 | METHOD FOR CONDUCTIVITY CONTROL OF (Al,In,Ga,B)N - A method of controlled p-type conductivity in (Al,In,Ga,B)N semiconductor crystals. Examples include {10 | 07-26-2012 |
| 20120193636 | Very high transmittance, back-illuminated, silicon-on-sapphire semiconductor wafer substrate for high quantum efficiency and high resolution, solid-state, imaging focal plane arrays - An advanced, very high transmittance, back-illuminated, silicon-on-sapphire wafer substrate design is presented for enabling high quantum efficiency and high resolution, silicon or silicon-germanium avalanche photodiode detector arrays. The wafer substrate incorporates a stacked antireflective bilayer between the sapphire and silicon layers, comprised of single crystal aluminum nitride (AlN) and non-stoichiometric, silicon rich, amorphous silicon nitride (a-SiN | 08-02-2012 |
| 20120193637 | LOW GATE-LEAKAGE STRUCTURE AND METHOD FOR GALLIUM NITRIDE ENHANCEMENT MODE TRANSISTOR - The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; and a gate stack disposed on the AlGaN layer. The gate stack includes a III-V compound n-type doped layer; a III-V compound p-type doped layer adjacent the III-V compound n-type doped layer; and a metal layer formed over the III-V compound p-type doped layer and the III-V compound n-type doped layer. | 08-02-2012 |
| 20120193638 | METHOD FOR HETEROEPITAXIAL GROWTH OF HIGH-QUALITY N-FACE GaN, InN, AND AIN AND THEIR ALLOYS BY METAL ORGANIC CHEMICAL VAPOR DEPOSITION - Methods for the heteroepitaxial growth of smooth, high quality films of N-face GaN film grown by MOCVD are disclosed. Use of a misoriented substrate and possibly nitridizing the substrate allow for the growth of smooth N-face GaN and other Group III nitride films as disclosed herein. The present invention also avoids the typical large (μm sized) hexagonal features which make N-face GaN material unacceptable for device applications. The present invention allows for the growth of smooth, high quality films which makes the development of N-face devices possible. | 08-02-2012 |
| 20120193639 | GaN-BASED SEMICONDUCTOR ELEMENT - A GaN-based semiconductor element includes a substrate, a buffer layer formed on the substrate, including an electrically conductive portion, an epitaxial layer formed on the buffer layer, and a metal structure in ohmic contact with the electrically conductive portion of the buffer layer for controlling an electric potential of the buffer layer. | 08-02-2012 |
| 20120199841 | Gallium and Nitrogen Containing Trilateral Configuration for Optical Devices - Techniques for manufacturing optical devices, such as light emitting diodes (LEDs) using a separation process of thick gallium and nitrogen containing substrate members, are described. | 08-09-2012 |
| 20120199842 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A highly integrated DRAM is provided. A bit line is formed over a first insulator, a second insulator is formed over the bit line, third insulators which are in a stripe shape and the like are formed over the second insulator, and a semiconductor region and a gate insulator are formed to cover one of the third insulators. The bit line is connected to the semiconductor region through first contact plugs. Then, a conductive film is formed and subjected to anisotropic etching to form word lines at side surfaces of the third insulators, and a second contact plug is formed to be connected to a capacitor at a top of the one of the third insulators. By synchronizing the word lines, electric charge is accumulated or released through the capacitor. With such a structure, the area of a memory cell can be 4F | 08-09-2012 |
| 20120199843 | HIGH REFLECTIVE BOARD OR SUBSTRATE FOR LEDS - Light emitting devices and methods are disclosed that provide improved light output. The devices have an LED mounted to a substrate, board or submount characterized by improved reflectivity, which reduces the absorption of LED light. This increases the amount of light that can emit from the LED device. The LED devices also exhibit improved emission characteristics by having a reflective coating on the submount that is substantially non-yellowing. One embodiment of a light emitting device according to the present invention comprises a submount having a circuit layer. A reflective coating is included between at least some of the elements of the circuit layer. A light emitting diode mounted to the circuit layer, the reflective coating being reflective to the light emitted by the light emitting diode. In some embodiments, the reflective coating comprises a carrier with scattering particles having a different index of refraction than said carrier material. | 08-09-2012 |
| 20120199844 | NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride-based semiconductor device according to the present disclosure includes a nitride-based semiconductor multilayer structure | 08-09-2012 |
| 20120205661 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a supporting substrate, a conductive layer placed on the supporting substrate, and at least one group III nitride semiconductor layer placed on the conductive layer. Of the group III nitride semiconductor layers, a conductive-layer-neighboring group III nitride semiconductor layer has n type conductivity, dislocation density of at most 1×10 | 08-16-2012 |
| 20120205662 | SEMICONDUCTOR DEVICE, POWER SUPPLY DEVICE, AMPLIFIER, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor layer formed over a substrate; an insulating film formed over the semiconductor layer; and an electrode formed over the insulating film, wherein the insulating film includes an amorphous film including carbon. | 08-16-2012 |
| 20120205663 | SEMICONDUCTOR DEVICE, POWER-SUPPLY UNIT, AMPLIFIER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device, includes a semiconductor layer formed above a substrate; an insulating film formed on the semiconductor layer; and an electrode formed on the insulating film. The insulating film has a membrane stress at a side of the semiconductor layer lower than a membrane stress at a side of the electrode. | 08-16-2012 |
| 20120205664 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises: an active layer; a first nitride semiconductor layer on the active layer; a first delta-doped layer on the first nitride semiconductor layer; a second nitride semiconductor layer on the first delta-doped layer; a second delta-doped layer on the second nitride semiconductor layer; a third nitride semiconductor layer on the second delta-doped layer. | 08-16-2012 |
| 20120205665 | HIGH-QUALITY NON-POLAR/SEMI-POLAR SEMICONDUCTOR DEVICE ON POROUS NITRIDE SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF - Provided are a high-quality non-polar/semi-polar semiconductor device having reduced defect density of a nitride semiconductor layer and improved internal quantum efficiency and light extraction efficiency, and a manufacturing method thereof. The method for manufacturing a semiconductor device is to form a template layer and a semiconductor device structure on a sapphire, SiC or Si substrate having a crystal plane for a growth of a non-polar or semi-polar nitride semiconductor layer. The manufacturing method includes: forming a nitride semiconductor layer on the substrate; performing a porous surface modification such that the nitride semiconductor layer has pores; forming the template layer by re-growing a nitride semiconductor layer on the surface-modified nitride semiconductor layer; and forming the semiconductor device structure on the template layer. | 08-16-2012 |
| 20120211759 | STRUCTURE AND METHOD TO REDUCE WAFER WARP FOR GALLIUM NITRIDE ON SILICON WAFER - The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions. | 08-23-2012 |
| 20120211760 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND POWER SUPPLY APPARATUS - A semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a p-type nitride semiconductor layer provided over the nitride semiconductor stacked structure and including an active region and an inactive region; an n-type nitride semiconductor layer provided on the inactive region in the p-type nitride semiconductor layer; and a gate electrode provided over the active region in the p-type nitride semiconductor layer. | 08-23-2012 |
| 20120211761 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor layer disposed above a substrate; an insulating film formed by oxidizing a portion of the semiconductor layer; and an electrode disposed on the insulating film, wherein the insulating film includes gallium oxide, or gallium oxide and indium oxide. | 08-23-2012 |
| 20120211762 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND ELECTRONIC CIRCUIT - A semiconductor device includes: a semiconductor chip having an electrode; a lead corresponding to the electrode; a metal line coupling the electrode to the lead; a first resin portion covering a coupling portion between the metal line and the electrode and a coupling portion between the metal line and the lead; and a second resin portion covering the metal line, the first resin portion, and the semiconductor chip. | 08-23-2012 |
| 20120211763 | NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A nitride semiconductor substrate suitable for a normally-off type high breakdown-voltage device and a method of manufacturing the substrate are provided allowing both a higher threshold voltage and improvement in current collapse. | 08-23-2012 |
| 20120211764 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material. | 08-23-2012 |
| 20120211765 | EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT, AND METHOD FOR PRODUCING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT - Provided is an epitaxial substrate using a silicon substrate as a base substrate. An epitaxial substrate, in which a group of group-III nitride layers are formed on a (111) single crystal Si substrate such that a (0001) crystal plane of the group of group-III nitride layers is substantially in parallel with a surface of the substrate, includes: a first group-III nitride layer made of AlN with many defects configured of at least one kind from a columnar or granular crystal or domain; a second group-III nitride layer whose interface with the first group-III nitride layer is shaped into a three-dimensional concave-convex surface; and a third group-III nitride layer epitaxially formed on the second group-III nitride layer as a graded composition layer in which the proportion of existence of Al is smaller in a portion closer to a fourth group-III nitride. | 08-23-2012 |
| 20120211766 | IMAGE DISPLAY DEVICE AND LIGHT EMISSION DEVICE - An image display device including a light emission section which emits light to an intensity adjusting section and a wavelength conversion section which change the intensity and wavelength of the emitted light. Phosphors and phosphor like materials are employed in wavelength conversion and a liquid crystal is employed for the light adjustment. The light emission device may include plural semiconductor light emitting elements having a different wavelength ranges such as diodes stacked in a compact and predetermined order such that wavelengths of light from each diode are emitted from the light emitting elements. | 08-23-2012 |
| 20120217503 | METHOD OF MANUFACTURING GaN POWDER AND NITRIDE-BASED LIGHT EMITTING DEVICE USING GaN POWDER MANUFACTURED BY THE METHOD - Disclosed herein is a method of manufacturing GaN powders using a GaN etching product produced during manufacture of a GaN-based light emitting device. The method includes collecting a GaN etching product produced during etching of the GaN-based light emitting device, cleaning the collected GaN etching product; heating the cleaned GaN etching product to remove indium (In) components from the GaN etching product, and pulverizing the GaN etching product having the indium components removed therefrom into powders. A nitride-based light emitting device using the GaN powders is also disclosed. | 08-30-2012 |
| 20120217504 | NITRIDE BASED LIGHT EMITTING DEVICE USING SILICON SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a nitride-based light emitting device using a silicon substrate. The nitride-based light emitting device includes a silicon (Si) substrate, a seed layer for nitride growth formed on the silicon substrate, and a light emitting structure formed on the seed layer and having a plurality of nitride layers stacked therein. The seed layer for nitride growth is comprised of GaN powders, thereby minimizing occurrence of dislocations caused by a difference in lattice constant between a nitride layer and the silicon substrate. A method of manufacturing the same is also disclosed. | 08-30-2012 |
| 20120217505 | SEMICONDUCTOR DEVICE - A semiconductor device including a field effect transistor having a buffer layer subjected to lattice relaxation, a channel layer, and an electron supply layer formed in this order with group-III nitride semiconductors respectively in a growth mode parallel with a [0001] or [000-1] crystallographic axis over a substrate and having a source electrode and a drain electrode, those being coupled electrically to the channel layer, and a gate electrode formed over the electron supply layer, in which, in the buffer layer and the electron supply layer, a layer existing on the group-III atomic plane side of the channel layer has an A-axis length larger than a layer existing on the group-V atomic plane side of the channel layer; and the electron supply layer has a bandgap larger than the channel layer. | 08-30-2012 |
| 20120217506 | III-Nitride Heterojunction Devices Having a Multilayer Spacer - In accordance with one implementation of the present disclosure, a III-Nitride heterojunction device includes a III-Nitride channel layer, a III-Nitride multilayer spacer situated over the III-Nitride channel layer, and a III-Nitride barrier layer situated over the III-Nitride multilayer spacer. A two-dimensional electron gas (2DEG) is formed near an interface of said III-Nitride Channel layer and said III-Nitride multilayer spacer. The III-Nitride multilayer spacer includes a III-Nitride interlayer. In one implementation, the III-Nitride multilayer spacer includes a III-Nitride polarization layer that is situated over the III-Nitride interlayer. The III-Nitride polarization layer has a higher total polarization than the III-Nitride interlayer, the III-Nitride channel layer, and the III-Nitride barrier layer. | 08-30-2012 |
| 20120217507 | SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a substrate, a semiconductor layer formed above the substrate and including a nitride semiconductor, an electrode formed above the semiconductor layer and including gold, a barrier film formed above the electrode and a protection film formed above the semiconductor layer and including one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The protection film is formed on the barrier film. The barrier film includes a metal oxide material, a metal nitride film, or a metal oxynitride film. | 08-30-2012 |
| 20120217508 | Semiconductor White Light Sources - A semiconductor white light source includes a blue emitting semiconductor; a dispersant material disposed about the blue emitting semiconductor; an ultraviolet emitting semiconductor; and a wavelength shifting medium with maximum excitation in the ultraviolet spectrum disposed about the dispersant material and the ultraviolet emitting semiconductor such that ultraviolet light output by the ultraviolet emitting semiconductor illuminates the wavelength shifting medium directly and blue light output by the blue emitting semiconductor illuminates the wavelength shifting medium after passage of the blue light through the dispersant material. The dispersant material and the wavelength shifting medium are separate materials. The blue emitting semiconductor and the ultraviolet emitting semiconductor are arranged to emit light into a common illumination field. | 08-30-2012 |
| 20120217509 | LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - A light-emitting device comprises a first conductive type semiconductor layer; a second conductive type semiconductor layer under the first conductive type semiconductor layer; an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer; a nonconductive semiconductor layer on the first conductive type semiconductor layer and including a light extraction structure formed in the nonconductive semiconductor layer; a recess disposed from the nonconductive semiconductor layer to an upper portion of the first conductive type semiconductor layer; a first electrode layer on the upper portion of the first conductive type semiconductor layer; a second electrode layer under the second conductive type semiconductor layer. | 08-30-2012 |
| 20120217510 | LIGHT-EMITTING SEMICONDUCTOR DEVICE USING GROUP III NITROGEN COMPOUND - A method of producing a light-emitting semiconductor device of a group III nitride compound includes forming a high carrier concentration N | 08-30-2012 |
| 20120217511 | VERTICAL POWER TRANSISTOR DEVICE, SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING A VERTICAL POWER TRANSISTOR DEVICE - A vertical power transistor device comprises: a substrate formed from a III-V semiconductor material and a multi-layer stack at least partially accommodated in the substrate. The multi-layer stack comprises: a semi-insulating layer disposed adjacent the substrate and a first layer formed from a first III-V semiconductor material and disposed adjacent the semi-insulating layer. The multi-layer stack also comprises a second layer formed from a second III-V semiconductor material disposed adjacent the first layer and a heterojunction is formed at an interface of the first and second layers. | 08-30-2012 |
| 20120217512 | LATERAL POWER TRANSISTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A lateral power transistor device comprises a substrate and a multi-layer mesa structure comprising a heterojunction. A filled trench region is located adjacent the multi-layer mesa structure, the filled trench region being occupied by a metal. | 08-30-2012 |
| 20120223317 | OHMIC CONTACT SCHEMES FOR GROUP III-V DEVICES HAVING A TWO-DIMENSIONAL ELECTRON GAS LAYER - A semiconductor device includes a first layer and a second layer over the first layer. The first and second layers are configured to form an electron gas layer at an interface of the first and second layers. The semiconductor device also includes an Ohmic contact and multiple conductive vias through the second layer. The conductive vias are configured to electrically couple the Ohmic contact to the electron gas layer. The conductive vias could have substantially vertical sidewalls or substantially sloped sidewalls, or the conductive vias could form a nano-textured surface on the Ohmic contact. The first layer could include Group III-nitride nucleation, buffer, and channel layers, and the second layer could include a Group III-nitride barrier layer. | 09-06-2012 |
| 20120223318 | P-CHANNEL FLASH WITH ENHANCED BAND-TO-BAND TUNNELING HOT ELECTRON INJECTION - A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a substrate, forming a layer on the substrate by selective epitaxial growth, on each side of the dummy gate stack, forming spacers on the layer, forming raised source/drains, removing the dummy gate stack, forming a cavity between the spacers, and forming a memory gate stack in the cavity. Different embodiments include forming the layer of a narrow bandgap material, a narrow bandgap layer under the spacers and a wide bandgap layer adjacent thereto, or a wide bandgap layer under the spacers, a narrow bandgap layer adjacent thereto, and a wide bandgap layer on the narrow bandgap layer. | 09-06-2012 |
| 20120223319 | SEMICONDUCTOR DIODES WITH LOW REVERSE BIAS CURRENTS - A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents. | 09-06-2012 |
| 20120223320 | ELECTRODE CONFIGURATIONS FOR SEMICONDUCTOR DEVICES - A III-N semiconductor device can include an electrode-defining layer having a thickness on a surface of a III-N material structure. The electrode-defining layer has a recess with a sidewall, the sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a first width, and a portion of the recess proximal to the III-N material structure has a second width, the first width being larger than the second width. An electrode is in the recess, the electrode including an extending portion over the sidewall of the recess. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The sidewall forms an effective angle of about 40 degrees or less relative to the surface of the III-N material structure. | 09-06-2012 |
| 20120223321 | III-Nitride Transistor Stacked with FET in a Package - One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (FET), such as a silicon FET, stacked atop a III-nitride transistor, such that a drain of the FET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages. | 09-06-2012 |
| 20120223322 | III-Nitride Transistor Stacked with Diode in a Package - One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages. | 09-06-2012 |
| 20120223323 | WAFER, CRYSTAL GROWTH METHOD, AND SEMICONDUCTOR DEVICE - According to one embodiment, a wafer includes a substrate, a base layer, a foundation layer, an intermediate layer and a functional unit. The substrate has a major surface. The base layer is provided on the major surface and includes a silicon compound. The foundation layer is provided on the base layer and includes GaN. The intermediate layer is provided on the foundation layer and includes a layer including AlN. The functional unit is provided on the intermediate layer and includes a nitride semiconductor. The foundation layer has a first region on a side of the base layer, and a second region on a side of the intermediate layer. A concentration of silicon atoms in the first region is higher than a concentration of silicon atoms in the second region. The foundation layer has a plurality of voids provided in the first region. | 09-06-2012 |
| 20120223324 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - An LED includes a substrate, a first n-type GaN layer, a connecting layer, a second n-type GaN layer, a light emitting layer, and a p-type GaN layer. The first n-type GaN layer, the connecting layer, and the second n-type GaN layer are formed on the substrate in sequence. The connecting layer is etchable by alkaline solution, and a bottom surface of the second n-type GaN layer facing towards the connecting layer has a roughed exposed portion. The GaN on the bottom surface of the second n-type GaN layer is N-face GaN. A top surface of the second n-type GaN layer facing away from the connecting layer includes a first area and a second area. The light emitting layer and the p-type GaN layer are formed on the first area of the top surface of the second n-type GaN layer in sequence. | 09-06-2012 |
| 20120223325 | MICROELECRONIC ASSEMBLY WITH AN EMBEDDED WAVEGUIDE ADAPTER AND METHOD FOR FORMING THE SAME - A microelectronic assembly and a method for forming a microelectronic assembly are provided. A semiconductor substrate is provided. The semiconductor substrate has first and second opposing sides and first and second portions. A tuning depression is formed on the second opposing side and the second portion of the semiconductor substrate. A radio frequency conductor is formed on the first opposing side of the first semiconductor substrate. The radio frequency conductor has a first end on the first portion of the first semiconductor substrate and a second end on the second portion of the first semiconductor substrate. A microelectronic die having an integrated circuit formed therein is attached to the first opposing side and the first portion of the semiconductor substrate such that the integrated circuit is electrically connected to the first end of the radio frequency conductor. | 09-06-2012 |
| 20120223326 | LIGHT EMITTING DIODE AND METHOD FOR FABRICATING THE SAME - A light emitting diode and a method for fabricating the same are provided. The light emitting diode includes: a transparent substrate; a semiconductor material layer formed on the top surface of a substrate with an active layer generating light; and a fluorescent layer formed on the back surface of the substrate with controlled varied thicknesses. The ratio of light whose wavelength is shifted while propagating through the fluorescent layer and the original light generated in the active layer can be controlled by adjusting the thickness of the fluorescent layer, to emit desirable homogeneous white light from the light emitting diode. | 09-06-2012 |
| 20120223327 | Programmable Gate III-Nitride Semiconductor Device - A III-nitride semiconductor device which includes a charged gate insulation body. | 09-06-2012 |
| 20120223328 | GROUP III NITRIDE EPITAXIAL LAMINATE SUBSTRATE - A Group III nitride epitaxial laminate substrate comprising a substrate, a buffer and a main laminate in this order, wherein the buffer includes an initial growth layer, a first superlattice laminate and a second superlattice laminate in this order, the first superlattice laminate includes five to 20 sets of first AlN layers and second GaN layers, the first AlN layers and the second GaN layers being alternately stacked, and each one set of the first AlN layer and the second GaN layer has a thickness of less than 44 nm, the second superlattice laminate includes a plurality of sets of first layers made of an AlN material or an AlGaN material and second layers made of an AlGaN material having a different band gap from the first layers, the first and second layers being alternately stacked. | 09-06-2012 |
| 20120223329 | Production Method of a Layered Body - Disclosed is a novel method for group III polarity growth on a sapphire substrate. Specifically disclosed is a method for producing a laminate wherein a group III nitride single crystal layer is laminated on a sapphire substrate by an MOCVD method. The method for producing a laminate comprises: a pretreatment step in which an oxygen source gas is supplied onto the sapphire substrate; a first growth step in which an initial single crystal layer that contains oxygen at a concentration of 5×10 | 09-06-2012 |
| 20120228625 | NITRIDE SEMICONDUCTOR DEVICE - According to one embodiment, a nitride semiconductor device includes a first, a second, a third and a fourth transistor of n-type channel and a resistor. The first transistor has a first gate, a first source, and a first drain. The second transistor has a second gate, a second source electrically connected to the first gate, and a second drain. The third transistor has a third gate, a third source electrically connected to the first source, and a third drain electrically connected to the first gate and the second source. The fourth transistor has a fourth gate electrically connected to the third gate, a fourth source electrically connected to the first source and the third source, and a fourth drain electrically connected to the second gate. The resistor has one end electrically connected to the second drain and one other end electrically connected to the second gate and the fourth drain. | 09-13-2012 |
| 20120228626 | SEMICONDUCTOR DEVICE AND ITS FABRICATION METHOD - In a semiconductor device including a stack structure having heterojunction units formed by alternately stacking GaN (gallium nitride) films and barrier films which are different in forbidden band width, a first electrode formed in a Schottky barrier contact with one sidewall of the stack structure, and a second electrode formed in contact with the other sidewall, an oxide film is interposed between the first electrode and the barrier films. Therefore, the reverse leakage current is prevented from flowing through defects remaining in the barrier films due to processing of the barrier films, so that a reverse leakage current of a Schottky barrier diode is reduced. | 09-13-2012 |
| 20120228627 | METHOD FOR PRODUCING COMPOUND SEMICONDUCTOR CRYSTAL, METHOD FOR PRODUCING ELECTRONIC DEVICE, AND SEMICONDUCTOR WAFER - A method for producing a compound semiconductor crystal, includes; a sacrificial layer formation step of forming a sacrificial layer containing C | 09-13-2012 |
| 20120235156 | NITRIDE SEMICONDUCTOR DEVICE - According to one embodiment, a nitride semiconductor device includes a semiconductor layer, a source electrode, a drain electrode, a first and a second gate electrode. The semiconductor layer includes a nitride semiconductor. The source electrode provided on a major surface of the layer forms ohmic contact with the layer. The drain electrode provided on the major surface forms ohmic contact with the layer and is separated from the source electrode. The first gate electrode is provided on the major surface between the source and drain electrodes. The second gate electrode is provided on the major surface between the source and first gate electrodes. When a potential difference between the source and first gate electrodes is 0 volts, a portion of the layer under the first gate electrode is conductive. The first gate electrode is configured to switch a constant current according to a voltage applied to the second gate electrode. | 09-20-2012 |
| 20120235157 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - An LED includes a substrate, a first n-type GaN layer, a connecting layer, a second n-type GaN layer, a light emitting layer, and a p-type GaN layer formed on the substrate in sequence, the connecting layer being etchable by alkaline solution, a bottom surface of the second n-type GaN layer facing towards the connecting layer having a roughened exposed portion, the GaN on the bottom surface of the second n-type GaN layer having an N-face polarity, a blind hole extending through the p-type GaN layer, the light emitting layer and the second n-type GaN layer to expose the connecting layer, and an annular rough portion formed on the bottom surface of the second n-type GaN layer and surrounding each blind hole. | 09-20-2012 |
| 20120235158 | LIGHT EMITTING DEVICE HAVING A PLURALITY OF NON-POLAR LIGHT EMITTING CELLS AND A METHOD OF FABRICATING THE SAME - The present invention relates to a light emitting device having a plurality of non-polar light emitting cells and a method of fabricating the same. Nitride semiconductor layers are disposed on a Gallium Nitride substrate having an upper surface. The upper surface is a non-polar or semi-polar crystal and forms an intersection angle with respect to a c-plane. The nitride semiconductor layers may be patterned to form light emitting cells separated from one another. When patterning the light emitting cells, the substrate may be partially removed in separation regions between the light emitting cells to form recess regions. The recess regions are filled with an insulating layer, and the substrate is at least partially removed by using the insulating layer. | 09-20-2012 |
| 20120235159 | Group III Nitride Field Effect Transistors (FETS) Capable of Withstanding High Temperature Reverse Bias Test Conditions - Group III Nitride based field effect transistor (FETs) are provided having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (V | 09-20-2012 |
| 20120235160 | Normally-Off Semiconductor Devices - Normally-off semiconductor devices are provided. A Group III-nitride buffer layer is provided. A Group III-nitride barrier layer is provided on the Group III-nitride buffer layer. A non-conducting spacer layer is provided on the Group III-nitride barrier layer. The Group III-nitride barrier layer and the spacer layer are etched to form a trench. The trench extends through the barrier layer and exposes a portion of the buffer layer. A dielectric layer is formed on the spacer layer and in the trench and a gate electrode is formed on the dielectric layer. Related methods of forming semiconductor devices are also provided herein. | 09-20-2012 |
| 20120235161 | GROUP III NITRIDE TEMPLATES AND RELATED HETEROSTRUCTURES, DEVICES, AND METHODS FOR MAKING THEM - A templated substrate includes a base layer, and a template layer is disposed on the base layer and having a composition including a single-crystal Group III nitride. The template layer includes a continuous sublayer on the base layer and a nanocolumnar sublayer on the first sublayer, wherein the nanocolumnar sublayer includes a plurality of nano-scale columns. | 09-20-2012 |
| 20120241751 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a third electrode, a first insulating film and a second insulating film. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer is provided on the first layer, includes a nitride semiconductor, and includes a hole. The first electrode is provided in the hole. The second electrode is provided on the second layer. The third electrode is provided on the second layer so that the first electrode is disposed between the third and second electrodes. The first insulating film is provided between the first electrode and an inner wall of the hole and between the first and second electrodes, and is provided spaced from the third electrode. The second insulating film is provided in contact with the second layer between the first and third electrodes. | 09-27-2012 |
| 20120241752 | LOW CONTACT RESISTANCE SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A low contact resistance semiconductor structure includes a substrate, a semiconductor stacked layer, a low contact resistance layer and a transparent conductive layer. The low contact resistance layer is formed on one side of a P-type GaN layer of the semiconductor stacked layer. The low contact resistance layer is formed at a thickness smaller than 100 Angstroms and made of a material selected from the group consisting of aluminum, gallium, indium, and combinations thereof. Through the low contact resistance layer, the resistance between the P-type GaN layer and transparent conductive layer can be reduced and light emission efficiency can be improved when being used on LEDs. The method of fabricating the low contact resistance semiconductor structure of the invention forms a thin and consistent low contact resistance layer through a Metal Organic Chemical Vapor Deposition (MOCVD) method to enhance matching degree among various layers. | 09-27-2012 |
| 20120241753 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor device includes a substrate, a nitride layer and a nitride semiconductor layer. The substrate includes an indented structure provided at a major surface. The nitride layer provided entirely on the major surface is at least one of polycrystalline and amorphous, and includes at least one of p-type impurity and n-type impurity. The nitride semiconductor layer is provided on the nitride layer. | 09-27-2012 |
| 20120241754 | LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THEREOF - This invention directs to a light-emitting diode. The light-emitting diode includes a substrate, a semiconductor layer and an active layer. The semiconductor layer is disposed on the substrate and has a plurality of undulating structures. The active layer is conformably disposed on the semiconductor layer to have another plurality of undulating structures. | 09-27-2012 |
| 20120241755 | METHOD FOR REDUCING INTERNAL MECHANICAL STRESSES IN A SEMICONDUCTOR STRUCTURE AND A LOW MECHANICAL STRESS SEMICONDUCTOR STRUCTURE - A semiconductor structure with low mechanical stresses, formed of nitrides of group III metals on a (0001) oriented foreign substrate ( | 09-27-2012 |
| 20120241756 | High Voltage Composite Semiconductor Device with Protection for a Low Voltage Device - There are disclosed herein various implementations of composite semiconductor devices including a voltage protected device. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor having a first output capacitance, and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device, the LV device having a second output capacitance. A ratio of the first output capacitance to the second output capacitance is set based on a ratio of a drain voltage of the normally ON III-nitride power transistor to a breakdown voltage of the LV device so as to provide voltage protection for the LV device. | 09-27-2012 |
| 20120241757 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light emitting device and a method of manufacturing the same are disclosed. The light emitting device includes a buffer layer formed on a substrate, a nitride semiconductor layer including a first semiconductor layer, an active layer, and a second semiconductor layer, which are sequentially stacked on the buffer layer, a portion of the first semiconductor layer being exposed to the outside by performing mesa etching from the second semiconductor layer to the portion of the first semiconductor layer, and at least one nanocone formed on the second semiconductor layer. | 09-27-2012 |
| 20120241758 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A compound semiconductor device is provided with a first nitride semiconductor layer of a first conductivity type, a second nitride semiconductor layer of the first conductivity type which is formed over the first nitride semiconctor layer and being in contact with the first nitride semiconductor layer, a third nitride semiconductor layer of a second conductivity type being in contact with the second nitride semiconductor layer, a fourth nitride semiconductor layer of the first conductivity type being in contact with the third nitride semiconductor layer, and an insulating film insulating the first nitride semiconductor layer and the fourth nitride, semiconductor layer from each other. A source electrode is positioned inside an Outer edge of the insulating film in planar view. | 09-27-2012 |
| 20120241759 | NITRIDE SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A nitride semiconductor device having a high withstand voltage and being capable of reducing a leakage current, is provided. The nitride semiconductor device | 09-27-2012 |
| 20120241760 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed is a semiconductor light emitting element ( | 09-27-2012 |
| 20120248456 | NITRIDE SEMICONDUCTOR MULTILAYER STRUCTURE, METHOD FOR PRODUCING SAME, AND NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT - The nitride semiconductor light-emitting element of the invention has a stacked structure of a buffer layer, an n-type nitride semiconductor layer, a light-emitting layer, and a p-type nitride semiconductor layer, on one surface side of a single crystal substrate of a sapphire substrate. A nitride semiconductor multilayer structure as the buffer layer includes: a plurality of island-like nuclei formed of AlN and formed on the one surface of the single crystal substrate; a first nitride semiconductor layer formed of an AlN layer and formed on the one surface side of the single crystal substrate so as to fill gaps between adjacent nuclei and to cover all the nuclei; and a second nitride semiconductor layer formed of an AlN layer and formed on the first nitride semiconductor layer. | 10-04-2012 |
| 20120248457 | GROUP III NITRIDE SEMICONDUCTOR MULTILAYER STRUCTURE AND PRODUCTION METHOD THEREOF - According to the present invention, an AlN crystal film seed layer having high crystallinity is combined with selective/lateral growth, whereby a Group III nitride semiconductor multilayer structure more enhanced in crystallinity can be obtained. The Group III nitride semiconductor multilayer structure of the present invention is a Group III nitride semiconductor multilayer structure where an AlN crystal film having a crystal grain boundary interval of 200 nm or more is formed as a seed layer on a C-plane sapphire substrate surface by a sputtering method and an underlying layer, an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer, each composed of a Group III nitride semiconductor, are further stacked, wherein regions in which the seed layer is present and is absent are formed on the C-plane sapphire substrate surface and/or regions capable of epitaxial growth and incapable of epitaxial growth are formed in the underlying layer. | 10-04-2012 |
| 20120248458 | VERTICALLY STRUCTURED GROUP III NITRIDE SEMICONDUCTOR LED CHIP AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing vertically structured Group III nitride semiconductor LED chips includes a step of forming a light emitting laminate on a growth substrate; a step of forming a plurality of separate light emitting structures by partially removing the light emitting laminate to partially expose the growth substrate; a step of forming a conductive support on the plurality of light emitting structures; a step of lifting off the growth substrate from the plurality of light emitting structures; and a step of cutting the conductive support thereby singulating a plurality of LED chips each having the light emitting structure. The step of partially removing the light emitting laminate is performed such that each of the plurality of light emitting structures has a top view shape of a circle or a 4n-gon en” is a positive integer) having rounded corners. | 10-04-2012 |
| 20120248459 | SUBSTRATE, TEMPLATE SUBSTRATE, SEMICONDUCTOR LIGHT EMITTING ELEMENT, SEMICONDUCTOR LIGHT EMITTING ELEMENT PRODUCING METHOD, ILLUMINATION DEVICE USING SEMICONDUCTOR LIGHT EMITTING ELEMENT AND ELECTRONIC DEVICE - Disclosed is a semiconductor light emitting element (LC) provided with a substrate ( | 10-04-2012 |
| 20120256187 | DOUBLE SUBSTRATE MULTI-JUNCTION LIGHT EMITTING DIODE ARRAY STRUCTURE - The present disclosure provides one embodiment of a light-emitting structure. The light-emitting structure includes a carrier substrate having first metal features; a transparent substrate having second metal features; a plurality of light-emitting diodes (LEDs) bonded with the carrier substrate and the transparent substrate, sandwiched between the carrier substrate and the transparent substrate; and metal pillars bonded to the carrier substrate and the transparent substrate, each of the metal pillars being disposed between adjacent two of the plurality of LEDs, wherein the first metal features, the second metal features and the metal pillars are configured to electrically connect the plurality of LEDs. | 10-11-2012 |
| 20120256188 | Stacked Composite Device Including a Group III-V Transistor and a Group IV Lateral Transistor - In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device. | 10-11-2012 |
| 20120256189 | Stacked Composite Device Including a Group III-V Transistor and a Group IV Vertical Transistor - In one implementation, a stacked composite device comprises a group IV vertical transistor and a group III-V transistor stacked over the group IV vertical transistor. A drain of the group IV vertical transistor is in contact with a source of the group III-V transistor, a source of the group IV vertical transistor is coupled to a gate of the group III-V transistor to provide a composite source on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on a top side of the stacked composite device. A gate of the group IV vertical transistor provides a composite gate on the top side of the stacked composite device. | 10-11-2012 |
| 20120256190 | Stacked Composite Device Including a Group III-V Transistor and a Group IV Diode - In one implementation, a stacked composite device comprises a group IV diode and a group III-V transistor stacked over the group IV diode. A cathode of the group IV diode is in contact with a source of the group III-V transistor, an anode of the group IV diode is coupled to a gate of the group III-V transistor to provide a composite anode on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite cathode on a top side of the stacked composite device. | 10-11-2012 |
| 20120256191 | EPITAXIAL GROWTH METHOD AND DEVICES - Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride. | 10-11-2012 |
| 20120267636 | Lateral High Electron Mobility Transistor - A lateral HEMT includes a substrate, a first semiconductor layer above the substrate and a second semiconductor layer on the first semiconductor layer. The lateral HEMT further includes a gate electrode, a source electrode, a drain electrode and a rectifying Schottky junction. A first terminal of the rectifying Schottky junction is electrically coupled to the source electrode and a second terminal of the rectifying Schottky junction is electrically coupled to the second semiconductor layer. | 10-25-2012 |
| 20120267637 | Nitride semiconductor device and manufacturing method thereof - Provided is a nitride semiconductor device including: a nitride semiconductor layer over a substrate wherein the nitride semiconductor has a two-dimensional electron gas (2DEG) channel inside; a drain electrode in ohmic contact with the nitride semiconductor layer; a source electrode in Schottky contact with the nitride semiconductor layer wherein the source electrode is spaced apart from the drain electrode; a floating guard ring in Schottky contact with the nitride semiconductor layer between the drain electrode and the source electrode; a dielectric layer formed on the nitride semiconductor layer between the drain electrode and the source electrode and on at least a portion of the source electrode wherein the dielectric layer is applied to the floating guard ring between the drain electrode and the source electrode; and a gate electrode formed on the dielectric layer to be spaced apart from the drain electrode, wherein a portion of the gate electrode is formed over a drain-side edge portion of the source electrode with the dielectric layer interposed therebetween, and a manufacturing method thereof. | 10-25-2012 |
| 20120267638 | GaN FILM STRUCTURE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A method of fabricating a gallium nitride (GaN) thin layer structure includes forming a sacrificial layer on a substrate, forming a first buffer layer on the sacrificial layer, forming an electrode layer on the first buffer layer, forming a second buffer layer on the electrode layer, partially etching the sacrificial layer to form at least two support members configured to support the first buffer layer and define at least one air cavity between the substrate and the first buffer layer, and forming a GaN thin layer on the second buffer layer. | 10-25-2012 |
| 20120267639 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a nitride semiconductor device and a method for manufacturing the same. According to an exemplary embodiment, there is provided a nitride semiconductor device, including: a nitride semiconductor layer having a 2DEG channel; a drain electrode ohmic-contacted with the nitride semiconductor layer; a source electrode Schottky-contacted with the nitride semiconductor layer, including a plurality of patterned protrusion portions protruded to the drain electrode direction, and including an ohmic pattern ohmic-contacted with the nitride semiconductor layer therein; a dielectric layer disposed on the nitride semiconductor layer between the drain electrode and the source electrode and over at least a portion of the source electrode including the patterned protrusion portions; and a gate electrode disposed on the dielectric, wherein a portion of the gate electrode is disposed on the dielectric layer over the patterned protrusion portions and a drain direction edge portion of the source electrode. | 10-25-2012 |
| 20120267640 | SEMICONDUCTOR HETEROSTRUCTURE DIODES - Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG. | 10-25-2012 |
| 20120267641 | EPITAXIAL WAFER FOR LIGHT EMITTING DIODE, LIGHT EMITTING DIODE CHIP AND METHODS FOR MANUFACTURING THE SAME - An epitaxial wafer for a light emitting diode (LED) and a method for manufacturing the same are provided. The method comprises: providing a substrate; forming a first LED epitaxial structure on a first surface of the substrate, in which the first LED epitaxial structure comprises a first n-type semiconductor layer, a first light emitting layer, a first anti-diffusion layer between the first n-type semiconductor layer and the first light emitting layer, a first p-type semiconductor layer, and a second anti-diffusion layer between the first p-type semiconductor layer and the first light emitting layer; and forming a second LED epitaxial structure on a second surface of the substrate. An LED chip comprising the epitaxial wafer and a method for manufacturing the same are also provided. | 10-25-2012 |
| 20120273793 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a substrate, a first electrode, a first conductivity type layer, a light emitting layer, a second conductivity type layer and a second electrode. The first conductivity type layer includes a first contact layer, a window layer having a lower impurity concentration than the first contact layer and a first cladding layer. The second conductivity type layer includes a second cladding layer, a current spreading layer and a second contact layer. The second electrode includes a narrow-line region on the second contact layer and a pad region electrically connected to the narrow-line region. Band gap energies of the first contact and window layers are larger than that of the light emitting layer. The first contact layer is provided selectively between the window layer and the first electrode and without overlapping the second contact layer as viewed from above. | 11-01-2012 |
| 20120273794 | SEMICONDUCTOR LIGHT EMITTING DEVICE, WAFER, AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, an active layer, and a second semiconductor layer. The first layer has a first upper surface and a first side surface. The active layer has a first portion covering the first upper surface and having a second upper surface, and a second portion covering the first side surface and having a second side surface. The second layer has a third portion covering the second upper surface, and a fourth portion covering the second side surface. The first and second layers include a nitride semiconductor. The first portion along a stacking direction has a thickness thicker than the second portion along a direction from the first side surface toward the second side surface. The third portion along the stacking direction has a thickness thicker than the fourth portion along the direction. | 11-01-2012 |
| 20120273795 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device comprising a back barrier layer that is formed by a group III-V compound semiconductor above a substrate; a channel layer that is formed of a group III-V compound semiconductor having less bandgap energy than the back barrier layer, is formed on the back barrier layer, and includes a recessed portion formed in at least a portion of the channel layer above the back barrier layer to be thinner than other portions of the channel layer; a first electrode that is in ohmic contact with the channel layer; and a second electrode formed at least above the recessed portion of the channel layer. | 11-01-2012 |
| 20120273796 | HIGH INDIUM UPTAKE AND HIGH POLARIZATION RATIO FOR GROUP-III NITRIDE OPTOELECTRONIC DEVICES FABRICATED ON A SEMIPOLAR (20-2-1) PLANE OF A GALLIUM NITRIDE SUBSTRATE - A Group-III nitride optoelectronic device fabricated on a semipolar (20-2-1) plane of a Gallium Nitride (GaN) substrate is characterized by a high Indium uptake and a high polarization ratio. | 11-01-2012 |
| 20120273797 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - There are provided a semiconductor device that includes a bypass protection unit against surge voltage or the like, achieves good withstand voltage characteristics and low on-resistance (low On-state voltage), has a simple structure, and is used for large-current purpose and a method for producing the semiconductor device. | 11-01-2012 |
| 20120280243 | SEMICONDUCTOR SUBSTRATE AND FABRICATING METHOD THEREOF - A fabricating method of a semiconductor substrate is provided. A patterned mask layer is formed on a substrate base. The patterned mask layer includes a plurality of apertures, and each aperture exposes a portion of the substrate base. A plurality of nano-pillars is formed on the substrate base, wherein each nano-pillar is grown on the portion of the substrate base exposed by each aperture. An insulating layer is formed on a sidewall of each nano-pillar. An epitaxial lateral overgrowth process is performed on a top portion of each nano-pillar, so as to form a semiconductor layer on the nano-pillars, wherein the semiconductor layer is exposed by a plurality of gaps disposed between the nano-pillars. | 11-08-2012 |
| 20120280244 | High Electron Mobility Transistors And Methods Of Manufacturing The Same - High electron mobility transistors (HEMTs) and methods of manufacturing the same. A HEMT may include a channel layer and a channel supply layer, and the channel supply layer may be a multilayer structure. The channel supply layer may include an etch stop layer and an upper layer on the etch stop layer. A recess region may be in the upper layer. The recess region may be a region recessed to an interface between the upper layer and the etch stop layer. A gate electrode may be on the recess region. | 11-08-2012 |
| 20120280245 | High Voltage Cascoded III-Nitride Rectifier Package with Stamped Leadframe - Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package with a stamped leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked atop a source of the III-nitride transistor, and a stamped leadframe comprising a first bent lead coupled to a gate of the III-nitride transistor and the anode of the diode, and a second bent lead coupled to a drain of the III-nitride transistor. The bent leads expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts. | 11-08-2012 |
| 20120280246 | High Voltage Cascoded III-Nitride Rectifier Package with Etched Leadframe - Some exemplary embodiments of high voltage cascaded III-nitride semiconductor package with an etched leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked over a source of the III-nitride transistor, and a leadframe that is etched to form a first leadframe paddle portion coupled to a gate of the III-nitride transistor and the anode of the diode, and a second leadframe paddle portion coupled to a drain of the III-nitride transistor. The leadframe paddle portions enable the package to be surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts. | 11-08-2012 |
| 20120280247 | High Voltage Cascoded III-Nitride Rectifier Package Utilizing Clips on Package Support Surface - Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing. | 11-08-2012 |
| 20120280248 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting device comprises a first conductive type semiconductor layer, an active layer, a first thin insulating layer, and a second conductive type semiconductor layer. The active layer is formed on the first conductive type semiconductor layer. The first thin insulating layer is formed on the active layer. The second conductive type semiconductor layer is formed on the thin insulating layer. | 11-08-2012 |
| 20120280249 | METHODS FOR IMPROVING THE QUALITY OF STRUCTURES COMPRISING SEMICONDUCTOR MATERIALS - Methods which can be applied during the epitaxial growth of semiconductor structures and layers of III-nitride materials so that the qualities of successive layers are successively improved. An intermediate epitaxial layer is grown on an initial surface so that growth pits form at surface dislocations present in the initial surface. A following layer is then grown on the intermediate layer according to the known phenomena of epitaxial lateral overgrowth so it extends laterally and encloses at least the agglomerations of intersecting growth pits. Preferably, prior to growing the following layer, a discontinuous film of a dielectric material is deposited so that the dielectric material deposits discontinuously so as to reduce the number of dislocations in the laterally growing material. The methods of the invention can be performed multiple times to the same structure. Also, semiconductor structures fabricated by these methods. | 11-08-2012 |
| 20120286284 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND WAFER - According to one embodiment, a semiconductor light emitting device includes: a foundation layer, a first semiconductor layer, a light emitting part, and a second semiconductor layer. The foundation layer includes a nitride semiconductor. The foundation layer has a dislocation density not more than 5×10 | 11-15-2012 |
| 20120286285 | METHOD OF IMPLANTING A WORKPIECE TO IMPROVE GROWTH OF A COMPOUND SEMICONDUCTOR - A workpiece is implanted to improve growth of a compound semiconductor, such as GaN. This workpiece may be implanted such that the workpiece has a dose at a center different from a dose at a periphery. This workpiece also may be implanted one or more times to form a pattern of lines, which may be a grid, a series of circles, or other shapes. The distance between certain pairs of lines may be different across the workpiece. | 11-15-2012 |
| 20120286286 | NON-POLAR NITRIDE-BASED LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed are a non-polar nitride-based light emitting device and a method for fabricating the same. The non-polar nitride-based light emitting device includes a substrate, a first-type semiconductor layer on the substrate, an active layer on the active layer, a second-type semiconductor layer on the active layer, a light extraction layer on the second-type semiconductor layer and including at least one layer including indium having a plurality of unit structures having an inverted pyramidal intaglio shape, a first electrode electrically connected to the first-type semiconductor layer, and a second electrode electrically connected to the second-type semiconductor layer. | 11-15-2012 |
| 20120286287 | VERTICAL GALLIUM NITRIDE-BASED LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a vertical GaN-based semiconductor diode and a method of manufacturing the same. The GaN-based πi-V group semiconductor device includes a substrate, a p-type ohmic electrode layer on the substrate, a p-type GaN-based πi-V group compound semiconductor layer on the p-type ohmic electrode layer, an n-type GaN-based πi-V group compound semiconductor layer on the p-type GaN-based πi-V group compound semiconductor layer, and an n-type ohmic electrode layer on the n-type GaN-based IE-V group compound semiconductor layer. The p-type ohmic electrode layer is an Ag-based highly reflective electrode having a high reflectivity of 70% or more, and a surface of the n-type GaN-based E-V group compound semiconductor layer is subjected to at least one of a process of forming photonic crystals and a process of surface roughening. | 11-15-2012 |
| 20120292629 | LIGHT EMITTING DIODE AND METHOD OF FABRICATION THEREOF - A method includes providing an LED element including a substrate and a gallium nitride (GaN) layer disposed on the substrate. The GaN layer is treated. The treatment includes performing an ion implantation process on the GaN layer. The ion implantation process may provide a roughened surface region of the GaN layer. In an embodiment, the ion implantation process is performed at a temperature of less than approximately 25 degrees Celsius. In a further embodiment, the substrate is at a temperature less than approximately zero degrees Celsius during the ion implantation process. | 11-22-2012 |
| 20120292630 | LED SUBSTRATE AND LED - A light emitting diode (LED) substrate including a sapphire substrate is provided. The sapphire substrate has a surface consisting of a plurality of upper trigonal and lower hexagonal tapers, wherein each of the upper trigonal and lower hexagonal tapers is consisted of a hexagonal taper and a trigonal taper on the hexagonal taper, and a pitch of the upper trigonal and lower hexagonal tapers is less than 10 μm. This LED substrate has high light-emitting efficiency. | 11-22-2012 |
| 20120292631 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a stacked structure body, a first electrode, a second electrode, and a dielectric body part. The stacked structure body includes a first semiconductor layer, having a first portion and a second portion juxtaposed with the first portion, a light emitting layer provided on the second portion, a second semiconductor layer provided on the light emitting layer. The first electrode includes a contact part provided on the first portion and contacting the first layer. The second electrode includes a first part provided on the second semiconductor layer and contacting the second layer, and a second part electrically connected with the first part and including a portion overlapping with the contact part when viewed from the first layer toward the second layer. The dielectric body part is provided between the contact part and the second part. | 11-22-2012 |
| 20120292632 | NITRIDE SEMICONDUCTOR DEVICE, NITRIDE SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAYER - According to one embodiment, a nitride semiconductor device includes a foundation layer and a functional layer. The foundation layer is formed on an Al-containing nitride semiconductor layer formed on a silicon substrate. The foundation layer has a thickness not less than 1 micrometer and including GaN. The functional layer is provided on the foundation layer. The functional layer includes a first semiconductor layer. The first semiconductor layer has an impurity concentration higher than an impurity concentration in the foundation layer and includes GaN of a first conductivity type. | 11-22-2012 |
| 20120292633 | LIGHT EMITTING DIODE ARRAY AND METHOD FOR MANUFACTURING THE SAME - An LED array includes a substrate and a plurality of LEDs formed on the substrate. The LEDs are electrically connected with each other. Each of the LEDs includes a connecting layer, an n-type GaN layer, an active layer, and a p-type GaN layer formed on the substrate in sequence. The connecting layer is etchable by alkaline solution. A bottom surface of the n-type GaN layer which connects the connecting layer has a roughened exposed portion. The bottom surface of the n-type GaN layer has an N-face polarity. A method for manufacturing the LED array is also provided. | 11-22-2012 |
| 20120292634 | GALIUM-NITRIDE LIGHT EMITTING DEVICE OF MICROARRAY TYPE STRUCTURE AND MANUFACTURING THEREOF - Disclosed are a microarray type nitride light emitting device and a method of manufacturing the same. More particularly, a uniform current distribution property is ensured by dividing a fine light emitting region by using a first transparent contact layer according to a resistance change property in heat treatment of a material of a transparent conducting oxide used as a transparent contact layer, and connecting the divided light emitting regions by using a second transparent contact layer. | 11-22-2012 |
| 20120292635 | COMPOSITE SEMICONDUCTOR DEVICE - This composite semiconductor device has a normally-on first field effect transistor and a normally-off second field effect transistor connected in series between first and second terminals, gates of the first and second field effect transistors being connected to second and third terminals, respectively, and N diodes being connected in series in a forward direction between a drain and a source of the second field effect transistor. Therefore, a drain-source voltage (Vds) of the second field effect transistor can be restricted to a voltage not higher than a withstand voltage of the second field effect transistor. | 11-22-2012 |
| 20120299010 | GROUP-III NITRIDE SEMICONDUCTOR DEVICE, EPITAXIAL SUBSTRATE, AND METHOD OF FABRICATING GROUP-III NITRIDE SEMICONDUCTOR DEVICE - A III-nitride semiconductor device has a support base comprised of a III-nitride semiconductor and having a primary surface extending along a first reference plane perpendicular to a reference axis inclined at a predetermined angle with respect to a c-axis of the III-nitride semiconductor, and an epitaxial semiconductor region provided on the primary surface of the support base. The epitaxial semiconductor region includes GaN-based semiconductor layers. The reference axis is inclined at a first angle from the c-axis of the III-nitride semiconductor toward a first crystal axis, either the m-axis or a-axis. The reference axis is inclined at a second angle from the c-axis of the III-nitride semiconductor toward a second crystal axis, the other of the m-axis and a-axis. Morphology of an outermost surface of the epitaxial semiconductor region includes a plurality of pits. A pit density of the pits is not more than 5×10 | 11-29-2012 |
| 20120299011 | FIELD-EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased. | 11-29-2012 |
| 20120299012 | Gallium Nitride for Liquid Crystal Electrodes - Described herein is a liquid crystal (LC) device having Gallium Nitride HEMT electrodes. The Gallium Nitride HEMT electrodes can be grown on a variety of substrates, including but not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium flouride buffer layer), and spinel. Also described is a structure provided from GaN HEMT grown on large area silicon substrates and transferred to another substrate with appropriate properties for OPA devices. Such substrates include, but are not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer), and spinel. The GaN HEMT structure includes an AlN interlayer for improving the mobility of the structure. | 11-29-2012 |
| 20120305931 | GOLD-FREE OHMIC CONTACTS - A semiconductor structure is provided having: a semiconductor; a gold-free electrically conductive structure in ohmic contact with the semiconductor; and a pair of electrically conductive layers separated by a layer of silicon. The structure includes: a refractory metal layer disposed in contact with the semiconductor; and wherein one of the pair of electrically conductive layers separated by the layer of silicon is the refractory metal layer. A second layer of silicon is disposed on a second one of the pair of pair of electrically conductive layers and including a third electrically conducive layer on the second layer of silicon. In one embodiment, the semiconductor includes a III-V material. | 12-06-2012 |
| 20120305932 | LATERAL TRENCH MESFET - A transistor includes a trench formed in a semiconductor body, the trench having sidewalls and a bottom. The transistor further includes a first semiconductor material disposed in the trench adjacent the sidewalls and a second semiconductor material disposed in the trench and spaced apart from the sidewalls by the first semiconductor material. The second semiconductor material has a different band gap than the first semiconductor material. The transistor also includes a gate material disposed in the trench and spaced apart from the first semiconductor material by the second semiconductor material. The gate material provides a gate of the transistor. Source and drain regions are arranged in the trench with a channel interposed between the source and drain regions in the first or second semiconductor material so that the channel has a lateral current flow direction along the sidewalls of the trench. | 12-06-2012 |
| 20120305933 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A group III nitride semiconductor light-emitting device includes a GaN crystal substrate and at least one group III nitride semiconductor layer disposed on a main surface of the GaN crystal substrate. The substrate includes a matrix crystal region and a c-axis-inverted crystal region. An off angle θ is formed between the main surface and a {0001} plane, and an off-angle component of a first direction has an absolute value |θ | 12-06-2012 |
| 20120305934 | NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A nitride semiconductor light emitting element has: a substrate for growth; an n-type nitride semiconductor layer formed on the substrate for growth; a light emitting layer formed on the n-type nitride semiconductor layer; and a p-type nitride semiconductor layer formed on the light emitting layer, wherein pipe holes are formed at a density of 5000 pipe holes/cm | 12-06-2012 |
| 20120305935 | APPARATUS FOR PRODUCING METAL CHLORIDE GAS AND METHOD FOR PRODUCING METAL CHLORIDE GAS, AND APPARATUS FOR HYDRIDE VAPOR PHASE EPITAXY, NITRIDE SEMICONDUCTOR WAFER, NITRIDE SEMICONDUCTOR DEVICE, WAFER FOR NITRIDE SEMICONDUCTOR LIGHT EMITTING DIODE, METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR FREESTANIDNG SUBSTRATE AND NITRIDE SEMICONDUCTOR CRYSTAL - There is provided an apparatus for producing metal chloride gas, comprising: a source vessel configured to store a metal source; a gas supply port configured to supply chlorine-containing gas into the source vessel; a gas exhaust port configured to discharge metal chloride-containing gas containing metal chloride gas produced by a reaction between the chlorine-containing gas and the metal source, to outside of the source vessel; and a partition plate configured to form a gas passage continued to the gas exhaust port from the gas supply port by dividing a space in an upper part of the metal source in the source vessel, wherein the gas passage is formed in one route from the gas supply port to the gas exhaust port, with a horizontal passage width of the gas passage set to 5 cm or less, with bent portions provided on the gas passage. | 12-06-2012 |
| 20120305936 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a nitride semiconductor layer; a source electrode, a gate electrode and a drain electrode; an insulating layer covering at least the gate electrode and a part of the nitride semiconductor layer; and a field plate on the insulating layer, a width of a region of the field plate between an edge of the field plate of a side of the drain electrode and an edge of the side face of the insulating layer covering a side face of the gate electrode of a side of the drain electrode being 0.1 μm or more, a distance between an edge of the field plate and an edge of the drain electrode in a contact face between the nitride semiconductor layer and the drain electrode being 3.5 μm or more, an operating frequency of the semiconductor device being 4 GHz or less. | 12-06-2012 |
| 20120305937 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting diode, and method of fabricating same, wherein an indium (In)-containing light-emitting layer, as well as subsequent device layers, is deposited on a textured surface. The resulting device is a phosphor-free white light source. | 12-06-2012 |
| 20120305938 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light emitting device is provided. The semiconductor light emitting device includes a first nitride layer, an active layer, and a second nitride layer. The first nitride layer includes an irregular, uneven surface, and the active layer is formed on the irregular, uneven surface. The second nitride layer is formed on the active layer. A plurality of quantum dots are formed at the active layer. | 12-06-2012 |
| 20120305939 | LIGHT EMITTING DIODES INCLUDING BARRIER SUBLAYERS - Semiconductor light emitting devices, such as light emitting diodes, include a substrate, an epitaxial region on the substrate that includes a light emitting region such as a light emitting diode region, and a multilayer conductive stack including a reflector layer, on the epitaxial region. A barrier layer is provided on the reflector layer and extending on a sidewall of the reflector layer. The multilayer conductive stack can also include an ohmic layer between the reflector and the epitaxial region. The barrier layer further extends on a sidewall of the ohmic layer. The barrier layer can also extend onto the epitaxial region outside the multilayer conductive stack. The barrier layer can be fabricated as a series of alternating first and second sublayers. | 12-06-2012 |
| 20120313105 | UNIPOLAR DIODE WITH LOW TURN-ON VOLTAGE - A unipolar diode with low turn-on voltage includes a subcathode semiconductor layer, a low-doped, wide bandgap cathode semiconductor layer, and a high-doped, narrow bandgap anode semiconductor layer. A junction between the cathode layer and the anode layer creates an electron barrier in the conduction band, with the barrier configured to produce a low turn-on voltage for the diode. A unipolar diode with low turn-on voltage includes an n | 12-13-2012 |
| 20120313106 | Enhancement Mode Group III-V High Electron Mobility Transistor (HEMT) and Method for Fabrication - According to one disclosed embodiment, an enhancement mode high electron mobility transistor (HEMT) comprises a heterojunction including a group III-V barrier layer situated over a group III-V semiconductor body, and a gate structure formed over the group III-V barrier layer and including a P type group III-V gate layer. The P type group III-V gate layer prevents a two dimensional electron gas (2DEG) from being formed under the gate structure. One embodiment of a method for fabricating such an enhancement mode HEMT comprises providing a substrate, forming a group III-V semiconductor body over the substrate, forming a group III-V barrier layer over the group III-V semiconductor body, and forming a gate structure including the P type group III-V gate layer over the group III-V barrier layer. | 12-13-2012 |
| 20120313107 | Semiconductor Device - A semiconductor device includes a main body made of a GaN-based semiconductor material, and at least one electrode structure. The electrode structure includes an ohmic contact layer that is formed on the main body, a buffer layer that is formed on the ohmic contact layer opposite to the main body, and a circuit layer that is made of a copper-based material and that is formed on the buffer layer opposite to the ohmic contact layer. The ohmic contact layer is made of a material selected from titanium, aluminum, nickel, and alloys thereof. The buffer layer is made of a material different from the material of the ohmic contact layer and selected from titanium, tungsten, titanium nitride, tungsten nitride, and combinations thereof. | 12-13-2012 |
| 20120313108 | SEMICONDUCTOR DIODE - To provide a semiconductor diode with a part of a semiconductor lamination portion having a mesa structure portion, which is the part where a pn-junction is formed by lamination of an n-type semiconductor layer and a p-type semiconductor layer on a substrate, comprising: a protective insulating film formed by coating a main surface of the mesa structure portion, a side face of the mesa structure portion in which an interface of the pn-junction is exposed, and an etched and exposed surface of the n-type semiconductor layer; and an anode electrode formed in ohmic-contact with the p-type semiconductor layer exposed from an opening formed on a part of the main surface of the mesa structure portion of the protective insulating film, extending from the main surface, through the side face of the mesa structure portion, to the surface of the n-type semiconductor layer. | 12-13-2012 |
| 20120313109 | Nitride Semiconductor Light Emitting Device and Fabrication Method Thereof - Provided is a nitride semiconductor light emitting device including: a first nitride semiconductor layer; an active layer formed above the first nitride semiconductor layer; and a delta doped second nitride semiconductor layer formed above the active layer. According to the present invention, the optical power of the nitride semiconductor light emitting device is enhanced, optical power down phenomenon is improved and reliability against ESD (electro static discharge) is enhanced. | 12-13-2012 |
| 20120313110 | LIGHT EMITTING DEVICE - Disclosed are a light emitting device. A light emitting diode comprises a light emitting device comprises a plurality of N-type semiconductor layers including a first N-type semiconductor layer and a second N-type semiconductor layer on the first N-type semiconductor layer, an active layer on the second N-type semiconductor layer, and a P-type semiconductor layer on the active layer, wherein the first N-type semiconductor layer comprises a Si doped Nitride layer and the second N-type semiconductor layer comprises a Si doped Nitride layer, and wherein the first and second N-type semiconductor layers have a Si impurity concentration different from each other. | 12-13-2012 |
| 20120319125 | SILICON CARBIDE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A first single crystal substrate has a first side surface and it is composed of silicon carbide. A second single crystal substrate has a second side surface opposed to the first side surface and it is composed of silicon carbide. A bonding portion connects the first and second side surfaces to each other between the first and second side surfaces. At least a part of the bonding portion is made of particles composed of silicon carbide and having a maximum length not greater than 1 μm. | 12-20-2012 |
| 20120319126 | Optoelectronic Semiconductor Chip and Method for Fabrication Thereof - An optoelectronic semiconductor chip has a first semiconductor layer sequence which comprises a multiplicity of microdiodes, and a second semiconductor layer sequence which comprises an active region the first semiconductor layer sequence and the second semiconductor layer sequence are based on a nitride compound semiconductor material, the first semiconductor layer sequence is before the first semiconductor layer sequence in the direction of growth, and the microdiodes form an ESD protection for the active region. | 12-20-2012 |
| 20120319127 | CURRENT APERTURE VERTICAL ELECTRON TRANSISTORS WITH AMMONIA MOLECULAR BEAM EPITAXY GROWN P-TYPE GALLIUM NITRIDE AS A CURRENT BLOCKING LAYER - A current aperture vertical electron transistor (CAVET) with ammonia (NH | 12-20-2012 |
| 20120319128 | SEMICONDUCTOR STRUCTURES, DEVICES AND ENGINEERED SUBSTRATES INCLUDING LAYERS OF SEMICONDUCTOR MATERIAL HAVING REDUCED LATTICE STRAIN - Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure. | 12-20-2012 |
| 20120319129 | SUBSTRATE, EPITAXIAL LAYER PROVIDED SUBSTRATE, METHOD FOR PRODUCING SUBSTRATE, AND METHOD FOR PRODUCING EPITAXIAL LAYER PROVIDED SUBSTRATE - The present invention provides a substrate formed at a low cost and having a controlled plate shape, an epitaxial layer provided substrate obtained by forming an epitaxial layer on the substrate, and methods for producing them. The method for producing the substrate according to the present invention includes an ingot growing step (S | 12-20-2012 |
| 20120319130 | LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a light emitting device and a method of fabricating the same. The light emitting device comprises: a first conductive semiconductor layer; an active layer comprising an InGaN well layer and a GaN barrier layer on the first conductive semiconductor layer; and a second conductive semiconductor layer on the active layer. The GaN barrier layer comprises an AlGaN layer. | 12-20-2012 |
| 20120319131 | METHODS OF GROWING NITRIDE SEMICONDUCTORS AND METHODS OF MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATES - Methods of growing nitride semiconductor layers including forming nitride semiconductor dots on a substrate and growing a nitride semiconductor layer on the nitride semiconductor dots. The nitride semiconductor layer may be separated from the substrate to be used as a nitride semiconductor substrate. | 12-20-2012 |
| 20120326159 | LED STRUCTURE WITH ENHANCED MIRROR REFLECTIVITY - Embodiments of the present invention are generally related to LED chips having improved overall emission by reducing the light-absorbing effects of barrier layers adjacent mirror contacts. In one embodiment, a LED chip comprises one or more LEDs, with each LED having an active region, a first contact under the active region having a highly reflective mirror, and a barrier layer adjacent the mirror. The barrier layer is smaller than the mirror such that it does not extend beyond the periphery of the mirror. In another possible embodiment, an insulator is further provided, with the insulator adjacent the barrier layer and adjacent portions of the mirror not contacted by the active region or by the barrier layer. In yet another embodiment, a second contact is provided on the active region. In a further embodiment, the barrier layer is smaller than the mirror such that the periphery of the mirror is at least 40% free of the barrier layer, and the second contact is below the first contact and accessible from the bottom of the chip. | 12-27-2012 |
| 20120326160 | SEMICONDUCTOR DEVICE HAVING NITRIDE SEMICONDUCTOR LAYER - A semiconductor device includes a silicon substrate, an aluminum nitride layer which is arranged on the silicon substrate and has a region where silicon is doped thereof as an impurity, a buffer layer which is arranged on the aluminum nitride layer and has a structure where a plurality of nitride semiconductor films are laminated, and a semiconductor functional layer which is arranged on the buffer layer and made of nitride semiconductor. | 12-27-2012 |
| 20120326161 | NITRIDE SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREFOR - An exemplary nitride-based semiconductor device includes: a semiconductor multilayer structure | 12-27-2012 |
| 20130001584 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a stacked structure unit, a transparent, p-side and n-side electrodes. The unit includes n-type semiconductor layer, a light emitting portion provided on a part of the n-type semiconductor layer and p-type semiconductor layer provided on the light emitting portion. The transparent electrode is provided on the p-type semiconductor layer. The p-side electrode is provided on the transparent electrode. The n-side electrode is provided on the n-type semiconductor layer. The transparent electrode has a hole provided between the n-side and p-side electrodes. A width of the hole along an axis perpendicular to an axis from the p-side electrode toward the n-side electrode is longer than widths of the n-side and p-side electrodes. A distance between the hole and the n-side electrode is not longer than a distance between the hole and the p-side electrode. | 01-03-2013 |
| 20130001585 | GALLIUM NITRIDE RECTIFYING DEVICE - A gallium nitride rectifying device includes a p-type gallium nitride based semiconductor layer and an n-type gallium nitride based semiconductor layer, the two layers forming a pn junction with each other. The p-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×10 | 01-03-2013 |
| 20130001586 | SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING - A method for forming a substrate includes forming a base layer comprising a Group III-V material on a substrate, cooling the base layer and inducing cracks in the base layer, and forming a bulk layer comprising a Group III-V material on the base layer after cooling. | 01-03-2013 |
| 20130001587 | HIGH ELECTRON MOBILITY TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - High electron mobility transistors (HEMTs) including a cavity below a drain and methods of manufacturing HEMTS including removing a portion of a substrate below a drain. | 01-03-2013 |
| 20130001588 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor device composed of a Group III nitride semiconductor has the following structure. A substrate has on it an n-type first semiconductor layer, an active layer, and a p-type second semiconductor layer in this order. Two first end faces are formed by cleavage and oppose each other in planar view. Two trenches extend to the two first end faces in the direction orthogonal to the first end faces in planar view. Bottoms of the trenches are positioned at least below the lower surface of the active layer. Second end faces are formed by laser scribing in the direction orthogonal to the first end faces and outside the trenches. | 01-03-2013 |
| 20130001589 | LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) WITH TAPERED DIELECTRIC PLATES TO ACHIEVE A HIGH DRAIN-TO-BODY BREAKDOWN VOLTAGE, A METHOD OF FORMING THE TRANSISTOR AND A PROGRAM STORAGE DEVICE FOR DESIGNING THE TRANSISTOR - A lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) with a high drain-to-body breakdown voltage (Vb) incorporates gate structure extensions on opposing sides of a drain drift region. The extensions are tapered such that a distance between each extension and the drift region increases linearly from one end adjacent to the channel region to another end adjacent to the drain region. In one embodiment, these extensions can extend vertically through the isolation region that surrounds the LEDMOSFET. In another embodiment, the extensions can sit atop the isolation region. In either case, the extensions create a strong essentially uniform horizontal electric field profile within the drain drift. Also disclosed are a method for forming the LEDMOSFET with a specific Vb by defining the dimensions of the extensions and a program storage device for designing the LEDMOSFET to have a specific Vb. | 01-03-2013 |
| 20130001590 | LIGHT EMITTING DIODES AND METHODS FOR MANUFACTURING LIGHT EMITTING DIODES - Light emitting diodes and methods for manufacturing light emitting diodes are disclosed herein. In one embodiment, a method for manufacturing a light emitting diode (LED) comprises applying a first light conversion material to a first region on the LED and applying a second light conversion material to a second, different region on the LED. A portion of the LED is exposed after applying the first and second light conversion materials. | 01-03-2013 |
| 20130009164 | POWER DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a power device. The power device may include a two-dimensional electron gas (2-DEG) layer in a portion corresponding to a gate electrode pattern since a second nitride layer is further formed on a lower portion of the gate electrode pattern after a first nitride layer is formed and thus, may be capable of performing a normally-OFF operation. Accordingly, the power device may adjust generation of the 2-DEG layer based on a voltage of a gate, and may reduce power consumption. The power device may regrow only the portion corresponding to the gate electrode pattern or may etch a portion excluding the portion corresponding to the gate electrode pattern and thus, a recess process may be omissible, a reproducibility of the power device may be secured, and a manufacturing process may be simplified. | 01-10-2013 |
| 20130009165 | NITRIDE SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME AND NITRIDE SEMICONDUCTOR POWER DEVICE - Disclosed herein are a nitride semiconductor device, a method for manufacturing the same, and a nitride semiconductor power device. According to an exemplary embodiment of the present invention, a nitride semiconductor device includes: a nitride semiconductor layer over a substrate wherein the nitride semiconductor layer has a two-dimensional electron gas (2DEG) channel formed therein; a D-mode FET that includes a gate electrode Schottky-contacting with the nitride semiconductor layer to form a normally-on operating depletion-mode (D-mode) HEMT structure; and a Schottky diode part that includes an anode electrode Schottky-contacting with the nitride semiconductor layer and increases a gate driving voltage of the D-mode FET, the anode electrode being connected to the gate electrode of the D-mode FET. In addition, the nitride semiconductor power device and the method for manufacturing a nitride semiconductor device are proposed. | 01-10-2013 |
| 20130009166 | SEMICONDUCTOR DEVICE - One embodiment of a semiconductor device according to the present invention includes a substrate, a base compound semiconductor layer layered on the substrate to form a base, a channel defining compound semiconductor layer layered on the base compound semiconductor layer to define a channel, and an impact ionization control layer that is layered within a layering range of the base compound semiconductor layer and controls the location of impact ionization, wherein the base compound semiconductor layer is formed of a first compound semiconductor, the channel defining compound semiconductor layer is formed of a second compound semiconductor, and the impact ionization control layer is formed of a third compound semiconductor that has a smaller band gap than the first compound semiconductor. | 01-10-2013 |
| 20130015460 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAMEAANM CHEN; Po-ChihAACI Hsinchu CityAACO TWAAGP CHEN; Po-Chih Hsinchu City TWAANM YU; Jiun-Lei JerryAACI Zhudong TownshipAACO TWAAGP YU; Jiun-Lei Jerry Zhudong Township TWAANM YAO; Fu-WeiAACI Hsinchu CityAACO TWAAGP YAO; Fu-Wei Hsinchu City TWAANM HSU; Chun-WeiAACI Taichung CityAACO TWAAGP HSU; Chun-Wei Taichung City TWAANM YANG; Fu-ChihAACI Fengshan CityAACO TWAAGP YANG; Fu-Chih Fengshan City TWAANM TSAI; Chun LinAACI HsinchuAACO TWAAGP TSAI; Chun Lin Hsinchu TW - An embodiment of the disclosure includes a semiconductor structure. The semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. An interface is defined between the first III-V compound layer and the second III-V compound layer. A gate is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on opposite side of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second III-V compound layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface. | 01-17-2013 |
| 20130015461 | Light-emitting Device Capable of Producing White Light And Light Mixing Method For Producing White Light With SameAANM Lin; Kuen-ChiuanAACO USAAGP Lin; Kuen-Chiuan US - A light-emitting device capable of producing white light includes at least two types of LED elements and at least one encapsulant material. Each of the LED elements has an epitaxial light-emitting layer grown on a substrate; and the epitaxial light-emitting layers for the LED elements are the same series of AlGaInN materials having emission wavelengths in a region from violet to green light and different from one another by at least 30 nm. The encapsulant material encapsulates the LED elements and contains an adequate amount of fluorescent powder, which can be excited to emit complementary color lights to mix with color lights from the LED elements to produce bluish, yellowish, greenish or reddish white light. At least two types of the white light-emitting devices can be differently arrayed in a module or a system to produce a white light with high color-rendering index and good light mixing effect. | 01-17-2013 |
| 20130015462 | TRANSISTORS WITH DUAL LAYER PASSIVATION - Semiconductor devices are provided with dual passivation layers. A semiconductor layer is formed on a substrate and covered by a first passivation layer (PL- | 01-17-2013 |
| 20130015463 | NITRIDE-BASED SEMICONDUCTOR DEVICE HAVING EXCELLENT STABILITYAANM LEE; Jae HoonAACI Suwon-siAACO KRAAGP LEE; Jae Hoon Suwon-si KR - A nitride-based semiconductor device is provided. The nitride-based semiconductor device may include an aluminum silicon carbide (AlSi | 01-17-2013 |
| 20130015464 | POWER SEMICONDUCTOR DEVICEAANM HUR; Seung BaeAACI Suwon-siAACO KRAAGP HUR; Seung Bae Suwon-si KRAANM Kim; Ki SeAACI Suwon-siAACO KRAAGP Kim; Ki Se Suwon-si KR - A power semiconductor device and a manufacturing method thereof are provided. The power semiconductor device includes an anode electrode including an anode electrode pad, electrode bus lines connected to a first side and a second side on the anode electrode pad, the electrode bus lines each having a decreasing width in a direction away from the anode electrode pad, and pluralities of first anode electrode fingers and second anode electrode fingers connected with a third side and a fourth side on the anode electrode pad and with both sides of the electrode bus line, a cathode electrode including a first cathode electrode pad and a second cathode electrode pad, a plurality of cathode electrode fingers connected with the first cathode electrode pad, and a plurality of second cathode electrode fingers connected with the second cathode electrode pad, and an insulation layer disposed at an external portion of the anode. | 01-17-2013 |
| 20130015465 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICEAANM LEE; Jae-hoonAACI Suwon-siAACO KRAAGP LEE; Jae-hoon Suwon-si KR - A nitride light-emitting device includes an N-type nitride semiconductor layer; an active layer disposed on the N-type nitride semiconductor layer; and a P-type nitride semiconductor layer disposed on the active layer. The P-type nitride semiconductor includes a heterojunction structure having a GaN layer and an N-type Al | 01-17-2013 |
| 20130015466 | EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Provided is an epitaxial substrate for a semiconductor device, which has excellent schottky contact characteristics that are stable over time. The epitaxial substrate for a semiconductor device includes a base substrate, a channel layer formed of a first group III nitride containing at least Ga and having a composition of In | 01-17-2013 |
| 20130020580 | HETEROEPITAXIAL GROWTH USING ION IMPLANTATION - In one embodiment, a method of growing a heteroepitaxial layer comprises providing a patterned substrate containing patterned features having sidewalls. The method also includes directing ions toward the sidewalls in an exposure, wherein altered sidewall regions are formed, and depositing the heteroepitaxial layer under a set of deposition conditions effective to preferentially promote epitaxial growth on the sidewalls in comparison to other surfaces of the patterned features. | 01-24-2013 |
| 20130020581 | EPITAXIAL WAFER INCLUDING NITRIDE-BASED SEMICONDUCTOR LAYERS - An epitaxial wafer including nitride-based semiconductor layers usable for a hetero-junction field effect type transistor, includes a first buffer layer of AlN or AlON, a second buffer layer of Al | 01-24-2013 |
| 20130020582 | RAPID FABRICATION METHODS FOR FORMING NITRIDE BASED SEMICONDUCTORS BASED ON FREESTANDING NITRIDE GROWTH SUBSTRATES - High temperature bonding and interconnect methods can be used for LED and other optoelectronic devices based on freestanding nitride devices. Inorganic glasses, especially those which exhibit a CTE, which substantially matches the CTE of the freestanding nitride devices, can provide hermetic sealing of the freestanding nitride devices or the contact regions of the freestanding nitride devices. The freestanding nitride devices are typically freestanding nitride veneers. | 01-24-2013 |
| 20130020583 | EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE - Provided is a crack-free epitaxial substrate. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer formed of a first and a second lamination unit being alternately laminated such that each of an uppermost and a lowermost portion of the buffer layer is formed of the first lamination unit. The first lamination unit is formed of a first and a second composition layer having different compositions being alternately laminated so as to increase the thickness of the second composition layer in a portion more distant from the base substrate side, to thereby cause a compressive strain to exist in the first lamination unit such that it increases in a portion more distant from the base substrate. The second lamination unit is formed as an intermediate layer that is substantially strain-free and formed with a thickness of 15 nm or more and 150 nm or less. | 01-24-2013 |
| 20130020584 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - In the present invention, provided is a semiconductor device, including: a GaN channel layer which is provided on a substrate and through which electrons run; a barrier layer which is provided on the GaN channel layer and which contains at least one of In, Al, and Ga and contains N; a gate electrode which is provided on the barrier layer; and a source electrode and a drain electrode which are provided on the substrate across the gate electrode, in which, in a portion of the barrier layer between the gate electrode and the drain electrode, a magnitude of polarization of the barrier layer is smaller on the gate electrode side than on the drain electrode side. Thus, PAE can be improved by reducing Rd and Cgd simultaneously. | 01-24-2013 |
| 20130026480 | Nucleation of Aluminum Nitride on a Silicon Substrate Using an Ammonia Preflow - A silicon wafer used in manufacturing crystalline GaN for light emitting diodes (LEDs) includes a silicon substrate, a buffer layer of aluminum nitride (AlN) and an upper layer of GaN. The silicon wafer has a diameter of at least 200 millimeters and an Si(111)1×1 surface. The AlN buffer layer overlies the Si(111) surface. The GaN upper layer is disposed above the buffer layer. Across the entire wafer substantially no aluminum atoms of the AlN are present in a bottom most plane of atoms of the AlN, and across the entire wafer substantially only nitrogen atoms of the AlN are present in the bottom most plane of atoms of the AlN. A method of making the AlN buffer layer includes preflowing a first amount of ammonia equaling less than 0.01% by volume of hydrogen flowing through a chamber before flowing trimethylaluminum and then a subsequent amount of ammonia through the chamber. | 01-31-2013 |
| 20130026481 | TEXTURED OPTOELECTRONIC DEVICES AND ASSOCIATED METHODS OF MANUFACTURE - Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state optoelectronic device can include forming a conductive transparent texturing material on a substrate. The method can further include forming a transparent conductive material on the texturing material. Upon heating the device, the texturing material causes the conductive material to grow a plurality of protuberances. The protuberances can improve current spreading and light extraction from the device. | 01-31-2013 |
| 20130026482 | Boron-Containing Buffer Layer for Growing Gallium Nitride on Silicon - A silicon wafer used in manufacturing GaN for LEDs includes a silicon substrate, a buffer layer of boron aluminum nitride (B | 01-31-2013 |
| 20130026483 | Gallium and Nitrogen Containing Triangular or Diamond-Shaped Configuration for Optical Devices - A gallium and nitrogen containing optical device has a base region and no more than three major planar side regions configured in a triangular arrangement provided from the base region. | 01-31-2013 |
| 20130026484 | Multi-Color Light Emitting Devices with Compositionally Graded Cladding Group III-Nitride Layers Grown on Substrates - A light emitting device includes a substrate, multiple n-type layers, and multiple p-type layers. The n-type layers and the p-type layers each include a group III nitride alloy. At least one of the n-type layers is a compositionally graded n-type group III nitride, and at least one of the p-type layers is a compositionally graded p-type group III nitride. A first ohmic contact for injecting current is formed on the substrate, and a second ohmic contact is formed on a surface of at least one of the p-type layers. Utilizing the disclosed structure and methods, a device capable of emitting light over a wide spectrum may be made without the use of phosphor materials. | 01-31-2013 |
| 20130026485 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device is provided. The power semiconductor device includes a source electrode disposed on a device activation region and widened in a direction toward a first side, a drain electrode arranged alternately with the source electrode on the device activation region and widened in a direction toward a second side facing the first side, an insulating layer disposed on the source electrode and the drain electrode and configured to include a plurality of via contacts contacting the source electrode and the drain electrode, a source electrode pad disposed in a first region on the insulating layer to be brought into contact with the source electrode, and a drain electrode pad disposed in a second region separated from the first region on the insulating layer and brought into contact with the plurality of via contacts contacting the drain electrode. | 01-31-2013 |
| 20130026486 | EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE - Provided is a crack-free epitaxial substrate having excellent breakdown voltage properties in which a silicon substrate is used as a base substrate thereof. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer including a composition modulation layer that is formed of a first composition layer made of AlN and a second composition layer made of Al | 01-31-2013 |
| 20130026487 | NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT - An object of the present invention is to provide a nitride semiconductor light emitting element having a novel transparent electrode. The nitride semiconductor light emitting element has the transparent electrode on a p-type nitride semiconductor layer, wherein the p-type nitride semiconductor layer and the transparent electrode can be in good ohmic contact to each other and wherein the variability of the forward voltage (Vf) within the wafer can be reduced. | 01-31-2013 |
| 20130026488 | EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE - Provided is a crack-free epitaxial substrate having excellent breakdown voltage properties in which a silicon substrate is used as a base substrate thereof. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer including a plurality of composition modulation layers each formed of a first composition layer made of AlN and a second composition layer made of Al | 01-31-2013 |
| 20130032810 | LED ON SILICON SUBSTRATE USING ZINC-SULFIDE AS BUFFER LAYER - A vertical GaN-based blue LED has an n-type GaN layer that was grown over a ZnS layer that in turn was grown directly on a silicon substrate. In one example, the ZnS layer is a transitional buffer layer that is 50 nm thick, and the n-type GaN layer is at least 2000 nm thick. Growing the n-type GaN layer on the ZnS buffer layer reduces lattice defect density in the n-type layer. The ZnS buffer layer provides a good lattice constant match with the silicon substrate and provides a compound polar template for subsequent GaN growth. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate and the ZnS buffer layer are then removed. Electrodes are added and the structure is singulated to form finished LED devices. | 02-07-2013 |
| 20130032811 | METHOD AND SYSTEM FOR A GAN VERTICAL JFET UTILIZING A REGROWN GATE - A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction. | 02-07-2013 |
| 20130032812 | METHOD AND SYSTEM FOR A GAN VERTICAL JFET UTILIZING A REGROWN CHANNEL - A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction, and the channel region extends along at least a portion of the second surface of the gate region. | 02-07-2013 |
| 20130032813 | METHOD AND SYSTEM FOR DOPING CONTROL IN GALLIUM NITRIDE BASED DEVICES - A method of growing a III-nitride-based epitaxial structure includes providing a substrate in an epitaxial growth reactor and heating the substrate to a predetermined temperature. The method also includes flowing a gallium-containing gas into the epitaxial growth reactor and flowing a nitrogen-containing gas into the epitaxial growth reactor. The method further includes flowing a gettering gas into the epitaxial growth reactor. The predetermined temperature is greater than 1000° C. | 02-07-2013 |
| 20130032814 | METHOD AND SYSTEM FOR FORMATION OF P-N JUNCTIONS IN GALLIUM NITRIDE BASED ELECTRONICS - A semiconductor device includes a III-nitride substrate having a first conductivity type and a first electrode electrically coupled to the III-nitride substrate. The semiconductor device also includes a III-nitride material having a second conductivity type coupled to the III-nitride substrate at a regrowth interface and a p-n junction disposed between the III-nitride substrate and the regrowth interface. | 02-07-2013 |
| 20130032815 | LIGHT EMITTING DIODE ARRAY AND METHOD FOR MANUFACTURING THE SAME - An LED array includes a substrate, protrusions formed on a top surface of the substrate, and LEDs formed on the top surface of the substrate and located at a top of the protrusions. The LEDs are electrically connected with each other. Each LED includes a connecting layer, an n-type GaN layer, an active layer, and a p-type GaN layer formed on a top of the protrusions in sequence. A bottom surface of the n-type GaN layer connecting the connecting layer has a roughened exposed portion. The bottom surface of the n-type GaN layer has an N-face polarity. | 02-07-2013 |
| 20130032816 | HIGH ELECTRON MOBILITY TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - High electron mobility transistors (HEMTs) including a substrate and a HEMT stack on the substrate, the HEMT stack including a compound semiconductor layer that includes a 2-dimensional electron gas (2DEG), an upper compound semiconductor layer that has a polarization index higher than a polarization index of the compound semiconductor layer, and a source electrode, a drain electrode, and a gate that are disposed on the upper compound semiconductor layer. The substrate may be a nitride substrate that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of a silicon substrate. The substrate may include an insulating layer that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of the silicon substrate, a metal layer that is deposited on the insulating layer, and a plate that is attached to the metal layer. | 02-07-2013 |
| 20130032817 | POWER AMPLIFIER - A power amplifier includes a semiconductor substrate including transistor cells, a drain electrode for the transistor cells located on the semiconductor substrate, a drain pad located on the semiconductor substrate and connected to the drain electrode, an ion-implanted resistance located in the semiconductor substrate and extending along and in contact with the drain pad, a floating electrode located on the semiconductor substrate and in contact with the ion-implanted resistance, and an output matching circuit located outside the semiconductor substrate. The power amplifier further includes a wire connecting the drain pad to the output matching circuit. | 02-07-2013 |
| 20130032818 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a buffer layer that is disposed over a substrate, a high-resistance layer that is disposed over the buffer layer, the high-resistance layer being doped with a transition metal for achieving high resistance, a low-resistance region that is disposed in a portion of the high-resistance layer or over the high-resistance layer, the low-resistance region being doped with an impurity element for achieving low resistance, an electron travel layer that is disposed over the high-resistance layer including the low-resistance region, an electron supply layer that is disposed over the electron travel layer, a gate electrode that is disposed over the electron supply layer, and a source electrode and a drain electrode that are disposed over the electron supply layer. | 02-07-2013 |
| 20130032819 | SEMICONDUCTOR TRANSISTOR - The semiconductor transistor according the present invention includes an active layer composed of a GaN-based semiconductor and a gate insulating film formed on the active layer. The gate insulating film has a first insulating film including one or more compounds selected from the group consisting of Al | 02-07-2013 |
| 20130032820 | Optoelectronic Component and Method for Producing an Optoelectronic Component - The invention concerns an optoelectronic component ( | 02-07-2013 |
| 20130037819 | LIGHT EMITTING DEVICE - Disclosed are a light emitting device, a method of manufacturing the light emitting device, a light emitting device package and a lighting system. The light emitting device includes a silicon substrate; a nitride buffer layer on the silicon substrate; and a gallium nitride epitaxial layer on the nitride buffer layer, wherein the nitride buffer layer includes a first nitride buffer layer having a first aluminum nitride layer on the silicon substrate and a first gallium nitride layer on the first aluminum nitride layer. | 02-14-2013 |
| 20130037820 | NITROGEN COMPOUND SEMICONDUCTOR LIGHT EMITTING ELEMENT AND MANUFACTURING METHOD THEREOF - A nitrogen compound semiconductor light emitting element having an n-type layer, an active layer comprising AlGaInN and a p-type layer, emitting ultraviolet radiation with an emission peak wavelength of at most 400 nm and having a high emission intensity as well as a manufacturing method thereof are provided. In the nitrogen compound semiconductor light emitting element of the present invention having an n-type layer, an active layer and a p-type layer, the active layer consists of a nitrogen compound semiconductor layer with an emission peak wavelength of at most 400 nm comprising AlGaN, and the n-type layer has an n-type AlGaN layer comprising AlGaN and a GaN protective layer which does not contain Al and has a thickness of at least 5 nm. The active layer is formed on the protective layer. The manufacturing method comprises processes of growing the n-type AlGaN layer at a high substrate temperature of at least 1000° C.; growing the GaN protective layer of at most 400 nm not containing Al thereon; interrupting the growth process and decreasing the substrate temperature; and forming the active layer on the protective layer at a low substrate temperature of less than 1000° C. | 02-14-2013 |
| 20130043481 | HIGH-VOLTAGE SOLID-STATE TRANSDUCERS AND ASSOCIATED SYSTEMS AND METHODS - High-voltage solid-state transducer (SST) devices and associated systems and methods are disclosed herein. An SST device in accordance with a particular embodiment of the present technology includes a carrier substrate, a first terminal, a second terminal and a plurality of SST dies connected in series between the first and second terminals. The individual SST dies can include a transducer structure having a p-n junction, a first contact and a second contact. The transducer structure forms a boundary between a first region and a second region with the carrier substrate being in the first region. The first and second terminals can be configured to receive an output voltage and each SST die can a forward junction voltage less than the output voltage. | 02-21-2013 |
| 20130043482 | HIGH LINEARITY BANDGAP ENGINEERED TRANSISTOR - A high linearity bandgap engineered transistor device is provided. In one example configuration, the device generally includes a substrate and an oxide layer formed on the substrate. The device further includes a wide-bandgap body material formed between a portion of the oxide layer and a gate dielectric layer. The wide-bandgap body material has an energy bandgap of 1.35 eV or higher and is lattice matched to the substrate. The device further includes a source-drain material formed on the oxide layer adjacent to the wide-bandgap body material so as to define a hetero-structure interface where the source-drain material contacts the wide-bandgap body material. The wide-bandgap body material is also lattice matched to the source-drain material. The device further includes a gate material formed over the gate dielectric layer. Other features and variations will be apparent in light of this disclosure. | 02-21-2013 |
| 20130043483 | HIGH LINEARITY HYBRID TRANSISTOR DEVICE - A hybrid transistor device is provided. In one example case, the device includes a substrate, an oxide layer formed on the substrate, and a wide-bandgap body material formed between a portion of the oxide layer and a gate dielectric layer. The wide-bandgap body material has an energy bandgap higher than that of silicon. The device includes source-drain/emitter material formed on the oxide layer adjacent to the wide-bandgap body material so as to define a hetero-structure interface where the source-drain/emitter material contacts the wide-bandgap body material. The device includes a gate material formed over the gate dielectric layer, a base material formed over a portion of the source-drain/emitter material, and a collector material formed over a portion of the base material. The source-drain/emitter material is shared so as to electrically combine a drain of a first transistor type portion of the device and an emitter of a second transistor type portion. | 02-21-2013 |
| 20130043484 | HEMT WITH INTEGRATED LOW FORWARD BIAS DIODE - A high electron mobility transistor includes a source, gate and drain, a first III-V semiconductor region having a two-dimensional electron gas (2DEG) which provides a first conductive channel controllable by the gate between the source and drain, and a second III-V semiconductor region below the first III-V semiconductor region and having a second conductive channel connected to the source or drain and not controllable by the gate. The first and second III-V semiconductor regions are spaced apart from one another by a region of the high electron mobility transistor having a different band gap than the first and second III-V semiconductor regions. | 02-21-2013 |
| 20130043485 | GaN-BASED SEMICONDUCTOR DEVICE - A p-type GaN-based semiconductor device is provided. Porivded is a GaN-based semiconductor device including: a first channel layer which is formed from a GaN-based semiconductor, and in which a carrier gas of a first conductivity type occurs; a barrier layer formed on the first channel layer from a GaN-based semiconductor having a higher bandgap than the first channel layer; and a second channel layer which is formed on the barrier layer from a GaN-based semiconductor having a lower bandgap than the barrier layer, and in which a carrier gas of a second conductivity type occurs, wherein the carrier concentration of the carrier gas of the second conductivity type is lower in a region below a first gate electrode than in other regions between a first source electrode and a first drain electrode, and is controlled by the first gate electrode. | 02-21-2013 |
| 20130043486 | SYSTEM AND METHODS FOR PREPARING FREESTANDING FILMS USING LASER-ASSISTED CHEMICAL ETCH, AND FREESTANDING FILMS FORMED USING SAME - Systems and methods for preparing freestanding films using laser-assisted chemical etch (LACE), and freestanding films formed using same, are provided. In accordance with one aspect a substrate has a surface and a portion defining an isotropically defined cavity; and a substantially continuous film is disposed at the substrate surface and spans the isotropically defined cavity. In accordance with another aspect, a substrate has a surface and a portion defining an isotropically defined cavity; and a film is disposed at the substrate surface and spans the isotropically defined cavity, the film including at least one of hafnium oxide (HfO | 02-21-2013 |
| 20130043487 | LAYOUT DESIGN FOR A HIGH POWER, GaN-BASED FET - A FET includes a first and second set of finger arrays that each include a source, gate and drain. A first source pad is electrically coupled to source electrodes in the first set of finger arrays. A second source pad is electrically coupled to the source electrodes in the second set of finger arrays. A common drain pad is electrically coupled to drain electrodes in the first and second set of finger arrays. A first gate pad is electrically coupled to gate electrodes in the first set of finger arrays. A second gate pad is electrically coupled to gate electrodes in the second set of finger arrays. A substrate is also provided on which are disposed the first and second set of finger arrays, the first and second source pads, the common drain pad, and the first and second gate pads. | 02-21-2013 |
| 20130043488 | EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE - Provided is a crack-free epitaxial substrate having excellent breakdown voltage properties in which a silicon substrate is used as a base. The epitaxial substrate includes a (111) single crystal Si substrate and a buffer layer including a plurality of first lamination units. Each of those units includes a composition modulation layer formed of a first composition layer made of AlN and a second composition layer made of Al | 02-21-2013 |
| 20130049007 | WIDE-BANDGAP SEMICONDUCTOR DEVICE - A wide-bandgap semiconductor device includes: a semiconductor substrate made of a semiconductor material having a bandgap larger than 1.42 eV; a semiconductor layer on the semiconductor substrate and made of a semiconductor material having a bandgap larger than 1.42 eV; and an active region in the semiconductor layer and including a transistor, wherein the wide-bandgap semiconductor device is opaque to light in a visible light wavelength range, from a wavelength of 360 nm to a wavelength of 830 nm. | 02-28-2013 |
| 20130049008 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - A light emitting device according to the embodiment includes a support substrate; a first light emitting structure disposed on the support substrate and including a first conductive type first semiconductor layer, a first active layer, and a second conductive type second semiconductor layer; a first reflective electrode under the first light emitting structure; a first metal layer around the first reflective electrode; a second light emitting structure disposed on the support substrate and including a first conductive type third semiconductor layer, a second active layer, and a second conductive type fourth semiconductor layer; a second reflective electrode under the second light emitting structure; a second metal layer around the second reflective electrode; and a contact part making contact with an inner portion of the first conductive type first semiconductor layer of the first light emitting structure and electrically connected to the second reflective electrode. | 02-28-2013 |
| 20130049009 | Substrate For Vertical Light-Emitting Diode - A multi-layer substrate for a vertical light-emitting diode (LED) includes a conductive and reflective base substrate and an n-type gallium nitride (GaN) layer formed on the base substrate. | 02-28-2013 |
| 20130049010 | HIGH DENSITY GALLIUM NITRIDE DEVICES USING ISLAND TOPOLOGY - A Gallium Nitride (GaN) series of devices—transistors and diodes are disclosed—that have greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The devices also include a simpler and superior flip chip connection scheme and a means to reduce the thermal resistance. A simplified fabrication process is disclosed and the layout scheme which uses island electrodes rather than finger electrodes is shown to increase the active area density by two to five times that of conventional inter-digitated structures. Ultra low on resistance transistors and very low loss diodes can be built using the island topology. Specifically, the present disclosure provides a means to enhance cost/effective performance of all lateral GaN structures. | 02-28-2013 |
| 20130056743 | METHOD AND SYSTEM FOR LOCAL CONTROL OF DEFECT DENSITY IN GALLIUM NITRIDE BASED ELECTRONICS - A diode includes a substrate characterized by a first dislocation density and a first conductivity type, a first contact coupled to the substrate, and a masking layer having a predetermined thickness and coupled to the semiconductor substrate. The masking layer comprises a plurality of continuous sections and a plurality of openings exposing the substrate and disposed between the continuous sections. The diode also includes an epitaxial layer greater than 5 μm thick coupled to the substrate and the masking layer. The epitaxial layer comprises a first set of regions overlying the plurality of openings and characterized by a second dislocation density and a second set of regions overlying the set of continuous sections and characterized by a third dislocation density less than the first dislocation density and the second dislocation density. The diode further includes a second contact coupled to the epitaxial layer. | 03-07-2013 |
| 20130056744 | Semiconductor Devices with Guard Rings - Semiconductor devices with guard rings are described. The semiconductor devices may be, e.g., transistors and diodes designed for high-voltage applications. A guard ring is a floating electrode formed of electrically conducting material above a semiconductor material layer. A portion of an insulating layer is between at least a portion of the guard ring and the semiconductor material layer. A guard ring may be located, for example, on a transistor between a gate and a drain electrode. A semiconductor device may have one or more guard rings. | 03-07-2013 |
| 20130056745 | Buffer Layer for GaN-on-Si LED - A buffer layer of zinc telluride (ZnTe) or titanium dioxide (TiO | 03-07-2013 |
| 20130056746 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an electron-transit layer made of a semiconductor, the electron-transit layer having a first band gap; an electron-supply layer disposed on the electron-transit layer, the electron-supply layer being made of a semiconductor having a second band gap that is wider than the first band gap; a barrier-forming layer disposed on the electron-supply layer, the barrier-forming layer being made of a semiconductor having a third band gap that is narrower than the second band gap; an upper-channel layer disposed on the barrier-forming layer, the upper-channel layer being made of a semiconductor doped with an impurity; a side-surface of the barrier-forming layer and the upper-channel layer formed by partly removing the barrier-forming layer and the upper-channel layer; an insulating-film disposed on the side-surface; a gate-electrode disposed on the insulating-film; a source-electrode connected to the upper-channel layer; and a drain-electrode connected to the electron-supply layer or the electron-transit layer. | 03-07-2013 |
| 20130056747 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A nitride semiconductor light emitting device and a manufacturing method thereof are provided. The nitride semiconductor light emitting device includes: forming a first conductivity-type nitride semiconductor layer on a substrate; forming an active layer on the first conductivity-type nitride semiconductor layer; and forming a second conductivity-type nitride semiconductor layer on the active layer. High output can be obtained by increasing doping efficiency in growing the conductivity type nitride semiconductor layer. | 03-07-2013 |
| 20130056748 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - A light emitting device includes a light emitting layer, a substrate that is transparent to an emission wavelength of the light emitting layer and positioned to receive an emission wavelength from the light emitting layer, a convex pattern including a collection of a plurality of convex portions discretely arranged on a front surface of the substrate with a first pitch, an n type nitride semiconductor layer located on the front surface of the substrate to cover the convex pattern and a p type nitride semiconductor layer located on the light emitting layer. The light emitting layer is located on the n type semiconductor layer. Each of the convex portions includes a sub convex pattern comprising a plurality of fine convex portions discretely formed at the top of the convex portion with a second pitch smaller than the first pitch, and a base supporting the sub convex pattern. | 03-07-2013 |
| 20130056749 | BROAD-AREA LIGHTING SYSTEMS - In accordance with certain embodiments, illumination systems are formed by aligning light-emitting elements with optical elements and/or disposing light-conversion materials on the light-emitting elements, as well as by providing electrical connectivity to the light-emitting elements | 03-07-2013 |
| 20130056750 | NITRIDE BASED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME AND BONDING SUBSTRATE - A nitride based semiconductor package includes a nitride based semiconductor device, a package substrate, and a bonding substrate. The semiconductor device includes, on a surface thereof, a first electrode pattern having a source electrode, a drain electrode and a gate electrode. The bonding substrate includes, on a first surface thereof, a second electrode pattern corresponding to the first electrode pattern, and at least one first groove pattern. The first groove pattern exposes the second electrode pattern. The first electrode pattern is received in the at least one first groove pattern. The second electrode pattern is bonded to the first electrode pattern received in the at least one first groove pattern. A second surface of the bonding substrate is bonded to the package substrate. | 03-07-2013 |
| 20130056751 | Method for Integrating MEMS Microswitches on Gan Substrates Comprising Electronic Power Components - Methods of fabrication of electronic modules comprise, on the one hand, power electronic components fabricated on a substrate made of gallium nitride (GaN) and, on the other hand, micro-switches using electrostatic activation of the MEMS (Micro Electro Mechanical System) type. The electronic components and the micro-switches are fabricated on a single gallium nitride substrate and the fabrication method comprises at least the following steps: fabrication of the power components on the gallium nitride substrate; deposition of a first common passivation layer on said components and on the substrate; fabrication of the micro-switches on said substrate. | 03-07-2013 |
| 20130062609 | III-N FET ON SILICON USING FIELD SUPPRESSING REO - A III-N on silicon substrate with enhanced breakdown voltage including a rare earth oxide structure deposited on the silicon substrate and a layer of single crystal III-N semiconductor material deposited on the rare earth oxide structure. The rare earth oxide has a dielectric constant greater (approximately twice) than the III-N semiconductor material. The rare earth oxide structure is selected to cooperate with the layer of single crystal III-N semiconductor material to reduce the thickness of the layer of single crystal III-N semiconductor material required for a selected breakdown voltage to a value less than a thickness of the layer of single crystal III-N semiconductor material for the selected breakdown voltage without the cooperating single crystal rare earth oxide. | 03-14-2013 |
| 20130062610 | LATTICE MATCHED CRYSTALLINE REFLECTOR - A virtual substrate structure with a lattice matched crystalline reflector for a light emitting device including a single crystal rare earth oxide layer deposited on a silicon substrate and substantially crystal lattice matched to the silicon substrate. A reflective layer of single crystal electrically conductive material is deposited on the layer of single crystal rare earth oxide and a layer of single crystal semiconductor material is positioned in overlying relationship to the reflective layer and substantially crystal lattice matched to the reflective layer. A single crystal rare earth oxide layer is optionally deposited between the reflective layer and the layer of semiconductor material. | 03-14-2013 |
| 20130062611 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes: a first semiconductor layer made of Al | 03-14-2013 |
| 20130062612 | NITRIDE SEMICONDUCTOR DEVICE, NITRIDE SEMICONDUCTOR WAFER, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAYER - According to one embodiment, a nitride semiconductor device includes a foundation layer, a first stacked intermediate layer, and a functional layer. The foundation layer includes an AlN buffer layer formed on a substrate. The first stacked intermediate layer is provided on the foundation layer. The first stacked intermediate layer includes a first AlN intermediate layer provided on the foundation layer, a first AlGaN intermediate layer provided on the first AlN intermediate layer, and a first GaN intermediate layer provided on the first AlGaN intermediate layer. The functional layer is provided on the first stacked intermediate layer. The first AlGaN intermediate layer includes a first step layer in contact with the first AlN intermediate layer. An Al composition ratio in the first step layer decreases stepwise in a stacking direction from the first AlN intermediate layer toward the first step layer. | 03-14-2013 |
| 20130062613 | LIGHT EMITTING DEVICE - According to one embodiment, a light emitting device includes a first lead, a light emitting element, a second lead and a molded body. The light emitting element is fixed on the first lead. The second lead is provided away from the first lead and electrically connected to the light emitting element via a metal wire. The, molded body made of a sealing resin covers the light emitting element, end portions of the first lead and the second lead, the light emitting element being fixed on the end portion of the first read, and the metal wire being bonded on the end portion of the second lead. The first groove is provided between first and second portions in a front surface of the second lead, the first portion being in contact with an outer edge of the molded body and the metal wire being bonded on the second portion. | 03-14-2013 |
| 20130062614 | GROUP III-V ENHANCEMENT MODE TRANSISTOR WITH THYRISTOR GATE - An apparatus includes an enhancement mode transistor having multiple Group III-V layers above a substrate and a gate above the Group III-V layers. The gate includes multiple layers of material that form at least a portion of a thyristor. The multiple layers of material may include a first p-type layer of material, an n-type layer of material on the first p-type layer, and a second p-type layer of material on the n-type layer. The multiple layers of material may also include a p-type layer of material, an n-type layer of material on the p-type layer, and a Schottky metal layer on the n-type layer. The enhancement mode transistor may represent a high electron mobility transistor (HEMT) or a heterostructure field effect transistor (HFET). | 03-14-2013 |
| 20130062615 | SOLID STATE LIGHTING DEVICES WITH SELECTED THERMAL EXPANSION AND/OR SURFACE CHARACTERISTICS, AND ASSOCIATED METHODS - Solid state lighting (SSL) devices and methods are disclosed. A particular method includes forming an SSL formation structure having a CTE, selecting a first material of an interlayer structure to have a first material CTE greater than the substrate CTE, and selecting a second material based at least in part on the second material having a CTE less than the first material CTE. The intelayer structure is formed over the SSL formation structure e.g., with a first layer of the first material over the SSL formation structure, a portion of the second material over the first material, and a second layer of the first material over the second material. The CTE difference between the first and second materials can counteract a force placed on the formation structure by the first material. Particular formation structures can have an off-cut angle with a non-zero value of up to about 4.5 degrees. | 03-14-2013 |
| 20130062616 | GaN-BASED FIELD EFFECT TRANSISTOR - A GaN-based field effect transistor (MOSFET) is comprised of a channel layer comprised of p-type GaN, an electron supply layer, a surface layer having band gap energy smaller than that of said electron supply layer, sequentially laminated on a substrate, and recess section is formed by removing a part of the drift layer, the electron supply layer, and the surface layer down to a depth that reaches to the channel layer. A source electrode and a drain electrode are formed so that the recess section positions between them, a gate insulation film is formed on the surface layer and on inner-surface of the recess section including the channel layer, and a gate electrode is formed on the gate insulating film in the recess section. | 03-14-2013 |
| 20130062617 | LIGHT EMITTING DIODE STRUCTURE WITH TRANSPARENT CONDUCTIVE HEAT DISSIPATION FILM - An LED structure includes a sapphire substrate, an epitaxy light emitting structure, a transparent conductive heat dissipation film, a first metal contact layer and a second metal contact layer. The transparent conductive heat dissipation film is electrically conductive and thermally radiative, and has a surface microscopic crystalline structure. The heat generated by the epitaxy light emitting structure is propagated by thermal radiation in a direction from the upper surface to the lower surface of the transparent conductive heat dissipation film. The transparent conductive heat dissipation film successfully replaces the transparent ITO (indium tin oxide) film to provide similar optical and electrical feature and performs fast heat dissipation by directive thermal radiation. The heat dissipation and efficiency of light emitting are greatly improved so as to prolong the lifetime of LED and final LED products. | 03-14-2013 |
| 20130062618 | LIGHT EMITTING DIODE WITH THERMORADIATION HEAT-DISSIPATION LAYERS - A light emitting diode (LED) includes a sapphire substrate, a first thermoradiation heat-dissipation layer, a second thermoradiation heat-dissipation layer, an epitaxy light emitting structure, a first metal contact layer and a second metal contact layer. The first and second thermoradiation heat-dissipation layers are fabricated from a mixture of metal and nonmetal, and are fabricated on the upper and lower surfaces of the sapphire substrate, respectively. The heat generated by the epitaxy light emitting structure propagates through the first and second thermoradiation heat-dissipation layers by directive thermal radiation. The efficiency of heat dissipation is improved to increase the efficiency of light emitting and prolong the lifespan of LED and LED products. | 03-14-2013 |
| 20130069071 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer. Therefore, negative charge is higher than positive charge at the interface between the cap layer and the barrier layer and the interface between the channel layer and the buffer layer, while positive charge is higher than negative charge at the interface between the barrier layer and the channel. The channel layer has a stacked layer structure of a first layer, a second layer, and a third layer. The second layer has a higher electron affinity than those of the first layer and the third layer. | 03-21-2013 |
| 20130069072 | SEMICONDUCTOR CRYSTAL SUBSTRATE, MANUFACTURING METHOD OF SEMICONDUCTOR CRYSTAL SUBSTRATE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, POWER UNIT, AND AMPLIFIER - A semiconductor crystal substrate includes a substrate; and a protection layer formed by applying nitride on a surface of the substrate. The protection layer is in an amorphous state in a peripheral area at an outer peripheral part of the substrate, and the protection layer is crystallized in an internal area of the protection layer that is inside the peripheral area of the protection layer. | 03-21-2013 |
| 20130069073 | White Organic Light Emitting Device - The white organic light emitting device for improved efficiencies includes an anode and a cathode opposing each other on a substrate, a charge generation layer between the anode and the cathode, a first stack and a second stack interposed between the anode and the charge generation layer, and between the charge generation layer and the cathode, respectively, wherein at least one of a first hole transport layer and a second hole transport layer has a triplet energy level higher than a triplet energy level of the light emitting layer adjacent thereto, and a difference between a triplet energy level and a singlet energy level of 0.01 eV to 0.6 eV. | 03-21-2013 |
| 20130069074 | POWER DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an example embodiment, a power device includes a substrate, a nitride-containing stack on the substrate, and an electric field dispersion unit. Source, drain, and gate electrodes are on the nitride-containing stack. The nitride-containing stack includes a first region that is configured to generate a larger electric field than that of a second region of the nitride-containing stack. The electric field dispersion unit may be between the substrate and the first region of the nitride-containing stack. | 03-21-2013 |
| 20130069075 | NITRIDE SEMICONDUCTOR CRYSTAL PRODUCING METHOD, NITRIDE SEMICONDUCTOR EPITAXIAL WAFER, AND NITRIDE SEMICONDUCTOR FREESTANDING SUBSTRATE - A nitride semiconductor crystal producing method, a nitride semiconductor epitaxial wafer, and a nitride semiconductor freestanding substrate, by which it is possible to suppress the occurrence of cracking in the nitride semiconductor crystal and to ensure the enhancement of the yield of the nitride semiconductor crystal. The nitride semiconductor crystal producing method includes growing a nitride semiconductor crystal over a seed crystal substrate, while applying an etching action to an outer end of the seed crystal substrate during the growing of the nitride semiconductor crystal. | 03-21-2013 |
| 20130069076 | NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - Provided is a nitride semiconductor device comprising a base substrate; a buffer layer formed above the base substrate; an active layer formed on the buffer layer; and at least two electrodes formed above the active layer. The buffer layer includes one or more composite layers that each have a plurality of nitride semiconductor layers with different lattice constants, and at least one of the one or more composite layers is doped with carbon atoms and oxygen atoms in at least a portion of a carrier region of the nitride semiconductor having the largest lattice constant among the plurality of nitride semiconductor layers, the carrier region being a region in which carriers are generated due to the difference in lattice constants between this nitride semiconductor layer and the nitride semiconductor layer formed directly thereon. | 03-21-2013 |
| 20130069077 | White Organic Light Emitting Device - Disclosed white organic light emitting device includes an anode and a cathode opposing each other; a charge generation layer interposed between the anode and the cathode; a first stack interposed between the anode and the charge generation layer, the first stack including a first hole transport layer and a first light emitting layer emitting blue fluorescent light; and a second stack interposed between the charge generation layer and the cathode, the second stack including a second hole transport layer and a second light emitting layer formed by doping one host with at least one of phosphorescent dopant, wherein a triplet energy level of the first hole transport layer is higher than a triplet energy level of the first light emitting layer, and a hole mobility of the first hole transport layer is 5.0×10 | 03-21-2013 |
| 20130069078 | CRYSTAL PRODUCING APPARATUS, CRYSTAL PRODUCING METHOD, SUBSTRATE PRODUCING METHOD, GALLIUM NITRIDE CRYSTAL, AND GALLIUM NITRIDE SUBSTRATE - A crystal producing apparatus includes a crystal forming unit and a crystal growing unit. The crystal forming unit forms a first gallium nitride (GaN) crystal by supplying nitride gas into melt mixture containing metal sodium (Na) and metal gallium (Ga). The first GaN crystal is sliced and polished to form GaN wafers. The crystal growing unit grows a second GaN crystal on a substrate formed by using a GaN wafer, by the hydride vapor phase epitaxy method, thus producing a bulked GaN crystal. | 03-21-2013 |
| 20130069079 | Method of Producing Template for Epitaxial Growth and Nitride Semiconductor Device - A surface of a sapphire (0001) substrate is processed so as to have recesses and protrusions so that protrusion tops are made flat and have a given plan-view pattern. An initial-stage AlN layer is epitaxially grown on the surface of the sapphire (0001) substrate so that new recesses are formed over the recesses, by performing C axis orientation control so that a C+ axis oriented AlN layer grows on flat surfaces of the protrusion tops, excluding edges. A first ELO layer including an AlN (0001) layer is epitaxially grown on the initial-stage AlN layer by an epitaxial lateral overgrowth method, and stops growing before a recess upper region above the new recesses is completely covered with the first ELO layer that is laterally grown from a protrusion upper surface of the initial-stage AlN layer. A second ELO layer including an Al | 03-21-2013 |
| 20130075748 | METHOD AND SYSTEM FOR DIFFUSION AND IMPLANTATION IN GALLIUM NITRIDE BASED DEVICES - A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer. | 03-28-2013 |
| 20130075749 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; a first p-type semiconductor layer formed between the electron supply layer and the gate electrode; and a second p-type semiconductor layer formed between the electron supply layer and at least one of the source electrode and the drain electrode. The one of the source electrode and the drain electrode on the second p-type semiconductor layer includes: a first metal film; and a second metal film Which contacts the first metal film on the gate electrode side of the first metal film, and a resistance of which is higher than that of the first metal film. | 03-28-2013 |
| 20130075750 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer formed on a substrate; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer; and a source electrode and a drain electrode formed on the second semiconductor layer. The third semiconductor layer is formed with a semiconductor material doped with a p-type impurity element. In the third semiconductor layer, a p-type area is formed immediately below the gate electrode, and a high resistance area having a higher resistance than the p-type area is formed in an area other than the p-type area. | 03-28-2013 |
| 20130075751 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; a p-type semiconductor layer formed between the electron supply layer and the gate electrode; and a hole barrier layer formed between the electron supply layer and the p-type semiconductor layer, a band gap of the hole barrier layer being larger than that of the electron supply layer. | 03-28-2013 |
| 20130075752 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first semiconductor layer formed on a substrate; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer; and a source electrode and a drain electrode formed in contact with the second semiconductor layer, wherein a semiconductor material of the third semiconductor layer is doped with a p-type impurity element; and the third semiconductor layer has a jutting out region that juts out beyond an edge of the gate electrode toward a side where the drain electrode is provided. | 03-28-2013 |
| 20130075753 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate comprised of gallium nitride; an active layer provided on the substrate; a first buffer layer that is provided between the substrate and the active layer and is comprised of indium aluminum nitride (In | 03-28-2013 |
| 20130075754 | SEMICONDUCTOR DEVICE, FABRICATION METHOD OF THE SEMICONDUCTOR DEVICES - In a semiconductor device, a YAG substrate is formed as a single-crystal substrate of any of surface orientations (100), (110), and (111). In the fabrication of the semiconductor device, a TMAl gas is first fed onto the YAG substrate so as to form a nucleation layer made of aluminum, which is a group-III element. Then, an NH | 03-28-2013 |
| 20130075755 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a light emitting device and a manufacturing method thereof. The light emitting device comprises a first conductive semiconductor layer with a lower surface being uneven in height, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer. | 03-28-2013 |
| 20130082273 | P-TYPE DOPING LAYERS FOR USE WITH LIGHT EMITTING DEVICES - A light emitting diode (LED) comprises an n-type Group III-V semiconductor layer, an active layer adjacent to the n-type Group III-V semiconductor layer, and a p-type Group III-V semiconductor layer adjacent to the active layer. The active layer includes one or more V-pits. A portion of the p-type Group III-V semiconductor layer is in the V-pits. A p-type dopant injection layer provided during the formation of the p-type Group III-V layer aids in providing a predetermined concentration, distribution and/or uniformity of the p-type dopant in the V-pits. | 04-04-2013 |
| 20130082274 | LIGHT EMITTING DEVICES HAVING DISLOCATION DENSITY MAINTAINING BUFFER LAYERS - A method for forming a light emitting device comprises forming a buffer layer having a plurality of layers comprising a substrate, an aluminum gallium nitride layer adjacent to the substrate, and a gallium nitride layer adjacent to the aluminum gallium nitride layer. During the formation of each of the plurality of layers, one or more process parameters are selected such that an individual layer of the plurality of layers is strained. | 04-04-2013 |
| 20130082275 | METHOD FOR GROWING CONFORMAL EPI LAYERS AND STRUCTURE THEREOF - A method for forming a conformal buffer layer of uniform thickness and a resulting semiconductor structure are disclosed. The conformal buffer layer is used to protect highly-doped extension regions during formation of an epitaxial layer that is used for inducing mechanical stress on the channel region of transistors. | 04-04-2013 |
| 20130082276 | NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention relates to a nitride semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a nitride semiconductor device including: a nitride semiconductor layer having a 2DEG channel; a source electrode in ohmic contact with the nitride semiconductor layer; a drain electrode in ohmic contact with the nitride semiconductor layer; a p-type nitride layer formed on the nitride semiconductor layer between the source and drain electrodes; an n-type nitride layer formed on the p-type nitride layer; and a gate electrode formed between the source and drain electrodes to be close to the source electrode and in contact with the n-type nitride layer so that a source-side sidewall thereof is aligned with source-side sidewalls of the p-type and n-type nitride layers is provided. Further, a method of manufacturing a nitride semiconductor device is provided. | 04-04-2013 |
| 20130082277 | NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention relates to a nitride semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a nitride semiconductor device including: a nitride semiconductor layer having a 2DEG channel; a source electrode in ohmic contact with the nitride semiconductor layer; a drain electrode in ohmic contact with the nitride semiconductor layer; a plurality of p-type nitride semiconductor segments formed on the nitride semiconductor layer and each formed lengthways from a first sidewall thereof, which is spaced apart from the source electrode, to a drain side; and a gate electrode formed to be close to the source electrode and in contact with the nitride semiconductor layer between the plurality of p-type semiconductor segments and portions of the p-type semiconductor segments extending in the direction of a source-side sidewall of the gate electrode aligned with the first sidewalls of the p-type nitride semiconductor segments is provided. | 04-04-2013 |
| 20130082278 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A nitride semiconductor device and a method to produce the same are disclosed. The method includes steps of sequentially growing a channel layer and a first layer with bandgap energy Eg greater than that of channel layer; forming a gate replica on the first layer; selectively growing a second layer with Eg also greater than or equal to Eg of the channel layer; removing the gate replica to form a recess in the second layer; and forming the gate electrode in the recess and onto the first layer. | 04-04-2013 |
| 20130082279 | GROUP III-V SUBSTRATE MATERIAL WITH PARTICULAR CRYSTALLOGRAPHIC FEATURES - A substrate including a body comprising a Group III-V material and having an upper surface, the body comprising an offcut angle defined between the upper surface and a crystallographic reference plane, and the body further having an offcut angle variation of not greater than about 0.6 degrees. | 04-04-2013 |
| 20130087803 | MONOLITHICALLY INTEGRATED HEMT AND SCHOTTKY DIODE - An integrated device including a III-nitride HEMT and a Schottky diode includes a substrate comprising a first III-nitride material and a drift region comprising a second III-nitride material coupled to the substrate and disposed adjacent to the substrate along a vertical direction. The integrated device also includes a first barrier layer coupled to the drift region and a channel layer comprising a third III-nitride material having a first bandgap and coupled to the barrier layer. The integrated device further includes a second barrier layer characterized by a second bandgap and coupled to the channel layer and a Schottky contact coupled to the drift region. The second bandgap is greater than the first bandgap. | 04-11-2013 |
| 20130087804 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A carrier channel depleting layer is disposed on the second III-V compound layer. The carrier channel depleting layer is deposited using plasma and a portion of the carrier channel depleting layer is under at least a portion of the gate electrode. | 04-11-2013 |
| 20130087805 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer and a light emitting layer. The emitting layer is provided between the n-type layer and the p-type layer, and includes a plurality of barrier layers and a plurality of well layers, being alternately stacked. The p-side barrier layer being closest to the p-type layer among the plurality of barrier layer includes a first layer and a second layer, containing group III elements. An In composition ratio in the group III elements of the second layer is higher than an In composition ratio in the group III elements of the first layer. An average In composition ratio of the p-side layer is higher than an average In composition ratio of an n-side barrier layer that is closest to the n-type layer among the plurality of barrier layers. | 04-11-2013 |
| 20130087806 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a light emitting unit, a second semiconductor layer, a reflecting electrode, an oxide layer and a nitrogen-containing layer. The first semiconductor layer is of a first conductivity type. The light emitting unit is provided on the first semiconductor layer. The second semiconductor layer is provided on the light emitting unit and is of a second conductivity type. The reflecting electrode is provided on the second semiconductor layer and includes Ag. The oxide layer is provided on the reflecting electrode. The oxide layer is insulative and has a first opening. The nitrogen-containing layer is provided on the oxide layer. The nitrogen-containing layer is insulative and has a second opening communicating with the first opening. | 04-11-2013 |
| 20130087807 | EPITAXIAL GROWTH SUBSTRATE, SEMICONDUCTOR DEVICE, AND EPITAXIAL GROWTH METHOD - In heteroepitaxially growing a group-III nitride semiconductor on a Si single crystal substrate, the occurrence of cracks initiating in the wafer edge portion can be suppressed. Region A is an outermost peripheral portion outside the principal surface, being a bevel portion tapered. Regions B and C are on the same plane (the principal surface), region B (mirror-surface portion) being the center portion of the principal surface, and region C a region in the principal surface edge portion surrounding region B. The principal surface has a plane orientation, and in region B, is mirror-surface-finished. Region B occupies most of the principal surface of this Si single crystal substrate, and a semiconductor device is manufactured therein. Region C (surface-roughened portion) has a plane orientation as with region B, however, region B is mirror-surface-finished, whereas region C is surface-roughened. | 04-11-2013 |
| 20130092947 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING - In some embodiments, a metal insulator semiconductor heterostructure field effect transistor (MISHFET) is disclosed that has a source, a drain, an insulation layer, a gate dielectric, and a gate. The source and drain are on opposing sides of a channel region of a channel layer. The channel region is an upper portion of the channel layer. The channel layer comprises gallium nitride. The insulation layer is over the channel layer and has a first portion and a second portion. The first portion is nearer the drain than the source and has a first thickness. The second portion is nearer the source than drain and has the first thickness. The insulation layer has an opening through the insulation layer. The opening is between the first portion and the second portion. | 04-18-2013 |
| 20130092948 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE - The semiconductor device having flip chip structure includes: an insulating substrate; a signal wiring electrode disposed on the insulating substrate; a power wiring electrode disposed on the insulating substrate or disposed so as to pass through the insulating substrate; a semiconductor chip disposed in flip chip configuration on the insulating substrate and comprising a semiconductor substrate, a source pad electrode and a gate pad electrode disposed on a surface of the semiconductor substrate, and a drain pad electrode disposed on a back side surface of the semiconductor substrate; agate connector disposed on the gate pad electrode; and a source connector disposed on the source pad electrode. The gate connector, the gate pad electrode and the signal wiring electrode are bonded, and the source connector, the source pad electrode and the power wiring electrode are bonded, by using solid phase diffusion bonding. | 04-18-2013 |
| 20130092949 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×10 | 04-18-2013 |
| 20130092950 | NITRIDE SEMICONDUCTOR GROWTH SUBSTRATE AND MANUFACTURING METHOD OF THE SAME, NITRIDE SEMICONDUCTOR EPITAXIAL SUBSTRATE AND NITRIDE SEMICONDUCTOR ELEMENT - A nitride semiconductor growth substrate includes a principal surface including a C-plane of a sapphire substrate, and a convex portion that is formed on the principal surface, has a cone or pyramid shape or a truncated cone or pyramid shape, is disposed to form a lattice pattern in a top view thereof, and includes a side surface inclined at an angle of less than 90 degrees relative to the principal surface. The convex portion has a height of 0.5 to 3 μm from the principal surface. A distance between adjacent ones of the convex portion is 1 to 6 μm. The side surface of the convex portion has a surface roughness (RMS) of not more than 10 nm. | 04-18-2013 |
| 20130092951 | GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate. | 04-18-2013 |
| 20130092952 | SEMICONDUCTOR DEVICE - A transistor which includes an electron transit layer and an electron supply layer which are stacked in a thickness direction of a substrate; an electron transit layer formed over the substrate in parallel to the electron transit layer and the electron supply layer; an anode electrode which forms a Schottky junction with the electron transit layer; and a cathode electrode which forms an ohmic junction with the electron transit layer are provided. The anode electrode is connected to a source of the transistor, and the cathode electrode is connected to a drain of the transistor. | 04-18-2013 |
| 20130092953 | EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE - Provided is a crack-free epitaxial substrate having a small amount of warping, in which a silicon substrate is used as a base substrate. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer formed of a plurality of lamination units being continuously laminated. The lamination unit includes: a composition modulation layer formed of a first and a second unit layer having different compositions being alternately and repeatedly laminated such that a compressive strain exists therein; a termination layer formed on an uppermost portion of the composition modulation layer, the termination layer acting to maintain the compressive strain existing in the composition modulation layer; and a strain reinforcing layer formed on the termination layer, the strain reinforcing layer acting to enhance the compressive strain existing in the composition modulation layer. | 04-18-2013 |
| 20130099243 | SUBSTRATE BREAKDOWN VOLTAGE IMPROVEMENT FOR GROUP III-NITRIDE ON A SILICON SUBSTRATE - A circuit structure includes a substrate, a nucleation layer of undoped aluminum nitride, a graded buffer layer comprising aluminum, gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant, a ungraded buffer layer comprising gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant without aluminum, and a bulk layer of undoped gallium nitride over the ungraded buffer layer. The various dopants in the graded buffer layer and the ungraded buffer layer increases resistivity and results in layers having an intrinsically balanced conductivity. | 04-25-2013 |
| 20130099244 | METHOD OF GROWING SEMICONDUCTOR HETEROSTRUCTURES BASED ON GALLIUM NITRIDE - The method of growing non-polar epitaxial heterostructures for light-emitting diodes producing white emission and lasers, on the basis of compounds and alloys in AlGaInN system, comprising the step of vapor-phase deposition of one or multiple heterostructures layers described by the formula Al | 04-25-2013 |
| 20130099245 | FIELD EFFECT TRANSISTOR, METHOD FOR PRODUCING THE SAME, AND ELECTRONIC DEVICE - The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer | 04-25-2013 |
| 20130099246 | SUBSTRATE FOR EPITAXIAL GROWTH - A surface of the substrate consists in plurality of neighbouring stripe shaped flat surfaces of a width from 1 to 2000 μm. Longer edges of the flat surfaces are parallel one to another and planes of these surfaces are disoriented relatively to the crystallographic plane of gallium nitride crystal defined by Miller-Bravais indices (0001), (11-22) or (11-20). Disorientation angle of each of the flat surfaces is between 0 and 3 degree and is different for each pair of neighbouring flat surfaces. Substrate according to the invention allows epitaxial growth of a layered AlInGaN structure by MOCVD or MBE method which permits for realization of a non-absorbing mirrors laser diode emitting a light of the wavelength from 380 to 550 nm and a laser diodes array which may emit simultaneously light of various wavelengths in the range of 380 to 550 nm. | 04-25-2013 |
| 20130099247 | SEMICONDUCTOR DEVICES HAVING A RECESSED ELECTRODE STRUCTURE - An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance. | 04-25-2013 |
| 20130099248 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - There is provided a nitride semiconductor light emitting device including an n-type nitride semiconductor layer, an active layer disposed on the n-type nitride semiconductor layer, and a p-type nitride semiconductor layer disposed on the active layer. One or more current diffusion layers are disposed on a surface of the n-type nitride semiconductor layer. The current diffusion layer(s) includes a material having greater band gap energy than that of a material forming the n-type nitride semiconductor layer so as to form a two-dimensional electron gas layer at an interface with the material forming the n-type nitride semiconductor layer. | 04-25-2013 |
| 20130099249 | NITRIDE UV LIGHT SENSORS ON SILICON SUBSTRATES - An ultraviolet light sensor and method of manufacturing thereof are disclosed. The ultraviolet light sensor includes Group-III Nitride layers adjacent to a silicon wafer with one of the layers at least partially exposed such that a surface thereof can receive UV light to be detected. The Group-III Nitride layers include a p-type layer and an n-type layer, with p/n junctions therebetween forming at least one diode. Conductive contacts are arranged to conduct electrical current through the sensor as a function of ultraviolet light received at the outer Group-III Nitride layer. The Group-III Nitride layers may be formed from, e.g., GaN, InGaN, AlGaN, or InAlN. The sensor may include a buffer layer between one of the Group-III Nitride layers and the silicon wafer. By utilizing silicon as the substrate on which the UV sensor diode is formed, a UV sensor can be produced that is small, efficient, cost-effective, and compatible with other semiconductor circuits and processes. The sensor may be configured to be sensitive to a specific subtype or subband of ultraviolet radiation to be detected by selecting a specific composition of said Group-III Nitride layers. | 04-25-2013 |
| 20130105808 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME | 05-02-2013 |
| 20130105809 | LIGHT EMITTING DIODE CHIP WITH HIGH HEAT-DISSIPATION EFFICIENCY | 05-02-2013 |
| 20130105810 | COMPOUND SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC CIRCUIT | 05-02-2013 |
| 20130105811 | FIELD EFFECT TRANSISTOR, METHOD FOR PRODUCING THE SAME, AND ELECTRONIC DEVICE | 05-02-2013 |
| 20130105812 | SEMICONDUCTOR DEVICE | 05-02-2013 |
| 20130105813 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 05-02-2013 |
| 20130105814 | Active Area Shaping for III-Nitride Devices | 05-02-2013 |
| 20130105815 | DIODE | 05-02-2013 |
| 20130112985 | MONOLITHICALLY INTEGRATED VERTICAL JFET AND SCHOTTKY DIODE - An integrated device including a vertical III-nitride FET and a Schottky diode includes a drain comprising a first III-nitride material, a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, and a channel region comprising a third III-nitride material coupled to the drift region. The integrated device also includes a gate region at least partially surrounding the channel region, a source coupled to the channel region, and a Schottky contact coupled to the drift region. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride FET and the Schottky diode is along the vertical direction. | 05-09-2013 |
| 20130112986 | Gallium Nitride Semiconductor Devices and Method Making Thereof - The present disclosure relates to an enhancement mode gallium nitride (GaN) transistor device. The GaN transistor device has an electron supply layer located on top of a GaN layer. An etch stop layer (e.g., AlN) is disposed above the electron supply layer. A gate structure is formed on top of the etch stop layer, such that the bottom surface of the gate structure is located vertically above the etch stop layer. The position of etch stop layer in the GaN transistor device stack allows it to both enhance gate definition during processing (e.g., selective etching of the gate structure located on top of the AlN layer) and to act as a gate insulator that reduces gate leakage of the GaN transistor device. | 05-09-2013 |
| 20130112987 | LIGHT EMITTING DIODE AND FABRICATING METHOD THEREOF - A light emitting diode including a GaN substrate, a first type semiconductor layer, a light emitting layer, a second type semiconductor layer, a first electrode, and a second electrode is provided. The GaN substrate has a first surface and a second surface opposite thereto, and the second surface has a plurality of protuberances, the height of the protuberance is h μm and the distribution density of the protuberance on the second surface is d cm | 05-09-2013 |
| 20130112988 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND WAFER - A semiconductor light emitting device includes a first layer including at least one of n-type GaN and n-type AlGaN; a second layer including Mg-containing p-type AlGaN; and a light emitting section provided between the first and second layers. The light emitting section includes barrier layers of Si-containing Al | 05-09-2013 |
| 20130112989 | BROAD-AREA LIGHTING SYSTEMS - In accordance with certain embodiments, illumination systems are formed by aligning light-emitting elements with optical elements and/or disposing light-conversion materials on the light-emitting elements, as well as by providing electrical connectivity to the light-emitting elements | 05-09-2013 |
| 20130112990 | Gallium Nitride Devices with Compositionally-Graded Transition Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of o semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 05-09-2013 |
| 20130119393 | Vertical Gallium Nitride Schottky Diode - A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction nitride-based Schottky diode is thus realized. In another embodiment, a protection circuit for a vertical GaN Schottky diode employs a silicon-based vertical PN junction diode connected in parallel to the GaN Schottky diode to divert reverse bias avalanche current. | 05-16-2013 |
| 20130119394 | Termination Structure for Gallium Nitride Schottky Diode - A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure. | 05-16-2013 |
| 20130119395 | Tunnel FET and Methods for Forming the Same - A tunnel field-effect transistor (TFET) includes a gate electrode, a source region, and a drain region. The source and drain regions are of opposite conductivity types. A channel region is disposed between the source region and the drain region. A source diffusion barrier is disposed between the channel region and the source region. The source diffusion barrier and the source region are under and overlapping the gate electrode. The source diffusion barrier has a first bandgap greater than second bandgaps of the source region, the drain region, and the channel region. | 05-16-2013 |
| 20130119396 | TWO-TERMINAL SWITCHING DEVICES AND THEIR METHODS OF FABRICATION - Two-terminal switching devices characterized by high on/off current ratios and by high breakdown voltage are provided. These devices can be employed as switches in the driving circuits of active matrix displays, e.g., in electrophoretic, rotating element and liquid crystal displays. The switching devices include two electrodes, and a layer of a broad band semiconducting material residing between the electrodes. According to one example, the cathode comprises a metal having a low work function, the anode comprises an organic material having a p+ or p++ type of conductivity, and the broad band semiconductor comprises a metal oxide. The work function difference between the cathode and the anode material is preferably at least about 0.6 eV. The on/off current ratios of at least 10,000 over a voltage range of about 15 V can be achieved. The devices can be formed, if desired, on flexible polymeric substrates having low melting points. | 05-16-2013 |
| 20130119397 | NITRIDE-BASED HETEROJUCTION SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACUTRING THE SAME - Disclosed is a semiconductor device. More specifically, disclosed are a nitride-based heterojunction semiconductor device and a method for manufacturing the same. The nitride-based heterojunction semiconductor device includes a first drain electrode, a conductive semiconductor layer including a nitride-based semiconductor disposed on the first drain electrode, a channel layer disposed on the conductive semiconductor layer, a barrier layer disposed on the channel layer, a source electrode and a second drain electrode spaced from each other on the barrier layer, and a gate electrode disposed between the source electrode and the second drain electrode. | 05-16-2013 |
| 20130119398 | NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride-based semiconductor light-emitting device | 05-16-2013 |
| 20130119399 | METHOD FOR TESTING GROUP III-NITRIDE WAFERS AND GROUP III-NITRIDE WAFERS WITH TEST DATA - The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced from an ingot can be estimated from measurement data obtained from selected number of wafers sliced from the same ingot or an ingot before slicing. These estimated properties can be used for product certificate of untested wafers. This scheme can reduce a significant amount of time, labor and cost related to quality control. | 05-16-2013 |
| 20130119400 | SELF-ALIGNED SIDEWALL GATE GaN HEMT - A method of fabricating a GaN HEMT includes growing a first epitaxial layer on a substrate, growing a second epitaxial layer on the first epitaxial layer, growing a third epitaxial layer on the second epitaxial layer, depositing a first dielectric film on the third epitaxial layer, using dielectric films to form a first sidewall dielectric spacer, forming a sidewall gate adjacent the first sidewall dielectric spacer. The sidewall gate may be made to be less than 50 nm in length. | 05-16-2013 |
| 20130119401 | LARGE AREA NITRIDE CRYSTAL AND METHOD FOR MAKING IT - Techniques for processing materials in supercritical fluids including processing in a capsule disposed within a high-pressure apparatus enclosure are disclosed. The disclosed techniques are useful for growing crystals of GaN, AlN, InN, and their alloys, including InGaN, AlGaN, and AlInGaN for the manufacture of bulk or patterned substrates, which in turn can be used to make optoelectronic devices, lasers, light emitting diodes, solar cells, photoelectrochemical water splitting and hydrogen generation devices, photodetectors, integrated circuits, and transistors. | 05-16-2013 |
| 20130119402 | LIGHT EMITTING DEVICE - Disclosed is a method for fabricating a light emitting device. The method includes forming an oxide including gallium aluminum over a gallium oxide substrate, forming a nitride including gallium aluminum over the oxide including gallium aluminum and forming a light emitting structure over the nitride including gallium aluminum. | 05-16-2013 |
| 20130119403 | Semiconductor Structure and a Method of Forming the Same - Some embodiments show a semiconductor structure including a substrate with a {100} crystal surface plane which includes a plurality of adjacent structured regions at a top side of the substrate. The plurality of adjacent structured regions includes adjacent substrate surfaces with {111} crystal planes and a III-V semiconductor material layer above the top side of the substrate. A semiconductor device region includes at least one semiconductor device structure. The semiconductor device region is arranged above the plurality of adjacent structured regions at the top side of the substrate. | 05-16-2013 |
| 20130119404 | DEVICE STRUCTURE INCLUDING HIGH-THERMAL-CONDUCTIVITY SUBSTRATE - Methods and apparatuses for forming a device structure including a high-thermal-conductivity substrate are disclosed herein. A method forming such a device structure may comprise forming an active layer over a first substrate in a manner such that a frontside of the active layer faces the first substrate and a backside of the active layer faces away from the first substrate, forming a second substrate over the backside of the active layer, and removing the first substrate to expose the frontside of the active layer. Other embodiments are described and claimed. | 05-16-2013 |
| 20130126884 | ALUMINUM GALLIUM NITRIDE ETCH STOP LAYER FOR GALLIUM NITRIDE BASES DEVICES - A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure. | 05-23-2013 |
| 20130126885 | METHOD AND SYSTEM FOR FABRICATING FLOATING GUARD RINGS IN GAN MATERIALS - A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer. | 05-23-2013 |
| 20130126886 | GAN-BASED SCHOTTKY BARRIER DIODE WITH ALGAN SURFACE LAYER - A method of fabricating a Schottky diode using gallium nitride (GaN) materials includes providing an n-type GaN substrate having a first surface and a second surface. The second surface opposes the first surface. The method also includes forming an ohmic metal contact electrically coupled to the first surface of the n-type GaN substrate and forming an n-type GaN epitaxial layer coupled to the second surface of the n-type GaN substrate. The method further includes forming an n-type aluminum gallium nitride (AlGaN) surface layer coupled to the n-type GaN epitaxial layer and forming a Schottky contact electrically coupled to the n-type AlGaN surface layer. | 05-23-2013 |
| 20130126887 | LIGHT EMITTING DIODE - An LED includes a seat and an LED chip. The seat includes a main body, a first electrode protruding upwardly from the main body, and a second electrode formed on the main body. The LED chip includes a substrate, a first semiconductor layer disposed on the substrate, a light-emitting layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the light-emitting layer, and a third electrode fixed on the second semiconductor layer. The first electrode extends through the substrate and electrically connects with the first semiconductor layer, and the third electrode electrically connects with the second electrode via a wire. | 05-23-2013 |
| 20130126888 | Edge Termination by Ion Implantation in GaN - An edge terminated semiconductor device is described including a GaN substrate; a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region, wherein the ion-implanted region has a resistivity that is at least 90% of maximum resistivity and a conductive layer, such as a Schottky metal layer, disposed over the GaN epitaxial layer, wherein the conductive layer overlaps a portion of the ion-implanted region. A Schottky diode is prepared using the Schottky contact structure. | 05-23-2013 |
| 20130126889 | Manufacturable Enhancement-Mode Group III-N HEMT with a Reverse Polarization Cap - An enhancement-mode group III-N high electron mobility transistor (HEMT) with a reverse polarization cap is formed in a method that utilizes a reverse polarization cap structure, such as an InGaN cap structure, to deplete the two-dimensional electron gas (2DEG) and form a normally off device, and a spacer layer that lies below the reverse polarization cap structure and above the barrier layer of the HEMT which allows the reverse polarization cap layer to be etched without etching into the barrier layer. | 05-23-2013 |
| 20130126890 | INTEGRATING ACTIVE MATRIX INORGANIC LIGHT EMITTING DIODES FOR DISPLAY DEVICES - A method of forming an active matrix, light emitting diode (LED) array includes removing, from a base substrate, a layer of inorganic LED material originally grown thereupon; and bonding the removed layer of inorganic LED material to an active matrix, thin film transistor (TFT) backplane array. | 05-23-2013 |
| 20130126891 | MICRO LIGHT EMITTING DIODE - A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate. | 05-23-2013 |
| 20130126892 | P-Type Amorphous GaNAs Alloy as Low Resistant Ohmic Contact to P-Type Group III-Nitride Semiconductors - A new composition of matter is described, amorphous GaN | 05-23-2013 |
| 20130126893 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A nitride semiconductor layer formed from a nitride semiconductor is provided on at least one surface side of a semiconductor substrate. Impurity regions (a source region, a drain region, and the like) are provided on one surface side in the nitride semiconductor layer and contain an impurity of a first conductivity type. In addition, amorphous regions (a first amorphous region and a second amorphous region) are a part of the impurity regions and are located in a surface layer of the impurity regions. In addition, metallic layers (a source electrode and a drain electrode) come into contact with the amorphous regions (the first amorphous region and the second amorphous region). | 05-23-2013 |
| 20130126894 | LOW VOLTAGE DIODE WITH REDUCED PARASITIC RESISTANCE AND METHOD FOR FABRICATING - A method of making a diode begins by depositing an Al | 05-23-2013 |
| 20130126895 | Gallium Nitride Devices with Vias - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. | 05-23-2013 |
| 20130126896 | III-V SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING THE SAME - Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation. | 05-23-2013 |
| 20130126897 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An electrode ( | 05-23-2013 |
| 20130126898 | GALLIUM NITRIDE COMPOUND SEMICONDUCTOR LIGHT EMITTING ELEMENT AND LIGHT SOURCE PROVIDED WITH SAID LIGHT EMITTING ELEMENT - In a gallium nitride based compound semiconductor light-emitting element including an active layer, the active layer includes a well layer | 05-23-2013 |
| 20130126899 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor light emitting device includes: a light emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer; and a first electrode on the first conductive type semiconductor layer, wherein the light emitting structure includes an outer groove formed at an outer area of the light emitting structure, wherein a thickness of an outmost area of the light emitting structure is smaller than a thickness of an center area of the light emitting structure, and wherein the first conductive type semiconductor layer includes AlGaN layer and the second conductive type semiconductor layer includes AlGaN layer. | 05-23-2013 |
| 20130126900 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - Around a nitride-based semiconductor light-emitting element which has a polarization characteristic, a transparent encapsulating member which has a cylindrical shape is provided such that the symmetry plane of the cylindrical shape forms an angle of 25° to 65° with respect to the polarization direction of the nitride-based semiconductor light-emitting element. | 05-23-2013 |
| 20130126901 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A semiconductor light-emitting element according to the present invention includes: an n-type nitride semiconductor layer | 05-23-2013 |
| 20130126902 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light-emitting element according to the present invention includes: an n-type nitride semiconductor layer | 05-23-2013 |
| 20130134433 | Metallization structure for high power microelectronic devices - A semiconductor device structure is disclosed that includes a wide-bandgap semiconductor portion selected from the group consisting of silicon carbide and the Group III nitrides. An interconnect structure is made to the semiconductor portion, and the interconnect structure includes at least two diffusion barrier layers alternating with two respective high electrical conductivity layers. The diffusion barrier layers have a coefficient of thermal expansion different from and lower than the coefficient of thermal expansion of the high electrical conductivity layers. The difference in the respective coefficients of thermal expansions are large enough to constrain the expansion of the high conductivity layers but less than a difference that would create a strain between adjacent layers that would exceed the bond strength between the layers. | 05-30-2013 |
| 20130134434 | NITRIDE SEMICONDUCTOR SUBSTRATE - A nitride semiconductor device includes a main surface and an indicator portion. The main surface is a plane inclined by at least 71° and at most 79° in a [1-100] direction from a (0001) plane or a plane inclined by at least 71° and at most 79° in a [−1100] direction from a (000-1) plane. The indicator portion indicates a (−1017) plane, a (10-1-7) plane, or a plane inclined by at least −4° and at most 4° in the [1-100] direction from these planes and inclined by at least −0.5° and at most 0.5° in a direction orthogonal to the [1-100] direction. | 05-30-2013 |
| 20130134435 | HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE WITH IMPROVED BREAKDOWN VOLTAGE PERFORMANCE - A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided. | 05-30-2013 |
| 20130134436 | METHOD FOR BONDING SEMICONDUCTOR SUBSTRATES - A method is provided for bonding a first substrate carrying a semiconductor device layer on its front surface to a second substrate. The method comprises producing the semiconductor device layer on the front surface of the first substrate, depositing a first metal bonding layer or a stack of metal layers on the first substrate, on top of the semiconductor device layer, depositing a second metal bonding layer or a stack of metal layers on the front surface of the second substrate, depositing a metal stress-compensation layer on the back side of the second substrate, thereafter establishing a metal bond between the first and second substrate, by bringing the first and second metal bonding layers or stacks of layers into mutual contact under conditions of mechanical pressure and temperature suitable for obtaining the metal bond, and removing the first substrate. | 05-30-2013 |
| 20130134437 | METHOD FOR FORMING GALLIUM NITRIDE DEVICES WITH CONDUCTIVE REGIONS - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. | 05-30-2013 |
| 20130134438 | Light Emitting, Photovoltaic Or Other Electronic Apparatus and System - The present invention provides an electronic apparatus, such as a lighting device comprised of light emitting diodes (LEDs) or a power generating apparatus comprising photovoltaic diodes, which may be created through a printing process, using a semiconductor or other substrate particle ink or suspension and using a lens particle ink or suspension. An exemplary apparatus comprises a base; at least one first conductor; a plurality of diodes coupled to the at least one first conductor; at least one second conductor coupled to the plurality of diodes; and a plurality of lenses suspended in a polymer deposited or attached over the diodes. The lenses and the suspending polymer have different indices of refraction. In some embodiments, the lenses and diodes are substantially spherical, and have a ratio of mean diameters or lengths between about 10:1 and 2:1. The diodes may be LEDs or photovoltaic diodes, and in some embodiments, have a junction formed at least partially as a hemispherical shell or cap. | 05-30-2013 |
| 20130134439 | EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT, PN JUNCTION DIODE, AND METHOD FOR MANUFACTURING AN EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT - Provided is an epitaxial substrate for use in a semiconductor element, having excellent characteristics and capable of suitably suppressing diffusion of elements from a cap layer. An epitaxial substrate for use in a semiconductor element, in which a group of group-III nitride layers are laminated on a base substrate such that a (0001) crystal plane of the group of group-III nitride layers is substantially in parallel with a substrate surface of the base substrate, includes: a channel layer made of a first group-III nitride having a composition of In | 05-30-2013 |
| 20130134440 | High-resolution Parallel-detection Sensor Array Using Piezo-Phototronics Effect - A pressure sensor element includes a substrate, a first type of semiconductor material layer and an array of elongated light-emitting piezoelectric nanostructures extending upwardly from the first type of semiconductor material layer. A p-n junction is formed between each nanostructure and the first type semiconductor layer. An insulative resilient medium layer is infused around each of the elongated light-emitting piezoelectric nanostructures. A transparent planar electrode, disposed on the resilient medium layer, is electrically coupled to the top of each nanostructure. A voltage source is coupled to the first type of semiconductor material layer and the transparent planar electrode and applies a biasing voltage across each of the nanostructures. Each nanostructure emits light in an intensity that is proportional to an amount of compressive strain applied thereto. | 05-30-2013 |
| 20130134441 | GAN-BASED LEDS ON SILICON SUBSTRATES WITH MONOLITHICALLY INTEGRATED ZENER DIODES - GaN LEDs monolithically integrated with silicon-based ESD protection diodes. Hybrid MOCVD or HVPE epitaxial systems may be utilized for in-situ epitaxially growth of doped silicon containing films to form both the silicon-based ESD protection diode material stacks as well as a silicon containing transition layer prior to growth of a GaN-based LED material stack. The silicon-based ESD protection diodes may be interconnected with layers of a GaN LED material stack to form Zener diodes connected with the GaN LEDs. | 05-30-2013 |
| 20130140578 | CIRCUIT STRUCTURE HAVING ISLANDS BETWEEN SOURCE AND DRAIN - A circuit structure includes a substrate, an unintentionally doped gallium nitride (UID GaN) layer over the substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. A number of islands are over the donor-supply layer between the gate structure and the drain. The gate structure disposed between the drain and the source. The gate structure is adjoins at least a portion of one of the islands and/or partially disposed over at least a portion of at least one of the islands. | 06-06-2013 |
| 20130140579 | METHOD OF INTEGRATING A PLURALITY OF BENZOCYCLOBUTENE LAYERS WITH A SUBSTRATE AND AN ASSOCIATED DEVICE - A method of integrating benzocyclobutene (BCB) layers with a substrate is provided along with a corresponding device. A method includes forming a first BCB layer on the substrate and depositing a first metal layer on the first BCB layer and within vias defined by the first metal layer. The method also forms a second BCB layer on the first metal layer and deposits a second metal layer on the second BCB layer and within vias defined by the second metal layer. The second metal layer extends through the vias defined by the second metal layer to establish an operable connection with the first metal layer. The first and second metal layers are independent of an electrical connection to any circuit element carried by the substrate, but the first and second metal layers secure the second BCB layer to the underlying structure and reduce the likelihood of delamination. | 06-06-2013 |
| 20130140580 | Optoelectronic Component - An optoelectronic component can be used for mixing electromagnetic radiation having different wavelengths, in particular in the far field. The optoelectronic component includes a carrier. A first semiconductor chip has a first radiation exit surface for emitting electromagnetic radiation in a first spectral range is provided on the carrier and a second semiconductor chip as a second radiation exit surface for emitting electromagnetic radiation in a second spectral range is provided on the carrier. A diffusing layer is provided on the radiation exit surfaces of the semiconductor chips which face away from the carrier. | 06-06-2013 |
| 20130140581 | OPTICAL DEVICE - An optical device is provided. Multi-layer structures are disposed on a substrate, wherein each of the multi-layer structures is consisting of at least two insulated layers with different refractive indexes formed alternately. A buffer layer covers the multi-layer structures, so that said multi-layer structures are disposed between the buffer layer and the substrate, wherein said buffer layer is an un-doped GaN based semiconductor layer. A first conductive semiconductor layer is disposed on the buffer layer. An active layer is disposed on said first conductive semiconductor layer. A second conductive semiconductor layer is disposed on said active layer and a transparent conductive layer is disposed on said second conductive semiconductor layer. | 06-06-2013 |
| 20130140582 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - The present invention relates to a semiconductor device and a method for manufacturing the same. A RESURF layer ( | 06-06-2013 |
| 20130146885 | Vertical GaN-Based Metal Insulator Semiconductor FET - A semiconductor structure includes a III-nitride substrate having a top surface and an opposing bottom surface and a first III-nitride layer of a first conductivity type coupled to the top surface of the III-nitride substrate. The semiconductor structure also includes a second III-nitride layer of a second conductivity type coupled to the first III-nitride layer along a vertical direction and a third III-nitride layer of a third conductivity type coupled to the second III-nitride layer along the vertical direction. The semiconductor structure further includes a first trench extending through a portion of the third III-nitride layer to the first III-nitride layer, a second trench extending through another portion of the third III-nitride layer to the second III-nitride layer, and a first metal layer coupled to the second and the third III-nitride layers. | 06-13-2013 |
| 20130146886 | Vertical GaN JFET with Gate Source Electrodes on Regrown Gate - A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure. | 06-13-2013 |
| 20130146887 | DIODE FOR USE IN A SWITCHED MODE POWER SUPPLY - A tunable depletion diode is provided. Within this depletion diode, there is a depletion mode transistor that is coupled to the anode terminal at its gate and the cathode terminal at its drain. A diode is coupled between the source of the depletion mode transistor and the anode terminal, and a variable capacitor is coupled between the source of the depletion mode transistor and the anode terminal, where the capacitance of the variable capacitor is controls the reverse recovery time of the tunable depletion diode. | 06-13-2013 |
| 20130146888 | MONOLITHIC SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a monolithic semiconductor device including: a substrate; a high electron mobility transistor (HEMT) structure that is a first device structure formed on the substrate; and a laterally diffused metal oxide field effect transistor (LDMOSFET) structure that is a second device structure formed to be connected with the HEMT structure on the substrate.The monolithic semiconductor device according to preferred embodiments of the present invention is a device having characteristics of a normally-off device while maintaining high current characteristics in a normally-on state, thereby improving high current and high voltage operation characteristics. | 06-13-2013 |
| 20130146889 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An embodiment of a compound semiconductor device includes: a substrate; a nitride compound semiconductor stacked structure formed on or above the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. A recess positioning between the gate electrode and the drain electrode in a plan view is formed at a surface of the compound semiconductor stacked structure. | 06-13-2013 |
| 20130146890 | HIGH ELECTRON MOBILITY TRANSISTOR - A high electron mobility transistor (HEMT) according to example embodiments includes a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a reverse diode gate structure on the second semiconductor layer. A source and a drain may be on at least one of the first semiconductor layer and the second semiconductor layer. A gate electrode may be on the reverse diode gate structure. | 06-13-2013 |
| 20130146891 | ENHANCEMENT-MODE HFET CIRCUIT ARRANGEMENT HAVING HIGH POWER AND A HIGH THRESHOLD VOLTAGE - A circuit includes input drain, source and gate nodes. The circuit also includes a group III nitride enhancement-mode HFET having a source, drain and gate and a voltage shifter having a first terminal connected to the gate of the enhancement mode HFET at a common junction. The circuit also includes a load resistive element connected to the common junction. The drain of the enhancement-mode HFET serves as the input drain node, the source of the enhancement-mode HFET serves as the input source node and a second terminal of the voltage shifter serves as the input gate node. | 06-13-2013 |
| 20130146892 | METHOD FOR MANUFACTURING SUBSTRATE FOR SEMICONDUCTOR LIGHT EMITTING ELEMENT AND SEMICONDUCTOR LIGHT EMITTING ELEMENT USING THE SAME - A light emitting element having a recess-protrusion structure on a substrate is provided. A semiconductor light emitting element | 06-13-2013 |
| 20130146893 | SIC CRYSTALLINE ON SI SUBSTRATES TO ALLOW INTEGRATION OF GAN AND SI ELECTRONICS - A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate is provided. The silicon substrate includes the GaN-based device on a SiC crystalline region. The SiC crystalline region is formed in the silicon substrate. The silicon substrate also includes the Si-based device on a silicon region, and the silicon region is next to the SiC crystalline region on the silicon substrate. | 06-13-2013 |
| 20130153917 | INGAN OHMIC SOURCE CONTACTS FOR VERTICAL POWER DEVICES - A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region. The source includes a GaN-layer coupled to an InGaN layer. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction. | 06-20-2013 |
| 20130153918 | REO-Si TEMPLATE WITH INTEGRATED REO LAYERS FOR LIGHT EMISSION - A III-N on silicon LED constructed to emit light in the visible range includes a layer of single crystal III-N with a light emitting diode formed therein and designed to emit light at a first wavelength through a lower surface, a REO-Si template mated to the layer of single crystal III-N and designed to approximately crystal lattice match a silicon substrate, and a light emission layer of rare earth oxide selected to receive and absorb light at the first wavelength, up-convert the absorbed light, and re-emit light at a second wavelength in the visible range. The lower surface of the REO-Si template is either mated to the upper surface of a crystalline silicon substrate with the light emission layer integrated into the REO-Si template or mated to an upper surface of the light emission layer with a lower surface of the light emission layer mated to the crystalline silicon substrate. | 06-20-2013 |
| 20130153919 | III-V Semiconductor Devices with Buried Contacts - A semiconductor device such as a diode or transistor includes a semiconductor substrate, a first region of III-V semiconductor material on the semiconductor substrate and a second region of III-V semiconductor material on the first region. The second region is spaced apart from the semiconductor substrate by the first region. The second region is of a different composition than the first region. The semiconductor device further includes a buried contact extending from the semiconductor substrate to the second region through the first region. The buried contact electrically connects the second region to the semiconductor substrate. | 06-20-2013 |
| 20130153920 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor light emitting device includes a light emitting body including a semiconductor light emitting layer, a support substrate supporting the light emitting body, and a bonding layer provided between the light emitting body and the support substrate, the bonding layer bonding the light emitting body and the support substrate together. The device also includes a first barrier metal layer provided between the light emitting body and the bonding layer, and an electrode provided between the light emitting body and the first barrier metal layer. The first barrier layer includes a first layer made of nickel and a second layer made of a metal having a smaller linear expansion coefficient than nickel, and the first layer and the second layer are alternately disposed in a multiple-layer structure. The electrode is electrically connected to the light emitting body. | 06-20-2013 |
| 20130153921 | NITRIDE SEMICONDUCTOR DEVICE USING SELECTIVE GROWTH AND MANUFACTURING METHOD THEREOF - A semiconductor device including a first GaN layer, an AlGaN layer, a second GaN layer, a gate electrode, a source electrode, and a drain electrode sequentially stacked on a substrate, capable of improving a leakage current and a breakdown voltage characteristics generated in the gate electrode by locally forming a p type GaN layer on the AlGaN layer, and a manufacturing method thereof, and a manufacturing method thereof are provided. | 06-20-2013 |
| 20130153922 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device has a light emitting element, a first electrode layer, a second electrode layer, a seed electrode layer and a plated layer. The light emitting element has a nitride-based III-V compound semiconductor on a substrate and a light extraction surface. The first electrode layer is provided on the light extraction surface. The second electrode layer is provided on a surface opposite to the light extraction surface. The seed electrode layer is configured to cover the entire surface of the second electrode layer. The plated layer is provided on the seed electrode layer. The light emitting element has a light emitting layer, first conductive type semiconductor layer, and second conductive type semiconductor layer, and has a forward tapered shape of a width which gradually narrows in order of the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer. | 06-20-2013 |
| 20130153923 | ENHANCEMENT MODE III-NITRIDE DEVICE AND METHOD FOR MANUFACTURING THEREOF - Enhancement mode III-nitride HEMT and method for manufacturing an enhancement mode III-nitride HEMT are disclosed. In one aspect, the method includes providing a substrate having a stack of layers on the substrate, each layer including a III-nitride material, and a passivation layer having high temperature silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the HT silicon nitride is formed by MOCVD or LPCVD or any equivalent technique at a temperature higher than about 450° C. The method also includes forming a recessed gate region by removing the passivation layer only in the gate region, thereby exposing the underlying upper layer. The method also includes forming a p-doped GaN layer at least in the recessed gate region, thereby filling at least partially the recessed gate region, and forming a gate contact and source/drain contacts. | 06-20-2013 |
| 20130161633 | METHOD AND SYSTEM FOR JUNCTION TERMINATION IN GAN MATERIALS USING CONDUCTIVITY MODULATION - A semiconductor structure includes a GaN substrate having a first surface and a second surface opposing the first surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a first GaN epitaxial layer of the first conductivity type coupled to the second surface of the GaN substrate and a second GaN epitaxial layer of a second conductivity type coupled to the first GaN epitaxial layer. The second GaN epitaxial layer includes an active device region, a first junction termination region characterized by an implantation region having a first implantation profile, and a second junction termination region characterized by an implantation region having a second implantation profile. | 06-27-2013 |
| 20130161634 | METHOD AND SYSTEM FOR FABRICATING EDGE TERMINATION STRUCTURES IN GAN MATERIALS - A method for fabricating an edge termination, which can be used in conjunction with GaN-based materials, includes providing a substrate of a first conductivity type. The substrate has a first surface and a second surface. The method also includes forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The substrate, the first GaN epitaxial layer and the second GaN epitaxial layer can be referred to as an epitaxial structure. | 06-27-2013 |
| 20130161635 | METHOD AND SYSTEM FOR A GAN SELF-ALIGNED VERTICAL MESFET - A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region. | 06-27-2013 |
| 20130161636 | METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES USING THERMAL SPRAY PROCESSES, AND SEMICONDUCTOR STRUCTURES FABRICATED USING SUCH METHODS - Methods for fabricating a semiconductor substrate include forming a first substrate layer over a surface of a first semiconductor layer, and thermally spraying a second substrate layer on a side of the first substrate layer opposite the first semiconductor layer. At least one additional semiconductor layer is epitaxially grown over the first semiconductor layer on a side thereof opposite the first substrate layer. At least one of the first substrate layer and the second substrate layer may be formulated to exhibit a Coefficient of Thermal Expansion (CTE) closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer. Semiconductor structures are fabricated using such methods. | 06-27-2013 |
| 20130161637 | SEMICONDUCTOR DEVICES INCLUDING SUBSTRATE LAYERS AND OVERLYING SEMICONDUCTOR LAYERS HAVING CLOSELY MATCHING COEFFICIENTS OF THERMAL EXPANSION, AND RELATED METHODS - Embodiments relate to semiconductor structures and methods of forming semiconductor structures. The semiconductor structures include a substrate layer having a CTE that closely matches a CTE of one or more layers of semiconductor material formed over the substrate layer. In some embodiments, the substrate layers may comprise a composite substrate material including two or more elements. The substrate layers may comprise a metal material and/or a ceramic material in some embodiments. | 06-27-2013 |
| 20130161638 | HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE WITH IMPROVED BREAKDOWN VOLTAGE PERFORMANCE - A HEMT includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer, and a passivation material layer having one or more buried portions contacting or almost contacting the UID GaN layer. A carrier channel layer at the interface of the donor-supply layer and the UID GaN layer has patches of non-conduction in a drift region between the gate and the drain. A method for making the HEMT is also provided. | 06-27-2013 |
| 20130161639 | DRAIN INDUCED BARRIER LOWERING WITH ANTI-PUNCH-THROUGH IMPLANT - An integrated circuit containing an MOS transistor with epitaxial source and drain regions may be formed by implanting a retrograde anti-punch-through layer prior to etching the source drain regions for epitaxial replacement. The anti-punch-through layer is disposed between stressor tips of the epitaxial source and drain regions, and does not substantially extend into the epitaxial source and drain regions. | 06-27-2013 |
| 20130161640 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device is provided that prevents development of cracks, that has nitride semiconductor thin films with uniform thicknesses and good growth surface flatness, and is thus consistent in characteristics, and that can be fabricated at a satisfactory yield. In this nitride semiconductor device, the nitride semiconductor thin films are grown on a substrate having an off-angle between a direction normal to the surface of ridges and the crystal direction <0001>. This helps either reduce or intentionally promote diffusion or movement of the atoms or molecules of a source material of the nitride semiconductor thin films through migration thereof. As a result, a nitride semiconductor growth layer with good surface flatness can be formed, and thus a nitride semiconductor device with satisfactory characteristics can be obtained. | 06-27-2013 |
| 20130161641 | TRANSISTOR WITH ENHANCED CHANNEL CHARGE INDUCING MATERIAL LAYER AND THRESHOLD VOLTAGE CONTROL - High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region. | 06-27-2013 |
| 20130168685 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. The gate electrode includes a refractory metal. A depletion region is disposed in the carrier channel and under the gate electrode. | 07-04-2013 |
| 20130168686 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. Each of the source feature and the drain feature comprises a corresponding intermetallic compound at least partially embedded in the second III-V compound layer. Each intermetallic compound is free of Au and comprises Al, Ti or Cu. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A depletion region is disposed in the carrier channel and under the gate electrode. | 07-04-2013 |
| 20130168687 | ENHANCEMENT MODE GALLIUM NITRIDE BASED TRANSISTOR DEVICE - Provided is an enhancement mode GaN-based transistor device including an epitaxial stacked layer disposed on a substrate; a source layer and a drain layer disposed on a surface of the epitaxial stacked layer; a p-type metal oxide layer disposed between the source layer and the drain layer; and a gate layer disposed on the p-type metal oxide layer. Besides, the p-type metal oxide layer includes a body part disposed on the surface of the epitaxial stacked layer, and a plurality of extension parts connecting the body part and extending into the epitaxial stacked layer. With such structure, the enhancement mode GaN-based transistor device can effectively suppress generation of the gate leakage current. | 07-04-2013 |
| 20130168688 | NITRIDE BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A nitride based semiconductor device includes a first metallic junction layer, a Schottky junction layer on the first metallic junction layer, a first group III nitride semiconductor layer on the Schottky junction layer, a first insulating pattern layer on the first group III nitride semiconductor layer, the first insulating layer pattern including curved protrusions, a second group III nitride semiconductor layer laterally grown on the first group III nitride semiconductor layer, a first type group III nitride semiconductor layer on the second group III nitride semiconductor layer, the first type group III nitride semiconductor layer being simultaneously doped with aluminum (Al) and silicon (Si), an ohmic junction layer formed on the first type group III nitride semiconductor layer, a second metallic junction layer on the ohmic junction layer, and a metallic supporting substrate on the second metallic junction layer. | 07-04-2013 |
| 20130168689 | NITRIDE BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - With the formation of a Si | 07-04-2013 |
| 20130168690 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four O atoms and hexa-coordinated Al atoms each surrounded by six O atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms. | 07-04-2013 |
| 20130168691 | METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENT, SEMICONDUCTOR LIGHT EMITTING ELEMENT, ELECTRONIC DEVICE, AND MACHINE DEVICE - Provided is a method of manufacturing a semiconductor light emitting element that is capable of making a light emitting wavelength distribution σ of a semiconductor light emitting layer that is obtained small. The method includes a process of laminating a re-growth layer of a compound semiconductor layer on the compound semiconductor substrate which is obtained by forming at least one compound semiconductor layer on a substrate and in which a warping amount H is within a range of 50 μm≦H≦250 μm. The method adopts a method of manufacturing a semiconductor light emitting element including an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer that are formed from a compound semiconductor. This method includes: a process of preparing a compound semiconductor substrate which is obtained by forming at least one compound semiconductor layer on a substrate and in which a warping amount H is within a range of 50 μm≦H≦250 μm; and a process of laminating a re-growth layer of the compound semiconductor layer on the compound semiconductor layer of the compound semiconductor substrate in a metalorganic chemical vapor deposition apparatus. | 07-04-2013 |
| 20130168692 | POLYCRYSTALLINE ALUMINUM NITRIDE BASE MATERIAL FOR CRYSTAL GROWTH OF GaN-BASE SEMICONDUCTOR AND METHOD FOR MANUFACTURING GaN-BASE SEMICONDUCTOR USING THE SAME - There is provided a polycrystalline aluminum nitride substrate that is effective in growing a GaN crystal. The polycrystalline aluminum nitride base material for use as a substrate material for grain growth of GAN-base semiconductors, contains 1 to 10% by weight of a sintering aid component and has a thermal conductivity of not less than 150 W/m·K, the substrate having a surface free from recesses having a maximum diameter of more than 200 μm. | 07-04-2013 |
| 20130168693 | PROTECTIVE-FILM-ATTACHED COMPOSITE SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A protective-film-attached composite substrate includes a support substrate, an oxide film disposed on the support substrate, a semiconductor layer disposed on the oxide film, and a protective film protecting the oxide film by covering a portion that is a part of the oxide film and covered with none of the support substrate and the semiconductor layer. A method of manufacturing a semiconductor device includes the steps of: preparing the protective-film-attached composite substrate; and epitaxially growing, on the semiconductor layer of the protective-film-attached composite substrate, at least one functional semiconductor layer causing an essential function of a semiconductor device to be performed. Thus, there are provided a protective-film-attached composite substrate having a large effective region where a high-quality functional semiconductor layer can be epitaxially grown, and a method of manufacturing a semiconductor device in which the protective-film-attached composite substrate is used. | 07-04-2013 |
| 20130175537 | HIGH ELECTRON MOBILITY GaN-BASED TRANSISTOR STRUCTURE - A high electron mobility GaN-based transistor structure comprises a substrate, an epitaxial GaN layer formed on the substrate, at least one ohmic contact layer formed on the epitaxial GaN layer, a metallic gate layer formed on the epitaxial GaN layer, and a diffusion barrier layer interposed between the metallic gate layer and the epitaxial GaN layer. The diffusion barrier layer hinders metallic atoms of the metallic gate layer from diffusing into the epitaxial GaN layer, whereby are improved the electric characteristics and reliability of the GaN-based transistor. | 07-11-2013 |
| 20130175538 | SUBSTRATE STRUCTURE, SEMICONDUCTOR DEVICE FABRICATED FROM THE SAME, AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - According to example embodiments, a substrate structure may include a GaN-based third material layer, a GaN-based second material layer, a GaN-based first material layer, and a buffer layer on a non-GaN-based substrate. The GaN-based first material layer may be doped with a first conductive type impurity. The GaN-based second material layer may be doped with a second conductive type impurity at a density that is less than a density of the first conductive type impurity in the first GaN-based material layer. The GaN-based third material layer may be doped with a first conductive type impurity at a density that is less than the density of the first conductive type impurity of the GaN-based first material layer. After a second substrate is attached onto the substrate structure, the non-GaN-based substrate may be removed and a GaN-based vertical type semiconductor device may be fabricated on the second substrate. | 07-11-2013 |
| 20130175539 | HIGH ELECTRON MOBILITY TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - According to example embodiments, a high electron mobility transistor (HEMT) includes a channel supply layer and a channel layer. The channel layer may include an effective channel region and a high resistivity region. The effective channel region may be between the high resistivity region and the channel supply layer. The high resistivity region may be a region into which impurities are ion-implanted. According to example embodiments, a method of forming a HEMT includes forming a device unit, including a channel layer and a channel supply layer, on a first substrate; adhering a second substrate to the device unit; removing the first substrate; and forming a high resistivity region by ion-implanting impurities into at least a portion of the channel layer. | 07-11-2013 |
| 20130175540 | DOPED DIAMOND LED DEVICES AND ASSOCIATED METHODS - LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode. | 07-11-2013 |
| 20130175541 | METHOD OF GROWING NITRIDE SEMICONDUCTOR LAYER - A method of growing a nitride semiconductor layer may include preparing a substrate in a reactor, growing a first nitride semiconductor on the substrate at a first temperature, the first nitride semiconductor having a thermal expansion coefficient different from a thermal expansion coefficient of the substrate, and removing the substrate at a second temperature. | 07-11-2013 |
| 20130175542 | Group III-V and Group IV Composite Diode - In one implementation, a group III-V and group IV composite diode includes a group IV diode in a lower active die, the group IV diode having an anode situated on a bottom side of the lower active die. The group III-V and group IV composite diode also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a cathode of the group IV diode using a through-semiconductor via (TSV) of the upper active die. | 07-11-2013 |
| 20130175543 | COMPOSITE GaN SUBSTRATE, METHOD FOR MANUFACTURING COMPOSITE GaN SUBSTRATE, GROUP III NITRIDE SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR DEVICE - A composite GaN substrate of the present invention includes: a conductive GaN substrate having a specific resistance of less than 1 Ωcm; and a semi-insulative GaN layer disposed on the conductive GaN substrate, having a specific resistance of 1×10 | 07-11-2013 |
| 20130175544 | SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - It is an object to attain both high gain and a broad band (that is, to attain both reduction in a gate-drain capacitance and reduction in a source-drain capacitance). Provided is a semiconductor device, including: a GaN channel layer ( | 07-11-2013 |
| 20130181224 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a barrier layer, a spacer structure, and a channel layer. The barrier layer includes a group III nitride. The spacer structure includes first and second aluminum nitride layers and an intermediate layer. The intermediate layer includes a group III nitride and is between the first and second aluminum nitride layers. The intermediate layer has a first free charge carrier density at an interface with the second aluminum nitride layer. The spacer structure is between the barrier layer and the channel layer. The channel layer includes a group III nitride and has a second free charge carrier density at an interface with the first aluminum nitride layer of the spacer structure. The first aluminum nitride layer, the intermediate layer, and the second aluminum nitride layer have layer thicknesses so the first free charge carrier density is less than 10% of the second free charge carrier density. | 07-18-2013 |
| 20130181225 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a metal substrate including a metal base plate, an insulating sheet located on the metal base plate, and a wiring pattern located on the insulating sheet, and a semiconductor element located on the metal substrate. The semiconductor element is sealed with a molding resin. The molding resin extends to side surfaces of the metal substrate. On the side surfaces of the metal substrate, the insulating sheet and the wiring pattern are not exposed from the molding resin, whereas the metal base plate includes a projecting portion exposed from the molding resin. | 07-18-2013 |
| 20130181226 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - There are provided a semiconductor device in which a drain leak current can be reduced in the transistor operation while high vertical breakdown voltage is achieved and a method for producing the semiconductor device. In the semiconductor device, an opening | 07-18-2013 |
| 20130187168 | GaN-CONTAINING SEMICONDUCTOR LIGHT EMITTING DEVICE - A GaN-containing semiconductor light emitting device includes: an n-type semiconductor layer formed of GaN-containing semiconductor, an active layer formed on the n-type semiconductor layer, formed of GaN-containing semiconductor, and having a multiple quantum well structure including a plurality of barrier layers and well layers stacked alternately, and a p-type semiconductor layer formed on the active layer and formed of GaN-containing semiconductor, wherein: the barrier layers comprise: a first barrier layer disposed nearest to the n-type semiconductor layer among the barrier layers and formed of a GaN/AlGaN layer, and second barrier layers disposed nearer to the p-type semiconductor layer than the first barrier layer and including an InGaN/GaN layer which has a layered structure of a InGaN sublayer and a GaN sublayer; and the well layers are each formed of an InGaN layer having a narrower band gap than that in the InGaN sublayer. | 07-25-2013 |
| 20130187169 | SYSTEMS AND METHODS FOR DEPOSITING MATERIALS ON EITHER SIDE OF A FREESTANDING FILM USING SELECTIVE THERMALLY-ASSISTED CHEMICAL VAPOR DEPOSITION (STA-CVD), AND STRUCTURES FORMED USING SAME - Embodiments of the present invention provide systems and methods for depositing materials on either side of a freestanding film using selectively thermally-assisted chemical vapor deposition (STA-CVD), and structures formed using same. A freestanding film, which is suspended over a cavity defined in a substrate, is exposed to a fluidic CVD precursor that reacts to form a solid material when exposed to heat. The freestanding film is then selectively heated in the presence of the precursor. The CVD precursor preferentially deposits on the surface(s) of the freestanding film. | 07-25-2013 |
| 20130187170 | METHOD FOR PRODUCING ALUMINUM NITRIDE CRYSTALS - Provided is a method for producing inexpensive and high-quality aluminum nitride crystals. Gas containing N atoms is introduced into a melt of a Ga—Al alloy, whereby aluminum nitride crystals are made to epitaxially grow on a seed crystal substrate in the melt of the Ga—Al alloy. A growth temperature of aluminum nitride crystals is set at not less than 1000 degrees C. and not more than 1500 degrees C., thereby allowing GaN to be decomposed into Ga metal and nitrogen gas. | 07-25-2013 |
| 20130193441 | Semiconductor Substrates Using Bandgap Material Between III-V Channel Material and Insulator Layer - Improved semiconductor substrates are provided that employ a wide bandgap material between the channel and the insulator. A semiconductor substrate comprises a channel layer comprised of a III-V material; an insulator layer; and a wide bandgap material between the channel layer and the insulator layer, wherein a conduction band offset (ΔE | 08-01-2013 |
| 20130193442 | Light Emitting Device And Method For Manufacturing The Same - Provided are a light emitting device and a method for manufacturing the same. The light emitting device comprises a first conductive type semiconductor layer, an active layer, a second conductive type semiconductor layer, and a light extraction layer. The active layer is formed on the first conductive type semiconductor layer. The second conductive type semiconductor layer is formed on the active layer. The light extraction layer is formed on the second conductive type semiconductor layer. The light extraction layer has a refractive index smaller than or equal to a refractive index of the second conductive type semiconductor layer. | 08-01-2013 |
| 20130193443 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FORMANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor stacked unit and a silver layer. The semiconductor stacked unit includes a light emitting layer, and a semiconductor layer containing gallium provided on the light emitting layer. The silver layer contacts the semiconductor layer. A peak height belonging to a (100) plane of silver is not more than 3% of a peak height belonging to a (111) plane in an X-ray analysis. A detected intensity of a complex of gallium and nitrogen atoms at a first position is 1/100 of a maximum value in the semiconductor layer in a mass analysis. A detected intensity of gallium atoms at a second position at 40 nm distance from the first position is higher than 0.4% and lower than 3.8% of a maximum value of the detected intensity of gallium atoms in the semiconductor layer in the mass analysis. | 08-01-2013 |
| 20130193444 | HIGH VOLTAGE SWITCHING DEVICES AND PROCESS FOR FORMING SAME - The present invention relates to various switching device structures including Schottky diode, P-N diode, and P-I-N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm | 08-01-2013 |
| 20130200387 | NITRIDE BASED HETEROJUNCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A nitride based heterojunction semiconductor device includes a GaN layer on a substrate, an Al-doped GaN layer on the GaN layer, an AlGaN layer on the Al-doped GaN layer, a source electrode, a gate electrode, and a drain electrode on the AlGaN layer, a first field plate on the AlGaN layer, the first field plate being in contact with the gate electrode, and a second field plate on the AlGaN layer, the second field plate being separated from the first field plate by a distance. | 08-08-2013 |
| 20130200388 | NITRIDE BASED HETEROJUNCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A nitride based heterojunction semiconductor device includes a gallium nitride (GaN) layer disposed on a substrate, an aluminum (Al)-doped GaN layer disposed on the GaN layer, a Schottky electrode disposed in a first area on the Al-doped GaN layer, an AlGaN layer disposed in a second area on the Al-doped GaN layer, and an ohmic electrode disposed on the AlGaN layer. The first area is different from the second area. | 08-08-2013 |
| 20130200389 | NITRIDE BASED HETEROJUNCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A nitride based heterojunction semiconductor device includes a gallium nitride (GaN) layer disposed on a substrate, an aluminum (Al)-doped GaN layer disposed on the GaN layer, an AlGaN layer disposed on the Al-doped GaN layer, an ion-implanted layer disposed in an area on the AlGaN layer, excluding a first area and a second area. | 08-08-2013 |
| 20130200390 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light-emitting device includes an n-type semiconductor layer including a nitride semiconductor, a p-type semiconductor layer including a nitride semiconductor, a light-emitting portion and a stacked body. The light-emitting portion is provided between the n-type and p-type semiconductor layers and includes a barrier layer and a well layer. The well layer is stacked with the barrier layer. The stacked body is provided between the light-emitting portion and the n-type semiconductor layer and includes a first layer and a second layer. The second layer is stacked with the first layer. Average In composition ratio of the stacked body is higher than 0.4 times average In composition ratio of the light-emitting portion. The layer thickness t | 08-08-2013 |
| 20130200391 | GALLIUM NITRIDE BASED STRUCTURES WITH EMBEDDED VOIDS AND METHODS FOR THEIR FABRICATION - A gallium nitride-based structure includes a substrate, a first layer of gallium nitride disposed on a growth surface of the substrate, and a second gallium nitride layer disposed on the first gallium nitride layer. The first layer includes a region in which a plurality of voids is dispersed. The second layer has a lower defect density than the gallium nitride of the interfacial region. The gallium nitride-based structure is fabricated by depositing GaN on the growth surface to form the first layer, forming a plurality of gallium nitride nanowires by removing gallium nitride from the first layer, and growing additional GaN from facets of the nanowires. Gallium nitride crystals growing from neighboring facets coalesce to form a continuous second layer, below which the voids are dispersed in the first layer. The voids serve as sinks or traps for crystallographic defects, and also as expansion joints that ameliorate thermal mismatch between the Ga.N and the underlying substrate. The voids also provide improved light transmission properties in optoelectronic applications. | 08-08-2013 |
| 20130207118 | LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF - The present invention discloses an LED and its fabrication method. The LED comprises: a substrate; an epitaxial layer, an active layer and a capping layer arranged on the substrate in sequence; wherein a plurality of bifocal microlens structures are formed on the surface of the substrate away from the epitaxial layer. When the light emitted from the active layer passes through the surfaces of the bifocal microlens structures, the incident angle is always smaller than the critical angle of total reflection, thus preventing total reflection and making sure that most of the light pass through the surfaces of the bifocal microlens structures, in this way improving external quantum efficiency of the LED, avoiding the rise of the internal temperature of the LED and improving the performance of the LED. | 08-15-2013 |
| 20130207119 | LOW-DEFECT DENSITY GALLIUM NITRIDE SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS - A low-defect gallium nitride structure including a first gallium nitride layer comprising a plurality of gallium nitride columns etched into the first gallium nitride layer and a first dislocation density; and a second gallium nitride layer that extends over the gallium nitride columns and comprises a second dislocation density, wherein the second dislocation density may be lower than the first dislocation density. In addition, a method for fabricating a gallium nitride semiconductor layer that includes masking an underlying gallium nitride layer with a mask that comprises an array of columns and growing the underlying gallium nitride layer through the columns and onto said mask using metal-organic chemical vapor deposition pendeo-epitaxy to thereby form a pendeo-epitaxial gallium nitride layer coalesced on said mask to form a continuous pendeo-epitaxial monocrystalline gallium nitride semiconductor layer. | 08-15-2013 |
| 20130207120 | Power Device with Solderable Front Metal - Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson. | 08-15-2013 |
| 20130207121 | POWER CONVERSION DEVICE - A power conversion device includes a power conversion semiconductor element having an electrode, an electrode conductor electrically connected to the electrode of the power conversion semiconductor element and including a side face and an upper end portion having a substantially flat upper end face, and a seal material formed of resin to cover the power conversion semiconductor element and the side face of the electrode conductor. The substantially flat upper end face of the electrode conductor is exposed from an upper surface of the seal material, and the upper end portion of the electrode conductor having the substantially flat upper end face has a projecting portion projecting sideward. | 08-15-2013 |
| 20130214281 | METHOD OF GROWING A HIGH QUALITY III-V COMPOUND LAYER ON A SILICON SUBSTRATE - The present disclosure involves a method of fabricating a semiconductor device. A surface of a silicon wafer is cleaned. A first buffer layer is then epitaxially grown on the silicon wafer. The first buffer layer contains an aluminum nitride (AlN) material. A second buffer layer is then epitaxially grown on the first buffer layer. The second buffer layer includes a plurality of aluminum gallium nitride (Al | 08-22-2013 |
| 20130214282 | III-N ON SILICON USING NANO STRUCTURED INTERFACE LAYER - A method of fabricating a layer of single crystal semiconductor material on a silicon substrate including providing a crystalline silicon substrate and epitaxially depositing a nano structured interface layer on the substrate. The nano structured interface layer has a thickness up to a critical thickness. The method further includes epitaxially depositing a layer of single crystal semiconductor material in overlying relationship to the nano structured interface layer. Preferably, the method includes the nano structured interface layer being a layer of coherently strained nano dots of selected material. The critical thickness of the nano dots includes a thickness up to a thickness at which the nano dots become incoherent. | 08-22-2013 |
| 20130214283 | Power Transistor Having Segmented Gate - There are disclosed herein various implementations of a transistor having a segmented gate region. Such a transistor may include at least one segmentation dielectric segment and two or more gate dielectric segments. The segmentation dielectric segment or segments are thicker than the gate dielectric segments, and is/are situated between the gate dielectric segments. The segmentation dielectric segment or segments cause an increase in the effective gate length so as to improve resistance to punch-through breakdown between a drain electrode and a source electrode of the transistor when the transistor is off. | 08-22-2013 |
| 20130214284 | METHOD FOR THE REUSE OF GALLIUM NITRIDE EPITAXIAL SUBSTRATES - A method for the reuse of gallium nitride (GaN) epitaxial substrates uses band-gap-selective photoelectrochemical (PEC) etching to remove one or more epitaxial layers from bulk or free-standing GaN substrates without damaging the substrate, allowing the substrate to be reused for further growth of additional epitaxial layers. The method facilitates a significant cost reduction in device production by permitting the reuse of expensive bulk or free-standing GaN substrates. | 08-22-2013 |
| 20130214285 | Semiconductor Component and Method for Producing a Semiconductor Component - A semiconductor component has a semiconductor layer sequence made of a nitridic composite semiconductor material on a substrate. The substrate includes a silicon surface facing the semiconductor layer sequence. The semiconductor layer sequence includes an active region and at least one intermediate layer made of an oxygen-doped AN composite semiconductor material between the substrate and the active region. | 08-22-2013 |
| 20130214286 | Method of Manufacturing Light Emitting Device - To make a light emitting device, a light emitting element is placed in a recess of a package, powders having a fluorescent material and coated with inorganic particles are provided, the fluorescent powders, fillers and a resin are mixed, the light emitting element placed in the recess of the package is sealed with the resin, and a centrifugal force is applied to the sealed package so that the fluorescent powders and the fillers sediment are pushed toward a bottom of the recess. | 08-22-2013 |
| 20130214287 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is provided with: a GaN layer; an anode electrode that forms a Schottky junction with a Ga face of the GaN layer; and an InGaN layer positioned between at least a part of the anode electrode and the GaN layer. | 08-22-2013 |
| 20130214288 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND MANUFACTURING METHOD THEREFOR - A nitride-based semiconductor light-emitting device of an embodiment includes a semiconductor multilayer structure having a growing plane which is an m-plane and being made of a GaN-based semiconductor. The semiconductor multilayer structure includes a n-type semiconductor layer, a p-type semiconductor layer, a p-side electrode provided on the p-type semiconductor layer, and an active layer interposed between the n-type semiconductor layer and the p-type semiconductor layer. The ratio of the thickness of the active layer to the thickness of the n-type semiconductor layer, D, is in the range of 1.8×10 | 08-22-2013 |
| 20130221363 | Integrated Schottky Diode for HEMTs - An embodiment of a transistor device includes a compound semiconductor material on a semiconductor carrier and a source region and a drain region spaced apart from each other in the compound semiconductor material with a channel region interposed between the source and drain regions. A Schottky diode is integrated with the semiconductor carrier, and contacts extend from the source and drain regions through the compound semiconductor material. The contacts are in electrical contact with the Schottky diode so that the Schottky diode is connected in parallel between the source and drain regions. In another embodiment, the integrated Schottky diode is formed by a region of doped amorphous silicon or doped polycrystalline silicon disposed in a trench structure on the drain side of the device. | 08-29-2013 |
| 20130221364 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. Two slanted field plates are disposed on the two side walls of the combined opening of the opening in a protection layer and the opening in a dielectric cap layer disposed on the second III-V compound layer. | 08-29-2013 |
| 20130221365 | Method For Processing Semiconductors Using A Combination Of Electron Beam And Optical Lithography - Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN. | 08-29-2013 |
| 20130221366 | NORMALLY-OFF COMPOUND SEMICONDUCTOR TUNNEL TRANSISTOR - Disclosed herein are embodiments of a normally-off compound semiconductor tunnel field effect transistor having a drive current above 100 mA per mm of gate length and a sub-threshold slope below 60 mV per decade at room temperature, and methods of manufacturing such a normally-off compound semiconductor tunnel transistor. The compound semiconductor tunnel field effect transistor is fast-switching and can be used for high voltage applications e.g. 30V up to 600V and higher. | 08-29-2013 |
| 20130221367 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a light emitting layer, a first electrode, a first conductivity type layer, a second conductivity type layer, and a second electrode. The first electrode includes a reflection metal layer. The first conductivity type layer is provided between the light emitting layer and the first electrode. The second conductivity type layer has a first surface on the light emitting layer side and a second surface on an opposite side of the first surface. The second electrode is provided on the second surface of the second conductivity type layer. A plurarity of interfaces, provided between the first conductivity type layer and the reflection metal layer, has at least first concave-convex structures. A region of the second surface of the second conductivity type layer, where the second electrode is not provided, has second concave-convex structures. | 08-29-2013 |
| 20130221368 | ACTIVE LED MODULE - LED modules are disclosed having a control MOSFET, or other transistor, in series with an LED. In one embodiment, a MOSFET wafer is bonded to an LED wafer and singulated to form thousands of active 3-terminal LED modules with the same footprint as a single LED. Despite the different forward voltages of red, green, and blue LEDs, RGB modules may be connected in parallel and their control voltages staggered at 60 Hz or greater to generate a single perceived color, such as white. The RGB modules may be connected in a panel for general illumination or for a color display. A single dielectric layer in a panel may encapsulate all the RGB modules to form a compact and inexpensive panel. Various addressing techniques are described for both a color display and a lighting panel. Various circuits are described for reducing the sensitivity of the LED to variations in input voltage. | 08-29-2013 |
| 20130221369 | OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD FOR THE PRODUCTION THEREOF - An optoelectronic semiconductor chip includes a semiconductor layer stack consisting of a nitride compound semiconductor material on a carrier substrate, wherein the carrier substrate includes a surface containing silicon. The semiconductor layer stack includes a recess extending from a back of the semiconductor layer stack through an active layer to a layer of a first conductivity type. The layer of the first conductivity type connects electrically to a first electrical connection layer which covers at least a portion of the back through the recess. The layer of a second conductivity type connects electrically to a second electrical connection layer arranged at the back. | 08-29-2013 |
| 20130221370 | COMPOUND SEMICONDUCTOR DEVICE - The compound semiconductor device comprises an i-GaN buffer layer | 08-29-2013 |
| 20130221371 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes a substrate; a nitride semiconductor layer formed above the substrate and having a laminated structure including at least three layers; a heterojunction bipolar transistor formed in a region of the nitride semiconductor layer; and a field-effect transistor formed in a region of the nitride semiconductor layer, the region being different from the region in which the heterojunction bipolar transistor is formed. | 08-29-2013 |
| 20130221372 | LIGHT EMITTING DIODE ASSEMBLY AND METHOD FOR FABRICATING THE SAME - The present invention is directed to a light emitting diode (LED) assembly and a method for fabricating the same. According to the present invention, there is provided an LED assembly comprising an LED comprising at least an N-type semiconductor layer and a P-type semiconductor layer; and bumps provided on the LED and electrically connected to the semiconductor layers, wherein the bump comprises a first region made of a gold (Au) compound including tin (Sn) and a second region made of gold. | 08-29-2013 |
| 20130228787 | SEMICONDUCTOR DEVICE - A semiconductor device has a shield plate electrode connected to a source terminal electrode near a drain electrode. The source terminal electrode is arranged between an active region AA and a drain terminal electrode, and a shield plate electrode is connected to the source terminal electrode. | 09-05-2013 |
| 20130228788 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; a gate electrode which is arranged on a first surface of the substrate and has a plurality of gate finger electrodes, a source electrode which is arranged on the first surface of the substrate and has a plurality of source finger electrodes, the source finger electrode is close to the gate finger electrode; a drain electrode which is arranged on the first surface of the substrate and has a plurality of drain finger electrodes, the drain finger electrode faces the source finger electrode via the gate finger electrode; and a shield plate electrode which is arranged on the drain finger electrode and the first surface of the substrate between the gate finger electrode and the drain finger electrode via an insulating layer, is short-circuited to the source finger electrode, and shields electrically the gate finger electrode and the drain finger electrode from each other. | 09-05-2013 |
| 20130228789 | SEMICONDUCTOR DEVICE - A semiconductor device has a shield plate electrode short-circuited to a source electrode near the drain electrode. The shield plate electrode is connected to the source terminal electrode which has a VIA hole via the first line of air-bridge structure or overlay structure. | 09-05-2013 |
| 20130228790 | SEMICONDUCTOR DEVICE - A semiconductor device, comprising: a substrate; a plurality of gate finger electrodes which are arranged on the substrate; a plurality of source finger electrodes which are arranged on the substrate, each source finger electrode is close to the gate finger electrode; a plurality of drain finger electrodes which are arranged on the substrate, each drain finger electrode faces the source finger electrode via the gate finger electrode; a shield plate electrode which is arranged via an insulating layer over the drain finger electrode and the first surface of the substrate between the gate finger electrode and the drain finger electrode, is short-circuited to the source finger electrode, and shields electrically the gate finger electrode and the drain finger electrode from each other; and a slot VIA hole which is formed in the substrate under the source finger electrode and is connected to the source finger electrode. | 09-05-2013 |
| 20130228791 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor light emitting device includes a first conductive semiconductor layer including a V-shaped recess in a cross-sectional view. An active layer is disposed on the first conductive semiconductor layer, conforming to the shape of the V-shaped recess. An intermediate layer is disposed on the active layer and is doped with a first impurity. A second conductive semiconductor layer is disposed on the intermediate layer. The intermediate layer includes a first intermediate layer and a second intermediate layer. The first intermediate layer is disposed on the active layer, conforming to the shape of the V-shape recess. The second intermediate layer is disposed on the first intermediate layer and includes a protrusion to fill the V-shaped recess. | 09-05-2013 |
| 20130228792 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a substrate having a through hole formed in a thickness direction thereof and a conductive nanowire provided in at least a portion of the through hole, and a light emitting structure formed on the substrate and including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. | 09-05-2013 |
| 20130228793 | LIGHT EMITTING DEVICE HAVING A PLURALITY OF NON-POLAR LIGHT EMITTING CELLS AND A METHOD OF FABRICATING THE SAME - The present invention relates to a light emitting device having a plurality of non-polar light emitting cells and a method of fabricating the same. Nitride semiconductor layers are disposed on a Gallium Nitride substrate having an upper surface. The upper surface is a non-polar or semi-polar crystal and forms an intersection angle with respect to a c-plane. The nitride semiconductor layers may be patterned to form light emitting cells separated from one another. When patterning the light emitting cells, the substrate may be partially removed in separation regions between the light emitting cells to form recess regions. The recess regions are filled with an insulating layer, and the substrate is at least partially removed by using the insulating layer. | 09-05-2013 |
| 20130228794 | Stacked Half-Bridge Package with a Common Leadframe - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal. | 09-05-2013 |
| 20130228795 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode. | 09-05-2013 |
| 20130234145 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. In one embodiment, the semiconductor device includes two different semiconductor materials. The two semiconductor materials are arranged adjacent one another in a common plane. | 09-12-2013 |
| 20130234146 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device is disclosed. One embodiment includes a lateral HEMT (High Electron Mobility Transistor) structure with a heterojunction between two differing group III-nitride semiconductor compounds and a layer arranged on the heterojunction. The layer includes a group III-nitride semiconductor compound and at least one barrier to hinder current flow in the layer. | 09-12-2013 |
| 20130234147 | Semiconductor Structures and Methods with High Mobility and High Energy Bandgap Materials - An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin. | 09-12-2013 |
| 20130234148 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING III-V SEMICONDUCTOR MATERIAL USING SUBSTRATES COMPRISING MOLYBDENUM, AND STRUCTURES FORMED BY SUCH METHODS - Methods of fabricating semiconductor structures include the formation of molybdenum nitride at one or more surfaces of a substrate comprising molybdenum, and providing a layer of III-V semiconductor material such as GaN over the substrate. Semiconductor structures formed by methods described herein may include a substrate comprising molybdenum, molybdenum nitride at one or more surfaces of the substrate, and a layer of GaN bonded to the molybdenum nitride. | 09-12-2013 |
| 20130234149 | SIDEWALL TEXTURING OF LIGHT EMITTING DIODE STRUCTURES - A light emitting diode is made using a laser to texture the sidewalls of the bottom contact layer, without damaging a mesa. To do so, the substrate is mounted on a laser machining platform, and trenches are cut along lines through the semiconductor layer on the substrate using a first sequence of laser pulses having short pulse lengths that result in formation of textured sidewalls in the trenches, without causing recasting of the material. Then the substrate can be scribed along the lines of the trenches using a second sequence of laser pulses for singulation of die. | 09-12-2013 |
| 20130234150 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode includes a substrate, a transitional layer on the substrate and an epitaxial layer on the transitional layer. The transitional layer includes a planar area with a flat top surface and a patterned area with a rugged top surface. An AlN material includes a first part consisting of a plurality of spheres and a second part consisting of a plurality of slugs. The spheres are on a top surface of the transitional layer, both at the planar area and the patterned area. The slugs are in grooves defined in the patterned area. Air gaps are formed between the slugs and a bottom surface of the epitaxial layer. The spheres and slugs of the AlN material help reflection of light generated by the epitaxial layer to a light output surface of the LED. | 09-12-2013 |
| 20130234151 | NITRIDE SEMICONDUCTOR ELEMENT AND NITRIDE SEMICONDUCTOR WAFER - According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of Al | 09-12-2013 |
| 20130234152 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device of an embodiment includes a semiconductor layer formed of a III-V group nitride semiconductor, a first silicon nitride film formed on the semiconductor layer, a gate electrode formed on the first silicon nitride film, a source electrode and a drain electrode formed on the semiconductor layer such that the gate electrode is interposed between the source electrode and the drain electrode, and a second silicon nitride film formed between the source electrode and the gate electrode and between the drain electrode and the gate electrode and having an oxygen atom density lower than that of the first silicon nitride film. | 09-12-2013 |
| 20130234153 | ENHANCEMENT MODE GaN HEMT DEVICE - An enhancement-mode GaN transistor. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process. | 09-12-2013 |
| 20130234154 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, an insulating film, a first interconnection, a second interconnection, a barrier metal layer, a first metal pillar, a second metal pillar, and a resin. The semiconductor layer has a first major surface, a second major surface formed on an opposite side to the first major surface, and a light emitting layer. The first electrode is provided on the second major surface of the semiconductor layer. The second electrode is provided on the second major surface of the semiconductor layer and includes a silver layer. The insulating film is provided on the second major surface side of the semiconductor layer. The barrier metal layer is provided between the second electrode and the insulating film and between the second electrode and the second interconnection to cover the second electrode. | 09-12-2013 |
| 20130234155 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes: a semiconductor layer made of p-type nitride semiconductor; an oxide layer formed on the semiconductor layer, the oxide layer being made of a crystalline nickel oxide, and the oxide layer having a thickness of 3 nm or less; and a metal layer formed on the oxide layer. | 09-12-2013 |
| 20130234156 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. A GaN-based stacked layer | 09-12-2013 |
| 20130234157 | METHODS FOR FORMING GROUP III-NITRIDE MATERIALS AND STRUCTURES FORMED BY SUCH METHODS - Embodiments of the invention include methods for forming Group III-nitride semiconductor structure using a halide vapor phase epitaxy (HVPE) process. The methods include forming a continuous Group III-nitride nucleation layer on a surface of a non-native growth substrate, the continuous Group III-nitride nucleation layer concealing the upper surface of the non-native growth substrate. Forming the continuous Group III-nitride nucleation layer may include forming a Group III-nitride layer and thermally treating said Group III-nitride layer. Methods may further include forming a further Group III-nitride layer upon the continuous Group III-nitride nucleation layer. | 09-12-2013 |
| 20130240893 | BREAKDOWN VOLTAGE MULTIPLYING INTEGRATION SCHEME - A circuit includes a first field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal; and a second field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal. The second field effect transistor and the first field effect transistor are of the same type, i.e., both n-channel transistors or both p-channel transistors. The second drain-source terminal of the first field effect transistor is coupled to the first drain-source terminal of the second field effect transistor; and the gate of the second field effect transistor is coupled to the first drain-source terminal of the second field effect transistor. The resulting three-terminal device can be substituted for a single field effect transistor that would otherwise suffer breakdown under proposed operating conditions. | 09-19-2013 |
| 20130240894 | Overvoltage Protection Device for Compound Semiconductor Field Effect Transistors - An overvoltage protection device for compound semiconductor field effect transistors includes an implanted region disposed in a compound semiconductor material. The implanted region has spatially distributed trap states which cause the implanted region to become electrically conductive at a threshold voltage. A first contact is connected to the implanted region. A second contact spaced apart from the first contact is also connected to the implanted region. The distance between the first and second contacts partly determines the threshold voltage of the overvoltage protection device. | 09-19-2013 |
| 20130240895 | SEMICONDUCTOR ELEMENT HAVING HIGH BREAKDOWN VOLTAGE - A semiconductor element having a high breakdown voltage includes a substrate, a buffer layer, a semiconductor composite layer and a bias electrode. The buffer layer disposed on the substrate includes a high edge dislocation defect density area. The semiconductor composite layer disposed on the buffer layer includes a second high edge dislocation defect density area formed due to the first high edge dislocation defect density area. The bias electrode is disposed on the semiconductor composite layer. A virtual gate effect of defect energy level capturing electrons is generated due to the first and second high edge dislocation defect density areas, such that an extended depletion region expanded from the bias electrode is formed at the semiconductor composite layer. When the bias electrode receives a reverse bias, the extended depletion region reduces a leakage current and increases the breakdown voltage of the semiconductor element. | 09-19-2013 |
| 20130240896 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device may form a nitride semiconductor layer on a substrate, form a first insulator layer on the nitride semiconductor layer by steam oxidation of ALD, form a second insulator layer on the first insulator layer by oxygen plasma oxidation of ALD, form a gate electrode on the second insulator layer, and form a source and drain electrodes on the nitride semiconductor layer. The nitride semiconductor layer may include a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer. | 09-19-2013 |
| 20130240897 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor layer formed over a substrate; a second semiconductor layer formed over the first semiconductor layer; electrodes formed over the second semiconductor layer; and a third semiconductor layer formed on the second semiconductor layer; wherein the third semiconductor layer is formed so as to surround each element, in which the electrodes are formed, and wherein the third semiconductor layer is a semiconductor layer of a conductivity type whose polarity is opposite to that of carriers produced in the first semiconductor layer. | 09-19-2013 |
| 20130240898 | Group III-V and Group IV Composite Switch - In one implementation, a group III-V and group IV composite switch includes a group IV transistor in a lower active die, the group IV transistor having a source and a gate situated on a bottom side of the lower active die. The group III-V and group IV composite switch also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a drain of the group IV transistor using a through-semiconductor via (TSV) of the upper active die. | 09-19-2013 |
| 20130240899 | NITRIDE SEMICONDUCTOR DEVICE - According to one embodiment a nitride semiconductor device includes a first, a second and a third semiconductor layer, a first and a second main electrode and a control electrode. The first layer made of a nitride semiconductor of a first conductivity type is provided on a substrate. The second layer made of a nitride semiconductor of a second conductivity type is provided on the first layer. The third layer made of a nitride semiconductor is provided on the second layer. The first electrode is electrically connected with the second layer. The second electrode is provided at a distance from the first electrode and electrically connected with the second layer. The control electrode is provided within a first trench via an insulating film. The first trench is disposed between the first and the second main electrodes, penetrates the third and the second layers, and reaches the first layer. | 09-19-2013 |
| 20130240900 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - There is provided a semiconductor device or the like which includes a channel and a gate electrode in an opening and in which electric field concentration near a bottom portion of the opening can be reduced. The semiconductor device includes n | 09-19-2013 |
| 20130240901 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a substrate, and a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, and a fourth nitride semiconductor layer sequentially formed on the substrate. A channel is formed in the third nitride semiconductor layer, and includes carriers accumulated near an interface between the third nitride semiconductor layer and the fourth nitride semiconductor layer. The second nitride semiconductor layer has a band gap larger than that of the third nitride semiconductor layer. The first nitride semiconductor layer has a band gap equal to or larger than that of the second nitride semiconductor layer, and has a carbon concentration higher than that of the second nitride semiconductor layer. | 09-19-2013 |
| 20130248872 | SEMICONDUCTOR DEVICE, NITRIDE SEMICONDUCTOR CRYSTAL, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR CRYSTAL - A semiconductor device includes: a nucleation layer formed over a substrate; a buffer layer formed over the nucleation layer; a first nitride semiconductor layer formed over the buffer layer; and a second nitride semiconductor layer formed over the first nitride semiconductor layer, wherein the ratio of yellow luminescence emission to band edge emission in photoluminescence is 400% or less and the twist value in an X-ray rocking curve is 1,000 arcsec or less. | 09-26-2013 |
| 20130248873 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nitride semiconductor device includes a substrate; semiconductor stacked layers including a nitride semiconductor provided on the substrate, and having a buffer layer, a carrier running layer provided on the buffer layer, and a barrier layer provided on the carrier running layer; a source electrode and a drain electrode provided on the semiconductor stacked layers and in contact with the semiconductor stacked layers; and a gate electrode provided on the semiconductor stacked layers and provided between the source electrode and the drain electrode. | 09-26-2013 |
| 20130248874 | NITRIDE SEMICONDUCTOR DEVICE - According to one embodiment, a nitride semiconductor device includes semiconductor stacked layers provided on a substrate and including a nitride semiconductor; a source electrode and a drain electrode provided on the layers and being in contact with the layers; and a gate electrode provided on the layers and provided between the source electrode and the drain electrode. The layers have a first barrier layer, a second barrier layer, and a carrier running layer interposed between the first barrier layer and the second barrier layer. The second barrier layer and the carrier running layer are removed in a region in which the source electrode on the layers is provided. A part of the source electrode is in contact with the first barrier layer. And another part of the source electrode other than the part of the source electrode is in contact with the second barrier layer. | 09-26-2013 |
| 20130248875 | LIGHT-EMITTING DIODE COMPRISING STACKED-TYPE SCATTERING LAYER AND MANUFACTURING METHOD THEREOF - Disclosed is a light-emitting diode with a semiconductor layer including stacked-type scattering layer, and a manufacturing method thereof. The semiconductor layer includes a non-flat structure and at least two scattering layers disposed therein. The scattering layers are stacked on the non-flat structure. The top surface of each layer of the scattering layers is non-flat having an undulating fashion, and refractive indices of two adjacent layers of the scattering layers are different from each other. Photons emitted from the active layer are scattered by the scattering layers as photon scattering structure so that the probability of photons escaping from the light-emitting diode is increased, and thus total internal reflection is reduced, thereby increasing the extraction efficiency; in addition, the lateral epitaxial growth mode is enhanced, resulting in direction change of threading dislocations or formation of dislocation loops, and thus the defect density is reduced, thereby increasing the internal quantum efficiency. | 09-26-2013 |
| 20130248876 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - In a vertical semiconductor device including a channel in an opening, a semiconductor device whose high-frequency characteristics can be improved and a method for producing the semiconductor device are provided. The semiconductor device includes n-type GaN-based drift layer | 09-26-2013 |
| 20130248877 | GALLIUM NITRIDE BASED SEMICONDUCTOR LIGHT-EMITTING ELEMENT, LIGHT SOURCE, AND METHOD FOR FORMING UNEVENNESS STRUCTURE - The light extraction surface of a nitride semiconductor light-emitting element, including a crystal plane other than a c plane, is subjected to a surface modification process to control its wettability, and then covered with a layer of fine particles. By etching that layer of fine particles after that, an unevenness structure, in which roughness curve elements have an average length (RSm) of 150 nm to 800 nm, is formed on the light extraction surface. | 09-26-2013 |
| 20130248878 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE AND THE SAME MANUFACTURED THEREOF - Disclosed is a nitride semiconductor device and a method for manufacturing the same and the method for manufacturing the nitride semiconductor device comprising: growing a buffer layer including a first semiconductor on a substrate; growing a first barrier layer including a second semiconductor different from the first semiconductor; forming an oxide film layer on a portion where a recess is to be formed; growing a second barrier layer including the second semiconductor; forming a recess by removing the oxide film layer; and forming a gate electrode on the recess. | 09-26-2013 |
| 20130256679 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature. | 10-03-2013 |
| 20130256680 | Vertical Semiconductor Device and Manufacturing Method Thereof - The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array. | 10-03-2013 |
| 20130256681 | GROUP III NITRIDE-BASED HIGH ELECTRON MOBILITY TRANSISTOR - A group III nitride-based high electron mobility transistor (HEMT) is disclosed. The group III nitride-based high electron mobility transistor (HEMT) comprises sequentially a substrate, a GaN buffer layer, a GaN channel layer, a AlN spacer layer, a barrier layer, a GaN cap layer, and a delta doped layer inserted between the AlN spacer layer and the barrier layer. The HEMT structure of the present invention can improve the electron mobility and concentration of the two-dimensional electron gas, while keeping a low contact resistance. | 10-03-2013 |
| 20130256682 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a method of manufacturing a compound semiconductor device includes: forming an initial layer over a substrate; forming a buffer layer over the initial layer; forming an electron transport layer and an electron supply layer over the buffer layer; and forming a gate electrode, a source electrode and a gate electrode over the electron supply layer. The forming an initial layer includes: forming a first compound semiconductor film with a flow rate ratio being a first value, the flow rate ratio being a ratio of a flow rate of a V-group element source gas to a flow rate of a III-group element source gas; and forming a second compound semiconductor film with the flow rate ratio being a second value different from the first value over the first compound semiconductor film. The method further includes forming an Fe-doped region between the buffer layer and the electron transport layer. | 10-03-2013 |
| 20130256683 | COMPOUND SEMICONDUCTOR AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: a substrate; an electron transport layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed over the electron supply layer; a p-type semiconductor layer formed between the electron supply layer and the gate electrode; and a hole canceling layer formed between the electron supply layer and the p-type semiconductor layer, the hole canceling layer containing a donor or a recombination center and canceling a hole. | 10-03-2013 |
| 20130256684 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: a substrate; an electron transport layer formed over the substrate; an electron supply layer formed over the electron transport layer; a source electrode and a drain electrode formed over the electron supply layer; a gate electrode formed over the electron supply layer between the source electrode and the drain electrode; a p-type compound semiconductor layer formed between the electron supply layer and the gate electrode; and a compound semiconductor layer containing an n-type impurity formed between the electron supply layer and the p-type compound semiconductor layer. | 10-03-2013 |
| 20130256685 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A compound semiconductor device includes a compound semiconductor composite structure in which two-dimensional electron gas is generated; and an electrode that is formed on the compound semiconductor composite structure, wherein the compound semiconductor composite structure includes a p-type semiconductor layer below a portion where the two-dimensional electron gas is generated, and the p-type semiconductor layer includes a portion containing a larger amount of an ionized acceptor than other portions of the p-type semiconductor layer, the portion being located below the electrode. | 10-03-2013 |
| 20130256686 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer formed over a substrate; a second semiconductor layer formed over the first semiconductor layer; an insulating film including a first insulating film formed over the second semiconductor layer, a second insulating film, and a third insulating film stacked sequentially over the first insulating film, and an electrode formed over the insulating film, wherein, in the first insulating film, a region containing halogen ions is formed under a region provided with the electrode, and the third insulating film contains a halogen. | 10-03-2013 |
| 20130256687 | GROUP III NITRIDE COMPOUND SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR PRODUCING THE SAME - A group III nitride compound semiconductor light emitting device that inhibits occurrence of dislocation in a strain relaxation layer in forming a group III nitride compound semiconductor layer on a thin GaN substrate, and a method for producing the same are provided. A light emitting device | 10-03-2013 |
| 20130256688 | NITRIDE SEMICONDUCTOR SCHOTTKY DIODE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a nitride semiconductor Schottky diode includes a first layer including a first nitride semiconductor and a second layer provided on the first layer and including a second nitride semiconductor having a wider band gap than the first nitride semiconductor. The diode also includes an ohmic electrode provided on the second layer and a Schottky electrode provided on the second layer. The second layer includes a region containing an acceptor in the vicinity of the Schottky electrode between the Schottky electrode and the ohmic electrode. | 10-03-2013 |
| 20130256689 | NANOWIRE-BASED OPTOELECTRONIC SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE OF SUCH A STRUCTURE - The invention concerns an optoelectronic semiconductor structure ( | 10-03-2013 |
| 20130256690 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - A semiconductor device may include a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a source electrode and a drain electrode in contact with the first semiconductor layer or the second semiconductor layer, an opening formed in the second semiconductor layer, an insulating film formed on an inner surface of the opening formed in the second semiconductor layer and above the second semiconductor layer, a gate electrode formed in the opening via the insulating film, and a protective film formed on the insulating film and including an amorphous film containing carbon as a major component. | 10-03-2013 |
| 20130256691 | METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - A method for manufacturing a semiconductor light emitting device is provided. The device includes: an n-type semiconductor layer; a p-type semiconductor layer; and a light emitting unit provided between the n-type semiconductor layer and the p-type semiconductor layer. The method includes: forming a buffer layer made of a crystalline Al | 10-03-2013 |
| 20130256692 | EPITAXIAL DEVICES - Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride. | 10-03-2013 |
| 20130256693 | SEMICONDUCTOR DEVICE, POWER-SUPPLY UNIT, AMPLIFIER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device, includes a semiconductor layer formed above a substrate; an insulating film formed on the semiconductor layer; and an electrode formed on the insulating film. The insulating film has a membrane stress at a side of the semiconductor layer lower than a membrane stress at a side of the electrode. | 10-03-2013 |
| 20130256694 | Programmable Gate III-Nitride Semiconductor Device - A III-nitride semiconductor device which includes a charged gate insulation body. | 10-03-2013 |
| 20130256695 | III-Nitride Heterojunction Device - A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof. | 10-03-2013 |
| 20130256696 | Prepared and Stored GaN Substrate - A GaN substrate is stored within an atmosphere in which the oxygen concentration is not greater than 15 vol. % and the water-vapor concentration is not greater than 20 g/m | 10-03-2013 |
| 20130256697 | GROUP-III-NITRIDE BASED LAYER STRUCTURE AND SEMICONDUCTOR DEVICE - A group-III-nitride based layer sequence fabricated by means of an epitaxial process on a silicon substrate, the layer sequence comprising at least one doped first group-III-nitride layer ( | 10-03-2013 |
| 20130264576 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device, in which the generation of interface states in the interface region between a nitride semiconductor layer and an aluminum oxide layer is suppressed, includes a first nitride semiconductor layer and an aluminum oxide layer. The first nitride semiconductor layer includes Ga. The aluminum oxide layer directly contacts the upper surface of the first nitride semiconductor layer, and includes H (hydrogen) atoms at least within a defined region from the interface with the first nitride semiconductor layer. In addition, the peak value of an H atom concentration in the above region is in a range of 1×10 | 10-10-2013 |
| 20130264577 | HIGH FLUX HIGH BRIGHTNESS LED LIGHTING DEVICES - Methods, systems, and devices are disclosed for implementing high brightness lighting. In one aspect, an LED lighting device includes a substrate capable of dissipating heat, an LED die located on the substrate, an optically reflective structure that is electrically insulative and located on the substrate and structured to form an optically reflective cavity around the LED die, an electrically conductive line structured at least partially within the optically reflective structure and electrically connected to the LED die for electrically driving the LED die to emit the light, a phosphor material located to receive light emitted by the LED die to emit light under optical excitation of the light from the LED die, and an optical element placed in an optical path of the light emitted by the phosphor material to produce better directionality of the emitted light than directionality of emitted light by the phosphor material without the optical element. | 10-10-2013 |
| 20130264578 | N-POLAR III-NITRIDE TRANSISTORS - An N-polar III-N transistor includes a III-N buffer layer, a first III-N barrier layer, and a III-N channel layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the access regions of the III-N channel layer. The transistor also includes a source, a gate, a drain, and a second III-N barrier layer between the gate and the III-N channel layer. The second III-N barrier layer has an N-face proximal to the gate and a group-III face opposite the N-face, and has a larger bandgap than the III-N channel layer. The lattice constant of the first III-N barrier layer is within 0.5% of the lattice constant of the buffer layer. | 10-10-2013 |
| 20130264579 | III-Nitride Heterojunction Device - A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof. | 10-10-2013 |
| 20130264580 | Lateral High Electron Mobility Transistor With Schottky Junction - A lateral HEMT includes a first semiconductor layer on a second semiconductor layer, a heterojunction at an interface between the first semiconductor layer and the second semiconductor layer, and a rectifying Schottky junction. The rectifying Schottky junction has a first terminal electrically coupled to a source electrode and a second terminal electrically coupled to the second semiconductor layer. | 10-10-2013 |
| 20130270571 | SCHOTTKY BARRIER DIODE AND MANUFACTURING METHOD THEREOF - The present invention discloses a Schottky barrier diode (SBD) and a manufacturing method thereof. The SBD is formed on a substrate. The SBD includes: a gallium nitride (GaN) layer; an aluminum gallium nitride (AlGaN), formed on the GaN layer; a high work function conductive layer, formed on the AlGaN layer, wherein a first Schottky contact is formed between the high work function conductive layer and the AlGaN layer; a low work function conductive layer, formed on the AlGaN layer, wherein a second Schottky contact is formed between the low work function conductive layer and the AlGaN layer; and an ohmic contact metal layer, formed on the AlGaN layer, wherein an ohmic contact is formed between the ohmic contact metal layer and the AlGaN layer, and wherein the ohmic contact conductive layer is separated from the high and low work function conductive layers by a dielectric layer. | 10-17-2013 |
| 20130270572 | GROUP III-N HFET WITH A GRADED BARRIER LAYER - A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer. | 10-17-2013 |
| 20130270573 | LEDs with Efficient Electrode Structures - Aspects include Light Emitting Diodes that have a GaN-based light emitting region and a metallic electrode. The metallic electrode can be physically separated from the GaN-based light emitted region by a layer of porous dielectric, which provides a reflecting region between at least a portion of the metallic electrode and the GaN-based light emitting region. | 10-17-2013 |
| 20130270574 | NITRIDE-BASED SEMICONDUCTOR ELEMENT AND METHOD FOR FABRICATING THE SAME - A nitride-based semiconductor element according to an embodiment of the present disclosure includes: a p-type contact layer, of which the growing plane is an m plane; and an electrode which is arranged on the growing plane of the p-type contact layer. The p-type contact layer is a GaN-based semiconductor layer which has a thickness of 26 nm to 60 nm and which includes oxygen at a concentration that is equal to or higher than Mg concentration of the p-type contact layer. In the p-type contact layer, the number of Ga vacancies is larger than the number of N vacancies. | 10-17-2013 |
| 20130270575 | SEMICONDUCTOR WAFER COMPRISING GALLIUM NITRIDE LAYER HAVING ONE OR MORE SILICON NITRIDE INTERLAYER THEREIN - A semiconductor wafer comprising a substrate layer and a first GaN layer having one or more SiNx interlayers therein, wherein in the first GaN layer at least one SiNx interlayer has GaN penetrated through one or more portions of said SiNx interlayer and preferably has a thickness of from 0.5 to 10 nm. | 10-17-2013 |
| 20130277680 | High Speed Gallium Nitride Transistor Devices - A low leakage current switch device ( | 10-24-2013 |
| 20130277681 | LIGHT-EMITTING DEVICE - A light-emitting device includes a case including a first substrate and a sidewall on the first substrate, a light-emitting, element that is mounted on the first substrate in a region surrounded by the sidewall and includes a second substrate and a crystal layer, the light-emitting element being formed rectangular in a plane viewed in a direction perpendicular to the first substrate, and a low-refractive-index layer that is located between the light-emitting element and the sidewall and has a smaller refractive index than the second substrate. A side surface along a longitudinal direction of the second substrate is provided with a tapered portion on a side of the first substrate. | 10-24-2013 |
| 20130277682 | LIGHT EMITTING ELEMENT WITH A PLURALITY OF CELLS BONDED, METHOD OF MANUFACTURING THE SAME, AND LIGHT EMITTING DEVICE USING THE SAME - The present invention relates to a light emitting device, including a conductive substrate, vertical light emitting cells arranged on the conductive substrate, an insulating layer interposed between the conductive substrate and the vertical light emitting cells, and a wire electrically connecting the vertical light emitting cells. | 10-24-2013 |
| 20130277683 | NON-PLANAR III-N TRANSISTOR - Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (10 | 10-24-2013 |
| 20130277684 | NITRIDE SEMICONDUCTOR STRUCTURE, NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT, NITRIDE SEMICONDUCTOR TRANSISTOR ELEMENT, METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR STRUCTURE, AND METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR ELEMENT - A nitride semiconductor structure in which a first nitride semiconductor underlying layer is provided on a substrate having a recess portion and a projection portion provided between the recess portions at a surface thereof, the first nitride semiconductor underlying layer has at least 6 first oblique facet planes surrounding the projection portion on an outer side of the projection portion, and a second nitride semiconductor underlying layer buries the first oblique facet planes, a nitride semiconductor light emitting element, a nitride semiconductor transistor element, a method of manufacturing a nitride semiconductor structure, and a method of manufacturing a nitride semiconductor element are provided. | 10-24-2013 |
| 20130285064 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a phosphor layer, and a transparent film. The semiconductor layer has a first face, a second face opposite to the first face, and a light emitting layer. The p-side electrode is provided on the second face in an area including the light emitting layer. The n-side electrode is provided on the second face in an area not including the light emitting layer. The phosphor layer is provided on the first face. The phosphor layer includes a transparent resin and phosphor dispersed in the transparent resin. The transparent film is provided on the phosphor layer and has an adhesiveness lower than an adhesiveness of the transparent resin. | 10-31-2013 |
| 20130285065 | PVD BUFFER LAYERS FOR LED FABRICATION - Fabrication of gallium nitride-based light devices with physical vapor deposition (PVD)-formed aluminum nitride buffer layers is described. Process conditions for a PVD AlN buffer layer are also described. Substrate pretreatments for a PVD aluminum nitride buffer layer are also described. In an example, a method of fabricating a buffer layer above a substrate involves pre-treating a surface of a substrate. The method also involves, subsequently, reactive sputtering an aluminum nitride (AlN) layer on the surface of the substrate from an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-based gas or plasma. | 10-31-2013 |
| 20130285066 | METHOD OF FABRICATING GALLIUM NITRIDE SEMICONDUCTOR, METHOD OF FABRICATING GROUP III NITRIDE SEMICONDUCTOR DEVICE, AND GROUP III NITRIDE SEMICONDUCTOR DEVICE - Provided is a method of fabricating a gallium nitride semiconductor which enables activation of a p-type dopant with a heat treatment performed for a relatively short period of time. The fabricating method comprises the step of performing, in a vacuum, a heat treatment of a group III nitride semiconductor region, the group III nitride semiconductor region comprising a gallium nitride semiconductor, the gallium nitride semiconductor including a p-type dopant, the a group III nitride semiconductor region having a group III nitride semiconductor surface inclined with respect to a reference plane perpendicular to a reference axis, and the reference axis extending in a direction of a c-axis of the gallium nitride semiconductor. | 10-31-2013 |
| 20130285067 | METHOD FOR FORMING A BURIED METAL LAYER STRUCTURE - The invention relates to a method for fabricating a structure including a semiconductor material comprising: a) implanting one or more ion species to form a weakened region delimiting at least one seed layer in a substrate of semiconductor material, b) forming, before or after step a), at least one metallic layer on the substrate in semiconductor material, c) assembling the at least one metallic layer with a transfer substrate, then fracturing the implanted substrate at the weakened region, d) forming at least one layer in semiconductor material on the at least one seed layer, for example, by epitaxy. | 10-31-2013 |
| 20130292683 | Semiconductor Heterobarrier Electron Device And Method of Making - An electronic device comprising a substrate; a pair of stacks of polar semiconductor materials which create a charge by spontaneous and/or piezoelectric polarization; one of the pair of stacks having a spontaneous and/or piezoelectric polarity which is in a direction opposite to the other of the pair of stacks; whereby due to the opposing polarities, the polarization is balanced. A method of substantially eliminating the bias required to offset polarization charges in an electronic device having a heterobarrier comprising providing a substrate; growing at least one pair of stacks of semiconductor materials; one of the pair of stacks having a spontaneous and/or piezoelectric polarity which is opposite to the other of the pair of stacks; whereby due to the opposing polarities, the polarization is balanced to substantially eliminate the need for a voltage bias. | 11-07-2013 |
| 20130292684 | Semiconductor Package and Methods of Formation Thereof - In one embodiment, a semiconductor package includes a semiconductor chip having a first contact region on a first major surface and a second contact region on an opposite second major surface. The semiconductor chip is configured to regulate flow of a current from the first contact region to the second contact region. An encapsulant is disposed at the semiconductor chip. A first contact plug is disposed within the encapsulant and coupled to the first contact region. A second side conductive layer is disposed under the second major surface and coupled to the second contact region. A through via is disposed within the encapsulant and coupled to the second side conductive layer. The first contact plug and the through via form terminals above the first major surface for contacting the semiconductor package. | 11-07-2013 |
| 20130292685 | Structures and Devices Based on Boron Nitride and Boron Nitride-III-Nitride Heterostructures - The present invention relates to optoelectronic device layer structures, light emitting devices, and detectors based upon heterostructures formed between hexagonal boron nitride (hNB) and III-nitrides, and more particularly, to heterojunction devices capable of emitting and detecting photons in the ultraviolet (UV) and extremely ultraviolet (RUV) spectral range. The present invention also relates to neutron detectors based on epitaxially grown hBN thin films (or epitaxial layers) and hBN stacked thin films (or epitaxial layers) to satisfy the thickness required for capturing all incoming neutrons. | 11-07-2013 |
| 20130292686 | METHOD AND SYSTEM FOR PLANAR REGROWTH IN GAN ELECTRONIC DEVICES - A vertical JFET includes a III-nitride substrate and a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer has a first dopant concentration. The vertical JFET also includes a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer. The III-nitride epitaxial structure includes a set of channels of the first conductivity type and having a second dopant concentration, a set of sources of the first conductivity type, having a third dopant concentration greater than the first dopant concentration, and each characterized by a contact surface, and a set of regrown gates interspersed between the set of channels. An upper surface of the set of regrown gates is substantially coplanar with the contact surfaces of the set of sources. | 11-07-2013 |
| 20130292687 | Structures and Devices Based on Boron Nitride and Boron Nitride-III-Nitride Heterostructures - The present invention relates to optoelectronic device layer structures, light emitting devices, and detectors based upon heterostructures formed between hexagonal boron nitride (hNB) and III nitrides, and more particularly, to heterojunction devices capable of emitting and detecting photons in the ultraviolet (UV) and extremely ultraviolet (RUV) spectral range. The present invention also relates to neutron detectors based on epitaxially grown hBN thin films (or epitaxial layers) and hBN stacked thin films (or epitaxial layers) to satisfy the thickness required for capturing all incoming neutrons. | 11-07-2013 |
| 20130292688 | GALLIUM NITRIDE SEMICONDUCTOR SUBSTRATE WITH SEMICONDUCTOR FILM FORMED THEREIN - A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more single crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis. Each predetermined plane is inclined to the predetermined axis. Each substrate has a mirror polished primary surface. The primary surface has a first area and a second area. The first area is between an edge of the substrate and a line 3 millimeter away from the edge. The first area surrounds the second area. An axis perpendicular to the primary surface forms an off-angle with c-axis of the substrate. The off-angle takes a minimum value at a first position in the first area of the primary surface. | 11-07-2013 |
| 20130292689 | WAFER LEVEL PACKAGED GAN POWER SEMICONDUCTOR DEVICE AND THE MANUFACTURING METHOD THEREOF - Disclosed are a GaN (gallium nitride) compound power semiconductor device and a manufacturing method thereof. The gallium nitride compound power semiconductor device includes: a gallium nitride compound element formed by being grown on a wafer; a contact pad including a source, a drain, and a gate connecting with the gallium nitride compound element; a module substrate to which the nitride gallium compound element is flip-chip bonded; a bonding pad formed on the module substrate; and a bump formed on the bonding pad of the module substrate so that the contact pad and the bonding pad are flip-chip bonded. By this configuration, it is possible to reduce the process costs by forming the bump on the substrate based on the wafer level, rapidly emit the heat generated from an AlGaN HEMT device by forming the sub source contact pad and the sub drain contact pad of the substrate in the active region, and efficiently emit the heat generated from the AlGaN HEMT device by forming a via hole on the substrate and filling the via hole with the conductive metal. | 11-07-2013 |
| 20130292690 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a high electron mobility transistor, with a normally-off operation maintained, on-resistance can be sufficiently reduced, so that the performance of a semiconductor device including the high electron mobility transistor is improved. Between a channel layer and an electron supply layer, a spacer layer whose band gap is larger than the band gap of the electron supply layer is provided. Thereby, due to the fact that the band gap of the spacer layer is large, a high potential barrier (electron barrier) is formed in the vicinity of an interface between the channel and the electron supply layer. | 11-07-2013 |
| 20130292691 | TECHNIQUES FOR FORMING OPTOELECTRONIC DEVICES - Embodiments relate to use of a particle accelerator beam to form thin films of material from a bulk substrate are described. In particular embodiments, a bulk substrate having a top surface is exposed to a beam of accelerated particles. In certain embodiments, this bulk substrate may comprise GaN; in other embodiments this bulk substrate may comprise (111) single crystal silicon. Then, a thin film or wafer of material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. In certain embodiments this separated material is incorporated directly into an optoelectronic device, for example a GaN film cleaved from GaN bulk material. In some embodiments, this separated material may be employed as a template for further growth of semiconductor materials (e.g. GaN) that are useful for optoelectronic devices. | 11-07-2013 |
| 20130292692 | LIGHT EMITTING DIODE - An LED includes a substrate, a first n-type GaN layer, a connecting layer, a second n-type GaN layer, a light emitting layer, and a p-type GaN layer. The first n-type GaN layer, the connecting layer, and the second n-type GaN layer are formed on the substrate in sequence. The connecting layer is etchable by alkaline solution, and a bottom surface of the second n-type GaN layer facing towards the connecting layer has a roughed exposed portion. The GaN on the bottom surface of the second n-type GaN layer is N-face GaN. A top surface of the second n-type GaN layer facing away from the connecting layer includes a first area and a second area. The light emitting layer and the p-type GaN layer are formed on the first area of the top surface of the second n-type GaN layer in sequence. | 11-07-2013 |
| 20130292693 | LIGHT EMITTING DIODE - An LED includes a substrate, a first n-type GaN layer, a connecting layer, a second n-type GaN layer, a light emitting layer, and a p-type GaN layer formed on the substrate in sequence. The connecting layer is etchable by alkaline solution. A bottom surface of the second n-type GaN layer faces towards the connecting layer and has a roughened exposed portion. The GaN on the bottom surface of the second n-type GaN layer has an N-face polarity. A blind hole extends through the p-type GaN layer, the light emitting layer and the second n-type GaN layer to expose the connecting layer. An annular rough portion is formed on the bottom surface of the second n-type GaN layer and surrounds each blind hole. | 11-07-2013 |
| 20130292694 | Enhancement Mode III-Nitride Transistors with Single Gate Dielectric Structure - According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge. | 11-07-2013 |
| 20130292695 | SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING SCHOTTKY BARRIER DIODE - A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×10 | 11-07-2013 |
| 20130292696 | CHAMFERED FREESTANDING NITRIDE SEMICONDUCTOR WAFER AND METHOD OF CHAMFERING NITRIDE SEMICONDUCTOR WAFER - Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 μm to Ra 6 μm. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra10 nm and Ra5 μm at edges of wafers. | 11-07-2013 |
| 20130292697 | GALLIUM NITRIDE BASED LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF - A light emitting diode (LED) and a method for fabricating the same, capable of improving brightness by forming a InGaN layer having a low concentration of indium, and whose lattice constant is similar to that of an active layer of the LED, is provided. The LED includes: a buffer layer disposed on a sapphire substrate; a GaN layer disposed on the buffer layer; a doped GaN layer disposed on the GaN layer; a GaN layer having indium disposed on the GaN layer; an active layer disposed on the GaN layer having indium; and a P-type GaN disposed on the active layer. Here, an empirical formula of the GaN layer having indium is given by In(x)Ga(1−x)N and a range of x is given by 0| 11-07-2013 | |
| 20130292698 | III-N MATERIAL STRUCTURE FOR GATE-RECESSED TRANSISTORS - III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack. | 11-07-2013 |
| 20130292699 | NITRIDE SEMICONDUCTOR DEVICE - The present invention prevents breakage of a gate insulating film of a MOS device and provides a nitride semiconductor device having improved reliability. An SBD metal electrode provided between a drain electrode and a gate electrode is configured to form a Schottky junction with an AlGaN layer. Further, the SBD metal electrode and a source electrode are connected and electrically short-circuited. Consequently, when an off signal is inputted to the gate electrode, a MOSFET part is turned off and the drain-side voltage of the MOSFET part becomes close to the drain electrode voltage. When the drain electrode voltage increases, the SBD metal electrode voltage becomes lower than the drain-side voltage of the MOSFET part, thus the drain side of the MOSFET part and the drain electrode are electrically disconnected by the SBD metal electrode. | 11-07-2013 |
| 20130292700 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device including GaN (gallium nitride) that composes a semiconductor layer and includes forming a gate insulating film, in which at least one film selected from the group of a SiO | 11-07-2013 |
| 20130299840 | SCHOTTKY BARRIER DIODE AND MANUFACTURING METHOD THEREOF - The present invention discloses a Schottky barrier diode (SBD) and a manufacturing method thereof. The SBD includes: a semiconductor layer, which has multiple openings forming an opening array; and an anode, which has multiple conductive protrusions protruding into the multiple openings and forming a conductive array; wherein a Schottky contact is formed between the semiconductor layer and the anode. | 11-14-2013 |
| 20130299841 | GaN-Based Optocoupler - An optocoupler includes a GaN-based photosensor disposed on a substrate and a GaN-based light source disposed on the same substrate as the GaN-based photosensor. A transparent material is interposed between the GaN-based photosensor and the GaN-based light source. The transparent material provides galvanic isolation and forms an optical channel between the GaN-based photosensor and the GaN-based light source. | 11-14-2013 |
| 20130299842 | Contact Structures for Compound Semiconductor Devices - A semiconductor device includes a semiconductor body including a plurality of compound semiconductor layers and a two-dimensional charge carrier gas channel region formed in one of the compound semiconductor layers. The semiconductor device further includes a contact structure disposed in the semiconductor body. The contact structure includes a metal region and a doped region. The metal region extends into the semiconductor body from a first side of the semiconductor body to at least the compound semiconductor layer which includes the channel region. The doped region is formed in the semiconductor body between the metal region and the channel region so that the channel region is electrically connected to the metal region through the doped region. | 11-14-2013 |
| 20130299843 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element having a substrate of GaAs, InP, or GaN, and an element securing member bonded to the semiconductor element by solder. The element securing member is a composite material of Cu and carbon or a composite of Al and carbon. | 11-14-2013 |
| 20130299844 | ENHANCED LIGHT EXTRACTION EFFICIENCY FOR LIGHT EMITTING DIODES - Systems, methods, and other embodiments associated with increased light extraction efficiency in light emitting diodes are described. According to one embodiment, a light emitting diode apparatus includes a device having a first material and a second material separated by an active region. The apparatus further includes a plurality of curvatures formed on the second semiconductor material. The curvatures may be hemi-sphereical, hemi-ellipsoidic, micro domes, or micro domes with a flat surface. The plurality of curvatures and the second material have the same index of refraction. | 11-14-2013 |
| 20130299845 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MODULE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device including first and second semiconductor elements, first and second external connection terminals and a sealing member. The first external connection terminal is provided at a first surface of the first semiconductor element. The second semiconductor element is provided at a second surface side, that is at a side opposite to the first surface, of the first semiconductor element. The second external connection terminal is connected to the second semiconductor element, and the second external connection terminal is configured to be, together with the first external connection terminal, connected to a wiring board. The sealing member seals the first and second semiconductor elements and exposes a portion, that is configured to be connected to the wiring board, of the first external connection terminal and a portion, that is configured to be connected to the wiring board, of the second external connection terminal. | 11-14-2013 |
| 20130299846 | GROUP 13 NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF ITS MANUFACTURE - Disclosed is a semiconductor device comprising a substrate ( | 11-14-2013 |
| 20130299847 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor light emitting device includes: a laminated structure body including an n-type semiconductor layer, a p-type semiconductor layer and a light emitting layer provided between the n-type semiconductor layer and the p-type semiconductor layer; a first electrode connected to the n-type semiconductor layer and containing at least one of silver and a silver alloy; and a second electrode connected to the p-type semiconductor layer. | 11-14-2013 |
| 20130306976 | LIGHT EMITTING DIODE ELEMENT - An object of the present invention is to provide a GaN-based light emitting diode element having a great emission efficiency and suitable for an excitation light source for a white LED. The GaN-based light emitting diode element includes an n-type conductive m-plane GaN substrate, a light emitting diode structure which is formed of a GaN-based semiconductor, on a front face of the m-plane GaN substrate, and an n-side ohmic electrode formed on a rear face of the m-plane GaN substrate, wherein a forward voltage is 4.0 V or less when a forward current applied to the light emitting diode element is 20 mA. | 11-21-2013 |
| 20130306977 | COMPOUND SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME - A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal silicon carbide. In each of the first substrate and the second substrate, one surface is a (000-1) C-face and an opposite surface is a (0001) Si-face. The first substrate and the second substrate are bonded to each other in a state where the (0001) Si-face of the first substrate and the (0001) Si-face of the second substrate face each other, and the (000-1) C-face of the first substrate and the (000-1) C-face of the second substrate are exposed. | 11-21-2013 |
| 20130306978 | PASSIVATION OF GROUP III-NITRIDE HETEROJUNCTION DEVICES - Passivation of group III-nitride heterojunction devices is described herein. The passivation facilitates simultaneous realization of effective/high current collapse suppression and low leakage current without the use of a sophisticated multiple-field plate technique. The passivation can be achieved by growing a charge-polarized AlN thin film on the surface of a group III-nitride based heterojunction device by plasma-enhanced atomic layer deposition such that positive polarization charges are induced at the interface to compensate for a majority of negative charges at the interface. | 11-21-2013 |
| 20130306979 | SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATE - A GaN-based semiconductor is epitaxially grown on a silicon substrate with a surface orientation of (111). The difference between the lattice constant of the GaN and the silicon (111) surface is approximately 17%, which is quite large. Therefore, the dislocation density of the grown GaN exceeds 10 | 11-21-2013 |
| 20130306980 | NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A nitride semiconductor device includes a substrate, an electron transit layer and an electron supply layer that are sequentially formed above the substrate, where the electron supply layer has a different band gap energy than the electron transit layer, a drain electrode, a gate electrode, and a source electrode that is formed on the opposite side of the drain electrode with the gate electrode being sandwiched between the drain electrode and the source electrode. Here, a plurality of lower concentration regions are formed so as to be spaced away from each other on the surface of the electron transit layer between the gate electrode and the drain electrode. In the lower concentration regions, the concentration of a two-dimensional electron gas is lower than in other regions. | 11-21-2013 |
| 20130306981 | NITRIDE SEMICONDUCTOR DEVICE, NITRIDE SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAYER - According to one embodiment, a nitride semiconductor device includes a foundation layer and a functional layer. The foundation layer is formed on an Al-containing nitride semiconductor layer formed on a silicon substrate. The foundation layer has a thickness not less than 1 micrometer and including GaN. The functional layer is provided on the foundation layer. The functional layer includes a first semiconductor layer. The first semiconductor layer has an impurity concentration higher than an impurity concentration in the foundation layer and includes GaN of a first conductivity type. | 11-21-2013 |
| 20130306982 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor device according to an embodiment of the present invention includes: a semiconductor layer | 11-21-2013 |
| 20130306983 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor device according to the present invention includes a semiconductor layer made of a wide bandgap semiconductor having a gate trench provided with a sidewall and a bottom wall, a gate insulating film formed on the sidewall and the bottom wall of the gate trench, and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film, while the semiconductor layer includes a first conductivity type source region formed to be exposed on the side of a front surface of the semiconductor layer for partially forming the sidewall of the gate trench, a second conductivity type body region formed on a side of the source region closer to a rear surface of the semiconductor layer to be in contact with the source region for partially forming the sidewall of the gate trench, a first conductivity type drift region formed on a side of the body region closer to the rear surface of the semiconductor layer to be in contact with the body region for forming the bottom wall of the gate trench, and a second conductivity type first breakdown voltage holding region selectively formed on an edge portion of the gate trench where the sidewall and the bottom wall intersect with each other in a partial region of the gate trench. | 11-21-2013 |
| 20130306984 | NORMALLY-OFF-TYPE HETEROJUNCTION FIELD-EFFECT TRANSISTOR - A normally-off-type HFET includes an undoped Al | 11-21-2013 |
| 20130313560 | NON-UNIFORM TWO DIMENSIONAL ELECTRON GAS PROFILE IN III-NITRIDE HEMT DEVICES - A HEMT device has a substrate; a buffer layer disposed above the substrate; a carrier supplying layer disposed above the buffer layer; a gate element penetrating the carrier supplying layer; and a drain element disposed on the carrier supplying layer. The carrier supplying layer has a non-uniform thickness between the gate element and the drain element, the carrier supplying layer having a relatively greater thickness adjacent the drain element and a relatively thinner thickness adjacent the gate element. A non-uniform two-dimensional electron gas conduction channel is formed in the carrier supplying layer, the two-dimensional electron gas conduction channel having a non-uniform profile between the gate and drain elements. | 11-28-2013 |
| 20130313561 | GROUP III-NITRIDE TRANSISTOR WITH CHARGE-INDUCING LAYER - Embodiments of the present disclosure describe apparatuses, methods, and systems of a device such as a transistor. The device includes a buffer layer disposed on a substrate, the buffer layer being configured to serve as a channel of a transistor and including gallium (Ga) and nitrogen (N), a barrier layer disposed on the buffer layer, the barrier layer being configured to supply mobile charge carriers to the channel and including aluminum (Al), gallium (Ga), and nitrogen (N), a charge-inducing layer disposed on the barrier layer, the charge-inducing layer being configured to induce charge in the channel and including aluminum (Al) and nitrogen (N), and a gate terminal disposed in the charge-inducing layer and coupled with the barrier layer to control the channel. Other embodiments may also be described and/or claimed. | 11-28-2013 |
| 20130313562 | PACKAGE-INTEGRATED THIN FILM LED - LED epitaxial layers (n-type, p-type, and active layers) are grown on a substrate. For each die, the n and p layers are electrically bonded to a package substrate that extends beyond the boundaries of the LED die such that the LED layers are between the package substrate and the growth substrate. The package substrate provides electrical contacts and conductors leading to solderable package connections. The growth substrate is then removed. Because the delicate LED layers were bonded to the package substrate while attached to the growth substrate, no intermediate support substrate for the LED layers is needed. The relatively thick LED epitaxial layer that was adjacent the removed growth substrate is then thinned and its top surface processed to incorporate light extraction features. There is very little absorption of light by the thinned epitaxial layer, there is high thermal conductivity to the package because the LED layers are directly bonded to the package substrate without any support substrate therebetween, and there is little electrical resistance between the package and the LED layers so efficiency (light output vs. power input) is high. The light extraction features of the LED layer further improves efficiency. | 11-28-2013 |
| 20130313563 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device which reduces a source resistance and a manufacturing method for the same are provided. The semiconductor device has a nitride based compound semiconductor layer arranged on a substrate, an active region which has an aluminum gallium nitride layer arranged on the nitride based compound semiconductor layer, and a gate electrode, source electrode and drain electrode arranged on the active region. The semiconductor device has gate terminal electrodes, source terminal electrodes and drain terminal electrode connected to the gate electrode, source electrode and drain electrode respectively. The semiconductor device has end face electrodes which are arranged on a side face of the substrate by a side where the source terminal electrode is arranged, and which are connected to the source terminal electrode. The semiconductor device has a projection arranged on the end face electrode which prevents solder used in die bonding from reaching the source terminal electrodes. | 11-28-2013 |
| 20130313564 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - There are provided a semiconductor device that includes a bypass protection unit against surge voltage or the like, achieves good withstand voltage characteristics and low on-resistance (low On-state voltage), has a simple structure, and is used for large-current purpose and a method for producing the semiconductor device. | 11-28-2013 |
| 20130313565 | COMPOUND SEMICONDUCTOR DEVICE - The compound semiconductor device comprises an i-GaN buffer layer | 11-28-2013 |
| 20130313566 | GaN Epitaxy With Migration Enhancement and Surface Energy Modification - Methods and apparatus for depositing thin films incorporating the use of a surfactant are described. Methods and apparatuses include a deposition process and system comprising multiple isolated processing regions which enables rapid repetition of sub-monolayer deposition of thin films. The use of surfactants allows the deposition of high quality epitaxial films at lower temperatures having low values of surface roughness. The deposition of Group III-V thin films such as GaN is used as an example. | 11-28-2013 |
| 20130313567 | BASE SUBSTRATE, GALLIUM NITRIDE CRYSTAL MULTI-LAYER SUBSTRATE AND PRODUCTION PROCESS THEREFOR - A GaN crystal multi-layer substrate having surfaces with various crystal orientations formed on a sapphire base substrate, such as a substrate whose principal surface is a <11-20> plane which is the a-plane, a <1-100> plane which is the m-plane, or a <11-22> plane having a low threading dislocation density and high crystal quality of a GaN crystal, and a production process therefor. | 11-28-2013 |
| 20130320349 | IN-SITU BARRIER OXIDATION TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer layer including gallium (Ga) and nitrogen (N), a barrier layer disposed on the buffer layer, the barrier layer including aluminum (Al) and nitrogen (N), wherein the barrier layer includes an oxidized portion of the barrier layer, a gate dielectric disposed on the oxidized portion of the barrier layer, and a gate electrode disposed on the gate dielectric, wherein the oxidized portion of the barrier layer is disposed in a gate region between the gate electrode and the buffer layer. | 12-05-2013 |
| 20130320350 | Compound Semiconductor Transistor with Self Aligned Gate - A transistor device includes a compound semiconductor body having a first surface and a two-dimensional charge carrier gas disposed below the first surface in the compound semiconductor body. The transistor device further includes a source in contact with the two-dimensional charge carrier gas and a drain spaced apart from the source and in contact with the two-dimensional charge carrier gas. A first passivation layer is in contact with the first surface of the compound semiconductor body, and a second passivation layer is disposed on the first passivation layer. The second passivation layer has a different etch rate selectivity than the first passivation layer. A gate extends through the second passivation layer into the first passivation layer. | 12-05-2013 |
| 20130320351 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light emitting device is provided and includes a protective element including a first lower conductivity-type semiconductor layer and a second lower conductivity-type semiconductor layer. First and second lower electrodes are connected to the first lower conductivity-type semiconductor layer and the second lower conductivity-type semiconductor layer, respectively. A light emitting structure includes a first upper conductivity-type semiconductor layer, an active layer, and a second upper conductivity-type semiconductor layer sequentially formed on the protective element. First and second upper electrodes are connected to the first upper conductivity-type semiconductor layer and the second upper conductivity-type semiconductor layer, respectively. | 12-05-2013 |
| 20130320352 | Ohmic Contact to Semiconductor Layer - A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s). The perforating elements can be separated from one another by a characteristic length scale selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer. The structure can be annealed using a set of conditions configured to ensure formation of the set of metal protrusions. | 12-05-2013 |
| 20130320353 | METHOD OF FORMING A GROUP III-NITRIDE CRYSTALLINE FILM ON A PATTERNED SUBSTRATE BY HYDRIDE VAPOR PHASE EPITAXY (HVPE) - A method of depositing a high quality low defect single crystalline Group III-Nitride film. A patterned substrate having a plurality of features with inclined sidewalls separated by spaces is provided. A Group III-Nitride film is deposited by a hydride vapor phase epitaxy (HVPE) process over the patterned substrate. The HVPE deposition process forms a Group III-Nitride film having a first crystal orientation in the spaces between features and a second different crystal orientation on the inclined sidewalls. The first crystal orientation in the spaces subsequently overgrows the second crystal orientation on the sidewalls and in the process turns over and terminates treading dislocations formed in the first crystal orientation. | 12-05-2013 |
| 20130320354 | Semiconductor Device Including a Normally-Off Transistor and Transistor Cells of a Normally-On GaN HEMT - A semiconductor device includes a first semiconductor die including a normally-off transistor and a second semiconductor die including a plurality of transistor cells of a normally-on GaN HEMT. One of a source terminal and a drain terminal of the normally-off transistor is electrically coupled to a gate terminal of the normally-on GaN HEMT, and the other one of the source terminal and the drain terminal of the normally-off transistor is electrically coupled to one of a source terminal and a drain terminal of the normally-on GaN HEMT. The second semiconductor die further includes a gate resistor electrically coupled between the gate terminal of the normally-off transistor and respective gates of the plurality of transistor cells, and a voltage clamping element electrically coupled between the gate terminal and one of the source terminal and the drain terminal of the normally-on GaN HEMT. | 12-05-2013 |
| 20130320355 | Substrate Structure, Method of Forming the Substrate Structure and Chip Comprising the Substrate Structure - A groove structure formed on a surface of a substrate. The groove structure includes a lateral epitaxial pattern in a cross section perpendicular to the surface, which has: a first edge inclined to the surface; a second edge adjacent to first edge and parallel to the surface; a third edge parallel to the first edge, having a projection on the surface covering the second edge; and a fourth edge adjacent to the third edge. A first intersection between the second edge and the third edge on the second edge and an injection of a second intersection between the third edge and the fourth edge on the second edge are located on two sides of a third intersection between the first edge and the second edge, or the injection of the second intersection between the third edge and the fourth edge on the second edge coincides with the third intersection. | 12-05-2013 |
| 20130328054 | GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gallium nitride based semiconductor device includes a silicon-based layer doped simultaneously with boron (B) and germanium (Ge) at a relatively high concentration, a buffer layer on the silicon-based layer, and a nitride stack on the buffer layer. A doping concentration of boron (B) and germanium (Ge) may be higher than 1×10 | 12-12-2013 |
| 20130328055 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes first and second electrodes, first, second and third semiconductor layers, and a light emitting layer. The first semiconductor layer of a first conductivity type is provided on the first electrode. The light emitting layer is provided on the first semiconductor layer. The second semiconductor layer of a second conductivity type is provided on the light emitting layer. The third semiconductor layer with low impurity concentration is provided on a part of the second semiconductor layer. The second electrode includes a pad section and a narrow wire section. The pad section is provided on the third semiconductor layer. The narrow wire section extends out from the pad section and includes an extending portion extending along a plane perpendicular to a stacking direction. The narrow wire section is in contact with the second semiconductor layer. | 12-12-2013 |
| 20130328056 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - Disclosed is a light emitting device including a substrate, a buffer layer on the substrate, and a light-emitting structure on the buffer layer. The buffer layer has a refractive index decreased toward the substrate from the light-emitting structure. | 12-12-2013 |
| 20130328057 | LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME - Disclosed herein is a light emitting diode, the structure of the light emitting diode comprises a substrate, a first-type semiconductor layer, a structural layer, a light emitting layer, a second-type semiconductor layer, a transparent conductive layer, a first contact pad and a second contact pad in regular turn. The structural layer comprises a stacked structure having a trapezoid sidewall and nano columns extending from the trapezoid sidewall in regular arrangement. Also, a method for fabricating the light emitting diode is disclosed. | 12-12-2013 |
| 20130328058 | Transversely-illuminated high current photoconductive switches with geometry-constrained conductivity path - A photoconductive switch having a wide bandgap semiconductor material substrate between opposing electrodes, with one of the electrodes having an aperture or apertures at an electrode-substrate interface for transversely directing radiation therethrough from a radiation source into a triple junction region of the substrate, so as to geometrically constrain the conductivity path to within the triple junction region. | 12-12-2013 |
| 20130328059 | Method Of Manufacturing Gallium Nitride Substrate And Gallium Nitride Substrate Manufactured Thereby - A method of manufacturing a gallium nitride (GaN) substrate and a GaN substrate manufactured thereby. The method includes the steps of growing an aluminum nitride nucleation layer on a base substrate, growing a first gallium nitride film on the base substrate on which the aluminum nitride nucleation layer has been grown, the first gallium nitride film having a first content ratio of nitrogen to gallium, and growing a second gallium nitride film on the first gallium nitride film, the second gallium nitride film having a second content ratio of nitrogen to gallium which is lower than the first content ratio. Self-separation between the base substrate and the GaN substrate is possible during the growth process, thereby precluding mechanical separation, increasing a self-separation area, and minimizing the occurrence of warping. | 12-12-2013 |
| 20130328060 | LAYOUT DESIGN FOR A HIGH POWER, GaN-BASED FET - A FET includes a first and second set of finger arrays that each include a source, gate and drain. A first source pad is electrically coupled to source electrodes in the first set of finger arrays. A second source pad is electrically coupled to the source electrodes in the second set of finger arrays. A common drain pad is electrically coupled to drain electrodes in the first and second set of finger arrays. A first gate pad is electrically coupled to gate electrodes in the first set of finger arrays. A second gate pad is electrically coupled to gate electrodes in the second set of finger arrays. A substrate is also provided on which are disposed the first and second set of finger arrays, the first and second source pads, the common drain pad, and the first and second gate pads. | 12-12-2013 |
| 20130334536 | SINGLE-CRYSTAL REO BUFFER ON AMORPHOUS SiOx - A method of forming a layer of amorphous silicon oxide positioned between a layer of rare earth oxide and a silicon substrate. The method includes providing a crystalline silicon substrate and depositing a layer of rare earth metal on the silicon substrate in an oxygen deficient ambient at a temperature above approximately 500° C. The rare earth metal forms a layer of rare earth silicide on the substrate. A first layer of rare earth oxide is deposited on the layer of rare earth silicide with a structure and lattice constant substantially similar to the substrate. The structure is annealed in an oxygen ambience to transform the layer of rare earth silicide to a layer of amorphous silicon and an intermediate layer of rare earth oxide between the substrate and the first layer of rare earth oxide. | 12-19-2013 |
| 20130334537 | Optically Controlled Power Devices - An electro-optically triggered power switch is disclosed utilizing a wide bandgap, high purity III-nitride semiconductor material such as BN, AN, GaN, InN and their compounds. The device is electro-optically triggered using a laser diode operating at a wavelength of 10 to 50 nanometers off the material's bandgap, and at a power level of 10 to 100 times less than that required in a conventionally triggered device. The disclosed device may be configured as a high power RF MOSFET, IGBT, FET, or HEMT that can be electro-optically controlled using photons rather than an electrical signal. Electro-optic control lowers the power losses in the semiconductor device, decreases the turn-on time, and simplifies the drive signal requirements. It also allows the power devices to be operated from the millisecond to the sub-picosecond timeframe, thus allowing the power device to be operated at RF frequencies (i.e., kilohertz to terahertz range) and at high temperatures where the bandgap changes with temperature. | 12-19-2013 |
| 20130334538 | HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE AND METHOD - Embodiments of the present disclosure describe structural configurations of an integrated circuit (IC) device such as a high electron mobility transistor (HEMT) switch device and method of fabrication. The IC device includes a buffer layer formed on a substrate, a channel layer formed on the buffer layer to provide a pathway for current flow in a transistor device, a spacer layer formed on the channel layer, a barrier layer formed on the spacer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) or gallium (Ga), a gate dielectric directly coupled with the spacer layer or the channel layer, and a gate formed on the gate dielectric, the gate being directly coupled with the gate dielectric. Other embodiments may also be described and/or claimed. | 12-19-2013 |
| 20130334539 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, and an inorganic film. The semiconductor layer includes a first surface having an unevenness, a second surface opposite to the first surface, and a light emitting layer. The semiconductor layer includes gallium nitride. The inorganic film is provided to conform to the unevenness of the first surface and in contact with the first surface. The inorganic film has main components of silicon and nitrogen. The inorganic film has a refractive index between a refractive index of the gallium nitride and a refractive index of air. An unevenness is formed also in a surface of the inorganic film. | 12-19-2013 |
| 20130334540 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A first electrode, an intrinsic first compound semiconductor layer over the first electrode, a second compound semiconductor layer whose band gap is smaller than that of the first compound semiconductor layer on the first compound semiconductor layer, and a second electrode over the second compound semiconductor layer are provided. | 12-19-2013 |
| 20130341632 | CURRENT APERTURE DIODE AND METHOD OF FABRICATING SAME - A diode and a method of making same has a cathode an anode and one or more semiconductor layers disposed between the cathode and the anode. A dielectric layer is disposed between at least one of the one or more semiconductor layers and at least one of the cathode or anode, the dielectric layer having one or more openings or trenches formed therein through which the at least one of said cathode or anode projects into the at least one of the one or more semiconductor layers, wherein a ratio of a total surface area of the one or more openings or trenches formed in the dielectric layer at the at least one of the one or more semiconductor layers to a total surface area of the dielectric layer at the at least one of the one or more semiconductor layers is no greater than 0.25. | 12-26-2013 |
| 20130341633 | Semiconductor Device - Provided is a semiconductor device comprising: a GaN crystal substrate defining a principal, (0001) Ga face and defining a matrix, being a majority, polarity-determining domain of the GaN crystal, and inversion domains, being domains in which the polarity in the GaN crystal's [0001] direction is inverted with respect to the matrix, the GaN substrate having a ratio S | 12-26-2013 |
| 20130341634 | LIGHT EMITTING DIODE DIELECTRIC MIRROR - A high efficiency LED chip is disclosed that comprises an active LED structure comprising an active layer between two oppositely doped layers. A first reflective layer can be provided adjacent to one of the oppositely doped layers, with the first layer comprising a material with a different index of refraction than the active LED structure. The difference in IR between the active LED structure and the first reflective layer increases TIR of light at the junction. In some embodiments the first reflective layer can comprise an IR lower than the semiconductor material, increasing the amount of light that can experience TIR. Some embodiments of LED chips according to the present invention can also comprise a second reflective layer or metal layer on and used in conjunction with the first reflective layer such that light passing through the first reflective layer can be reflected by the second reflective layer. | 12-26-2013 |
| 20130341635 | DOUBLE ALUMINUM NITRIDE SPACERS FOR NITRIDE HIGH ELECTRON-MOBILITY TRANSISTORS - An epitaxial structure and a high electron mobility transistor (HEMT) employing the epitaxial structure includes a first spacer layer over a channel layer, a first barrier layer over the first spacer layer, and a second spacer layer over the first barrier layer. | 12-26-2013 |
| 20130341636 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND PRODUCTION METHOD THEREFOR - The present invention provides a Group III nitride semiconductor light-emitting device exhibiting improved light extraction efficiency. An AlGaN semiconductor layer is formed in contact with and on a p-GaN p-contact layer, and an ITO transparent electrode is formed in contact with and on the semiconductor layer. The semiconductor layer comprises AlGaN having an Al composition ratio of 10 mol % to 50 mol %, and has a thickness of 2 Å to 50 Å. The semiconductor layer has a refractive index at an emission wavelength lower than that of the p-contact layer, and larger than that of the transparent electrode. By forming such a semiconductor layer, the reflection is suppressed between the p-contact layer and the transparent electrode, thereby improving the light extraction efficiency. | 12-26-2013 |
| 20130341637 | CARBODIIMIDE PHOSPHORS - The invention relates to compounds of the general formula I | 12-26-2013 |
| 20140001478 | GROUP III-NITRIDE TRANSISTOR USING A REGROWN STRUCTURE | 01-02-2014 |
| 20140001479 | SWITCHING DEVICE WITH CHARGE DISTRIBUTION STRUCTURE | 01-02-2014 |
| 20140001480 | Lead Frame Packages and Methods of Formation Thereof | 01-02-2014 |
| 20140001481 | SEMICONDUCTOR DEVICE | 01-02-2014 |
| 20140001482 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 01-02-2014 |
| 20140001483 | LIGHT EMITTING DIODE AND METHOD FOR FABRICATING THE SAME | 01-02-2014 |
| 20140001484 | Method Of Manufacturing Gallium Nitride Substrate And Gallium Nitride Substrate Manufactured By The Same | 01-02-2014 |
| 20140001485 | GLASS-CERAMIC SUBSTRATES FOR SEMICONDUCTOR PROCESSING | 01-02-2014 |
| 20140001486 | COMPOSITE SEMIDCONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD | 01-02-2014 |
| 20140001487 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE | 01-02-2014 |
| 20140008660 | MATERIALS, STRUCTURES, AND METHODS FOR OPTICAL AND ELECTRICAL III-NITRIDE SEMICONDUCTOR DEVICES - The present invention provides materials, structures, and methods for III-nitride-based devices, including epitaxial and non-epitaxial structures useful for III-nitride devices including light emitting devices, laser diodes, transistors, detectors, sensors, and the like. In some embodiments, the present invention provides metallo-semiconductor and/or metallo-dielectric devices, structures, materials and methods of forming metallo-semiconductor and/or metallo-dielectric material structures for use in semiconductor devices, and more particularly for use in III-nitride based semiconductor devices. In some embodiments, the present invention includes materials, structures, and methods for improving the crystal quality of epitaxial materials grown on non-native substrates. In some embodiments, the present invention provides materials, structures, devices, and methods for acoustic wave devices and technology, including epitaxial and non-epitaxial piezoelectric materials and structures useful for acoustic wave devices. In some embodiments, the present invention provides metal-base transistor devices, structures, materials and methods of forming metal-base transistor material structures for use in semiconductor devices. | 01-09-2014 |
| 20140008661 | NITRIDE-BASED COMPOUND SEMICONDUCTOR DEVICE - A nitride-based compound semiconductor device includes a substrate, a first nitride-based compound semiconductor layer that is formed above the substrate with a buffer layer interposed between them, a second nitride-based compound semiconductor layer that is formed on the first nitride-based compound semiconductor layer and that has a larger band gap than a band gap of the first nitride-based compound semiconductor layer, and an electrode that is formed on the second nitride-based compound semiconductor layer. The second nitride-based compound semiconductor layer has a region in which carbon is doped near a surface of the second nitride-based compound semiconductor layer. | 01-09-2014 |
| 20140008662 | PHOTOVOLTAIC DEVICES INCLUDING HETEROJUNCTIONS - A photovoltaic cell including a first semiconductor layer that includes a III-V compound semiconductor, the first semiconductor layer positioned over a transparent conductive layer, and a second semiconductor layer that includes a II-VI compound semiconductor, the second semiconductor layer positioned between the first semiconductor layer and a back metal contact. The photovoltaic cell further includes an interfacial layer between the first and second semiconductor layers that enhances a rectifying junction formed between the III-V and II-VI compound semiconductor materials. | 01-09-2014 |
| 20140008663 | Integrated Composite Group III-V and Group IV Semiconductor Device - According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench. | 01-09-2014 |
| 20140014965 | Chemical vapor deposition system with in situ, spatially separated plasma - Chemical vapor deposition (CVD) systems and methods for forming layers on a substrate are disclosed. Embodiments of the system comprise a chamber having a controlled environmental temperature and pressure and containing a first environment for performing CVD on a substrate, and a second environment for contacting the substrate with a plasma; a substrate transport system capable of positioning a substrate for sequential processing in each environment, and a gas control system capable of maintaining site isolation. Methods of forming layers on a substrate comprise forming a first layer from a precursor on a substrate in a CVD environment, contacting the substrate with plasma in a plasma environment, wherein the forming and contacting steps are performed in the unitary system and repeating the forming and contacting steps until a layer of desired thickness is formed. The forming and contacting steps can be performed to form devices having multiple distinct layers, such as Group III-V thin film devices. | 01-16-2014 |
| 20140014966 | GALLIUM NITRIDE DEVICES HAVING LOW OHMIC CONTACT RESISTANCE - A semiconductor structure having mesa structure comprising: a lower semiconductor layer; an upper semiconductor layer having a higher band gap than, and in direct contact with, the lower semiconductor layer to form a two-dimension electron gas (2DEG) region between the upper semiconductor layer. The 2DEG region has outer edges terminating at sidewalls of the mesa. An additional electron donor layer has a band gap higher than the band gap of the lower layer disposed on sidewall portions of the mesa structure and on the region of the 2DEG region terminating at sidewalls of the mesa. An ohmic contact material is disposed on the electron donor layer. In effect, a sideway HEMT is formed with the electron donor layer, the 2DEG region and the ohmic contact material increasing the concentration of electrons (i.e., lowering ohmic contact resistance) all along the contact between the lower semiconductor layer and the electron donor layer. | 01-16-2014 |
| 20140014967 | Diffusion Barrier Layer for Group III Nitride on Silicon Substrate - The present disclosure is directed to an integrated circuit and its formation. In some embodiments, the integrated circuit includes a diffusion barrier layer. The diffusion barrier layer can be arranged to prevent diffusion of the Si and O | 01-16-2014 |
| 20140021479 | GAN POWER DEVICE WITH SOLDERABLE BACK METAL - A method for fabricating a vertical gallium nitride (GaN) power device can include providing a GaN substrate with a top surface and a bottom surface, forming a device layer coupled to the top surface of the GaN substrate, and forming a metal contact on a top surface of the vertical GaN power device. The method can further include forming a backside metal by forming an adhesion layer coupled to the bottom surface of the GaN substrate, forming a diffusion barrier coupled to the adhesion layer, and forming a protection layer coupled to the diffusion barrier. The vertical GaN power device can be configured to conduct electricity between the metal contact and the backside metal. | 01-23-2014 |
| 20140021480 | HIGH ELECTRON MOBILITY TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - A HEMT according to example embodiments may include a first semiconductor layer, a second semiconductor layer configured to induce a 2-dimensional electron gas (2DEG) in the second semiconductor layer, an insulating mask layer on the second semiconductor layer, a depletion forming layer on one of a portion of the first semiconductor layer and a portion of the second semiconductor layer that is exposed by an opening defined by the insulating mask layer, a gate on the depletion forming layer, and a source and a drain on at least one of the first semiconductor layer and the second semiconductor layer. The source and drain may be spaced apart from the gate. The depleting forming layer may be configured to form a depletion region in the 2DEG. | 01-23-2014 |
| 20140021481 | NITRIDE-BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A nitride-based semiconductor device includes a buffer layer on a substrate, a nitride-based semiconductor layer on the buffer layer, at least one ion implanted layer within the nitride-based semiconductor layer, and a channel layer on the nitride-based semiconductor layer. | 01-23-2014 |
| 20140021482 | LIGHT EMITTING DEVICE HAVING VERTICAL STRUCTURE AND PACKAGE THEREOF - A light emitting device having a vertical structure and a package thereof, which are capable of damping impact generated in a substrate separation process, and achieving an improvement in mass productivity. The device and package include a sub-mount, a first-type electrode, a second-type electrode, a light emitting device, a zener diode, and a lens on the sub-mount. | 01-23-2014 |
| 20140021483 | Forming Light-Emitting Diodes Using Seed Particles - A seed layer for growing a group | 01-23-2014 |
| 20140027777 | GROWING OF GALLIUM-NITRADE LAYER ON SILICON SUBSTRATE - Embodiments relate to growing an epitaxy gallium-nitride (GaN) layer on a porous silicon (Si) substrate. The porous Si substrate has a larger surface area compared to non-porous Si substrate to distribute and accommodate stress caused by materials deposited on the substrate. An interface adjustment layer (e.g., transition metal silicide layer) is formed on the porous silicon substrate to promote growth of a buffer layer. A buffer layer formed for GaN layer may then be formed on the silicon substrate. A seed-layer for epitaxial growth of GaN layer is then formed on the buffer layer. | 01-30-2014 |
| 20140027778 | Robust Fused Transistor - According to an exemplary implementation, a transistor includes a plurality of drain fingers interdigitated with a plurality of source fingers. The transistor further includes a gate configured to control current conduction between the plurality of drain fingers and the plurality of source fingers. Additionally, the transistor includes a plurality of drain fuses, each being configured to electrically disconnect a drain finger of the plurality of drain fingers from remaining ones of the plurality of drain fingers. At least one of the plurality of drain fuses can electrically couple the drain finger to a common drain pad. The transistor may further include a plurality of source fuses, each being configured to electrically disconnect a source finger of the plurality of source fingers from remaining ones of the plurality of source fingers. | 01-30-2014 |
| 20140027779 | HIGH ELECTRON MOBILITY TRANSISTOR - According to example embodiments, a high electron mobility transistor includes: a channel layer including a 2-dimensional electron gas (2DEG); a contact layer on the channel layer; a channel supply layer on the contact layer; a gate electrode on a portion of the channel layer; and source and drain electrodes on at least one of the channel layer, the contact layer, and the channel supply layer. The contact layer is configured to form an ohmic contact on the channel layer. The contact layer is n-type doped and contains a Group III-V compound semiconductor. The source electrode and the drain electrode are spaced apart from opposite sides of the gate electrode. | 01-30-2014 |
| 20140027780 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - Disclosed is a light-emitting device comprising a light-emitting element ( | 01-30-2014 |
| 20140034957 | Index-Matched Insulators - Devices are described including a first component and a second component, wherein the first component comprises a Group III-N semiconductor and the second component comprises a bimetallic oxide containing tin, having an index of refraction within 15% of the index of refraction of the Group III-N semiconductor, and having negligible extinction coefficient at wavelengths of light emitted or absorbed by the Group III-N semiconductor. The first component is in optical contact with the second component. Exemplary bimetallic oxides include Sn | 02-06-2014 |
| 20140034958 | LIGHT EMITTING DEVICE - A light emitting device is disclosed. The light emitting device includes a first-conductive-type semiconductor layer, a second-conductive-type semiconductor layer, and an active layer interposed between the first-conductive-type semiconductor layer and the second-conductive-type semiconductor layer. The second-conductive-type semiconductor layer includes an electron blocking region closely disposed to the active layer and having a pattern with a plurality of elements spaced apart from each other. | 02-06-2014 |
| 20140034959 | III-Nitride Semiconductor Device with Stepped Gate - A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same. | 02-06-2014 |
| 20140034960 | ELECTRONIC DEVICES WITH YIELDING SUBSTRATES - In accordance with certain embodiments, a semiconductor die is adhered directly to a yielding substrate with a pressure-activated adhesive notwithstanding any nonplanarity of the surface of the semiconductor die or non-coplanarity of the semiconductor die contacts. | 02-06-2014 |
| 20140034961 | SURFACE-MODIFIED SEMICONDUCTOR, METHOD OF MAKING THE SEMICONDUCTOR, AND METHOD OF ARRANGING PARTICLES - The terminating layer that covers the top layer of a GaN-based semiconductor having a principal surface which is either a non-polar plane or a semi-polar plane, is removed by performing an organic solvent cleaning process step, and replaced with an organic solvent cleaned layer. Next, by irradiating the semiconductor with an ultraviolet ray, the organic solvent cleaned layer is removed to form a surface-modified layer instead. By performing these process steps, the top layer of the GaN-based semiconductor becomes the surface-modified layer and an electrical polarity is given to the surface of the GaN-based semiconductor. As a result, the hydrophilicity, hydrophobicity and wettability of the GaN-based semiconductor can be controlled. | 02-06-2014 |
| 20140034962 | Normally-Off Compound Semiconductor Tunnel Transistor with a Plurality of Charge Carrier Gases - A tunnel transistor includes a first compound semiconductor, a second compound semiconductor on the first compound semiconductor, and a third compound semiconductor on the second compound semiconductor. A source extends through the second compound semiconductor into the first compound semiconductor. A drain spaced apart from the source extends through the third compound semiconductor into the second compound semiconductor. A first two-dimensional charge carrier gas extends in the first compound semiconductor from the source toward the drain and ends prior to reaching the drain. A second two-dimensional charge carrier gas extends in the second compound semiconductor from the drain toward the source and ends prior to reaching the source. A gate is over the first and second two-dimensional charge carrier gases. A corresponding method of manufacturing the tunnel transistor is also provided. | 02-06-2014 |
| 20140042446 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are in contact with the second III-V compound layer. A n-type doped region underlies each source feature and drain feature in the second III-V compound layer. A p-type doped region underlies each n-type doped region in the first III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the source feature and the drain feature. | 02-13-2014 |
| 20140042447 | METHOD AND SYSTEM FOR GALLIUM NITRIDE ELECTRONIC DEVICES USING ENGINEERED SUBSTRATES - A method for fabricating an electronic device includes providing an engineered substrate structure comprising a III-nitride seed layer, forming GaN-based functional layers coupled to the III-nitride seed layer, and forming a first electrode structure electrically coupled to at least a portion of the GaN-based functional layers. The method also includes joining a carrier substrate opposing the GaN-based functional layers and removing at least a portion of the engineered substrate structure. The method further includes forming a second electrode structure electrically coupled to at least another portion of the GaN-based functional layers and removing the carrier substrate. | 02-13-2014 |
| 20140042448 | High Breakdown Voltage III-Nitride Device - A semiconductor device includes a semiconductor body having a compound semiconductor material on a substrate. The compound semiconductor material has a channel region. A source region extends to the compound semiconductor material. A drain region also extends to the compound semiconductor material and is spaced apart from the source region by the channel region. An insulating region is buried in the semiconductor body between the compound semiconductor material and the substrate in an active region of the semiconductor device. The active region includes the source, the drain and the channel region of the device. The insulating region is discontinuous over a length of the channel region between the source region and the drain region. | 02-13-2014 |
| 20140042449 | HIGH ELECTRON MOBILITY TRANSISTOR - According to example embodiments, a high electron mobility transistor (HEMT) includes a channel supply layer that induces a two-dimensional electron gas (2DEG) in a channel layer, a source electrode and a drain electrode that are at sides of the channel supply layer, a depletion-forming layer that is on the channel supply layer and contacts the source electrode, a gate insulating layer on the depletion-forming layer, and a gate electrode on the gate insulating layer. The depletion-forming layer forms a depletion region in the 2DEG. | 02-13-2014 |
| 20140042450 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device is provided that includes a semiconductor layer and an electrode coupled to a semiconductor layer. The electrode includes first and second end portions, the first end portion being closer to the semiconductor layer than the second end portion. The first end portion is formed to have crystals of a first grain size, and the second end portion is formed to have crystals of a second grain size that is larger than the first grain size. | 02-13-2014 |
| 20140042451 | SEMICONDUCTOR DEVICE, HEMT DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which a reverse leakage current is suppressed and the mobility of a two-dimensional electron gas is high. A semiconductor device includes: an epitaxial substrate in which a group of group-III nitride layers are laminated on a base substrate such that a (0001) crystal plane is substantially in parallel with a substrate surface; and a Schottky electrode. The epitaxial substrate includes: a channel layer made of a first group-III nitride having a composition of In | 02-13-2014 |
| 20140042452 | III-NITRIDE ENHANCEMENT MODE TRANSISTORS WITH TUNABLE AND HIGH GATE-SOURCE VOLTAGE RATING - A semiconductor device includes an enhancement mode GaN FET with a depletion mode GaN FET electrically coupled in series between a gate node of the enhancement mode GaN FET and a gate terminal of the semiconductor device. A gate node of the depletion mode GaN FET is electrically coupled to a source node of the enhancement mode GaN FET. A source node of said enhancement mode GaN FET is electrically coupled to a source terminal of the semiconductor device, a drain node of the enhancement mode GaN FET is electrically coupled to a drain terminal of said semiconductor device, and a drain node of the depletion mode GaN FET is electrically coupled to a gate terminal of the semiconductor device. | 02-13-2014 |
| 20140042453 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300° C. or more and 1500° C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided. | 02-13-2014 |
| 20140042454 | SEMICONDUCTOR LIGHT EMTTING DEVICE - A semiconductor light emitting device includes a substrate, a buffer layer disposed on the substrate, the buffer layer comprising aluminum nitride, a composition grading layer disposed on the buffer layer, the composition grading layer comprising first aluminum nitride and second aluminum nitride, a capping layer disposed on the composition grading layer, and a cladding layer disposed on the capping layer. A composition of the first aluminum nitride and a composition of the second aluminum nitride change gradually in an alternating manner. | 02-13-2014 |
| 20140042455 | FIELD EFFECT TRANSISTOR DEVICE - A field effect transistor device is provided by the invention. The field effect transistor device includes: a substrate; a buffer layer, a channel layer, and a first barrier layer sequentially disposed on the substrate; a two-dimensional electron gas controlling layer disposed on the first barrier layer; a second barrier layer disposed on the two-dimensional electron gas controlling layer, wherein the second barrier layer has a recess passing through the second barrier layer; and a gate electrode filled into the recess and separated from the second barrier layer and the two-dimensional electron gas controlling layer by an insulating layer. | 02-13-2014 |
| 20140042456 | NITRIDE SEMICONDUCTOR LIGHT EMITTING CHIP, AND NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - A nitride semiconductor light emitting chip includes: a conductive substrate including a nitride semiconductor layer; an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer sequentially formed on a principal surface of the nitride semiconductor layer; and an n-side electrode formed in contact with the conductive substrate. A recess is formed in a back surface of the conductive substrate opposite to the principal surface. The n-side electrode is in contact with at least part of a surface of the recess. A depth D1 is not less than 25% of a thickness T, where T represents a thickness of the conductive substrate, and D1 represents a depth of the recess. | 02-13-2014 |
| 20140042457 | SCHOTTKY DIODE - A Schottky diode has: a semiconductor layer stack including a GaN layer formed over a substrate and an AlGaN layer formed on the GaN layer and having a wider bandgap than the GaN layer; an anode electrode and a cathode electrode which are formed at an interval therebetween on the semiconductor layer stack; and a block layer formed in a region between the anode electrode and the cathode electrode so as to contact the AlGaN layer. A part of the anode electrode is formed on the block layer so as not to contact the surface of the AlGaN layer. The barrier height between the anode electrode and the block layer is greater than that between the anode electrode and the AlGaN layer. | 02-13-2014 |
| 20140042458 | GROWTH OF MULTI-LAYER GROUP III-NITRIDE BUFFERS ON LARGE-AREA SILICON SUBSTRATES AND OTHER SUBSTRATES - A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer. | 02-13-2014 |
| 20140048815 | SCHOTTKY BARRIER DIODE AND MANUFACTURING METHOD THEREOF - A Schottky barrier diode (SBD) is disclosed, which includes: a gallium nitride (GaN) layer, formed on a substrate; an aluminum gallium nitride (AlGaN), formed on the GaN layer; an insulation layer, formed on the AlGaN layer; an anode conducive layer, formed on the insulation layer, wherein Schottky contact is formed between a part of the anode conductive layer and the AlGaN layer or between a part of the anode conductive layer and the GaN layer, and another part of the anode conductive layer is separated from the AlGaN layer by the insulation layer; and a cathode conductive layer, formed on the AlGaN layer, wherein an ohmic contact is formed between the cathode conductive layer and the GaN layer or between the cathode conductive layer and the AlGaN layer, and wherein the anode conductive layer is not directly connected to the cathode conductive layer. | 02-20-2014 |
| 20140048816 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a metal substrate, a first semiconductor layer, a first semiconductor layer, a second semiconductor layer, a light emitting layer, a first intermediate layer and a second intermediate layer. The substrate has a coefficient of thermal expansion not more than 10×10 | 02-20-2014 |
| 20140048817 | LIGHT EMITTING DEVICE WITH IMPROVED EXTRACTION EFFICIENCY - In embodiments of the invention, a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown on a substrate. The substrate is a non-III-nitride material. The substrate has an in-plane lattice constant a | 02-20-2014 |
| 20140048818 | PHOTOELECTRIC CONVERSION ELEMENT, PHOTOELECTRIC CONVERSION SYSTEM, AND METHOD FOR PRODUCTION OF PHOTOELECTRIC CONVERSION ELEMENT - A photoelectric conversion element of an embodiment is a photoelectric conversion element which performs photoelectric conversion by receiving illumination light having n light emission peaks having a peak energy Ap (eV) (where 1≦p≦n and 2≦n) of 1.59≦Ap≦3.26 and a full width at half maximum Fp (eV) (where 1≦p≦n and 2≦n), wherein the photoelectric conversion element includes m photoelectric conversion layers having a band gap energy Bq (eV) (where 1≦q≦m and 2≦m≦n), and the m photoelectric conversion layers each satisfy the relationship of Ap−Fp| 02-20-2014 | |
| 20140048819 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - According to one embodiment, a semiconductor light-emitting device includes: a first conductivity type first semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in a (0001) surface; a second conductivity type second semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in the (0001) surface; a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, containing a nitride semiconductor crystal, and having an average lattice constant larger than the lattice constant of the first semiconductor layer; and a first stress application layer provided on a side opposite to the light emitting layer of the first semiconductor layer and applying a compressive stress to the first semiconductor layer. | 02-20-2014 |
| 20140048820 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light emitting device includes a first and second conductive semiconductor layers including an n-type dopant on active layer; a third and fourth conductive semiconductor layers including a p-type dopant under the active layer; wherein the first to fourth conductive semiconductor layers are formed of an AlGaN-based semiconductor, wherein the active layer includes a plurality of quantum barrier layers and a plurality of quantum well layers, wherein the plurality of quantum well layers include an InGaN semiconductor layer, wherein the plurality of quantum barrier layers include an AlGaN-based semiconductor layer, wherein at least two of the plurality barrier layers have a thickness of about 50 Å to about 300 Å, respectively, wherein a cycle of the quantum barrier layer and the quantum well layer includes a cycle of 2 to 10, wherein the second conductive semiconductor layer has a thickness thinner than a thickness of the third conductive semiconductor layer. | 02-20-2014 |
| 20140048821 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - A nitride semiconductor light-emitting device includes a nitride semiconductor light-emitting chip including an active layer for outputting polarized light, the active layer having a non-polar plane or a semi-polar plane as a growth plane; and a light-transmissive cover for transmitting light from the active layer. The light-transmissive cover includes a first light-transmissive member located in an area, among areas to the side of the nitride semiconductor light-emitting chip, and in a direction perpendicular to a polarization direction of the polarized light, and a second light-transmissive member located in an area above the nitride semiconductor light-emitting chip. The first light-transmissive member has a higher diffuse transmittance than the second light-transmissive member. | 02-20-2014 |
| 20140048822 | LIGHT EMITTING DIODES INCLUDING CURRENT SPREADING LAYER AND BARRIER SUBLAYERS - Semiconductor light emitting devices, such as light emitting diodes, include a substrate, an epitaxial region on the substrate that includes a light emitting region such as a light emitting diode region, and a multilayer conductive stack including a current spreading layer, on the epitaxial region. A barrier layer is provided on the current spreading layer and extending on a sidewall of the current spreading layer. The multilayer conductive stack can also include an ohmic layer between the reflector and the epitaxial region. The barrier layer further extends on a sidewall of the ohmic layer. The barrier layer can also extend onto the epitaxial region outside the multilayer conductive stack. The barrier layer can be fabricated as a series of alternating first and second sublayers. | 02-20-2014 |
| 20140048823 | SEMICONDUCTOR STACKED BODY, METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR ELEMENT - A method for manufacturing a semiconductor stacked body, and a semiconductor element including the semiconductor stacked body includes a semiconductor stacked body, including a Ga | 02-20-2014 |
| 20140054593 | NITRIDE SEMICONDUCTOR STRUCTURE - A nitride semiconductor structure is provided. The nitride semiconductor structure at least includes a silicon substrate, a AlN layer, a AlGaN layer and a GaN layer formed on the AlGaN layer. The silicon substrate has a surface tilted at 0| 02-27-2014 | |
| 20140054594 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer, a light emitting layer, a dielectric layer, a first electrode, a second electrode and a support substrate. The first layer has a first and second surface. The second layer is provided on a side of the second surface of the first layer. The emitting layer is provided between the first and the second layer. The dielectric layer contacts the second surface and has a refractive index lower than that of the first layer. The first electrode includes a first and second portion. The first portion contacts the second surface and provided adjacent to the dielectric layer. The second portion contacts with an opposite side of the dielectric layer from the first semiconductor layer. The second electrode contacts with an opposite side of the second layer from the emitting layer. | 02-27-2014 |
| 20140054595 | COMPOSITE SUBSTRATE OF GALLIUM NITRIDE AND METAL OXIDE - The present invention discloses a novel composite substrate which solves the problem associated with the quality of substrate surface. The composite substrate has at least two layers comprising the first layer composed of Ga | 02-27-2014 |
| 20140054596 | SEMICONDUCTOR DEVICE WITH ELECTRICAL OVERSTRESS (EOS) PROTECTION - A semiconductor device with electrical overstress (EOS) protection is disclosed. The semiconductor device includes a semi-insulating layer, a first contact disposed onto the semi-insulating layer, and a second contact disposed onto the semi-insulating layer. A passivation layer is disposed onto the semi-insulating layer. The passivation layer has a dielectric strength that is greater than that of the semi-insulating layer to ensure that a voltage breakdown occurs within the semi-insulating layer within a semi-insulating region between the first contact and the second contact before a voltage breakdown can occur in the passivation layer. | 02-27-2014 |
| 20140054597 | POWER DEVICE AND PACKAGING THEREOF - The present disclosure provides a power device and power device packaging. Generally, the power device of the present disclosure includes a die backside and a die frontside. A semi-insulating substrate with epitaxial layers disposed thereon is sandwiched between the die backside and the die frontside. Pads on the die frontside are coupled to the die backside with patterned backmetals that are disposed within vias that pass through the semi-insulating substrate and epitaxial layers from the die backside to the die frontside. | 02-27-2014 |
| 20140054598 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Certain embodiments provide semiconductor device including a semiconductor layer including a channel layer, a barrier layer, and a cap layer, the semiconductor layer provided on a semiconductor substrate, a drain electrode and a source electrode, an opening of the cap layer, and a gate electrode. The drain electrode and the source electrode are provided on the barrier layer. The opening is provided in the cap layer provided between the drain electrode and the source electrode, the opening being separated from the drain electrode and the source electrode. The gate electrode is provided so as to be in contact with the barrier layer exposed in the opening of the cap layer and also insulated from a side surface of the opening of the cap layer. Inside the opening, a distance between the gate electrode and the side surface of the opening increases with a decreasing distance from the barrier layer. | 02-27-2014 |
| 20140054599 | FLEXIBLE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A flexible semiconductor device and a method of manufacturing the flexible semiconductor device are provided. The flexible semiconductor device may include at least one vertical semiconductor element that is at least partly embedded in a flexible material layer. The flexible semiconductor device may further include a first electrode formed on a first surface of the flexible material layer and a second electrode formed on a second surface of the flexible material layer. A method of manufacturing a flexible semiconductor device may include separating a flexible material layer, in which the at least one vertical semiconductor element is embedded, from a substrate by weakening or degrading an adhesive force between an underlayer and a buffer layer by using a difference in coefficients of thermal expansion of the underlayer and the buffer layer. | 02-27-2014 |
| 20140054600 | NITRIDE SEMICONDUCTOR AND FABRICATING METHOD THEREOF - This specification is directed to a semiconductor device capable of reducing a leakage current by forming a first GaN layer including a plurality of GaN layers and Fe | 02-27-2014 |
| 20140054601 | GALLIUM NITRIDE (GAN) DEVICE WITH LEAKAGE CURRENT-BASED OVER-VOLTAGE PROTECTION - A gallium nitride (GaN) device with leakage current-based over-voltage protection is disclosed. The GaN device includes a drain and a source disposed on a semiconductor substrate. The GaN device also includes a first channel region within the semiconductor substrate and between the drain and the source. The GaN device further includes a second channel region within the semiconductor substrate and between the drain and the source. The second channel region has an enhanced drain induced barrier lowering (DIBL) that is greater than the DIBL of the first channel region. As a result, a drain voltage will be safely clamped below a destructive breakdown voltage once a substantial drain current begins to flow through the second channel region. | 02-27-2014 |
| 20140054602 | FIELD EFFECT TRANSISTOR (FET) HAVING FINGERS WITH RIPPLED EDGES - A field effect transistor (FET) having fingers with rippled edges is disclosed. The FET includes a semiconductor substrate having a front side with a finger axis. A drain finger is disposed on the front side of the semiconductor substrate such that a greatest dimension of the drain finger lies parallel to the finger axis. A gate finger is disposed on the front side of the semiconductor substrate. The gate finger is spaced from the drain finger such that a greatest dimension of the gate finger lies parallel to the finger axis. A source finger is disposed on the front side of the semiconductor substrate. The source finger is spaced from the gate finger such that a greatest dimension of the source finger lies parallel to the finger axis. The drain finger, the gate finger, and the source finger each have rippled edges with an axis parallel with the finger axis. | 02-27-2014 |
| 20140054603 | Semiconductor Heterostructure Diodes - Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG. | 02-27-2014 |
| 20140054604 | SEMICONDUCTOR DEVICE HAVING IMPROVED HEAT DISSIPATION - A semiconductor device having improved heat dissipation is disclosed. The semiconductor device includes a semi-insulating substrate and epitaxial layers disposed on the semi-insulating substrate wherein the epitaxial layers include a plurality of heat conductive vias that are disposed through the epitaxial layers with the plurality of heat conductive vias being spaced along a plurality of finger axes that are aligned generally parallel across a surface of the epitaxial layers. The semiconductor device further includes an electrode having a plurality of electrically conductive fingers that are disposed along the plurality of finger axes such that the electrically conductive fingers are in contact with the first plurality of heat conductive vias. | 02-27-2014 |
| 20140054605 | Composite Substrates, Light Emitting Devices and a Method of Producing Composite Substrates - A plurality of protrusions | 02-27-2014 |
| 20140054606 | SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE PROVIDED OVER ACTIVE REGION IN P-TYPE NITRIDE SEMICONDUCTOR LAYER AND METHOD OF MANUFACTURING THE SAME, AND POWER SUPPLY APPARATUS - A semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a p-type nitride semiconductor layer provided over the nitride semiconductor stacked structure and including an active region and an inactive region; an n-type nitride semiconductor layer provided on the inactive region in the p-type nitride semiconductor layer; and a gate electrode provided over the active region in the p-type nitride semiconductor layer. | 02-27-2014 |
| 20140054607 | Group III-V Device with Strain-Relieving Layers - According to one exemplary embodiment, a group III-V semiconductor device includes at least one transition layer situated over a substrate. The group III-V semiconductor device further includes a first strain-relieving interlayer situated over the at least one transition layer and a second strain-relieving interlayer situated over the first strain-relieving interlayer. The group III-V semiconductor device further includes a first group III-V semiconductor body situated over the second strain-relieving interlayer. The first and second strain-relieving interlayers comprise different semiconductor materials so as to reduce a strain in the first group III-V semiconductor body. The second strain-relieving interlayer can be substantially thinner than the first strain-relieving interlayer. | 02-27-2014 |
| 20140061658 | High Electron Mobility Transistor and Manufacturing Method Thereof - The present invention discloses an enhanced mode high electron mobility transistor (HEMT) which includes: a P-type gallium nitride (GaN) layer; a barrier layer, which is formed on and connected to the GaN layer; a dielectric layer, which is formed on and connected to the GaN layer, wherein the barrier layer does not overlap at least part of the dielectric layer; a gate, which is formed on the dielectric layer for receiving a gate voltage; and a source and a drain, which are formed at two sides of the gate on the GaN layer respectively; wherein a two dimensional electron gas (2DEG) is formed at a junction of the GaN layer and the barrier layer which does not include a portion of the junction below the gate, and the 2DEG does not electrically connect the source to the drain when there is no voltage applied to the gate. | 03-06-2014 |
| 20140061659 | GaN Dual Field Plate Device with Single Field Plate Metal - A low leakage current transistor ( | 03-06-2014 |
| 20140061660 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor light emitting device includes a supporting substrate, a light emitting layer including a nitride semiconductor, and a nitride multilayer film. The nitride multilayer film includes a first layer including a first nitride semiconductor containing aluminum nitride, a second layer including a second nitride semiconductor containing gallium nitride, and a third layer including the first nitride semiconductor containing aluminum nitride. | 03-06-2014 |
| 20140061661 | SAPPHIRE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME AND NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT - [Technical Problem] | 03-06-2014 |
| 20140061662 | GROUP III NITRIDE WAFER AND ITS PRODUCTION METHOD - The present invention discloses a group III nitride wafer such as GaN, AlN, InN and their alloys having one surface visually distinguishable from the other surface. After slicing of the wafer from a bulk crystal of group III nitride with a mechanical method such as multiple wire saw, the wafer is chemically etched so that one surface of the wafer is visually distinguishable from the other surface. The present invention also discloses a method of producing such wafers. | 03-06-2014 |
| 20140061663 | SEMICONDUCTOR BUFFER STRUCTURE, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF - A semiconductor structure including a first nitride semiconductor layer, a second nitride semiconductor layer, and a third layer between the first nitride semiconductor layer and the second nitride semiconductor layer. The first nitride semiconductor layer has a first gallium composition ratio, the second nitride semiconductor layer has a second gallium composition ratio different from the first metal composition ratio, and the third layer has a third gallium composition ratio greater than at least one of the first gallium composition ratio or the second gallium composition ratio. The structure may also include a fourth layer for reducing tensile stress or increasing compression stress experienced by at least the second nitride semiconductor layer. | 03-06-2014 |
| 20140061664 | LIGHT EMITTING DEVICE USING GAN LED CHIP - A light emitting device is constituted by flip-chip mounting a GaN-based LED chip. The GaN-based LED chip includes a light-transmissive substrate and a GaN-based semiconductor layer formed on the light-transmissive substrate, wherein the GaN-based semiconductor layer has a laminate structure containing an n-type layer, a light emitting layer and a p-type layer in this order from the light-transmissive substrate side, wherein a positive electrode is formed on the p-type layer, the electrode containing a light-transmissive electrode of an oxide semiconductor and a positive contact electrode electrically connected to the light-transmissive electrode, and the area of the positive contact electrode is half or less of the area of the upper surface of the p-type layer. | 03-06-2014 |
| 20140061665 | NITRIDE SEMICONDUCTOR WAFER - A nitride semiconductor wafer includes a substrate, and a buffer layer formed on the substrate and including an alternating layer of Al | 03-06-2014 |
| 20140061666 | METHOD AND APPARATUS FOR PRODUCING LARGE, SINGLE-CRYSTALS OF ALUMINUM NITRIDE - Bulk single crystals of AlN having a diameter greater than about 25 mm and dislocation densities of about 10,000 cm | 03-06-2014 |
| 20140061667 | SEMICONDUCTOR CHIP, DISPLAY COMPRISING A PLURALITY OF SEMICONDUCTOR CHIPS AND METHODS FOR THE PRODUCTION THEREOF - An optoelectronic semiconductor chip including a semiconductor body of semiconductor material, an outcoupling face arranged downstream of the semiconductor body in an emission direction and a mirror layer, wherein the semiconductor body includes an active layer that generates radiation, the mirror layer is arranged on the side of the semiconductor body remote from the outcoupling face, and a gap between the active layer and the mirror layer is set such that radiation emitted by the active layer towards the outcoupling face interferes with radiation reflected at the mirror layer such that the semiconductor chip features an emitted radiation pattern with a selected direction in the forward direction. | 03-06-2014 |
| 20140061668 | GaN Single Crystal Substrate and Method of Manufacturing Thereof and GaN-based Semiconductor Device and Method of Manufacturing Thereof - A GaN single crystal substrate has a main surface with an area of not less than 10 cm | 03-06-2014 |
| 20140070226 | BONDABLE TOP METAL CONTACTS FOR GALLIUM NITRIDE POWER DEVICES - An embodiment of a semiconductor device includes a gallium nitride (GaN) substrate having a first surface and a second surface. The second surface is substantially opposite the first surface, at least one device layer is coupled to the first surface, and a backside metal is coupled to the second surface. A top metal stack is coupled to the at least one device layer. The top metal stack includes a contact metal coupled to a surface of the at least one device layer, a protection layer coupled to the contact metal, a diffusion barrier coupled to the protection layer, and a pad metal coupled to the diffusion barrier. The semiconductor device is configured to conduct electricity between the top metal stack and the backside metal. | 03-13-2014 |
| 20140070227 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor light emitting element comprises steps of forming a semiconductor layer composed of a Group III nitride based compound semiconductor on a principal surface of a substrate; forming a transparent conductive metal oxide film on the semiconductor layer; forming an electrode above the transparent conductive metal oxide film; forming a mask layer for covering a part of the transparent conductive metal oxide film; and heat treating the transparent conductive metal oxide film having the mask layer formed thereon in an oxygen-containing atmosphere; wherein, in the heat treatment step, an oxygen concentration of a remaining part of the transparent conductive metal oxide film which is not covered by the mask layer is made higher than an oxygen concentration of a part of the transparent conductive metal oxide film which is covered by the mask layer. | 03-13-2014 |
| 20140070228 | SEMICONDUCTOR DEVICES HAVING A RECESSED ELECTRODE STRUCTURE - An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance. | 03-13-2014 |
| 20140077217 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a substrate, a first semiconductor region, a second semiconductor region, a first electrode, a first electrode and a conducting section. The substrate includes a conductive region and has a first surface. The first semiconductor region is provided on the first surface side of the substrate and includes Al | 03-20-2014 |
| 20140077218 | GROUP 13 NITRIDE CRYSTAL, GROUP 13 NITRIDE CRYSTAL SUBSTRATE, AND METHOD OF MANUFACTURING GROUP 13 NITRIDE CRYSTAL - A group 13 nitride crystal having a hexagonal crystal structure contains at least a nitrogen atom and at least one metal atom selected from a group consisting of B, Al, Ga, In and Tl. Dislocation density of basal plane dislocations in a cross section parallel to a c-axis is 10 | 03-20-2014 |
| 20140077219 | GROUP-III NITRIDE COMPOUND SEMICONDUCTOR LIGHT EMITTING ELEMENT, MANUFACTURING METHOD THEREFOR AND SEMICONDUCTOR LIGHT EMITTING DEVICE - A group-III nitride compound semiconductor light emitting element includes a substrate that has a main face on which an concave and convex portion is formed, a group-III nitride compound semiconductor layer that is formed on the main face of the substrate, and a clearance that is formed between the substrate and the group-III nitride compound semiconductor layer at a first region of the semiconductor light emitting element. In the first region, a portion of the group-III nitride compound semiconductor layer and a portion of the clearance are disposed in a concave of the concave and convex portion on a section through two adjacent top portions of the concave and convex portion and a bottom portion located between the adjacent top portions. | 03-20-2014 |
| 20140077220 | Nanopyramid Sized Opto-Electronic Structure and Method for Manufacturing of Same - Aspects of the invention provide methods and devices. In one embodiment, the invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, LEDs and transistors. According to the method of the invention nitride semiconductor nanopyramids are grown utilizing a CVD based selective area growth technique. The nanopyramids are grown directly or as core-shell structures. | 03-20-2014 |
| 20140077221 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - An embodiment has an emission layer, a first electrode having a reflective metal layer, an insulating layer, first and second conductivity type layers, and a second electrode. The insulating layer is provided on the first electrode and has an opening where a portion of the first electrode is provided. The first conductivity type layer is provided between the insulating layer and the emission layer and has bandgap energy larger than that of the emission layer. The second conductivity type layer is provided on the emission layer and has a current diffusion layer and a second contact layer. The second contact layer is not superimposed on the opening of the insulating layer, and a thickness of the current diffusion layer is larger than that of the first contact layer. The second electrode has a pad portion and a thin portion extends from the pad portion onto the second contact layer. | 03-20-2014 |
| 20140077222 | Gallium Nitride Devices with Aluminum Nitride Alloy Intermediate Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 03-20-2014 |
| 20140077223 | STRUCTURE FOR GROWTH OF NITRIDE SEMICONDUCTOR LAYER, STACKED STRUCTURE, NITRIDE-BASED SEMICONDUCTOR ELEMENT, LIGHT SOURCE, AND MANUFACTURING METHOD FOR SAME - A structure for growth of a nitride semiconductor layer which is disclosed in this application includes: a sapphire substrate of which growing plane is an m-plane; and a plurality of ridge-shaped nitride semiconductor layers provided on the growing plane of the sapphire substrate, wherein a bottom surface of a recessed portion provided between respective ones of the plurality of ridge-shaped nitride semiconductor layers is the m-plane of the sapphire substrate, the growing plane of the plurality of ridge-shaped nitride semiconductor layers is an m-plane, and an absolute value of an angle between an extending direction of the plurality of ridge-shaped nitride semiconductor layers and a c-axis of the sapphire substrate is not less than 0° and not more than 35°. | 03-20-2014 |
| 20140084296 | NITRIDE SEMICONDUCTOR WAFER, NITRIDE SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR WAFER - A nitride semiconductor wafer includes a silicon substrate, a stacked multilayer unit, a silicon-containing unit, and an upper layer unit. The silicon substrate has a major surface. The stacked multilayer unit is provided on the major surface. The stacked multilayer unit includes N number of buffer layers. The buffer layers include an i-th buffer layer, and an (i+1)-th buffer layer provided on the i-th buffer layer. The i-th buffer layer has an i-th lattice length Wi in a first direction parallel to the major surface. The (i+1)-th buffer layer has an (i+1)-th lattice length W(i+1) in the first direction. A relation that (W(i+1)−Wi)/Wi≦0.008 is satisfied for all the buffer layers. The silicon-containing unit is provided on the stacked multilayer unit. The upper layer unit is provided on the silicon-containing unit. | 03-27-2014 |
| 20140084297 | GROUP III NITRIDE WAFERS AND FABRICATION METHOD AND TESTING METHOD - The invention provides, in one instance, a group III nitride wafer sliced from a group III nitride ingot, polished to remove the surface damage layer and tested with x-ray diffraction. The x-ray incident beam is irradiated at an angle less than 15 degree and diffraction peak intensity is evaluated. The group III nitride wafer passing this test has sufficient surface quality for device fabrication. The invention also provides, in one instance, a method of producing group III nitride wafer by slicing a group III nitride ingot, polishing at least one surface of the wafer, and testing the surface quality with x-ray diffraction having an incident beam angle less than 15 degree to the surface. The invention also provides, in an instance, a test method for testing the surface quality of group III nitride wafers using x-ray diffraction having an incident beam angle less than 15 degree to the surface. | 03-27-2014 |
| 20140084298 | NITRIDE COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A nitride compound semiconductor device includes: a substrate; a buffer layer formed on the substrate and including a plurality of composite layers each layered of: a first layer formed of a nitride compound semiconductor; and a second layer formed of a nitride compound semiconductor containing aluminum and having a lattice constant smaller than a lattice constant of the first layer; a semiconductor operating layer formed on the buffer layer; and a plurality of electrodes formed on the semiconductor operating layer. At least one of the second layers has oxygen added therein. | 03-27-2014 |
| 20140084299 | VERTICAL MICROELECTRONIC COMPONENT AND CORRESPONDING PRODUCTION METHOD - A vertical microelectronic component includes a semiconductor substrate having a front side and a back side, and a multiplicity of fins formed on the front side. Each fin has a side wall and an upper side and is separated from other fins by trenches. Each fin includes a GaN/AlGaN heterolayer region formed on the side wall and including a channel region extending essentially parallel to the side wall. Each fin includes a gate terminal region arranged above the GaN/AlGaN heterolayer region and electrically insulated from the channel region in the associated trench on the side wall. A common source terminal region arranged above the fins is connected to a first end of the channel region in a vicinity of the upper sides. A common drain terminal region arranged above the back side is connected to a second end of the channel region in a vicinity of the front side. | 03-27-2014 |
| 20140084300 | SEMICONDUCTOR DEVICE - A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In | 03-27-2014 |
| 20140091308 | SELF-ALIGNED STRUCTURES AND METHODS FOR ASYMMETRIC GAN TRANSISTORS & ENHANCEMENT MODE OPERATION - Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation. | 04-03-2014 |
| 20140091309 | PREDISPOSED HIGH ELECTRON MOBILITY TRANSISTOR - A predisposed high electron mobility transistor (HEMT) is disclosed. The predisposed HEMT includes a buffer layer, a HEMT channel layer on the buffer layer, a first HEMT barrier layer over the HEMT channel layer, and a HEMT cap layer on the first HEMT barrier layer. The HEMT cap layer has a drain region, a source region, and a gate region. Further, the HEMT cap layer has a continuous surface on the drain region, the source region, and the gate region. When no external voltage is applied between the source region and the gate region, the gate region either depletes carriers from the HEMT channel layer or provides carriers to the HEMT channel layer, thereby selecting a predisposed state of the predisposed HEMT. | 04-03-2014 |
| 20140091310 | SEMICONDUCTOR DEVICE USING 2-DIMENSIONAL ELECTRON GAS AND 2-DIMENSIONAL HOLE GAS AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a first compound semiconductor layer on a substrate, first through third electrodes spaced apart from each other on the first compound semiconductor layer, a second compound semiconductor layer on the first compound semiconductor layer between the first through third electrodes, a third compound semiconductor layer on the second compound semiconductor layer between the first and second electrodes, a first gate electrode on the third compound semiconductor layer, a fourth compound semiconductor layer having a smaller thickness than the third compound semiconductor layer on a portion of the second compound semiconductor layer between the second and third electrodes, and a second gate electrode on the fourth compound semiconductor layer. The first compound semiconductor layer between the second and third electrodes includes a 2-dimensional electron gas (2DEG) and the third compound semiconductor layer includes a 2-dimensional hole gas (2DHG). | 04-03-2014 |
| 20140091311 | NITRIDE SEMICONDUCTOR BASED POWER CONVERTING DEVICE - A nitride semiconductor based power converting device includes a nitride semiconductor based power transistor, and at least one nitride semiconductor based passive device. The passive device and the power transistor respectively include a channel layer including a first nitride semiconductor material, and a channel supply layer on the channel layer including a second nitride semiconductor material to induce a 2-dimensional electron gas (2DEG) at the channel layer. The passive device may be a resistor, an inductor, or a capacitor. | 04-03-2014 |
| 20140091312 | POWER SWITCHING DEVICE AND METHOD OF MANUFACTURING THE SAME - A power switching device includes a channel forming layer on a substrate which includes a 2-dimensional electron gas (2DEG), and a channel supply layer which corresponds to the 2DEG at the channel forming layer. A cathode is coupled to a first end of the channel supply layer and an anode is coupled to a second end of the channel supply layer. The channel forming layer further includes a plurality of depletion areas arranged in a pattern, and portions of the channel forming layer between the plurality of depletion areas are non-depletion areas. | 04-03-2014 |
| 20140091313 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a substrate; a buffer layer formed on the substrate; a first semiconductor layer formed on the buffer layer; and a second semiconductor layer formed on the first semiconductor layer. Further, the buffer layer is formed of AlGaN and doped with Fe, the buffer layer includes a plurality of layers having different Al component ratios from each other, and the Al component ratio of a first layer is greater than the Al component ratio of a second layer and a Fe concentration of the first layer is less than the Fe concentration of the second layer, the first and second layers being included in the plurality of layers, and the first layer being formed on a substrate side of the second layer. | 04-03-2014 |
| 20140091314 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a buffer layer formed on a substrate; an SLS (Strained Layer Supperlattice) buffer layer formed on the buffer layer; an electron transit layer formed on the SLS buffer layer and formed of a semiconductor material; and an electron supply layer formed on the electron transit layer and formed of a semiconductor material. Further, the buffer layer is formed of AlGaN and includes two or more layers with different Al composition ratios, the SLS buffer layer is formed by alternately laminating a first lattice layer including AlN and a second lattice layer including GaN, and the Al composition ratio in one of the layers of the buffer layer being in contact with the SLS buffer layer is greater than or equal to an Al effective composition ratio in the SLS buffer layer. | 04-03-2014 |
| 20140091315 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes an electron transit layer formed on a substrate; an electron supply layer formed on the electron transit layer; a doping layer formed on the electron supply layer, the doping layer being formed with a nitride semiconductor in which an impurity element to become p-type and C are doped; a p-type layer formed on the doping layer, the p-type layer being formed with a nitride semiconductor in which the impurity element to become p-type is doped; a gate electrode formed on the p-type layer; and a source electrode and a drain electrode formed on the doping layer or the electron supply layer. The p-type layer is formed in an area immediately below the gate electrode, and a density of the C doped in the doping layer is greater than or equal to 1×10 | 04-03-2014 |
| 20140091316 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer formed on a substrate; a second semiconductor layer and a third semiconductor layer formed on the first semiconductor layer; a fourth semiconductor layer formed on the third semiconductor layer; a gate electrode formed on the fourth semiconductor layer; and a source electrode and a drain electrode formed in contact with the second semiconductor layer. The third semiconductor layer and the fourth semiconductor layer are formed in an area immediately below the gate electrode, the fourth semiconductor layer is formed with a p-type semiconductor material, and the second semiconductor layer and the third semiconductor layer are formed with AlGaN, and the third semiconductor layer has a lower composition ratio of Al than that of the second semiconductor layer. | 04-03-2014 |
| 20140091317 | METHOD OF MANUFACTURING SEMICONDUCTOR CRYSTAL SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, SEMICONDUCTOR CRYSTAL SUBSTRATE, AND SEMICONDUCTOR APPARATUS - A method of manufacturing a semiconductor crystal substrate, includes forming a nitride layer by supplying a gas including a nitrogen component to a substrate formed of a material including silicon and nitriding a surface of the substrate; and forming an AlN layer on the nitride layer by supplying the gas including the nitrogen component and a source gas including Al. | 04-03-2014 |
| 20140091318 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a substrate; a buffer layer formed on the substrate; a strained layer superlattice buffer layer formed on the buffer layer; an electron transit layer formed of a semiconductor material on the strained layer superlattice buffer layer; and an electron supply layer formed of a semiconductor material on the electron transit layer; the strained layer superlattice buffer layer being an alternate stack of first lattice layers including AlN and second lattice layers including GaN; the strained layer superlattice buffer layer being doped with one, or two or more impurities selected from Fe, Mg and C. | 04-03-2014 |
| 20140091319 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes laminating and forming an electron transit layer, an electron supplying layer, an etching stop layer, and a p-type film on a substrate sequentially, the p-type film being formed of a nitride semiconductor material that includes Al doped with an impurity element that attains p-type, the etching stop layer being formed of a material that includes GaN, removing the p-type film in an area except an area where a gate electrode is to be formed, by dry etching to form a p-type layer in the area where the gate electrode is to be formed, the dry etching being conducted while plasma emission in the dry etching is observed, the dry etching being stopped after the dry etching is started and plasma emission originating from Al is not observed, and forming the gate electrode on the p-type layer. | 04-03-2014 |
| 20140091320 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a third semiconductor layer and a fourth semiconductor layer formed on the second semiconductor layer, a gate electrode formed on the third semiconductor layer, and a source electrode and a drain electrode contacting and formed on the fourth semiconductor layer, wherein the third semiconductor layer is formed of a semiconductor material for attaining p-type on an area just under the gate electrode, and a concentration of silicon in the fourth semiconductor layer is higher than that in the second semiconductor layer. | 04-03-2014 |
| 20140091321 | SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a semiconductor device including a semiconductor layer that includes an active region, semiconductor elements that are formed using the active region, connection regions that are obtained by metalizing parts of the semiconductor layer in an island shape isolated from the active region, an insulation film that is formed to cover one main surface side of the semiconductor layer, electrodes that are disposed to face the semiconductor elements and the connection regions via the insulation film, and contacts that penetrate through the insulation film to be selectively formed in portions according to necessity among portions that connect the semiconductor elements or the connection regions to the electrodes. | 04-03-2014 |
| 20140091322 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To enhance the reliability of the semiconductor device using a nitride semiconductor. A channel layer is formed over a substrate, a barrier layer is formed over the channel layer, a cap layer is formed over the barrier layer, and a gate electrode is formed over the cap layer. In addition, a nitride semiconductor layer is formed in a region where the cap layer over the barrier layer is not formed, and a source electrode and a drain electrode are formed over the nitride semiconductor layer. The cap layer is a p-type semiconductor layer, and the nitride semiconductor layer includes the same type of material as the cap layer and is in an intrinsic state or an n-type state. | 04-03-2014 |
| 20140091323 | SEMICONDUCTOR EPITAXIAL STRUCTURE - A semiconductor epitaxial structure is provided. The semiconductor epitaxial structure includes a substrate, a doped semiconductor epitaxial layer, and a carbon nanotube layer. The doped semiconductor epitaxial layer is located on the substrate. The carbon nanotube layer is located between the substrate and the doped semiconductor epitaxial layer. The carbon nanotube layer can be a carbon nanotube film drawn from a carbon nanotube array and including a number of successive and oriented carbon nanotubes joined end-to-end by van der Waals attractive force therebetween. | 04-03-2014 |
| 20140097441 | DEVICES, SYSTEMS, AND METHODS RELATED TO REMOVING PARASITIC CONDUCTION IN SEMICONDUCTOR DEVICES - Semiconductor devices and methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stack of semiconductor materials from an epitaxial substrate, where the stack of semiconductor materials defines a heterojunction, and where the stack of semiconductor materials and the epitaxial substrate further define a bulk region that includes a portion of the semiconductor stack adjacent the epitaxial substrate. The method further includes attaching the stack of semiconductor materials to a carrier, where the carrier is configured to provide a signal path to the heterojunction. The method also includes exposing the bulk region by removing the epitaxial substrate. | 04-10-2014 |
| 20140097442 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a silicon substrate, a nucleation layer, a first buffer layer, a first type nitride semiconductor layer, a light-emitting layer and a second type nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The first buffer layer is disposed on the nucleation layer. The first buffer layer includes a dopant and Gallium, and an atomic radius of the dopant is larger than an atomic radius of Gallium. The first type nitride semiconductor layer is disposed over the first buffer layer. The light-emitting layer is disposed on the first type nitride semiconductor layer. The second type nitride semiconductor layer is disposed on the light-emitting layer. | 04-10-2014 |
| 20140097443 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a silicon substrate, a nucleation layer, a buffer layer, a first type nitride semiconductor stacked layer, a light-emitting layer and a second type nitride semiconductor layer. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer. The first type nitride semiconductor stacked layer is disposed on the buffer layer. The first type nitride semiconductor stacked layer being a plurality of lattice mismatch stacked layers includes a plurality of first nitride semiconductor layers and a plurality of second nitride semiconductor layers. The first nitride semiconductor layers and the second nitride semiconductor layers are stacked alternately, and the first nitride semiconductor layers and the second nitride semiconductor layers are different material. The light-emitting layer is disposed on the first type nitride semiconductor stacked layer. The second type nitride semiconductor layer is disposed on the light-emitting layer. | 04-10-2014 |
| 20140097444 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a silicon substrate, a nucleation layer, a buffer layer, a first type nitride semiconductor layer, a light-emitting layer and a second type nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer. The first type nitride semiconductor layer is disposed on the buffer layer. The first type nitride semiconductor layer is doped with a first type dopant, at least one of the buffer layer and the first type nitride semiconductor layer comprises a codopant distributed therein, and an atomic radius of the codopant is larger than an atomic radius of the first type dopant. The light-emitting layer is disposed on the first type nitride semiconductor layer. The second type nitride semiconductor layer is disposed on the light-emitting layer, the second type nitride semiconductor layer comprising a second type dopant. | 04-10-2014 |
| 20140097445 | SEMICONDUCTOR DEVICE - A transistor SEL is formed by using a compound semiconductor layer (channel layer CNL). The channel layer CNL is formed over a buffer layer BUF. In a first direction where a drain electrode DRE, a gate electrode GE, and a source electrode SOE of the transistor SEL are arranged, at least a portion of the buried electrode BE is situated on the side opposing the source electrode SOE with reference to the gate electrode GE. The buried electrode BE is connected to the source electrode SOE of the transistor SEL. The top end of the buried electrode BE intrudes into the buffer layer BUF. | 04-10-2014 |
| 20140097446 | Gallium Nitride Devices with Gallium Nitride Alloy Intermediate Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 04-10-2014 |
| 20140103352 | NITRIDE SEMICONDUCTOR AND FABRICATING METHOD THEREOF - The present disclosure relates to nitride semiconductor and a fabricating method thereof, and a nitride semiconductor according to an exemplary embodiment of the present disclosure includes a nitride based first and second electrode placed with a distance on a substrate, a nitride based channel layer which connects the first and second electrode, an insulating layer which covers the channel layer, and a third electrode which is formed to cover the insulating layer on the insulating layer. | 04-17-2014 |
| 20140103353 | GROUP III NITRIDE COMPOSITE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, LAMINATED GROUP III NITRIDE COMPOSITE SUBSTRATE, AND GROUP III NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A group III nitride composite substrate includes a support substrate and a group III nitride film. A ratio s | 04-17-2014 |
| 20140103354 | NITRIDE SEMICONDUCTOR STRUCTURE - A nitride semiconductor structure including a silicon substrate, a nucleation layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate includes a cubic silicon carbon nitride (SiCN) layer. The buffer layer is disposed on the nucleation layer. The nitride semiconductor layer is disposed on the buffer layer. | 04-17-2014 |
| 20140103355 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE - A semiconductor light emitting element includes: an n-type cladding layer containing n-type impurities (Si); a light emitting layer laminated on the n-type cladding layer; and a semiconductor layer containing a p-type cladding layer containing p-type impurities (Mg) and laminated on the light emitting layer. The light emitting layer has a multiple quantum well structure including first to fifth barrier layers and first to fourth well layers, and one well layer is sandwiched by two barrier layers. The thickness of the p-type cladding layer | 04-17-2014 |
| 20140103356 | INDIUM GALLIUM NITRIDE LIGHT EMITTING DEVICES - InGaN-based light-emitting devices fabricated on an InGaN template layer are disclosed. | 04-17-2014 |
| 20140103357 | SCHOTTKY DIODE STRUCTURE AND METHOD OF FABRICATION - The disclosed technology relates to a device including a diode. In one aspect, the device includes a lower group III metal nitride layer and an upper group III metal nitride layer and a heterojunction formed therebetween, where the heterojunction extends horizontally and is configured to form a two-dimensional electron gas (2DEG) that is substantially confined in a vertical direction and within the lower group III metal nitride layer. The device additionally includes a cathode forming an ohmic contact with the upper group III metal nitride layer. The device additionally includes an anode, which includes a first portion that forms a Schottky barrier contact with the upper group III metal nitride layer, and a second portion that is separated vertically from the upper group III metal nitride layer by a layer of dielectric material. The anode is configured such that the second portion is horizontally located between the anode and the cathode and the dielectric material is configured to pinch off the 2DEG layer in a reverse biased configuration of the device. The device further includes a passivation area formed between the anode and the cathode to horizontally separate the anode and the cathode from each other. | 04-17-2014 |
| 20140103358 | Composite Substrate - An epitaxial-deposition composite substrate, of more than about 50 mm diameter, in which a nitride-compound semiconductor first substrate is bonded together with a second substrate of either identical or different material. The first substrate is ion-implanted, and on its nitrogen-face side is coated with a special film of thickness within a predetermined range. On a bonding side of the second substrate a special coating of thickness within the predetermined range is formed. The join created by the coated nitrogen-face side of the first substrate being bonded to the coated bonding side of the second substrate occupies at least 90% of the surface area where the two substrates meet. | 04-17-2014 |
| 20140103359 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor light emitting device having enhanced luminous efficiency and a manufacturing method thereof are provided. The semiconductor light emitting device includes: an n-type semiconductor layer having at least one pit formed in an upper surface thereof; an active layer formed on the n-type semiconductor layer, a region of the active layer corresponding to the pit having an upper surface bent along the pit; and a p-type semiconductor layer formed on the active layer, a region of the p-type semiconductor layer corresponding to the pit having an upper surface bent along the bent portion of the active layer. | 04-17-2014 |
| 20140103360 | SEMICONDUCTOR DEVICE - A semiconductor device having: a substrate; a nitride semiconductor layer including a first semiconductor layer made of GaN or In | 04-17-2014 |
| 20140103361 | HIGH BRIGHTNESS LIGHT EMITTING DIODE COVERED BY ZINC OXIDE LAYERS ON MULTIPLE SURFACES GROWN IN LOW TEMPERATURE AQUEOUS SOLUTION - A high brightness III-Nitride based Light Emitting Diode (LED), comprising multiple surfaces covered by Zinc Oxide (ZnO) layers, wherein the ZnO layers are grown in a low temperature aqueous solution and each have a (0001) c-orientation and a top surface that is a (0001) plane. | 04-17-2014 |
| 20140103362 | Composite Substrates, A Method of Producing the Same, A Method of Producing Functional Layers Made of Nitrides of Group 13 Elements, and Functional Devices - A composite substrate | 04-17-2014 |
| 20140110720 | LIGHT EMITTING DEVICE - A light emitting device includes a first semiconductor layer having a first conductive dopant, an active layer on the first semiconductor layer, an electron blocking layer on the active layer, a carrier injection layer between the active layer and the electron blocking layer, and a second semiconductor layer having a second conductive dopant on the electron blocking layer. The carrier injection layer includes the first conductive dopant and the second conductive dopant, and the first conductive dopant of the carrier injection layer has a concentration lower than a concentration of the second conductive dopant. | 04-24-2014 |
| 20140110721 | Second Schottky Contact Metal Layer to Improve GaN Schottky Diode Performance - A Schottky contact is disposed atop the surface of the semiconductor. A first Schottky contact metal layer is disposed atop a first portion of the semiconductor surface. A second Schottky contact metal is disposed atop a second portion of the surface layer and joins the first Schottky contact metal layer. A first. Schottky contact metal layer has a lower work function than the second Schottky contact metal layer. | 04-24-2014 |
| 20140117373 | SEMICONDUCTOR DEVICE - Disclosed herein is a semiconductor device including: a source electrode formed on one side of an N-type AlGaN layer; N-type and P-type AlGaN layers formed on the other side of the P-type AlGaN layer and formed in a direction perpendicular to the source electrode; a gate electrode formed on one side of the N-type and P-type AlGaN layers; and a drain electrode formed on the other side of the N-type and P-type AlGaN layers. | 05-01-2014 |
| 20140117374 | SEMICONDUCTOR DEVICE - Disclosed herein is a semiconductor device including: a base substrate; a first nitride semiconductor layer formed on the base substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer; a cathode electrode formed on one side of the second nitride semiconductor layer; an anode electrode having one end and the other end, one end being recessed at the other side of the second nitride semiconductor layer up to a predetermined depth, and the other end being spaced apart from the cathode electrode and formed to be extended up to an upper portion of the cathode electrode; and an insulating film formed on the second nitride semiconductor layer between the anode electrode and the cathode electrode so as to cover the cathode electrode. | 05-01-2014 |
| 20140117375 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first electrode, a second electrode, a control electrode, and a third electrode. The second semiconductor layer is provided on the first semiconductor layer and has a band gap narrower than that of the first semiconductor layer. The second semiconductor layer includes a first portion and a second portion which is provided together with the first portion and contains an activated acceptor. The third semiconductor layer is provided on the first portion and has a band gap wider than or equal to the band gap of the second semiconductor layer. The first and the second electrodes are provided on the third semiconductor layer. The control electrode is provided between the first electrode and the second electrode. The third electrode is provided on the second portion. | 05-01-2014 |
| 20140117376 | Nitride Semiconductor Element and Method of Manufacturing the Same - A nitride semiconductor element having a high reverse breakdown voltage and a method of manufacturing the same are provided. A diode (a vertical-type SBD) has an n | 05-01-2014 |
| 20140117377 | OXYGEN-DOPED GALLIUM NITRIDE SINGLE CRYSTAL SUBSTRATE - Oxygen can be doped into a gallium nitride crystal by preparing a non-C-plane gallium nitride seed crystal, supplying material gases including gallium, nitrogen and oxygen to the non-C-plane gallium nitride seed crystal, growing a non-C-plane gallium nitride crystal on the non-C-plane gallium nitride seed crystal and allowing oxygen to infiltrating via a non-C-plane surface to the growing gallium nitride crystal. Oxygen-doped {20-21}, {1-101}, {1-100}, {11-20} or {20-22} surface n-type gallium nitride crystals are obtained. | 05-01-2014 |
| 20140117378 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light emitting device and a method of manufacturing the same are disclosed. The light emitting device includes a buffer layer formed on a substrate, a nitride semiconductor layer including a first semiconductor layer, an active layer, and a second semiconductor layer, which are sequentially stacked on the buffer layer, a portion of the first semiconductor layer being exposed to the outside by performing mesa etching from the second semiconductor layer to the portion of the first semiconductor layer, and at least one nanocone formed on the second semiconductor layer. | 05-01-2014 |
| 20140124788 | Chemical Vapor Deposition System - Chemical vapor deposition (CVD) systems for forming layers on a substrate are disclosed. Embodiments of the system comprise at least two processing chambers that may be linked in a cluster tool. A first processing chamber provides a chamber having a controlled environmental temperature and pressure and containing a first environment for performing CVD on a substrate, and a second environment for contacting the substrate with a plasma; a substrate transport system capable of positioning a substrate for sequential processing in each environment, and a gas control system capable of maintaining isolation. A second processing chamber provides a CVD system. Methods of forming layers on a substrate comprise forming one or more layers in each processing chamber. The systems and methods are suitable for preparing Group III-V, Group II-VI or Group IV thin film devices. | 05-08-2014 |
| 20140124789 | GaN High Voltage HFET with Passivation Plus Gate Dielectric Multilayer Structure - A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device. | 05-08-2014 |
| 20140124790 | NITRIDE SEMICONDUCTOR ELEMENT AND NITRIDE SEMICONDUCTOR WAFER - According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of Al | 05-08-2014 |
| 20140124791 | HEMT with Compensation Structure - A high electron mobility transistor includes a source, a gate and a drain, a first III-V semiconductor region, and a second III-V semiconductor region below the first III-V semiconductor region. The high electron mobility transistor further includes a compensation structure interposed between the first and second III-V semiconductor regions so that the first and second III-V semiconductor regions are spaced apart from one another by the compensation structure. The compensation structure has a different band gap than the first and second III-V semiconductor regions. | 05-08-2014 |
| 20140131720 | COMPOSITE LAYER STACKING FOR ENHANCEMENT MODE TRANSISTOR - A transistor includes a first layer of a first type disposed over a buffer layer and having a first concentration of a first material. A first layer of a second type is disposed over the first layer of the first type, and a second layer of the first type is disposed over the first layer of the second type. The second layer of the first type having a second concentration of a first material that is greater than the first concentration of the first material. A source and a drain are spaced laterally from one another and are disposed over the buffer layer. A gate disposed over at least a portion of the second layer of the first type and disposed within a recessed area defined by the first and second layers of the first type and the first layer of the second type. | 05-15-2014 |
| 20140131721 | LATERAL GAN JFET WITH VERTICAL DRIFT REGION - A gallium nitride (GaN)-based junction field-effect transistor (JFET) can include a GaN drain region having a top surface extending in a lateral dimension, a source region, and a GaN channel region of a first conductivity type coupled between the source region and the GaN drain region and operable to conduct electrical current between the source region and the GaN drain region. The JFET can also include a blocking layer disposed between the source region and the GaN drain region such that the GaN channel region is operable to conduct the electrical current substantially along the lateral dimension in a laterally-conductive region of the GaN channel region, and a GaN gate region of a second conductivity type coupled to the GaN channel region such that the laterally-conductive region of the GaN channel region is disposed between at least a portion of the blocking layer and the GaN gate region. | 05-15-2014 |
| 20140131722 | DUAL PHASE GALLIUM NITRIDE MATERIAL FORMATION ON (100) SILICON - A method for selective formation of a dual phase gallium nitride material on a (100) silicon substrate. The method includes forming a blanket layer of dielectric material on a surface of a (100) silicon substrate. The blanket layer of dielectric material is then patterned forming a plurality of patterned dielectric material structures on silicon substrate. An etch is employed that selectively removes exposed portions of the silicon substrate. The etch forms openings within the silicon substrate that expose a surface of the silicon substrate having a (111) crystal plane. A contiguous AlN buffer layer is then formed on exposed surfaces of each patterned dielectric material structure and on exposed surfaces of the silicon substrate. A dual phase gallium nitride material is then formed on a portion of the contiguous AlN buffer layer and surrounding each sidewall of each patterned dielectric material structure. | 05-15-2014 |
| 20140131723 | LASER ANNEALING OF GAN LEDS WITH REDUCED PATTERN EFFECTS - The disclosure is directed to laser annealing of GaN light-emitting diodes (LEDs) with reduced pattern effects. A method includes forming elongate conductive structures atop either an n-GaN layer or a p-GaN layer of a GaN LED structure, the elongate conductive structures having long and short dimensions, and being spaced apart and substantially aligned in the long dimensions. The method also includes generating a P-polarized anneal laser beam that has an anneal wavelength that is greater than the short dimension. The method also includes irradiating either the n-GaN layer or the p-GaN layer of the GaN LED structure through the conductive structures with the P-polarized anneal laser beam, including directing the anneal laser beam relative to the conductive structures so that the polarization direction is perpendicular to the long dimension of the conductive structures. | 05-15-2014 |
| 20140131724 | SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON - A method for selective formation of a gallium nitride material on a (100) silicon substrate. The method includes forming a blanket layer of dielectric material on a surface of a (100) silicon substrate. The blanket layer of dielectric material is then patterned forming a plurality of patterned dielectric material structures on silicon substrate. An etch is employed that selectively removes exposed portions of the silicon substrate. The etch forms openings within the silicon substrate that expose a surface of the silicon substrate having a (111) crystal plane. A contiguous AlN buffer layer is then formed on exposed surfaces of each patterned dielectric material structure and on exposed surfaces of the silicon substrate. A gallium nitride material is then formed on a portion of the contiguous AlN buffer layer and surrounding each sidewall of each patterned dielectric material structure. | 05-15-2014 |
| 20140131725 | LIGHT EMITTING DIODE EPITAXY STRUCTURE - A light emitting diode (LED) epitaxy structure includes an N-type semiconductor layer; an active layer arranged on the N-type semiconductor layer, and a P-type semiconductor layer arranged on the active layer. A horizontal cross-sectional area defined by the active layer is a parallelogram, and none of the internal angles of the parallelogram is a right angle. | 05-15-2014 |
| 20140131726 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - There are provided a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting device includes a base layer configured of a group III nitride semiconductor, a polarity modifying layer formed on a group III element polar surface of the base layer, and a light emitting laminate having a multilayer structure of the group III nitride semiconductor formed on the polarity modifying layer, an upper surface of at least one layer in the multilayer structure being formed of an N polar surface. | 05-15-2014 |
| 20140131727 | LIGHT EMITTING DIODE CHIP AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a light emitting diode chip includes following steps: providing a sapphire substrate, the sapphire substrate having a plurality of protrusions on an upper surface thereof; forming an un-doped GaN layer on the upper surface of the sapphire substrate, the un-doped GaN layer having an upper part covering top ends of the protrusions; forming a distributed bragg reflective layer on the un-doped GaN layer until the distributed bragg reflective layer totally covering the protrusions and the un-doped GaN layer; etching the distributed bragg reflective layer and the upper part of the un-doped GaN layer to expose the top ends of the protrusions; and forming an n-type GaN layer, an active layer, and a p-type GaN layer sequentially on the top ends of the protrusions and the distributed bragg reflective layer. An LED chip formed by the method described above is also provided. | 05-15-2014 |
| 20140131728 | CIGS- OR CZTS-BASED FILM SOLAR CELLS AND METHOD FOR PREPARING THE SAME - Provided is a copper indium gallium selenium (CIGS)- or copper zinc tin sulfur (CZTS)-based solar cell including a back electrode layer and a light-absorbing layer, wherein the light-absorbing layer has a composition of Cu | 05-15-2014 |
| 20140131729 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Exemplary embodiments of the present invention disclose a semiconductor device and a method of fabricating the same. The semiconductor device includes a gallium nitride substrate, a plurality of semiconductor stacks disposed on the gallium nitride substrate, and an insulation pattern disposed between the gallium nitride substrate and the plurality of semiconductor stacks, the insulation pattern insulating the semiconductor stacks from the gallium nitride substrate. | 05-15-2014 |
| 20140131730 | (IN,GA,AL)N OPTOELECTRONIC DEVICES GROWN ON RELAXED (IN,GA,AL)N-ON-GAN BASE LAYERS - A method of fabricating a heterostructure device, including (a) obtaining a first layer or substrate; (b) growing a second layer on the first layer or substrate; and (c) forming the second layer that is at least partially relaxed wherein (1) the first layer and the second layer have the same lattice structure but different lattice constants, (2) the first layer and the second layer form a heterojunction, and (3) the heterojunction forms an active area of a device or serves as a pseudo-substrate for the device. | 05-15-2014 |
| 20140131731 | LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - A light-emitting device according to an exemplary embodiment of the present invention includes a first conductivity-type semiconductor layer disposed on a substrate; an active layer disposed on the first conductivity-type semiconductor layer; a second conductivity-type semiconductor layer disposed on the active layer; and an irregular convex-concave pattern disposed on a surface of the first conductivity-type semiconductor layer. The irregular convex-concave pattern includes convex portions and concave portions, and the convex portions have irregular heights and the concave portions have irregular depths. The first conductivity-type semiconductor layer including the irregular convex-concave pattern is exposed from the active layer and the second conductivity-type semiconductor layer. | 05-15-2014 |
| 20140131732 | LIGHT EMITTING DIODE - A light emitting diode device may include a carrier, a p-type and n-type semiconductor layers, an active layer, a first electrode and a second electrode is provided. The carrier has a growth surface and at least one nano-patterned structure on the growth surface, in which the carrier includes a substrate and a semiconductor capping layer disposed between the substrate and the n-type semiconductor layer. The n-type semiconductor layer and the p-type semiconductor layer are located over the growth surface of the carrier. The active layer is located between the n-type and p-type semiconductor layers, in which a wavelength λ of light emitted by the active layer is 222 nm≦λ≦405 nm, and a defect density of the active layer is less than or equal to 5×10 | 05-15-2014 |
| 20140131733 | Photonic Systems and Methods of Forming Photonic Systems - Some embodiments include photonic systems. The systems may include a silicon-containing waveguide configured to direct light along a path, and a detector proximate the silicon-containing waveguide. The detector may comprise a detector material which has a lower region and an upper region, with the lower region having a higher concentration of defects than the upper region. The detector material may comprise germanium in some embodiments. Some embodiments include methods of forming photonic systems. | 05-15-2014 |
| 20140131734 | P-TYPE DOPING LAYERS FOR USE WITH LIGHT EMITTING DEVICES - A light emitting diode (LED) comprises an n-type Group III-V semiconductor layer, an active layer adjacent to the n-type Group III-V semiconductor layer, and a p-type Group III-V semiconductor layer adjacent to the active layer. The active layer includes one or more V-pits. A portion of the p-type Group III-V semiconductor layer is in the V-pits. A p-type dopant injection layer provided during the formation of the p-type Group III-V layer aids in providing a predetermined concentration, distribution and/or uniformity of the p-type dopant in the V-pits. | 05-15-2014 |
| 20140138697 | GaN-BASED SCHOTTKY DIODE HAVING PARTIALLY RECESSED ANODE - A semiconductor device such as a Schottky diode is provided which includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. A second electrode is in contact with the first active layer. The second electrode establishes an ohmic junction with the first active layer. | 05-22-2014 |
| 20140138698 | GaN-BASED SCHOTTKY DIODE HAVING DUAL METAL, PARTIALLY RECESSED ELECTRODE - A semiconductor device includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. The first portion of the first electrode has a lower Schottky potential barrier than the second portion of the first electrode. A second electrode is in contact with the first active layer. The second electrode establishes an ohmic junction with the first active layer | 05-22-2014 |
| 20140138699 | NITRIDE SEMICONDUCTOR DEVICE, NITRIDE SEMICONDUCTOR WAFER, AND METHOD FOR FORMING NITRIDE SEMICONDUCTOR LAYER - According to one embodiment, a nitride semiconductor device includes a stacked body and a functional layer. The stacked body includes an AlGaN layer of Al | 05-22-2014 |
| 20140138700 | NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a nitride-based semiconductor device includes: preparing a substrate; forming a buffer layer on the substrate, the buffer layer preventing dislocation with the substrate; forming a spacer on the buffer layer; forming a barrier layer on the spacer, the barrier layer forming a hetero-structure with the spacer; forming a protecting layer on the barrier layer; and forming an HfO | 05-22-2014 |
| 20140138701 | SEMICONDUCTOR DEVICE - The semiconductor device includes a substrate, a first GaN field effect transistor, a second GaN field effect transistor, and a GaN diode. The first GaN field effect transistor is disposed on or above the substrate, and the first GaN field effect transistor is a depletion mode field effect transistor. The second GaN field effect transistor is disposed on or above the substrate, and the second GaN field effect transistor is an enhancement mode field effect transistor. The GaN diode is disposed on or above the substrate. The first GaN field effect transistor, the second GaN field effect transistor, and the GaN diode are disposed on or above a same side of the substrate and electrically connected to each other. | 05-22-2014 |
| 20140138702 | SUBSTRATE RECYCLING METHOD AND RECYCLED SUBSTRATE - Exemplary embodiments of the present invention provide a substrate recycling method and a recycled substrate. The method includes separating a substrate having a first surface from an epitaxial layer, performing a first etching of the first surface using electrochemical etching, and performing, after the first etching, a second etching of the first surface using chemical etching, dry etching, or performing, after the first etching, chemical mechanical polishing of the first surface. | 05-22-2014 |
| 20140138703 | Optoelectronic Semiconductor Body and Method for Producing an Optoelectronic Semiconductor Body - An optoelectronic semiconductor body has a substrate that includes a strained layer that is applied to the substrate in a first epitaxy step. The strained layer includes at least one recess formed vertically in the strained layer. In a second epitaxy step, a further layer applied to the strained layer. The further layer fills the at least one recess and covers the strained layer at least in some areas. | 05-22-2014 |
| 20140138704 | SEMICONDUCTOR DEVICE - A semiconductor device includes a field effect transistor that has a first nitride semiconductor layer and a second nitride semiconductor layer larger in bandgap than the first nitride semiconductor layer formed on a substrate in this order and a gate electrode, a source electrode, and a drain electrode, and uses two-dimensional electron gas formed at the interface between the first and second nitride semiconductor layers as the channel. The field effect transistor further has a p-type nitride semiconductor layer formed between the gate electrode and the drain electrode and electrically connected to the drain electrode. | 05-22-2014 |
| 20140145201 | METHOD AND SYSTEM FOR GALLIUM NITRIDE VERTICAL JFET WITH SEPARATED GATE AND SOURCE - A semiconductor structure includes a III-nitride substrate and a first III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The semiconductor structure also includes a first III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial layer and a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure. The semiconductor structure further includes a second III-nitride epitaxial layer coupled to the first III-nitride epitaxial structure. The second III-nitride epitaxial layer is of a second conductivity type and is not electrically connected to the second III-nitride epitaxial structure. | 05-29-2014 |
| 20140145202 | NITRIDE SEMICONDUCTOR CRYSTAL - A method of producing a nitride semiconductor crystal uses a metal organic chemical vapor deposition process and offers good controllability with respect to a p-type nitride semiconductor crystal. To that end, an organic metal compound of a group III element, a hydride of nitrogen, and an organic compound having any of the partial structures C—C—O, C—C═O, C═C—O, C═C═O, C≡C—O, and C—O—C are used as source materials, and by a metal organic chemical vapor deposition process, C and O atoms are simultaneously introduced into the crystal to obtain p-type conductivity. | 05-29-2014 |
| 20140145203 | BIDIRECTIONAL TRANSISTOR WITH OPTIMIZED HIGH ELECTRON MOBILITY CURRENT - An apparatus includes a bidirectional hetero junction field-effect power transistor having a gate between conduction electrodes, semiconductor layers, one formed on the other, and the two meeting at an electron gas layer interface, and a reference electrode embedded in one layer. The reference electrode connects to a potential of a zone of the gas layer that is plumb with the reference electrode, A distance between the reference electrode and one conduction electrode and between the gate and that conduction electrode is between 45 and 55% of a distance between the conduction electrodes. A control circuit connected to the reference electrode generates a switching voltage for switching the transistor from a reference electrode voltage, and to apply a control voltage to the gate. | 05-29-2014 |
| 20140145204 | LIGHT-EMITTING DIODE AND METHOD FOR PREPARING THE SAME - A method for preparing a light-emitting diode having a vertical structure by stripping a GaN base epitaxial layer and a sapphire substrate by a wet process, the method including: a) preparing a graphical growth substrate; b) growing a GaN base light-emitting diode epitaxial layer on the graphical growth substrate, the GaN base light-emitting diode epitaxial layer from the bottom to the top successively including a N-type GaN layer and a P-type GaN layer; c) successively forming a transparent and electrically conductive film, an omni-directional reflection layer, an electrically conductive reflection layer, and a passive metal protection layer from the bottom to the top on the GaN base light-emitting diode epitaxial layer; and d) removing the first layer of stable material with a high melting point of the growth substrate by dry etching, exposing the N-type GaN layer, and preparing an N electrode on the N-type GaN layer. | 05-29-2014 |
| 20140145205 | LIGHT EMITTING DEVICE PACKAGE AND LIGHT UNIT HAVING THE SAME - Disclosed is an LED package. The LED package includes a package body, a first frame and a second frame on the package body and a light emitting device chip on the first frame. The first frame is separated from the second frame, and the first frame includes a bottom frame on the package body and at least two sidewall frames extending from the bottom frame and inclined with respect to the bottom frame. | 05-29-2014 |
| 20140151710 | Stacked Gate Structure, Metal-Oxide-Semiconductor Including the Same, and Method for Manufacturing the Stacked Gate Structure - The invention provides a stacked gate structure and metal-oxide-semiconductor including the same, and method for manufacturing the stacked gate structure. The stacked gate structure comprises a substrate, a semiconductor layer positioned on the substrate, a gate dielectric positioned on the semiconductor layer, and a gate electrode layer positioned on the gate dielectric, which the gate dielectric comprises a composite oxide layer composed of lanthanum oxide (La | 06-05-2014 |
| 20140151711 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device is provided. The semiconductor light-emitting device includes a buffer layer, a light-emitting layer, a first-conductivity semiconductor layer, a first light reflecting layer, a protective structure, and an adhesive layer. The first-conductivity semiconductor layer is disposed between the buffer layer and a first side of the light-emitting layer. The first light reflecting layer is disposed between the first-conductivity semiconductor layer and the buffer layer. The protective structure is disposed between the first reflecting layer and the buffer layer. The adhesive layer is disposed between the first-conductivity semiconductor layer and the protective structure. | 06-05-2014 |
| 20140151712 | ENHANCEMENT-MODE HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE AND METHOD OF MAKING SAME - An epitaxial structure, such as an enhancement-mode high electron mobility transistor (HEMT) includes a first barrier layer over an aluminum gallium nitride channel layer. The first barrier layer is formed at a first temperature and is overlaid by a second barrier layer formed at a second temperature that is lower than that of the first temperature. The first barrier layer acts as an etch stop when forming a gate recess in the second barrier layer by a wet or dry etching. | 06-05-2014 |
| 20140151713 | METHOD OF GROWING NITRIDE SEMICONDUCTOR LAYER, NITRIDE SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING THE SAME - Exemplary embodiments of the present invention provide a method of growing a nitride semiconductor layer including growing a gallium nitride-based defect dispersion suppressing layer on a gallium nitride substrate including non-defect regions and a defect region disposed between the non-defect regions, and growing a gallium nitride semiconductor layer on the defect dispersion suppressing layer. | 06-05-2014 |
| 20140151714 | GALLIUM NITRIDE SUBSTRATE AND METHOD FOR FABRICATING THE SAME - Exemplary embodiments of the present invention relate to a single-crystal substrate including a buffer layer including a nitride semiconductor, holes penetrating the buffer layer, and a single-crystal nitride semiconductor disposed on the buffer layer. | 06-05-2014 |
| 20140151715 | LIGHT EMITTING DIODE WITH NANOSTRUCTURED LAYER AND METHODS OF MAKING AND USING - A light emitting diode has a plurality of layers including at least two semiconductor layers. A first layer of the plurality of layers has a nanostructured surface which includes a quasi-periodic, anisotropic array of elongated ridge elements having a wave-ordered structure pattern, each ridge element having a wavelike cross-section and oriented substantially in a first direction. | 06-05-2014 |
| 20140151716 | PROCESS FOR THE MANUFACTURE OF A DOPED III-N BULK CRYSTAL AND A FREE-STANDING III-N SUBSTRATE, AND DOPED III-N BULK CRYSTAL AND FREE-STANDING III-N SUBSTRATE AS SUCH - A process for producing a doped III-N bulk crystal, wherein III denotes at least one element of the main group III of the periodic system, selected from Al, Ga and In, wherein the doped crystalline III-N layer or the doped III-N bulk crystal is deposited on a substrate or template in a reactor, and wherein the feeding of at least one dopant into the reactor is carried out in admixture with at least one group III material. In this manner, III-N bulk crystals and III-N single crystal substrates separated therefrom can be obtained with a very homogeneous distribution of dopants in the growth direction as well as in the growth plane perpendicular thereto, a very homogeneous distribution of charge carriers and/or of the specific electric resistivity in the growth direction as well as in the growth plane perpendicular thereto, and a very good crystal quality. | 06-05-2014 |
| 20140159048 | High Electron Mobility Transistor and Manufacturing Method Thereof - The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall. | 06-12-2014 |
| 20140159049 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other. | 06-12-2014 |
| 20140159050 | FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME - A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode. | 06-12-2014 |
| 20140159051 | MONOLITHICALLY INTEGRATED VERTICAL JFET AND SCHOTTKY DIODE - An integrated device including a vertical III-nitride FET and a Schottky diode includes a drain comprising a first III-nitride material, a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, and a channel region comprising a third III-nitride material coupled to the drift region. The integrated device also includes a gate region at least partially surrounding the channel region, a source coupled to the channel region, and a Schottky contact coupled to the drift region. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride FET and the Schottky diode is along the vertical direction. | 06-12-2014 |
| 20140167057 | REO/ALO/AlN TEMPLATE FOR III-N MATERIAL GROWTH ON SILICON - A method of forming a template on a silicon substrate includes providing a single crystal silicon substrate. The method further includes epitaxially depositing a layer of rare earth oxide on the surface of the silicon substrate. The rare earth oxide being substantially crystal lattice matched to the surface of the silicon substrate. The method further includes forming an aluminum oxide layer on the rare earth oxide, the aluminum oxide being substantially crystal lattice matched to the surface of the rare earth oxide and epitaxially depositing a layer of aluminum nitride (AlN) on the aluminum oxide layer substantially crystal lattice matched to the surface of the aluminum oxide. | 06-19-2014 |
| 20140167058 | COMPOSITIONALLY GRADED NITRIDE-BASED HIGH ELECTRON MOBILITY TRANSISTOR - An epitaxial structure on a substrate includes a gallium nitride buffer layer over the substrate and a graded channel layer over the gallium nitride layer. The graded channel layer consists essentially of In | 06-19-2014 |
| 20140167059 | PEC ETCHING OF (20-2-1) SEMIPOLAR GALLIUM NITRIDE FOR EXTERNAL EFFICIENCY ENHANCEMENT IN LIGHT EMITTING DIODE APPLICATIONS - A method of performing a photoelectrochemical (PEC) etch on an exposed surface of a semipolar {20-2-1} III-nitride semiconductor, for improving light extraction from and for enhancing external efficiency of one or more active layers formed on or above the semipolar {20-2-1} III-nitride semiconductor. | 06-19-2014 |
| 20140167060 | NORMALLY OFF POWER ELECTRONIC COMPONENT - An electronic power component including a normally on high-voltage transistor and a normally off low-voltage transistor. The normally on transistor and the normally off transistor are coupled in cascode configuration and are housed in a single package. The normally off transistor is of the bottom-source type. | 06-19-2014 |
| 20140167061 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer connected with the p-type semiconductor layer; a first electrode layer formed on the n-type semiconductor layer; and a second electrode layer formed on the p-type semiconductor layer. The first electrode layer and the second electrode layer are electrically connected such as to each operate at an identical potential. The second electrode layer is connected with at least a part of a surface of the first electrode layer which is opposite to a surface of the first electrode layer that is in contact with the n-type semiconductor layer. | 06-19-2014 |
| 20140167062 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes the steps of: forming a first electrode layer on a n-type semiconductor layer; forming a second electrode layer on a p-type semiconductor layer; and performing heat treatment for the first electrode layer and the second electrode layer formed on the semiconductor layers. Temperature of the heat treatment is not lower than 400 degrees centigrade and not higher than 650 degrees centigrade. | 06-19-2014 |
| 20140167063 | LED CHIP PACKAGING STRUCTURE, ITS MANUFACTURING METHOD, AND DISPLAY DEVICE - A LED chip packaging structure, its manufacturing method, and a display device are disclosed. A conductive unit is formed at two opposite sides of a LED chip unit, and comprises a first conductive layer formed at a side of, and electrically connected to, a first electrode, a second conductive layer formed at a side of, and electrically connected to, a second electrode, and an intermediate isolation layer formed at a side of a GaN layer. The LED chip unit and the conductive unit are connected laterally to form an electrical-connection channel as a whole, without welding a gold wire for the conductive channel as in a traditional LED. Thus, the method is able to reduce the total thickness of the LED chip device, increase the thermal conductivity effect of the LED chip and the overall stability, and improve the light-extraction effect of the surface of the LED chip. | 06-19-2014 |
| 20140167064 | GaN HEMTs AND GaN DIODES - A GaN hetereojunction structure has a three-layer dielectric structure. The lowermost and middle portions of the gate electrode together define the gate foot, and this is associated with two dielectric layers. A thinner first dielectric layer is adjacent the gate edge at the bottom of the gate electrode. The second dielectric layer corresponds to the layer in the conventional structure, and it is level with the main portion of the gate foot. | 06-19-2014 |
| 20140167065 | LED STRUCTURE WITH ENHANCED MIRROR REFLECTIVITY - Embodiments of the present invention are generally related to LED chips having improved overall emission by reducing the light-absorbing effects of barrier layers adjacent mirror contacts. In one embodiment, a LED chip comprises one or more LEDs, with each LED having an active region, a first contact under the active region having a highly reflective mirror, and a barrier layer adjacent the mirror. The barrier layer is smaller than the mirror, such that it does not extend beyond the periphery of the mirror. In another possible embodiment, an insulator is further provided, with the insulator adjacent the barrier layer and adjacent portions of the mirror not contacted by the active region or by the barrier layer. In yet another embodiment, a second contact is provided on the active region. In a further embodiment, the barrier layer is smaller than the mirror such that the periphery of the mirror is at least 40% free of the barrier layer, and the second contact is below the first contact and accessible from the bottom of the chip. | 06-19-2014 |
| 20140167066 | LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING SAME - A semiconductor light emitting element including, in a light extraction layer thereof, a photonic crystal periodic structure including two systems (structures) with different refractive indices. An interface between the two systems (structures) satisfies Bragg scattering conditions, and the photonic crystal periodic structure has a photonic band gap. | 06-19-2014 |
| 20140167067 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT HAVING SUPERIOR LEAKAGE CURRENT BLOCKING EFFECT AND METHOD FOR MANUFACTURING SAME - Disclosed are a nitride semiconductor light-emitting element and a method for manufacturing the same. The nitride semiconductor light-emitting element according to the present invention comprises: a current blocking part disposed between a substrate and an n-type nitride layer; an activation layer disposed on the top surface of the n-type nitride layer; and a p-type nitride layer disposed on the top surface of the activation layer, wherein the current blocking part is an Al | 06-19-2014 |
| 20140175450 | VERTICAL GAN POWER DEVICE WITH BREAKDOWN VOLTAGE CONTROL - A method for fabricating a vertical GaN power device includes providing a first GaN material having a first conductivity type and forming a second GaN material having a second conductivity type and coupled to the first GaN material to create a junction. The method further includes implanting ions through the second GaN material and into a first portion of the first GaN material to increase a doping concentration of the first conductivity type. The first portion of the junction is characterized by a reduced breakdown voltage relative to a breakdown voltage of a second portion of the junction. | 06-26-2014 |
| 20140175451 | NORMALLY OFF GALLIUM NITRIDE FIELD EFFECT TRANSISTORS (FET) - A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing it second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero-junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer. The power device further includes a floating gate located between the gate electrode an hetero-junction structure, wherein the gate electrode is insulated from the floating gate with an insulation layer and wherein the floating gate is disposed above and padded with a thin insulation layer from the hetero-junction structure and wherein the floating gate is charged for continuously applying a voltage to the 2DEG layer to pinch off the current flowing in the 2DEG layer between the source and drain electrodes whereby the HFET semiconductor power device is a normally off device. | 06-26-2014 |
| 20140175452 | SUCCESSIVE IONIC LAYER ADSORPTION AND REACTION PROCESS FOR DEPOSITING EPITAXIAL ZNO ON III-NITRIDE-BASED LIGHT EMITTING DIODE AND LIGHT EMITTING DIODE INCLUDING EPITAXIAL ZNO - A method of forming a ZnO layer on a substrate and an LED including a ZnO layer formed by the method are provided. The ZnO layer is formed by using a Successive Ionic Layer Adsorption and Reaction (SILAR) process. The SILAR process includes: applying a first solution to a substrate comprising GaN, to form an inner ionic layer on the substrate and an outer ionic layer on the inner ionic layer; performing a first washing operation on the substrate to remove the outer ionic layer; and applying a second solution to the washed substrate to convert the inner ionic layer into a ZnO oxide layer. | 06-26-2014 |
| 20140175453 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, POWER SUPPLY, AND HIGH-FREQUENCY AMPLIFIER - A semiconductor device includes: a first transistor that includes a first gate electrode, a first source electrode, a first drain electrode, and a first nitride semiconductor laminate that includes a first electron transit layer and a first electron supply layer; a second transistor that includes a second gate electrode, a second source electrode, a second drain electrode, and a second nitride semiconductor laminate that includes a second electrode transit layer and a second electron supply layer, the second drain electrode being a common electrode that also serves as the first source electrode, the second electron transit layer having part that underlies the second gate electrode and that contains a p-type dopant; and a p-type-dopant-diffusion-blocking layer. | 06-26-2014 |
| 20140175454 | DEVICES AND SYSTEMS FOR POWER CONVERSION CIRCUITS - Devices and systems comprising driver circuits are disclosed for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement to a high voltage GaN HEMT, for improved control of noise and voltage transients. Co-packaging of a GaN transistor die and a CMOS driver die using island topology contacts, through substrate vias, and a flip-chip, stacked configuration provides interconnections with low inductance and resistance, and provides effective thermal management. Co-packaging of a CMOS input interface circuit with the CMOS driver and GaN transistor allows for a compact, integrated CMOS driver with enhanced functionality including shut-down and start-up conditioning for safer operation, particularly for high voltage and high current switching. Preferred embodiments also provide isolated, self-powered, high speed driver devices, with reduced input losses. | 06-26-2014 |
| 20140175455 | FIELD-EFFECT TRANSISTOR - The field-effect transistor comprising: a semiconductor laminated structure comprising a first layer of a first nitride semiconductor, a second layer of a second nitride semiconductor having a bandgap larger than that of the first nitride semiconductor, and a two-dimensional electron gas layer; a source electrode; a drain electrode; and a gate electrode disposed over the second layer, the gate electrode being adapted to control the flow of electrons passing through the two-dimensional electron gas layer; a third layer of a p-type nitride semiconductor containing p-type dopant between the gate electrode and the second layer; and a fourth layer of a nitride semiconductor between the third layer and the gate electrode, wherein the fourth layer is in contact with the gate electrode, and wherein the fourth layer is an undoped layer which has a larger bandgap than that of the third layer. | 06-26-2014 |
| 20140175456 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a first nitride semiconductor layer formed of non-doped Al | 06-26-2014 |
| 20140183543 | METHOD AND SYSTEM FOR CO-PACKAGING GALLIUM NITRIDE ELECTRONICS - An electronic package includes a leadframe, a plurality of pins, a gallium-nitride (GaN) transistor, and a GaN diode. The GaN transistor includes a drain region, a drift region, a source region, and a gate region; the drain region includes a GaN substrate and a drain contact, the drift region includes a first GaN epitaxial layer coupled to the GaN substrate, the source region includes a source contact and is separated from the GaN substrate by the drift region, and the gate region includes a second GaN epitaxial layer and a gate contact. The GaN diode includes an anode region and a cathode region, the cathode region including the GaN substrate and a cathode contact, and the anode region including a third GaN epitaxial layer coupled to the GaN substrate and an anode contact. The drain contact and the anode contact are electrically connected to the leadframe. | 07-03-2014 |
| 20140183544 | COMPOUND SEMICONDUCTOR ESD PROTECTION DEVICES - The present invention relates to compound semiconductor ESD protection devices of three types. The device comprises a multi-gate enhancement mode FET (E-FET). For the type I compound semiconductor ESD protection device, the source electrode is connected to the plural gate electrodes through at least one first resistor, and the drain electrode is connected to the plural gate electrodes through at least one second resistor. For the type II compound semiconductor ESD protection device, the plural gate electrodes are connected to at least one of the inter-gate regions between two adjacent gate electrodes through at least one fourth resistor. For the type III compound semiconductor ESD protection device, the plural gate electrodes are connected to the source or drain electrodes through at least one seventh resistor. Any two gate electrodes in the three types of compound semiconductor ESD protection devices can be connected by a resistor. | 07-03-2014 |
| 20140183545 | POLARIZATION EFFECT CARRIER GENERATING DEVICE STRUCTURES HAVING COMPENSATION DOPING TO REDUCE LEAKAGE CURRENT - A semiconductor structure having: a first semiconductor layer; and an electric carrier generating layer disposed on the first semiconductor layer to generate electric carriers within the first semiconductor layer by polarization effects, the electric carrier generating layer having a predetermined conduction band and a predetermined valance band, the electric carrier generating layer having a concentration of non-carrier generating contaminants having an energy level, the difference in the energy level of the non-carrier type contaminants and the energy level of either the conduction band or the valence band being greater than 10 kT, where k is Boltzmann's constant and T is the temperature of the electric carrier generating semiconductor layer, the electric carrier generating semiconductor layer being doped with a dopant having an energy level, the difference in the energy level of the dopant and the energy level of either the conduction band or the valence band being greater than 10 kT, the dopant having a concentration equal to or greater than the concentration of the non-carrier generating contaminants. | 07-03-2014 |
| 20140183546 | NITRIDE-BASED SEMICONDUCTOR LIGHT-EMITTING DEVICE - A nitride-based semiconductor light-emitting device includes an n-type nitride-based semiconductor layer, an active layer, a p-type nitride-based semiconductor layer, an ohmic contact layer covering a portion of the p-type nitride-based semiconductor layer upper surface, and a p electrode including a first portion contacting the p-type nitride-based semiconductor layer and a second portion contacting the ohmic contact layer. | 07-03-2014 |
| 20140183547 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a base including a mounting portion having conductivity, and a terminal insulated from the mounting portion. The device also includes a semiconductor element provided on the mounting portion and having a first face and a second face opposite to the first face, the semiconductor element having an electrode electrically connected to the terminal on the first face, and contacting the mounting portion via the second face, and a resistance element electrically connecting the mounting portion to the terminal. A resistance value of the resistance element is greater than a reciprocal of the product ωC, wherein C is a capacitance value between the mounting portion and the terminal, and ω is an angular frequency of an electrical signal output from the semiconductor element. | 07-03-2014 |
| 20140183548 | LIGHT DETECTION DEVICE - A light detection device includes a substrate, a buffer layer disposed on the substrate, a first band gap change layer disposed on a portion of the buffer layer, a light absorption layer disposed on the first band gap change layer, a Schottky layer disposed on a portion of the light absorption layer, and a first electrode layer disposed on a portion of the Schottky layer. | 07-03-2014 |
| 20140183549 | PHOTO DETECTION DEVICE, PHOTO DETECTION PACKAGE INCLUDING THE PHOTO DETECTION DEVICE, AND PORTABLE DEVICE INCLUDING THE PHOTO DETECTION PACKAGE - Exemplary embodiments of the present invention relate to a photo detection device including a substrate, a first light absorption layer disposed on the substrate, a second light absorption layer disposed in a first region on the first light absorption layer, a third light absorption layer disposed in a second region on the second light absorption layer, and a first electrode layer disposed on each of the first, the second, and the third light absorption layers. | 07-03-2014 |
| 20140183550 | PARASITIC INDUCTANCE REDUCTION FOR MULTILAYERED BOARD LAYOUT DESIGNS WITH SEMICONDUCTOR DEVICES - A highly efficient, single sided circuit board layout design providing magnetic field self-cancellation and reduced parasitic inductance independent of board thickness. The low profile power loop extends through active and passive devices on the top layer of the circuit board, with vias connecting the power loop to a return path in an inner layer of the board. The magnetic effect of the portion of the power loop on the top layer is reduced by locating the inner layer return path directly underneath the power loop path on the top layer. | 07-03-2014 |
| 20140191240 | High Electron Mobility Transistor and Method of Forming the Same - A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode. | 07-10-2014 |
| 20140191241 | GALLIUM NITRIDE VERTICAL JFET WITH HEXAGONAL CELL STRUCTURE - An array of GaN-based vertical JFETs includes a GaN substrate comprising a drain of one or more of the JFETs and one or more epitaxial layers coupled to the GaN substrate. The array also includes a plurality of hexagonal cells coupled to the one or more epitaxial layers and extending in a direction normal to the GaN substrate. Sidewalls of the plurality of hexagonal cells are substantially aligned with respect to crystal planes of the GaN substrate. The array further includes a plurality of channel regions, each having a portion adjacent a sidewall of the plurality of hexagonal cells, a plurality of gate regions of one or more of the JFETs, each electrically coupled to one or more of the plurality of channel regions, and a plurality of source regions of one or more of the JFETs electrically coupled to one or more of the plurality of channel regions. | 07-10-2014 |
| 20140191242 | METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL TRANSISTOR - A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate. | 07-10-2014 |
| 20140191243 | PATTERNED ARTICLES AND LIGHT EMITTING DEVICES THEREFROM - A patterned article includes a substrate support having planar substrate surface portions including a substrate material having a substrate refractive index. A patterned surface is on the substrate support including a plurality of features lateral to the planar substrate surface portions protruding above a height of the planar substrate surface portions. At least a top surface of the plurality of features include an epi-blocking layer including at least one of (i) a non-single crystal material having a refractive index lower as compared to the substrate refractive index and (ii) a reflecting metal or a metal alloy (reflecting material). The epi-blocking layer is not on the planar substrate surface portions. | 07-10-2014 |
| 20140191244 | METHOD FOR CONDUCTIVITY CONTROL OF (Al,In,Ga,B)N - A method of controlled p-type conductivity in (Al,In,Ga,B)N semiconductor crystals. Examples include {10 | 07-10-2014 |
| 20140191245 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device. A light emitting device comprises a plurality of N-type semiconductor layers including a first N-type semiconductor layer and a second N-type semiconductor layer on the first N-type semiconductor layer, an active layer on the second N-type semiconductor layer, and a P-type semiconductor layer on the active layer, wherein the first N-type semiconductor layer comprises a Si doped Nitride layer and the second N-type semiconductor layer comprises a Si doped Nitride layer, and wherein the first and second N-type semiconductor layers have a Si impurity concentration different from each other. | 07-10-2014 |
| 20140191246 | BONDING TRANSISTOR WAFER TO LED WAFER TO FORM ACTIVE LED MODULES - LED modules are disclosed having a control MOSFET, or other transistor, in series with an LED. In one embodiment, a MOSFET wafer, containing an array of vertical MOSFETS, is aligned and bonded to an LED wafer, containing a corresponding array of vertical LEDs, and singulated to form thousands of active 3-terminal LED modules with the same footprint as a single LED. Despite the different forward voltages of red, green, and blue LEDs, RGB modules may be connected in parallel and their control voltages staggered at 60 Hz or greater to generate a single perceived color, such as white. The RGB modules may be connected in a panel for general illumination or for a color display. | 07-10-2014 |
| 20140197418 | SEMICONDUCTOR STRUCTURE HAVING SETS OF III-V COMPOUND LAYERS AND METHOD OF FORMING THE SAME - A semiconductor structure includes a substrate, a first III-V compound layer over the substrate, one or more sets of III-V compound layers over the first III-V compound layer, a second III-V compound layer over the one or more sets of III-V compound layers, and an active layer over the second III-V compound layer. The first III-V compound layer has a first type doping. Each of the one or more sets of III-V compound layers includes a lower III-V compound layer and an upper III-V compound layer over the lower III-V compound layer. The upper III-V compound layer having the first type doping, and the lower III-V compound layer is at least one of undoped, unintentionally doped having a second type doping, or doped having the second type doping. The second III-V compound layer is either undoped or unintentionally doped having the second type doping. | 07-17-2014 |
| 20140197419 | TECHNIQUES FOR FORMING OPTOELECTRONIC DEVICES - Embodiments relate to use of a particle accelerator beam to form thin films of material from a bulk substrate. In particular embodiments, a bulk substrate (e.g. donor substrate) having a top surface is exposed to a beam of accelerated particles. In certain embodiments, this bulk substrate may comprise GaN; in other embodiments this bulk substrate may comprise Si, SiC, or other materials. Then, a thin film or wafer of material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. In certain embodiments this separated material is incorporated directly into an optoelectronic device, for example a GaN film cleaved from GaN bulk material. In some embodiments, this separated material may be employed as a template for further growth of semiconductor materials (e.g. GaN) that are useful for optoelectronic devices. | 07-17-2014 |
| 20140197420 | Films of Nitrides of Group 13 Elements and Layered Body Including the Same | 07-17-2014 |
| 20140197421 | ELECTRODE CONFIGURATIONS FOR SEMICONDUCTOR DEVICES - A III-N semiconductor device can include an electrode-defining layer having a thickness on a surface of a III-N material structure. The electrode-defining layer has a recess with a sidewall, the sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a first width, and a portion of the recess proximal to the III-N material structure has a second width, the first width being larger than the second width. An electrode is in the recess, the electrode including an extending portion over the sidewall of the recess. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The sidewall forms an effective angle of about 40 degrees or less relative to the surface of the III-N material structure. | 07-17-2014 |
| 20140203287 | NITRIDE LIGHT-EMITTING DEVICE WITH CURRENT-BLOCKING MECHANISM AND METHOD FOR FABRICATING THE SAME - A nitride light emitting device comprises a current blocking Schottky junction zone formed below the p-electrode and above the active region so that current injection from the p-electrode to the area of the active region that is vertically shaded by the p-electrode is blocked by the Schottky junction zone. A method for fabricating the same is also provided. | 07-24-2014 |
| 20140203288 | COMPOUND SEMICONDUCTOR DEVICE HAVING GALLIUM NITRIDE GATE STRUCTURES - The present disclosure provides a semiconductor structure. The semiconductor structure includes a buffer layer on a substrate, an graded aluminum gallium nitride (AlGaN) layer disposed on the buffer layer, a gallium nitride (GaN) layer disposed on the graded AlGaN layer, a second AlGaN layer disposed on the GaN layer and a gate stack disposed on the second AlGaN layer. The gate stack includes one or more of a III-V compound p-doped layer, a III-V compound n-doped layer, an aluminum nitride (AlN) layer between the III-V compound p-doped and n-doped layers, and a metal layer formed over the p-doped, AlN, and n-doped layers. A dielectric layer can also underlie the metal layer. | 07-24-2014 |
| 20140203289 | High Electron Mobility Transistors - The present disclosure relates to a donor layer of bi-layer AlGaN and associated method of fabrication within a high electron mobility transistor (HEMT) configured to provide low-resistance ohmic source and drain contacts to reduce power consumption, while maintaining a high-mobility of a two-dimensional electron gas (2DEG) within a channel of the HEMT. The donor layer of bi-layer AlGaN comprises a mobility-enhancing layer of Al | 07-24-2014 |
| 20140203290 | Wire-Last Integration Method and Structure for III-V Nanowire Devices - In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches in the gap filler material. The SOI layer is removed from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device. The trenches are filled with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration. | 07-24-2014 |
| 20140203291 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: an FET chip; pads provided on an upper surface of the FET chip; bumps provided on at least one of the pads; leads having first portions that are connected to the FET chip by the bumps and extend along the upper surface of the FET chip, and second portions that contact surfaces of the first portions along the upper surface of the FET chip and extend along a side surface of the FET chip, the first and second portions being formed by press or cutting; and a seal layer that seals the FET chip and the leads and a surface from which the second portions of the leads are exposed, the surface of the seal layer being on a lower surface side of the FET chip. | 07-24-2014 |
| 20140203292 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a light-transmissive substrate, a light-transmissive buffer layer disposed on the light-transmissive substrate, and a light emitting structure. The light-transmissive buffer layer includes a first layer and a second layer having different refractive indices and disposed alternately at least once. The light emitting structure includes a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer sequentially disposed on the buffer layer. | 07-24-2014 |
| 20140203293 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - A nitride semiconductor light emitting device includes a substrate, a multi-layer structure, a light-transmitting concave-convex structure and a light emitting structure. The multi-layer structure has layers of a first layer and a second layer such that the first and second layers have different refractive indexes and are alternately stacked. The concave-convex structure is disposed in an upper surface of the multi-layer structure and includes a light-transmitting material. The light emitting structure is disposed on the multi-layer structure and includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. | 07-24-2014 |
| 20140203294 | Gallium Nitride Devices - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. | 07-24-2014 |
| 20140203295 | INTEGRATED POWER DEVICE WITH III-NITRIDE HALF BRIDGES - A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die. | 07-24-2014 |
| 20140203296 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor light emitting device includes a light emitting body including a semiconductor light emitting layer, a support substrate supporting the light emitting body, and a bonding layer provided between the light emitting body and the support substrate, the bonding layer bonding the light emitting body and the support substrate together. The device also includes a first barrier metal layer provided between the light emitting body and the bonding layer, and an electrode provided between the light emitting body and the first barrier metal layer. The first barrier layer includes a first layer made of nickel and a second layer made of a metal having a smaller linear expansion coefficient than nickel, and the first layer and the second layer are alternately disposed in a multiple-layer structure. The electrode is electrically connected to the light emitting body. | 07-24-2014 |
| 20140209918 | Thick ALN Inter-Layer for III-Nitride Layer on Silicon Substrate - The present disclosure relates to a gallium-nitride (GaN) transistor device having a composite gallium nitride layer with alternating layers of GaN and aluminum nitride (AlN). In some embodiments, the GaN transistor device has a first GaN layer disposed above a semiconductor substrate. An AlN inter-layer is disposed on the first GaN layer. A second GaN layer is disposed on the AlN inter-layer. The AlN inter-layer allows for the thickness of the GaN layer to be increased over continuous GaN layers, mitigating bowing and cracking of the GaN substrate, while improving the breakdown voltage of the disclosed GaN device. | 07-31-2014 |
| 20140209919 | METHOD OF IMPLANTING DOPANTS INTO A GROUP III-NITRIDE STRUCTURE AND DEVICE FORMED - A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopant and a second dopant, and the second dopant comprises a group V material. | 07-31-2014 |
| 20140209920 | High Electron Mobility Transistor Structure - The present disclosure relates to a channel layer of bi-layer of gallium nitride (GaN) within a HEMT. A first breakdown voltage layer of GaN is disposed beneath an active layer of the HEMT. A second breakdown voltage layer of GaN is disposed beneath the first breakdown voltage layer, wherein the first resistivity value is less than the second resistivity value. An increased resistivity of the second breakdown voltage layer results from an increased concentration of carbon dopants which increases the breakdown voltage in the second breakdown voltage layer, but can degrade the crystal structure. To alleviate this degradation, a crystal adaptation layer is disposed beneath the second breakdown voltage layer and configured to lattice-match to the second breakdown voltage layer of GaN. As a result, the HEMT achieves a high breakdown voltage without any associated degradation to the first breakdown voltage layer, wherein a channel of the HEMT resides. | 07-31-2014 |
| 20140209921 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element includes: an n-type semiconductor layer; a light emitting layer alternately laminating plural barrier layers and plural well layers; and a p-type semiconductor layer, wherein the light emitting layer includes three or more well layers and four or more barrier layers, each well layer being sandwiched by the barrier layers, one barrier layer contacting the n-type semiconductor layer, and another barrier layer contacting the p-type semiconductor layer, the well layers include plural n-side well layers from the n-type semiconductor layer side and one p-side well layer on the p-type semiconductor layer side, and a V-shaped concave portion including inclined surfaces is generated in the light emitting layer, and in at least one of the n-side well layers, a concentration of atoms of In on the inclined surface is not more than 50% of a concentration of atoms of In in the n-side well layer. | 07-31-2014 |
| 20140209922 | SEMICONDUCTOR DEVICE - A high electron mobility transistor having a channel layer, electron supply layer, source electrode, and drain electrode is included so as to have a cap layer formed on the electron supply layer between the source and drain electrodes and having an inclined side surface, an insulating film having an opening portion on the upper surface of the cap layer and covering the side surface thereof, and a gate electrode is formed in the opening portion and extending, via the insulating film, over the side surface of the cap layer on the drain electrode side. The gate electrode having an overhang on the drain electrode side can reduce the peak electric field. | 07-31-2014 |
| 20140209923 | OPTOELECTRONIC DEVICES INCORPORATING SINGLE CRYSTALLINE ALUMINUM NITRIDE SUBSTRATE - The invention provides an optoelectronic device adapted to emit ultraviolet light, including an aluminum nitride single crystalline substrate, wherein the dislocation density of the substrate is less than about 10 | 07-31-2014 |
| 20140209924 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device which reduces a source resistance and a manufacturing method for the same are provided. The semiconductor device has a nitride based compound semiconductor layer arranged on a substrate, an active region which has an aluminum gallium nitride layer arranged on the nitride based compound semiconductor layer, and a gate electrode, source electrode and drain electrode arranged on the active region. The semiconductor device has gate terminal electrodes, source terminal electrodes and drain terminal electrode connected to the gate electrode, source electrode and drain electrode respectively. The semiconductor device has end face electrodes which are arranged on a side face of the substrate by a side where the source terminal electrode is arranged, and which are connected to the source terminal electrode. The semiconductor device has a projection arranged on the end face electrode which prevents solder used in die bonding from reaching the source terminal electrodes. | 07-31-2014 |
| 20140209925 | METHODS FOR PRODUCING IMPROVED CRYSTALLINITY GROUP III-NITRIDE CRYSTALS FROM INITIAL GROUP III-NITRIDE SEED BY AMMONOTHERMAL GROWTH - The present invention discloses methods to create higher quality group III-nitride wafers that then generate improvements in the crystalline properties of ingots produced by ammonothermal growth from an initial defective seed. By obtaining future seeds from carefully chosen regions of an ingot produced on a bowed seed crystal, future ingot crystalline properties can be improved. Specifically, the future seeds are optimized if chosen from an area of relieved stress on a cracked ingot or from a carefully chosen N-polar compressed area. When the seeds are sliced out, miscut of 3-10° helps to improve structural quality of successive growth. Additionally a method is proposed to improve crystal quality by using the ammonothermal method to produce a series of ingots, each using a specifically oriented seed from the previous ingot. When employed, these methods enhance the quality of Group III nitride wafers and thus improve the efficiency of any subsequent device. | 07-31-2014 |
| 20140217416 | NITRIDES BASED SEMICONDUCTOR DEVICE - A nitride-based semiconductor device is disclosed, including a substrate, an active region including a plurality of nitride-based semiconductor layers disposed on the substrate, wherein a 2DEG channel and a two-dimensional hole gas (2DHG) under the two-dimensional electron gas (2DEG) channel are formed within the plurality of nitride-based semiconductor layers, a gate electrode disposed on the top of the active region and an interconnection structure electrically connected with the gate electrode and the 2DHG. | 08-07-2014 |
| 20140217417 | ILLUMINATION METHOD AND LIGHT-EMITTING DEVICE - To provide an illumination method and a light-emitting device which are capable of achieving, under an indoor illumination environment where illuminance is around 5000 lx or lower when performing detailed work and generally around 1500 lx or lower, a color appearance or an object appearance as perceived by a person, will be as natural, vivid, highly visible, and comfortable as though perceived outdoors in a high-illuminance environment, regardless of scores of various color rendition metric. Light emitted from the light-emitting device illuminates an object such that light measured at a position of the object satisfies specific requirements. A feature of the light-emitting device is that light emitted by the light-emitting device in a main radiant direction satisfies specific requirements. | 08-07-2014 |
| 20140217418 | SEMICONDUCTOR LIGHT EMITTING DEVICE HAVING ROUGHNESS LAYER - A semiconductor light emitting device is provided, including a substrate, a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer that includes a top surface and a bottom surface. The device includes a first roughness layer having a random horn shape and formed with irregular intervals, a second roughness layer, and at least one of a first AlGaN based semiconductor layer and a second AlGaN based semiconductor layer. The second conductive semiconductor layer includes a plurality of apexes on the top surface, where the distance between at least two apexes is of about 0.3 μm to about 1.0 μm. The second roughness layer includes a lower surface having a shape corresponding to the top surface of the second conductive semiconductor layer. The second roughness layer includes an upper surface having a shape corresponding to a top surface of the first roughness layer. | 08-07-2014 |
| 20140217419 | SEMICONDUCTOR STRUCTURES INCLUDING STACKS OF INDIUM GALLIUM NITRIDE LAYERS - Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods. | 08-07-2014 |
| 20140217420 | Methods and structures for preparing single crystal silicon wafers for use as substrates for epitaxial arowth of crack-free aallium nitride fi ms and devices - This document describes the fabrication and use of ceramic stabilizing layer fabricated right on the product silicon wafer to facilitate its use as a substrate for fabrication of gallium nitride films. A ceramic layer is formed and then attached to a single crystal silicon substrate to form a composite silicon substrate that has coefficient of thermal expansion comparable with GaN. The composite silicon substrates prepared by this invention are uniquely suited for use as growth substrates for crack-free gallium nitride films, benefitting from compressive stresses produced by choosing a ceramic having a desired higher coefficient thermal expansion than those of silicon and gallium nitride. | 08-07-2014 |
| 20140231815 | PACKAGE FOR HIGH-POWER SEMICONDUCTOR DEVICES - Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed. | 08-21-2014 |
| 20140231816 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is overlying and in contact with the second III-V compound layer. A gate dielectric is over the crystalline interfacial layer. A gate electrode is over the gate dielectric. A source region and a drain region are over the second III-V compound layer, and are on opposite sides of the gate electrode. | 08-21-2014 |
| 20140231817 | III-N MATERIAL GROWN ON ALO/ALN BUFFER ON SI SUBSTRATE - III-N material grown on a silicon substrate includes a single crystal buffer positioned on a silicon substrate. The buffer is substantially crystal lattice matched to the surface of the silicon substrate and includes aluminum oxynitride adjacent the substrate and aluminum nitride adjacent the upper surface. A first layer of III-N material is positioned on the upper surface of the buffer. An inter-layer of aluminum nitride (AlN) is positioned on the first III-N layer and an additional layer of III-N material is positioned on the inter-layer. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. | 08-21-2014 |
| 20140231818 | AlN CAP GROWN ON GaN/REO/SILICON SUBSTRATE STRUCTURE - III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer. | 08-21-2014 |
| 20140231819 | LED DEVICE - An LED device is disclosed in which an LED chip is encapsulated in a encapsulant. The LED device includes an LED chip mounted on a support and electrically connected and an encapsulant encapsulating the LED chip, wherein the encapsulant is a transparent amorphous solid made of a metal oxide, and the solid contains as a major component at least one metal oxide selected from the group consisting of Al | 08-21-2014 |
| 20140231820 | MEMORY DEVICE USING GRAPHENE AS CHARGE-TRAP LAYER AND METHOD OF OPERATING THE SAME - A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges. | 08-21-2014 |
| 20140231821 | LIGHT-EMITTING DEVICE - A light-emitting device includes a plurality of LED chips arranged in series and each including a chip substrate and a crystal layer including a light-emitting layer. One of the plurality of LED chips is configured such that the chip substrate thereof includes a side surface facing another adjacent LED chip of the plurality of LED chips. The side surface has a highest cleavability among all side surfaces of the chip substrate of the one of the plurality of LED chips. | 08-21-2014 |
| 20140231822 | VERTICAL TOPOLOGY LIGHT-EMITTING DEVICE - A vertical topology light emitting device comprises a metal support structure; an adhesion structure on the metal support structure, wherein the adhesion structure comprises a first adhesion layer and a second adhesion layer on the first adhesion layer; a metal layer on the adhesion structure, wherein the adhesion structure is thicker than the metal layer; a GaN-based semiconductor structure on the metal layer, wherein the GaN-based semiconductor structure has a thickness less than 5 micrometers; a multi-layered electrode structure on the GaN-based semiconductor structure; and a protective layer on a side surface and a top surface of the GaN-based semiconductor structure, wherein the protective layer is further disposed on the multi-layered electrode structure. | 08-21-2014 |
| 20140231823 | ELECTRODES FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A III-N semiconductor HEMT device includes an electrode-defining layer on a III-N material structure. The electrode-defining layer has a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, each sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a larger width than a portion of the recess proximal to the III-N material structure. An electrode is in the recess, the electrode including an extending portion over the first sidewall. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle. | 08-21-2014 |
| 20140231824 | NITRIDE SEMICONDUCTOR DEVICE, NITRIDE SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAYER - According to one embodiment, a nitride semiconductor device includes a foundation layer and a functional layer. The foundation layer is formed on an Al-containing nitride semiconductor layer formed on a silicon substrate. The foundation layer has a thickness not less than 1 micrometer and including GaN. The functional layer is provided on the foundation layer. The functional layer includes a first semiconductor layer. The first semiconductor layer has an impurity concentration higher than an impurity concentration in the foundation layer and includes GaN of a first conductivity type. | 08-21-2014 |
| 20140239305 | METHOD OF OPTIMIZING A GA-NITRIDE DEVICE MATERIAL STRUCTURE FOR A FREQUENCY MULTIPLICATION DEVICE - A preferred method of optimizing a Ga-nitride device material structure for a frequency multiplication device comprises:
| 08-28-2014 |
| 20140239306 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A diffusion barrier layer is disposed on top of the second III-V compound layer. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode. | 08-28-2014 |
| 20140239307 | REO GATE DIELECTRIC FOR III-N DEVICE ON Si SUBSTRATE - A rare earth oxide gate dielectric on III-N material grown on a silicon substrate includes a single crystal stress compensating template positioned on a silicon substrate. The stress compensating template is substantially crystal lattice matched to the surface of the silicon substrate. A GaN structure is positioned on the surface of the stress compensating template and substantially crystal lattice matched thereto. An active layer of single crystal III-N material is grown on the GaN structure and substantially crystal lattice matched thereto. A single crystal rare earth oxide dielectric layer is grown on the active layer of III-N material. | 08-28-2014 |
| 20140239308 | MIX DOPING OF A SEMI-INSULATING GROUP III NITRIDE - Embodiments of a semi-insulating Group III nitride and methods of fabrication thereof are disclosed. In one embodiment, a semi-insulating Group III nitride layer includes a first doped portion that is doped with a first dopant and a second doped portion that is doped with a second dopant that is different than the first dopant. The first doped portion extends to a first thickness of the semi-insulating Group III nitride layer. The second doped portion extends from approximately the first thickness of the semi-insulating Group III nitride layer to a second thickness of the semi-insulating Group III nitride layer. In one embodiment, the first dopant is Iron (Fe), and the second dopant is Carbon (C). In another embodiment, the semi-insulating Group III nitride layer is a semi-insulating Gallium Nitride (GaN) layer, the first dopant is Fe, and the second dopant is C. | 08-28-2014 |
| 20140239309 | Heterostructure Power Transistor With AlSiN Passivation Layer - A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts. | 08-28-2014 |
| 20140239310 | GROWTH SUBSTRATE, NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a method of manufacturing a light emitting device. More particularly, disclosed are a growth substrate, a nitride semiconductor device and a method of manufacturing a light emitting device. The method includes preparing a growth substrate including a metal substrate, forming a semiconductor structure including a nitride-based semiconductor on the growth substrate, providing a support structure on the semiconductor structure, and separating the growth substrate from the semiconductor structure. | 08-28-2014 |
| 20140239311 | SEMICONDUCTOR DEVICE - A semiconductor device includes a buffer layer, a channel layer and a barrier layer formed over a substrate, a trench penetrating through the barrier layer to reach the middle of the channel layer, and a gate electrode disposed inside the trench via a gate insulating film. The channel layer contains n-type impurities, and a region of the channel layer positioned on a buffer layer side has an n-type impurity concentration larger than a region of the channel layer positioned on a barrier layer side, and the buffer layer is made of nitride semiconductor having a band gap wider than that of the channel layer. The channel layer is made of GaN and the buffer layer is made of AlGaN. The channel layer has a channel lower layer containing n-type impurities at an intermediate concentration and a main channel layer formed thereon and containing n-type impurities at a low concentration. | 08-28-2014 |
| 20140239312 | Semiconductor Structure with Inhomogeneous Regions - A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher. | 08-28-2014 |
| 20140239313 | LIGHT-EMITTING SEMICONDUCTOR DEVICE USING GROUP III NITROGEN COMPOUND - A method of producing a light-emitting semiconductor device of a group III nitride compound includes forming a buffer layer on a sapphire substrate, forming a Si-doped N | 08-28-2014 |
| 20140246679 | III-N MATERIAL GROWN ON ErAlN BUFFER ON Si SUBSTRATE - III-N material grown on a buffer on a silicon substrate includes a single crystal electrically insulating buffer positioned on a silicon substrate. The single crystal buffer includes rare earth aluminum nitride substantially crystal lattice matched to the surface of the silicon substrate, i.e. a lattice co-incidence between REAlN and Si better than a 5:4 ratio. A layer of single crystal III-N material is positioned on the surface of the buffer and substantially crystal lattice matched to the surface of the buffer. | 09-04-2014 |
| 20140252366 | Semiconductor Structure Including Buffer With Strain Compensation Layers - A semiconductor structure includes a substrate and a semiconductor buffer structure overlying the substrate. The semiconductor buffer structure includes a semiconductor body of a gallium nitride material, and a stack of strain compensation layers. The stack of strain compensation layers includes a layer of a first semiconductor material with an in-plane lattice constant that is smaller than a lattice constant of the semiconductor body, and a layer of a second semiconductor material with an in-plane lattice constant that is greater than the lattice constant of the semiconductor body. | 09-11-2014 |
| 20140252367 | DRIVER FOR NORMALLY ON III-NITRIDE TRANSISTORS TO GET NORMALLY-OFF FUNCTIONALITY - A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate. | 09-11-2014 |
| 20140252368 | HIGH-ELECTRON-MOBILITY TRANSISTOR - A high-electron-mobility transistor (HEMT) device includes a plurality of semiconductor layers formed on a substrate, wherein a two-dimensional electron gas (2DEG) layer is formed in the semiconductor layers; an etch-stop layer formed on the plurality of semiconductor layers; a p-type semiconductor layer pattern formed on the etch-stop layer; and a gate electrode formed on the p-type semiconductor layer pattern. | 09-11-2014 |
| 20140252369 | NITRIDE-BASED SEMICONDUCTOR DEVICE - A nitride-based semiconductor device including a substrate; a GaN-containing layer on the substrate; a nitride-containing layer on the GaN layer; a channel blocking layer on the nitride-containing layer, the channel blocking layer including a nitride-based semiconductor; a gate insulation layer on the channel blocking layer; and a gate electrode on the gate insulation layer. | 09-11-2014 |
| 20140252370 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Exemplary embodiments of the present invention disclose a unidirectional heterojunction transistor including a channel layer made of a first nitride-based semiconductor having a first energy bandgap, a barrier layer made of a second nitride-based semiconductor having a second energy bandgap different from the first energy bandgap, the barrier layer including a recess, a drain electrode disposed on a first region of the barrier layer, and a recessed-drain Schottky electrode disposed in the recess of the barrier layer, the recessed-drain Schottky electrode contacting the drain electrode. | 09-11-2014 |
| 20140252371 | HETEROJUNCTION TRANSISTOR AND METHOD OF FABRICATING THE SAME - Exemplary embodiments of the present invention disclose a heterojunction transistor having a normally off characteristic using a gate recess structure and a method of fabricating the same. The heterojunction transistor may include a substrate, a channel layer disposed on the substrate and made of a first nitride-based semiconductor having a first energy bandgap, a first barrier layer disposed on the channel layer and made of a second nitride-based semiconductor having a second energy bandgap different from the first energy bandgap, a gate electrode disposed in a gate control region of the first barrier layer, and a second barrier layer disposed in gate non-control regions of the first barrier layer and separated from the first barrier layer. | 09-11-2014 |
| 20140252372 | VERTICAL GALLIUM NITRIDE SCHOTTKY DIODE - A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction nitride-based Schottky diode is thus realized. In another embodiment, a protection circuit for a vertical GaN Schottky diode employs a silicon-based vertical PN junction diode connected in parallel to the GaN Schottky diode to divert reverse bias avalanche current. | 09-11-2014 |
| 20140264358 | STRUCTURE AND METHOD FOR FORMING INTEGRAL NITRIDE LIGHT SENSORS ON SILICON SUBSTRATES - A semiconductor integrated circuit has one or more integral nitride-type sensors. In one embodiment, an integral nitride-type sensor and a coplanar supplemental circuit are formed from a common silicon substrate base. In another embodiment, an integral nitride-type sensor and a supplemental circuit are integrated in a vertical orientation. | 09-18-2014 |
| 20140264359 | Lightweight self-cooling light sources - A solid-state light source has light emitting diodes embedded in a thermally conductive translucent luminescent element. The thermally conductive translucent luminescent element has optically translucent thermal filler and at least one luminescent element in a matrix material. A leadframe is electrically connected to the light emitting diodes. The leadframe distributes heat from the light emitting diodes to the thermally conductive translucent luminescent element. The thermally conductive translucent luminescent element distributes heat from light emitting diodes and the thermally conductive translucent luminescent element. | 09-18-2014 |
| 20140264360 | TRANSISTOR WITH CHARGE ENHANCED FIELD PLATE STRUCTURE AND METHOD - Transistors and methods of fabricating are described herein. These transistors include a field plate ( | 09-18-2014 |
| 20140264361 | III-NITRIDE TRANSISTOR WITH ENGINEERED SUBSTRATE - A transistor includes a buffer layer, a channel layer over the buffer layer, a barrier layer over the channel layer, a source electrode electrically connected to the channel layer, a drain electrode electrically connected to the channel layer, a gate electrode on the barrier layer between the source electrode and the drain electrode, a backside metal layer, a substrate between a first portion of the buffer layer and the backside metal layer; and a dielectric between a second portion of the buffer layer and the backside metal layer. | 09-18-2014 |
| 20140264362 | Method and Apparatus for Forming a CMOS Device - A method and apparatus for forming a CMOS device are provided. The CMOS device may include an N-type channel region formed of an III-V material and a P-type channel region formed of a germanium material. Over each channel may be formed corresponding gates and source/drain regions. The source/drain regions may be formed of a germanium material and one or more metallization layers. An anneal may be performed to form ohmic contacts for the source/drain regions. Openings may be formed in a dielectric layer covering the device and conductive plugs may be formed to provide contact to the source/drain regions. | 09-18-2014 |
| 20140264363 | Oxygen Controlled PVD Aluminum Nitride Buffer for Gallium Nitride-Based Optoelectronic and Electronic Devices - Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer. | 09-18-2014 |
| 20140264364 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a first semiconductor layer formed on the substrate, a second semiconductor layer formed on the first semiconductor layer, a first insulation layer formed on the second semiconductor layer, the first insulation layer being formed of a material that includes SiO | 09-18-2014 |
| 20140264365 | Rectifier Structures with Low Leakage - An integrated circuit device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a gate dielectric over the second III-V compound layer, and a gate electrode over the gate dielectric. An anode electrode and a cathode electrode are formed on opposite sides of the gate electrode. The anode electrode is electrically connected to the gate electrode. The anode electrode, the cathode electrode, and the gate electrode form portions of a rectifier. | 09-18-2014 |
| 20140264366 | SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THE SAME - A semiconductor apparatus includes a semiconductor substrate that has a diameter of 2 inches or larger, and an N-type semiconductor layer that is stacked on the semiconductor substrate using a material including gallium nitride (GaN). A median of a plurality of measured values of the concentration of carbon (C) at a plurality of locations on a face of a region of the N-type semiconductor layer is equal to or lower than 1.0×10 | 09-18-2014 |
| 20140264367 | HEMT Semiconductor Device and a Process of Forming the Same - A HEMT semiconductor device can include a dielectric layer that includes a silicon nitride film and an AlN film. In an embodiment, the HEMT semiconductor device can include a GaN film and an AlGaN film. In a process of forming the HEMT device, the AlN can provide an etch stop when forming an opening for a gate electrode. | 09-18-2014 |
| 20140264368 | Semiconductor Wafer and a Process of Forming the Same - A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate. | 09-18-2014 |
| 20140264369 | HIGH ELECTRON MOBILITY SEMICONDUCTOR DEVICE AND METHOD THEREFOR - In one embodiment, Group III-nitride materials are used to form a semiconductor device. A fin structure is formed in the Group III-nitride material, and a gate structure, source electrodes and drain electrodes are formed in spaced relationship to the fin structure. The fin structure provides both polar and semi-polar 2DEG regions. In one embodiment, the gate structure is configured to control current flow in the polar 2DEG region. Shield conductor layers are included above the gate structure and in spaced relationship with drain regions of the semiconductor device. | 09-18-2014 |
| 20140264370 | CARBON DOPING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device can include forming a III-N semiconductor layer in a reactor and injecting a hydrocarbon precursor into the reactor, thereby carbon doping the III-N semiconductor layer and causing the III-N semiconductor layer to be insulating or semi-insulating. A semiconductor device can include a substrate and a carbon doped insulating or semi-insulating III-N semiconductor layer on the substrate. The carbon doping density in the III-N semiconductor layer is greater than 5×10 | 09-18-2014 |
| 20140264371 | SEMICONDUCTOR STRUCTURES HAVING ACTIVE REGIONS COMPRISING INGAN, METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES, AND LIGHT EMITTING DEVICES FORMED FROM SUCH SEMICONDUCTOR STRUCTURES - Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising In | 09-18-2014 |
| 20140264372 | STRUCTURE AND MANUFACTURING METHOD OF THE STRUCTURE, AND GALLIUM NITRIDE-BASED SEMICONDUCTOR LIGHT-EMITTING DEVICE USING THE STRUCTURE AND MANUFACTURING METHOD OF THE DEVICE - In a structure including a gallium nitride-based semiconductor having an m-plane as a principal plane, and a metal layer provided on the principal plane, the principal plane has an n-type conductivity. An interface between the gallium nitride-based semiconductor and the metal layer contains oxygen. The metal layer includes a crystal grain extending form a lower surface to an upper surface of the metal layer. | 09-18-2014 |
| 20140264373 | III-Nitride Heterojunction Device - A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions. | 09-18-2014 |
| 20140284609 | Method and Substrate for Thick III-N Epitaxy - A method of manufacturing an III-N substrate includes bonding a Si substrate to a support substrate, the Si substrate having a (111) growth surface facing away from the support substrate, thinning the Si substrate at the (111) growth surface to a thickness of 100 μm or less, and forming III-N material on the (111) growth surface of the Si substrate after the Si substrate is thinned. The support substrate has a coefficient of thermal expansion more closely matched to that of the III-N material than the Si substrate. Other methods of manufacturing an III-N substrate are disclosed, as well as the corresponding wafer structures. | 09-25-2014 |
| 20140284610 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a conductive substrate, a Schottky barrier diode, and a field-effect transistor. The Schottky barrier diode is mounted on the conductive substrate and includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the conductive substrate. The field-effect transistor is mounted on the conductive substrate and includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the field-effect transistor is electrically connected to the cathode electrode of the Schottky barrier diode. The gate electrode of the field-effect transistor is electrically connected to the anode electrode of the Schottky barrier diode. | 09-25-2014 |
| 20140284611 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a method for manufacturing a semiconductor light-emitting device includes growing a semiconductor film including a group III nitride semiconductor on a silicon substrate, dividing the grown semiconductor film into a plurality of sections by selectively removing the semiconductor film, forming an aluminum film to cover the semiconductor film, removing the aluminum film selectively, oxidizing the remained aluminum film, and removing the silicon substrate. | 09-25-2014 |
| 20140284612 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer stacked on a face of the substrate successively, a first electrode electrically connected to the first semiconductor layer, and a second electrode electrically connected to the second semiconductor layer. The first semiconductor layer is disposed adjacent to the substrate. A plurality of nanoscale holes are defined in the face of the substrate contacting the first semiconductor layer. A method for manufacturing the light emitting diode is also provided. | 09-25-2014 |
| 20140284613 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes a nitride semiconductor layer, a gate electrode provided above the nitride semiconductor layer, a source electrode provided above the nitride semiconductor layer, a drain electrode provided above the nitride semiconductor layer at a side opposite to the source electrode with respect to the gate electrode, a first silicon nitride film provided above the nitride semiconductor layer between the drain electrode and the gate electrode, and a second silicon nitride film provided between the nitride semiconductor layer and the gate electrode, an atomic ratio of silicon to nitrogen in the second silicon nitride film being lower than an atomic ratio of silicon to nitrogen in the first silicon nitride film. | 09-25-2014 |
| 20140284614 | METHODS FOR EPITAXIAL DEVICES - Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride. | 09-25-2014 |
| 20140291689 | LIGHT EMITTING DIODE WITH WAVE-SHAPED BRAGG REFLECTIVE LAYER AND METHOD FOR MANUFACTURING SAME - An exemplary light emitting diode includes a substrate and a first undoped GaN layer formed on the substrate. The first undoped GaN layer has ion implanted areas on an upper surface thereof. A plurality of second undoped GaN layers is formed on the first undoped GaN layer. Each of the second undoped GaN layers is island shaped and partly covers at least one corresponding ion implanted area. A Bragg reflective layer is formed on the second undoped GaN layer and on portions of upper surfaces of the ion implanted areas not covered by the second undoped GaN layers. An n-type GaN layer, an active layer and a p-type GaN layer are formed on an upper surface of the Bragg reflective layer in that sequence. A method for manufacturing the light emitting diode is also provided. | 10-02-2014 |
| 20140291690 | OPTICAL DEVICE AND METHOD FOR MANUFACTURING SAME - Provided are an optical device and a method for manufacturing same. The optical device according to the present invention including: a transparent amorphous substrate; a current injection layer formed on the substrate; a graphite layer formed on the current injection layer; and a semiconductor unit formed on the graphite layer, wherein the semiconductor unit is formed after forming the graphite layer on the amorphous substrate, thereby overcoming the problems of conventional methods that involve forming a semiconductor unit on an amorphous substrate, and the semiconductor unit of the present invention has superior crystallinity. | 10-02-2014 |
| 20140291691 | VERTICAL GALLIUM NITRIDE JFET WITH GATE AND SOURCE ELECTRODES ON REGROWN GATE - A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure. | 10-02-2014 |
| 20140291692 | HIGH TEMPERATURE GaN BASED SUPER SEMICONDUCTOR AND FABRICATION PROCESS - A low temperature GaN based super semiconductor comprising a GaN supercell having equal percentages of Cu and at least one material from the family of P, As, or Sb. The GaN supercell is doped in accordance with the formula Ga | 10-02-2014 |
| 20140291693 | GROUP III-N TRANSISTORS ON NANOSCALE TEMPLATE STRUCTURES - A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin. | 10-02-2014 |
| 20140291694 | PLANAR NONPOLAR GROUP-III NITRIDE FILMS GROWN ON MISCUT SUBSTRATES - A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction. | 10-02-2014 |
| 20140299885 | SUBSTRATE STRUCTURES AND SEMICONDUCTOR DEVICES EMPLOYING THE SAME - A substrate structure includes a substrate, a nucleation layer on the substrate and including a group III-V compound semiconductor material having a lattice constant that is different from that of the substrate by less than 1%, and a buffer layer on the nucleation layer and including first and second layers, wherein the first and second layers include group III-V compound semiconductor materials having lattice constants that are greater than that of the nucleation layer by 4% or more. | 10-09-2014 |
| 20140306230 | LED COMPONENT BY INTEGRATING EPITAXIAL STRUCTURE AND PACKAGE SUBSTRATE TOGETHER AND METHOD OF MANUFACTURING THE SAME - The present invention discloses an integral LED component which integrates LED epitaxial structures electrodes and interconnect with a package substrate together and an integral manufacturing process thereof. The integral LED component can be made with multiple epitaxial structures or with just a single epitaxial structure. The integral LED component can be mounted into a hollow carrier. And by having support by the hollow carrier, the package substrate can be mounted and contacted with a heat conductive or a dissipation device. The integral LED component is fabricated by wafer level process and cut from the wafer as an independent component. By different manufacturing process, the integral LED component can be made as Vertical LED structure or Lateral LED structure. | 10-16-2014 |
| 20140306231 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts. | 10-16-2014 |
| 20140306232 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - Disclosed is a semiconductor device comprising at least one active layer ( | 10-16-2014 |
| 20140306233 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor layer formed on a substrate, an electrode contact window that includes a recess formed on a surface of the semiconductor layer, an inner wall having a slope, and a source electrode, a drain electrode, and a gate electrode formed on the semiconductor layer, in which the drain electrode is in contact with the slope of the inner wall. | 10-16-2014 |
| 20140306234 | LIGHT EMITTING DEVICE - A light emitting device includes a light emitting diode whose front surface is supported and fixed on a package mounting surface and a transparent member bonded to the back surface of the light emitting diode. The light emitting diode has a light emitting layer on the front surface side. | 10-16-2014 |
| 20140306235 | Method for Producing a Semiconductor Device Comprising a Schottky Diode and a High Electron Mobility Transistor - A semiconductor device includes a Schottky diode and a High Electron Mobility Transistor (HEMT) formed on a III-nitride stack. The III-nitride stack includes at least a lower and an upper III-nitride layer forming a heterojunction therebetween, so that a 2-dimensional electron gas (2DEG) layer may be formed in the lower layer. The 2DEG layer serves as a charge carrier for the diode and the HEMT. A doped III-nitride layer may be present between a portion of the anode of the diode and the III-nitride stack, and the portion may be located between the diode's Schottky junction and the cathode. A further layer of doped III-nitride material may be present between the gate electrode of the HEMT and the III-nitride stack. The thickness of the III-nitride layers is not equal, so that the turn-on voltage of the diode and the threshold voltage of the HEMT may be tuned according to specific requirements. The disclosure also involves a method of producing such a semiconductor device. | 10-16-2014 |
| 20140306236 | SUCCESSIVE IONIC LAYER ADSORPTION AND REACTION PROCESS FOR DEPOSITING EPITAXIAL ZNO ON III-NITRIDE-BASED LIGHT EMITTING DIODE AND LIGHT EMITTING DIODE INCLUDING EPITAXIAL ZNO - A method of forming a ZnO layer on a substrate and an LED including a ZnO layer formed by the method are provided. The ZnO layer is formed by using a Successive Ionic Layer Adsorption and Reaction (SILAR) process. The SILAR process includes: applying a first solution to a substrate comprising GaN, to form an inner ionic layer on the substrate and an outer ionic layer on the inner ionic layer; performing a first washing operation on the substrate to remove the outer ionic layer; and applying a second solution to the washed substrate to convert the inner ionic layer into a ZnO oxide layer. | 10-16-2014 |
| 20140306237 | LIGHT EMITTING ELEMENT AND METHOD OF MAKING SAME - A light emitting element that includes a Ga | 10-16-2014 |
| 20140306238 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - According to a semiconductor device ( | 10-16-2014 |
| 20140312355 | METHOD OF FABRICATING A MERGED P-N JUNCTION AND SCHOTTKY DIODE WITH REGROWN GALLIUM NITRIDE LAYER - A method for fabricating a merged p-i-n Schottky (MPS) diode in gallium nitride (GaN) based materials includes providing an n-type GaN-based substrate having a first surface and a second surface. The method also includes forming an n-type GaN-based epitaxial layer coupled to the first surface of the n-type GaN-based substrate, and forming a p-type GaN-based epitaxial layer coupled to the n-type GaN-based epitaxial layer. The method further includes removing portions of the p-type GaN-based epitaxial layer to form a plurality of dopant sources, and regrowing a GaN-based epitaxial layer including n-type material in regions overlying portions of the n-type GaN-based epitaxial layer, and p-type material in regions overlying the plurality of dopant sources. The method also includes forming a first metallic structure electrically coupled to the regrown GaN-based epitaxial layer. | 10-23-2014 |
| 20140312356 | Semiconductor Device - A semiconductor device and a method of making the same. The device includes a semiconductor substrate. The device also includes a bipolar transistor on the semiconductor substrate. The bipolar transistor includes an emitter. The bipolar transistor also includes a base located above the emitter. The bipolar transistor further includes a laterally extending collector located above the base. The collector includes a portion that extends past an edge of the base. | 10-23-2014 |
| 20140312357 | SEMICONDUCTOR DEVICE - A semiconductor device of the invention includes an n-GaN layer provided on a substrate, a channel layer provided in contact with the upper surface of the n-GaN layer, an electron supply layer which is provided on the channel layer, and a gate electrode, a source electrode, and a drain electrode which are provided on the electron supply layer. The gate electrode is in contact with a underlying layer made from a nitride semiconductor. The semiconductor device has a ratio defined by the equation L/d1>=7, where L=the width of the gate electrode in contact with the underlying layer in a direction between the source electrode and drain electrode; d1 the distance between a surface of the n-type gallium nitride layer and a boundary between the gate electrode and the underlying layer. | 10-23-2014 |
| 20140312358 | NORMALLY-OFF GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICES - A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress. The method further includes forming a compressive layer over the relaxed layer, where the compressive layer has compressive stress. The compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers. The piezoelectric polarization in the compressive layer could be in an opposite direction than the spontaneous polarization in the compressive layer. The relaxed layer could include gallium nitride, the tensile layer could include aluminum gallium nitride, and the compressive layer could include aluminum indium gallium nitride. | 10-23-2014 |
| 20140312359 | METHOD FOR BONDING SEMICONDUCTOR SUBSTRATES - A method is provided for bonding a first substrate carrying a semiconductor device layer on its front surface to a second substrate. The method comprises producing the semiconductor device layer on the front surface of the first substrate, depositing a first metal bonding layer or a stack of metal layers on the first substrate, on top of the semiconductor device layer, depositing a second metal bonding layer or a stack of metal layers on the front surface of the second substrate, depositing a metal stress-compensation layer on the back side of the second substrate, thereafter establishing a metal bond between the first and second substrate, by bringing the first and second metal bonding layers or stacks of layers into mutual contact under conditions of mechanical pressure and temperature suitable for obtaining the metal bond, and removing the first substrate. | 10-23-2014 |
| 20140319532 | Heterojunction Semiconductor Device and Manufacturing Method - A heterojunction semiconductor device having a semiconductor body is provided. The semiconductor body includes a first semiconductor region comprising aluminum gallium nitride, a second semiconductor region comprising gallium nitride and forming a heterojunction with the first semiconductor region, an n-type third semiconductor region, a p-type fourth semiconductor region forming a first rectifying junction with the third semiconductor region, and an n-type seventh semiconductor region adjoining the heterojunction formed between the first semiconductor region and the second semiconductor region. The first rectifying junction forms a rectifying junction of a transistor structure which is in ohmic contact with the seventh semiconductor region. Further, a method for producing such a heterojunction semiconductor device is provided. | 10-30-2014 |
| 20140319533 | FLEXIBLE SEMICONDUCTOR DEVICES BASED ON FLEXIBLE FREESTANDING EPITAXIAL ELEMENTS - Flexible semiconductor devices based on flexible freestanding epitaxial elements are disclosed. The flexible freestanding epitaxial elements provide a virgin as grown epitaxy ready surface for additional growth layers. These flexible semiconductor devices have reduced stress due to the ability to flex with a radius of curvature less than 100 meters. Low radius of curvature flexing enables higher quality epitaxial growth and enables 3D device structures. Uniformity of layer formation is maintained by direct absorption of actinic radiation by the flexible freestanding epitaxial element within a reactor. In addition, standard post processing steps like lithography are enabled by the ability of the devices and elements to be flattened using a secondary support element or vacuum. Finished flexible semiconductor devices can be flexed to a radius of curvature of less than 100 meters. Nitrides, Zinc Oxides, and their alloys are preferred materials for the flexible freestanding epitaxial elements. | 10-30-2014 |
| 20140319534 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element comprises an optical semiconductor laminated layer providing vias, an electrode that is disposed on a surface of the optical semiconductor laminated layer and separated from the second semiconductor layer in a peripheral portion of the electrode, a first transparent insulating layer that is disposed between the peripheral portion of the electrode and the optical semiconductor laminated layer, and a second transparent insulating layer that is disposed to cover the electrode, that envelops the peripheral portion of the electrode together with the first transparent insulating layer. | 10-30-2014 |
| 20140319535 | NITRIDE SEMICONDUCTOR SUBSTRATE - A nitride semiconductor substrate is provided which is suitable for a high withstand voltage power device and prevents a warp and a crack from generating in a Si substrate when forming a thick nitride semiconductor layer on the substrate. A nitride semiconductor substrate | 10-30-2014 |
| 20140319536 | SOLID STATE LIGHTING DEVICES WITH CELLULAR ARRAYS AND ASSOCIATED METHODS OF MANUFACTURING - Solid state lighting (“SSL”) devices with cellular arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode includes a semiconductor material having a first surface and a second surface opposite the first surface. The semiconductor material has an aperture extending into the semiconductor material from the first surface. The light emitting diode also includes an active region in direct contact with the semiconductor material, and at least a portion of the active region is in the aperture of the semiconductor material. | 10-30-2014 |
| 20140319537 | WHITE EMITTING LIGHT SOURCE AND LUMINESCENT MATERIAL - The invention relates to a white emitting light source with an improved luminescent material of the formula (AEN2/3)*b (MN)*c (SiN4/3)*d1 CeO3/2*d2 EuO*x SiO2*y AlO3/2 wherein AE is an alkaline earth metal chosen of the group of Ca, Mg, Sr and Ba or mixtures thereof and M is a trivalent element chosen of the group of Al, B, Ga, Sc with d1>10*d2. In combination with a UV to blue light generating device this material leads to an improved light quality and stability, especially an improved temperature stability for a wide range of applications. | 10-30-2014 |
| 20140327010 | AVALANCHE ENERGY HANDLING CAPABLE III-NITRIDE TRANSISTORS - A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value. | 11-06-2014 |
| 20140327011 | III-NITRIDE TRANSISTOR LAYOUT - A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate. | 11-06-2014 |
| 20140327012 | HEMT TRANSISTORS CONSISTING OF (III-B)-N WIDE BANDGAP SEMICONDUCTORS COMPRISING BORON - An electronic HEMT transistor structure comprises a heterojunction formed from a first layer, called a buffer layer, of a first wide bandgap semiconductor material, and a second layer of a second wide bandgap semiconductor material, with a bandgap width EG | 11-06-2014 |
| 20140327013 | METHOD FOR MANUFACTURING A THICK EPTAXIAL LAYER OF GALLIUM NITRIDE ON A SILICON OR SIMILAR SUBSTRATE AND LAYER OBTAINED USING SAID METHOD - The invention relates to a method for manufacturing, by means of epitaxy, a monocrystalline layer of GaN on a substrate, wherein the coefficient of thermal expansion is less than the coefficient of thermal expansion of GaN, comprising the following steps: (b) three-dimensional epitaxial growth of a layer of GaN relaxed at the epitaxial temperature, (c1) growth of an intermediate layer of B | 11-06-2014 |
| 20140327014 | III-Nitride Rectifier Package - Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing. | 11-06-2014 |
| 20140327015 | METHOD OF PRODUCING MICROSTRUCTURE OF NITRIDE SEMICONDUCTOR AND PHOTONIC CRYSTAL PREPARED ACCORDING TO THE METHOD - The method of producing a GaN-based microstructure includes a step of preparing a semiconductor structure provided with a trench formed in a main surface of the nitride semiconductor and a heat-treating mask covering a main surface of the nitride semiconductor excluding the trench, a first heat-treatment step of heat-treating the semiconductor structure under an atmosphere containing nitrogen element to form a crystallographic face of the nitride semiconductor on at least a part of a sidewall of the trench, a step of removing the heat-treating mask after the first heat-treatment step and a second heat-treatment step of heat-treating the semiconductor structure under an atmosphere containing nitrogen element to close an upper portion of the trench on the sidewall of which the crystallographic face is formed with a nitride semiconductor. | 11-06-2014 |
| 20140327016 | GROUP III NITRIDE SEMICONDUCTOR FREQUENCY MULTIPLIER AND METHOD THEREOF - A varactor comprising two Schottky diodes, each diode comprising a substrate and a plurality of layers formed on the substrate including at least one GaN layer and at least one semi-insulating material layer formed of a material with an energy gap greater than 3.5 and free carrier mobility less than 300 cm | 11-06-2014 |
| 20140332820 | Flip Light Emitting Diode Chip and Method of Fabricating the Same - A method of fabricating a light emitting diode device comprises depositing conductive material to cover a portion of surface of a conductive and reflective layer to form a first contact pad, and surfaces between adjacent first trenches to form a second contact pad; and depositing a first passivation layer over uncovered portion of surface of the conductive and reflective layer to form a first planar passivation contact surface between the first contact pad and the second trench and depositing bonding material to cover a portion of surface of the first contact pad, a portion of the second contact pad and a portion of the first planar passivation contact to form a first light emitting diode bonding pad on the first contact pad, a second light emitting diode bonding pad on the second contact pad, and a third light emitting diode bonding pad on the first planar passivation contact. | 11-13-2014 |
| 20140332821 | SEMICONDUCTOR DEVICE, LIGHT EMITTING DEVICE USING THE SAME, AND LIGHT EMITTING DEVICE PACKAGE INCLUDING THE SAME - A semiconductor device includes a silicon substrate, an initial buffer layer disposed on the silicon substrate, a transition layer disposed on the initial buffer layer, and a device structure disposed on the transition layer. The transition layer includes at least one of Al | 11-13-2014 |
| 20140332822 | NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR AND MANUFACTURING METHODTHEREOF - A normally off nitride-based transistor may include a source electrode and a drain electrode, a channel layer serving as a charge transfer path between the source electrode and the drain electrode, and a gate electrode that controls charge transfer of the channel layer. The channel layer may have a junction structure of a first conductive nitride semiconductor layer and an intrinsic nitride semiconductor layer such that a fixed turn-off blocking electric field is generated in the channel layer between the source electrode and the drain electrode in a turn-off state. The intrinsic nitride semiconductor layer may include an intrinsic GaN semiconductor layer, and the first conductive nitride semiconductor layer may include a p type GaN semiconductor layer stacked over the intrinsic GaN semiconductor layer. | 11-13-2014 |
| 20140332823 | SCHOTTKY BARRIER DIODE - A Schottky barrier diode is provided with: an n-type semiconductor layer including Ga | 11-13-2014 |
| 20140339565 | LIGHT EMITTING DEVICE - A light emitting device includes a first conductive semiconductor layer on a substrate, a control layer interposed between the substrate and the first conductive semiconductor layer. The control layer includes a first nitride semiconductor layer having aluminum (Al), a plurality of nano-structures on the first nitride semiconductor layer, and a second nitride semiconductor layer provided on the first nitride semiconductor layer and having gallium (Ga). | 11-20-2014 |
| 20140339566 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Disclosed are a semiconductor device and a method of fabricating the same. The method includes forming a first GaN layer, a sacrificial layer and a second GaN layer on a GaN substrate, wherein the sacrificial layer has a bandgap narrower than those of the GaN layers; forming a groove penetrating the second GaN layer and the sacrificial layer; growing GaN-based semiconductor layers on the second GaN layer to form a semiconductor stack; forming a support substrate on the semiconductor stack; and removing the GaN substrate from the semiconductor stack by etching the sacrificial layer. Accordingly, since the sacrificial layer is etched using the groove, the support substrate can be separated from the semiconductor stack without damaging the support substrate. | 11-20-2014 |
| 20140339567 | LIGHT-EMITTING DEVICE - Provided is a high-efficiency light-emitting device. Further, provided is a light-emitting device with high efficiency and less variation in the color temperature of emitted white light in the case of configuring, for example, a white light-emitting device combining a blue LED and a phosphor layer. The light-emitting device includes a phosphor layer that emits light having a predetermined wavelength, and the phosphor layer contains at least one selected from the group consisting of a phosphor represented by a general formula: | 11-20-2014 |
| 20140346522 | METHOD AND SYSTEM FOR CO-PACKAGING VERTICAL GALLIUM NITRIDE POWER DEVICES - An electronic package includes a leadframe and a plurality of pins. The electronic package also includes a first gallium nitride (GaN) transistor comprising a source, gate, and drain and a second GaN transistor comprising a source, gate, and drain. The source of the first GaN transistor is electrically connected to the leadframe and the drain of the second GaN transistor is electrically connected to the leadframe. The electronic package further includes a first GaN diode comprising an anode and cathode and a second GaN diode comprising an anode and cathode. The anode of the first GaN diode is electrically connected to the leadframe and the cathode of the second GaN diode is electrically connected to the leadframe. | 11-27-2014 |
| 20140346523 | Enhanced GaN Transistor and the Forming Method Thereof - An enhanced GaN transistor is provided. The structure comprises a substrate, a heterostructure, a p-element epitaxy growth layer, a drain ohmic contact and a source ohmic contact disposed on the heterostructure and on two sides of the p-element epitaxy growth layer, a gate structure disposed on the p-element epitaxy growth layer, and is separated from the drain ohmic contact and the source ohmic contact, a surface passivation layer covered the drain ohmic contact, source ohmic contact, and p-element epitaxy growth layer, and covered portion of the gate structure. | 11-27-2014 |
| 20140346524 | GALLIUM AND NITROGEN CONTAINING TRILATERAL CONFIGURATION FOR OPTICAL DEVICES - Techniques for manufacturing optical devices, such as light emitting diodes (LEDs) using a separation process of thick gallium and nitrogen containing substrate members, are described. | 11-27-2014 |
| 20140346525 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate; a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer; a gate trench formed in the second semiconductor layer or in the second and first semiconductor layers; a gate electrode formed at the gate trench; and a source electrode and a drain electrode formed on the second semiconductor layer. The gate trench has terminal parts of a bottom of the gate trench formed shallower than a center part of the bottom. A part of a sidewall of the gate trench is formed of a surface including an a-plain surface. The center part of the bottom is a c-plain surface. The terminal parts of the bottom form a slope from the c-plain surface to the a-plain surface. | 11-27-2014 |
| 20140346526 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate; a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer; an insulating layer formed on the second semiconductor layer; a source electrode and a drain electrode formed on the second semiconductor layer; and a gate electrode formed on the insulating layer. The insulating layer is formed of a material including an oxide and is formed by laminating a first insulating layer and a second insulating layer in a positioning order of the first insulating layer followed by the second insulating layer from a side of the second semiconductor layer, and an amount of hydroxyl groups included in per unit volume of the first insulating layer is less than an amount of hydroxyl groups included in per unit volume of the second insulating layer. | 11-27-2014 |
| 20140346527 | Method of fabricating a gallium nitride p-i-n diode using implantation - A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region | 11-27-2014 |
| 20140353673 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a substrate; a first semiconductor layer formed on the substrate and formed of a nitride semiconductor; a second semiconductor layer formed on the first semiconductor layer and formed of a nitride semiconductor; first and second gate electrodes, a source electrode, and a drain electrode formed on the second semiconductor layer; an interlayer insulation film formed on the second semiconductor layer; and a field plate formed on the interlayer insulation film. Further, the first gate electrode and the second gate electrode are formed between a region where the source electrode is formed and a region where the field plate is formed, an element isolation region is formed in the first and the second semiconductor layers which are between the first and the second gate electrodes, and the second gate electrode is electrically connected to the source electrode. | 12-04-2014 |
| 20140353674 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a buffer layer of GaN containing at least one of Fe and C and disposed on the substrate, a channel layer of GaN disposed on the buffer layer and through which electrons travel, an electron supply layer disposed on the channel layer and producing a two-dimensional electron gas in the channel layer, a gate electrode, a drain electrode, and a source electrode. Recovery time of a drain current of the semiconductor device is no more than 5 seconds, where the recovery time is defined as the period of time after the semiconductor device is stopped from outputting high frequency power until the change in the drain current, after the stopping of the semiconductor device, reaches 95% of the change in the drain current occurring during the first 10 seconds after the stopping of the semiconductor device. | 12-04-2014 |
| 20140353675 | ELECTRODE, MIS SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF ELECTRODE - An electrode used in contact with an insulator comprises a layer mainly consisting of aluminum (Al) and a titanium nitride (TiN) layer that is placed between the layer mainly consisting of aluminum (Al) and the insulator and is arranged in contact with the layer mainly consisting of aluminum (Al). A ratio of thickness of the layer mainly consisting of aluminum (Al) to thickness of the titanium nitride (TiN) layer is in a range of not less than 3.00 and not greater than 12.00. | 12-04-2014 |
| 20140353676 | LIGHT EMITTING CHIP - A light emitting chip includes a device chip having a light emitting layer on a front surface side and a transparent member bonded to a back surface side of the device chip. The transparent member is transmissive to light emitted from the light emitting layer. The transparent member is formed into a frustum shape having a first surface, a second surface that has a smaller area than the first surface, and an inclined sidewall that connects the first surface and the second surface. | 12-04-2014 |
| 20140353677 | LOW-DEFECT SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a low-defect semiconductor device and a method of manufacturing the same. The method includes forming a buffer layer on a silicon substrate, forming an interface control layer on the buffer layer under a first growth condition, and forming a nitride stack on the interface control layer under a second growth condition different from the first growth condition. | 12-04-2014 |
| 20140353678 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region. Impurities of the second conductivity type are implanted to the second electric field relaxation layers at a second surface density lower than the first surface density, widths of which becoming larger as apart from the active region. | 12-04-2014 |
| 20140353679 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Disclosed are a semiconductor device and a method of fabricating the same. A light emitting diode (LED) includes a conductive substrate, and a gallium nitride (GaN)-based semiconductor stack positioned on the conductive substrate. The semiconductor stack includes an active layer that is a semi-polar semiconductor layer. Accordingly, it is possible to provide an LED having improved light emitting efficiency. | 12-04-2014 |
| 20140353680 | Gallium Nitride Semiconductor Structures With Compositionally-Graded Transition Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 12-04-2014 |
| 20140353681 | COMPOUND SEMICONDUCTOR DEVICE - The compound semiconductor device comprises an i-GaN buffer layer | 12-04-2014 |
| 20140361307 | LIGHT EMITTING CHIP - A light emitting chip including a device chip having a transparent substrate and a light emitting layer formed on a front side of the transparent substrate, and a transparent resin layer provided on a back side of the transparent substrate. The transparent resin layer contains transparent particles for transmitting and scattering light emitted from the light emitting layer. | 12-11-2014 |
| 20140361308 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device according to one aspect of the present invention includes a step of forming a first layer of InAlN, a step of forming a second layer of InAlGaN on the first layer under a growth temperature higher than that of the first layer, and a step of forming a third layer of GaN, AlGaN or InGaN under a growth temperature higher than that of the first layer. | 12-11-2014 |
| 20140361309 | Enhancement Mode III-N HEMTs - A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate. | 12-11-2014 |
| 20140361310 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is over the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located at an interface of the first III-V compound layer and the second III-V compound layer. A dielectric cap layer is over the second III-V compound layer and a protection layer is over the dielectric cap layer. Slanted field plates are in a combined opening in the dielectric cap layer and protection layer. | 12-11-2014 |
| 20140361311 | GaN Substrate, Semiconductor Device and Method for Fabricating GaN Substrate and Semiconductor Device - A gallium nitride (GaN) substrate, a semiconductor device, and methods for fabricating a GaN substrate and a semiconductor device are provided. The GaN substrate includes: a GaN base; an aluminum gallium nitride (AlGaN) layer, disposed on the GaN base; and a p-type conducting layer disposed on an active area of the AlGaN layer, and used to exhaust surface state negative electrons on the AlGaN layer and neutralize a dangling bond on the AlGaN layer. The p-type conducting layer is formed on the AlGaN layer, and a hole charge carrier in the p-type conducting layer can be used to exhaust the surface state negative electrons on an n-type AlGaN layer, neutralize the dangling bond on a section of the AlGaN layer, and prevent the forming of a virtual gate, so as to suppress a current collapse effect of the semiconductor device fabricated using the GaN substrate. | 12-11-2014 |
| 20140361312 | SEMICONDUCTOR DEVICE - In aspects of the invention, SiC reverse blocking MOSFET includes an active region including a MOS gate structure and a breakdown voltage structure portion surrounding the outer circumference of the active region, which are provided on the surface side of a SiC-n | 12-11-2014 |
| 20140367692 | LIGHT-EMITTING DEVICE AND THE MANUFACTURING METHOD THEREOF - A light-emitting device includes: a substrate including an upper surface, wherein the upper surface includes an ion implantation region; a semiconductor layer formed on the upper surface; a light-emitting stack formed on the semiconductor layer; and a plurality of scattering cavities formed between the semiconductor layer and the upper surface in accordance with the ion implantation region. | 12-18-2014 |
| 20140367693 | LIGHT-EMITTING DEVICE AND THE MANUFACTURING METHOD THEREOF - A light-emitting device, comprising: a substrate comprising an upper surface; an ion implantation region in the substrate; a semiconductor layer formed on the upper surface; a light-emitting stack formed on the semiconductor layer; and multiple cavities formed between the semiconductor layer and the upper surface in accordance with the ion implantation region. | 12-18-2014 |
| 20140367694 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first semiconductor layer configured to be formed of a nitride semiconductor on a substrate; a second semiconductor layer configured to be formed of a nitride semiconductor on the first semiconductor layer; an insulation film configured to include an opening, and to be formed on the second semiconductor layer; a source electrode and a drain electrode configured to be formed on the second semiconductor layer; and a gate electrode configured to be formed at the opening on the second semiconductor layer. Both the insulation film and the second semiconductor layer include carbon in a neighborhood of an interface between the insulation film and the second semiconductor layer. | 12-18-2014 |
| 20140367695 | TRENCH HIGH ELECTRON MOBILITY TRANSISTOR DEVICE - A method for producing a solid state device, including forming a first dielectric layer over an epitaxial layer at least partially covering the a Silicon substrate and depositing a photoresist material thereover, removing a predetermined portion first dielectric layer to define an exposed portion, implanting dopants into the exposed portion to define a doped portion, preferentially removing Silicon from the exposed portion to generate trenches having V-shaped cross-sections and having first and second angled sidewalls defining the V-shaped cross-section, wherein each angled sidewall defining the V-shaped cross-section is a Silicon face having a 111 orientation, and forming a 2DEG on at least one sidewall. | 12-18-2014 |
| 20140367696 | FORMATION OF GROUP III-V MATERIAL LAYERS ON PATTERNED SUBSTRATES - Methods of epitaxy of gallium nitride, and other such related films, and light emitting diodes on patterned sapphire substrates, and other such related substrates, are described. | 12-18-2014 |
| 20140367697 | LIGHT-EMITTING DIODE DEVICE AND MANUFACTURING METHOD THEREOF - A light-emitting diode device and a manufacturing method thereof. The light-emitting diode device comprises: a substrate ( | 12-18-2014 |
| 20140367698 | METHOD OF CONTROLLING STRESS IN GROUP-III NITRIDE FILMS DEPOSITED ON SUBSTRATES - Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. | 12-18-2014 |
| 20140367699 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE - The method for fabricating a semiconductor device is to fabricate a semiconductor device including GaN (gallium nitride) that composes a semiconductor layer and includes a step of forming a gate insulating film. In the step, at least one film selected from the group consisting of a SiO | 12-18-2014 |
| 20140374765 | Gate Stack for Normally-Off Compound Semiconductor Transistor - A normally-off compound semiconductor transistor includes a heterostructure body and a gate stack on the heterostructure body. The heterostructure body includes a source, a drain spaced apart from the source, and a channel for connecting the source and the drain. The channel includes a first two-dimensional charge carrier gas of a first polarity arising in the heterostructure body due to piezoelectric effects. The gate stack controls the channel in a region of the heterostructure body under the gate stack. The gate stack includes at least one III-nitride material which gives rise to a second two-dimensional charge carrier gas of a second polarity opposite the first polarity in the gate stack or in the heterostructure body under the gate stack due to piezoelectric effects. The second two-dimensional charge carrier gas counter-balances polarization charges in the first two-dimensional charge carrier gas so that the channel is disrupted under the gate stack. | 12-25-2014 |
| 20140374766 | BI-DIRECTIONAL GALLIUM NITRIDE SWITCH WITH SELF-MANAGED SUBSTRATE BIAS - A semiconductor device includes a bidirectional GaN FET formed on a non-insulating substrate. The semiconductor device further includes a first electrical clamp connected between the substrate and a first source/drain node of the bidirectional GaN FET, and a second electrical clamp connected between the substrate and a second source/drain node of the bidirectional GaN FET. The first clamp and the second clamp are configured to bias the substrate at a lower voltage level of an applied bias to the first source/drain node and an applied bias to the second source/drain node, within an offset voltage of the relevant clamp. | 12-25-2014 |
| 20140374767 | LIGHT EMITTING DIODE STRUCTURE - A light emitting diode (LED) structure includes a substrate, an LED element, a reverse current protection element, a third conductor, and a fourth conductor. The LED element includes a first N-type semiconductor layer, a first lighting layer, a first P-type semiconductor layer, a first transparent conductive layer, a first electrode, and a second electrode. The reverse current protection element is located on the substrate and surrounds the LED element. The reverse current protection element includes a stack layer, a first conductor, and a second conductor. The stack layer is formed on the substrate by sequentially stacking a second N-type semiconductor layer, a second lighting layer, and a second P-type semiconductor layer. The third conductor is electrically connected to the first conductor and the second electrode. The fourth conductor is electrically connected to the second conductor and the first electrode. | 12-25-2014 |
| 20140374768 | HIGH QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON - Substrates of GaN over silicon suitable for forming electronics devices such as heterostructure field effect transistors (HFETs), and methods of making the substrates, are disclosed. Voids in a crystalline Al | 12-25-2014 |
| 20140374769 | GAN-BASED SCHOTTKY BARRIER DIODE WITH ALGAN SURFACE LAYER - A Schottky diode and method of fabricating the Schottky diode using gallium nitride (GaN) materials is disclosed. The method includes providing an n-type GaN substrate having first and second opposing surfaces. The method also includes forming an ohmic metal contact electrically coupled to the first surface, forming an n-type GaN epitaxial layer coupled to the second surface, and forming an n-type aluminum gallium nitride (AlGaN) surface layer coupled to the n-type GaN epitaxial layer. The AlGaN surface layer has a thickness which is less than a critical thickness, and the critical thickness is determined based on an aluminum mole fraction of the AlGaN surface layer. The method also includes forming a Schottky contact electrically coupled to the n-type AlGaN surface layer, where, during operation, an interface between the n-type GaN epitaxial layer and the n-type AlGaN surface layer is substantially free from a two-dimensional electron gas. | 12-25-2014 |
| 20140374770 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element having a substrate of GaAs, InP, or GaN, and an element securing member bonded to the semiconductor element by solder. The element securing member is a composite material of Cu and carbon or a composite of Al and carbon. A stem is connected to the element securing member, and a cap is secured to the stem. The cap covers the semiconductor element and the element securing member. The stem and the element securing member are made of the same material. | 12-25-2014 |
| 20140374771 | SEMICONDUCTOR MULTI-LAYER SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor multi-layer substrate includes a substrate made of Si and a multi-layer semiconductor layer. The multi-layer semiconductor layer includes an active layer made of a nitride semiconductor, a first warp control layer being formed between the substrate and the active layer and giving a predetermined warp to the substrate, and a second warp control layer made of a nitride semiconductor of which amount of an increase in a warp per a unit thickness is smaller than an amount of increase in the warp per a unit thickness of the first warp control layer. A total thickness of the multi-layer semiconductor layer is equal to or larger than 4 μm. | 12-25-2014 |
| 20140374772 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor light-emitting device, and a method of manufacturing the same. The semiconductor light-emitting device includes a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked on a substrate, a first contact that passes through the substrate to be electrically connected to the first electrode layer, and a second contact that passes through the substrate, the first electrode layer, and the insulating layer to communicate with the second electrode layer. The first electrode layer is electrically connected to the first semiconductor layer by filling a contact hole that passes through the second electrode layer, the second semiconductor layer, and the active layer, and the insulating layer surrounds an inner circumferential surface of the contact hole to insulate the first electrode layer from the second electrode layer. | 12-25-2014 |
| 20150008441 | SOLID STATE LIGHTING DEVICES WITH SELECTED THERMAL EXPANSION AND/OR SURFACE CHARACTERISTICS, AND ASSOCIATED METHODS - Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods are disclosed. A method in accordance with a particular embodiment includes forming an SSL (solid state lighting) formation structure having a formation structure coefficient of thermal expansion (CTE), selecting a first material of an interlayer structure to have a first material CTE greater than the substrate CTE, and selecting a second material of the interlayer structure based at least in part on the second material having a second material CTE less than the first material CTE. The method can further include forming the interlayer structure over the SSL formation structure by disposing (at least) a first layer of the first material over the SSL formation structure, a portion of the second material over the first material, and a second layer of the first material over the second material. The SSL formation structure supports an SSL emitter material, and the method further includes counteracting a force placed on the formation structure by the first material, by virtue of the difference between the second material CTE and the first material CTE. In other embodiments, the SSL formation structure can have an off-cut angle with a non-zero value of up to about 4.5 degrees. | 01-08-2015 |
| 20150008442 | ISOLATION STRUCTURE IN GALLIUM NITRIDE DEVICES AND INTEGRATED CIRCUITS - An integrated semiconductor device which includes a substrate layer, a buffer layer formed on the substrate layer, a gallium nitride layer formed on the buffer layer, and a barrier layer formed on the gallium nitride layer. Ohmic contacts for a plurality of transistor devices are formed on the barrier layer. Specifically, a plurality of first ohmic contacts for the first transistor device are formed on a first portion of the surface of the barrier layer, and a plurality of second ohmic contacts for the second transistor device are formed on a second portion of the surface of the barrier layer. In addition, one or more gate structures formed on a third portion of the surface of the barrier between the first and second transistor devices. Preferably, the one or more gate structures and the spaces between the gate structures and the source contacts of the transistor devices collectively form an isolation region that electrically isolates the first transistor device from the second transistor device. | 01-08-2015 |
| 20150008443 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor module including a high-side first transistor and a low-side second transistor, a first control board located above the semiconductor module, a drive element connected to a first gate terminal and a first source terminal of the first transistor on the first control board, and a drive element connected to a second gate terminal and a second source terminal of the second transistor on the first control board, a second control board located above the first control board, and photocouplers provided on the second control board. The semiconductor module includes a positive electrode terminal, a ground terminal, and an output terminal. The first gate terminal and the first source terminal are located at the side provided with the positive electrode terminal and the ground terminal. The second gate terminal and the second source terminal are located at the side provided with the output terminal. | 01-08-2015 |
| 20150008444 | Device Comprising a III-N Layer Stack With Improved Passivation Layer and Associated Manufacturing Method - A device comprising a III-N layer stack featuring a two-dimensional electron gas is disclosed, comprising: a III-N layer; a AI-III-N layer on top of the III-N layer; a passivation layer on top of said AI-III-N layer, the passivation layer comprising Silicon Nitride (SiN); wherein said passivation layer comprises a fully crystalline sub layer at the AI-III-N interface and at least part of the fully crystalline sub layer comprises Al and/or B; and associated methods for manufacturing the device. | 01-08-2015 |
| 20150008445 | III-Nitride Device and FET in a Package - One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop a III-nitride transistor, such that a drain of the PET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages. | 01-08-2015 |
| 20150014695 | CONTACTS FOR AN N-TYPE GALLIUM AND NITROGEN SUBSTRATE FOR OPTICAL DEVICES - A method for fabricating LED devices. The method includes providing a gallium and nitrogen containing substrate member (e.g., GaN) comprising a backside surface and a front side surface. The method includes subjecting the backside surface to a polishing process, causing a backside surface to be characterized by a surface roughness, subjecting the backside surface to an anisotropic etching process exposing various crystal planes to form a plurality of pyramid-like structures distributed spatially in a non-periodic manner on the backside surface, treating the backside surface comprising the plurality of pyramid-like structures, to a plasma species, and subjecting the backside surface to a surface treatment. The method further includes forming a contact material comprising an aluminum bearing species or a titanium bearing species overlying the surface-treated backside to form a plurality of LED devices with the contact material. | 01-15-2015 |
| 20150014696 | GALLIUM NITRIDE POWER SEMICONDUCTOR DEVICE HAVING A VERTICAL STRUCTURE - A semiconductor device includes a substrate having first and second sides and a first active layer disposed over the first side of the substrate. A second active layer is disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. At least one trench extends through the first and second active layers and the two-dimensional electron gas layer and into the substrate. A conductive material lines the trench. A first electrode is disposed on the second active layer and a second electrode is disposed on the second side of the substrate. | 01-15-2015 |
| 20150014697 | LIGHT EMITTING DEVICE AND METHOD FOR MAKING THE SAME - A light emitting device comprises a substrate, a semiconductor body, and a transition layer. The semiconductor body is configured to generate light and comprises an n-type layer disposed on the substrate, a p-type layer disposed on the n-type layer, and an active layer disposed between the n-type layer and the p-type layer. The transition layer is disposed on the substrate and located between the n-type layer and the substrate, and comprises a plurality of sub-layers. The plurality of the sub-layers comprise compositions different from each other, and each sub-layer comprise the composition including IIIA metal, transition metal, and nitrogen. The light emitting device further comprises a p-contact layer disposed on the p-type layer of the semiconductor body. A substrate structure and a method for making the light emitting device are also presented. | 01-15-2015 |
| 20150014698 | Integrated III-Nitride D-Mode HFET with Cascoded Pair Half Bridge - There are disclosed herein various implementations of a group III-V power conversion circuit including a monolithically integrated half bridge having a depletion mode III-Nitride field-effect transistor (FET), and a normally OFF composite cascoded switch including a depletion mode III-Nitride FET and an enhancement mode group IV FET. In one exemplary implementation, the monolithically integrated half bridge includes a high side depletion mode III-Nitride FET having an enable switch coupled in the conduction path of the high side depletion mode III-Nitride FET. | 01-15-2015 |
| 20150014699 | VERTICAL TRANSISTORS HAVING P-TYPE GALLIUM NITRIDE CURRENT BARRIER LAYERS AND METHODS OF FABRICATING THE SAME - A vertical transistor includes a drain electrode disposed on a first region of a substrate, a drift layer disposed on a second region of the substrate spaced apart from the first region, and P-type gallium nitride current barrier layers disposed on the drift layer and comprising a current aperture disposed between current barrier layers. A channel layer is disposed on the drift layer and the current barrier layers. A semiconductor layer is disposed on the channel layer and configured to induce formation of a two-dimension electron gas layer adjacent to a top surface thereof. Metal contact plugs are disposed in the channel layer and contact the current barrier layers. A source electrode is disposed on the contact plugs and the channel layer. A gate insulation layer and a gate electrode are sequentially disposed on a top surface of the semiconductor layer opposite to the channel layer. | 01-15-2015 |
| 20150014700 | VERTICAL III-NITRIDE SEMICONDUCTOR DEVICE WITH A VERTICALLY FORMED TWO DIMENSIONAL ELECTRON GAS - A HEMT device comprising a III-Nitride material substrate, the surface of which follows a plane that is not parallel to the C-plane of the III-Nitride material; an epitaxial layer of III-Nitride material grown on said substrate; a recess etched in said epitaxial layer, having at least one plane wall parallel to a polar plane of the III-Nitride material; a carrier supply layer formed on a portion of the plane wall of the recess, such that a 2DEG region is formed along the portion of the plane wall of the recess; a doped source region formed at the surface of said epitaxial layer such that the doped source region is separated from said 2DEG region by a channel region of the epitaxial layer; a gate insulating layer formed on the channel region of the epitaxial layer; and a gate contact layer formed on the gate insulating layer. | 01-15-2015 |
| 20150014701 | III-Nitride Semiconductor Device with Reduced Electric Field - A conductive field plate is formed between the drain electrode and gate of each cell of a III-Nitride semiconductor and is connected to the source electrode to reduce the electric field between the gate and the drain. The electrodes may be supported on N | 01-15-2015 |
| 20150014702 | LIGHT-EMITTING DIODE HAVING IMPROVED LIGHT EXTRACTION EFFICIENCY AND METHOD FOR MANUFACTURING SAME - Disclosed are a light-emitting diode having improved light extraction efficiency and a method for manufacturing same. This light-emitting diode includes: a gallium nitride substrate having an upper surface and a lower surface; and a gallium nitride semiconductor multilayer structure disposed on the lower surface of the substrate, and having a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. Herein, the gallium nitride substrate has a main pattern having a protruding portion and a concave portion on the upper surface, and a rough surface formed on the protruding portion of the main pattern. The light-emitting diode is capable of improving light extraction efficiency through the upper surface thereof since the rough surface is formed along with the main pattern on the upper surface of the gallium nitride substrate. | 01-15-2015 |
| 20150014703 | III-NITRIDE Device with Solderable Front Metal - Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson. | 01-15-2015 |
| 20150021614 | CONTROLLED ON AND OFF TIME SCHEME FOR MONOLITHIC CASCODED POWER TRANSISTORS - A semiconductor device includes a depletion mode GaN FET cascoded with an enhancement mode NMOS transistor. A gate of the GaN FET is electrically coupled to a source of the NMOS transistor through a gate network. The gate network controls at least one of a turn-on time and a turn-off time of the GaN FET. The gate network may be controlled by an input signal to a gate of the NMOS transistor. | 01-22-2015 |
| 20150021615 | JUNCTION BARRIER SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF - The present invention discloses a junction barrier Schottky (JBS) diode and a manufacturing method thereof. The JBS diode includes: an N-type gallium nitride (GaN) substrate; an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate; a P-type gallium nitride (GaN) layer, which is formed on or above the N-type GaN substrate; an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; and a cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer. | 01-22-2015 |
| 20150021616 | NITRIDE-BASED SEMICONDUCTOR DEVICES - A nitride-based semiconductor device includes a barrier structure on a substrate, a nitride semiconductor layer on the barrier structure, and a source electrode, a drain electrode, and a gate electrode on the nitride semiconductor layer to be separated from each other. The barrier structure includes a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity on the first semiconductor layer, a third semiconductor layer having the first conductivity on the second semiconductor layer, and a fourth semiconductor layer having the second conductivity on the third semiconductor layer. A two-dimensional electrode gas (2DEG) channel is formed in the nitride semiconductor layer. | 01-22-2015 |
| 20150021617 | SEMICONDUCTOR DEVICE - A semiconductor device includes; a semiconductor layer mainly made of GaN; a protective film provided to have electrical insulation property and configured to coat the semiconductor layer; and an electrode provided to have electrical conductivity and configured to form a Schottky junction with the semiconductor layer. Tthe protective film includes: a first layer made of Al | 01-22-2015 |
| 20150021618 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a p-type semiconductor layer mainly made of GaN; an n-type semiconductor layer mainly made of GaN and joined with the p-type semiconductor layer; a protective film arranged to coat the p-type semiconductor layer and the n-type semiconductor layer; a gate insulating film arranged to coat the p-type semiconductor layer and the n-type semiconductor layer; and a gate electrode joined with the gate insulating film. The protective film includes: a first layer made of Al | 01-22-2015 |
| 20150021619 | III-Nitride Semiconductor Device with Reduced Electric Field Between Gate and Drain - A conductive field plate is formed between the drain electrode and gate of each cell of a III-Nitride semiconductor and is connected to the source electrode to reduce the electric field between the gate and the drain. The electrodes may be supported on N | 01-22-2015 |
| 20150021620 | LIGHT EMITTING DEVICE - The light emitting device includes a first semiconductor layer, a second semiconductor layer and an active layer provided between the first semiconductor layer and the second semiconductor layer. A first light extraction layer is provided on the first semiconductor layer and includes a nitride semiconductor layer. The first light extraction layer includes a plurality of first layers. The refractive indexes of the first layers decrease with increasing distance from the first semiconductor layer. | 01-22-2015 |
| 20150021621 | SELF-ALIGNED GATE BURIED CHANNEL FIELD EFFECT TRANSISTOR - This disclosure provides a transistor device formed on a wide band gap substrate. The transistor device includes a channel layer and a gate structure physically coupled to the channel layer. The gate structure can be formed on the channel layer using an epitaxial process instead of a lithographic process, thereby providing a mechanism to build small semiconductor features that are smaller than a resolution of the state-of-the-art lithographic process and reducing the amount of impurities between the channel layer and the gate structure. | 01-22-2015 |
| 20150021622 | LIGHT-EMITTING ELEMENT AND METHOD FOR MANUFACTURING SAME - In a light emitting element, a semiconductor layer including a light emitting layer is stacked on a GaN substrate | 01-22-2015 |
| 20150028345 | TRANSISTOR HAVING METAL DIFFUSION BARRIER AND METHOD OF MAKING THE SAME - A transistor includes a substrate, a channel layer over the substrate, an active layer over the channel layer, a metal diffusion barrier over the active layer, and a gate over the metal diffusion barrier. The active layer has a band gap discontinuity with the channel layer. | 01-29-2015 |
| 20150028346 | ALUMINUM NITRIDE BASED SEMICONDUCTOR DEVICES - Semiconductor structures and techniques are described which enable forming aluminum nitride (AIN) based devices by confining carriers in a region of AIN by exploiting the polar nature of AIN materials. Embodiments of AIN transistors utilizing polarization-based carrier confinement are described. | 01-29-2015 |
| 20150028347 | LIGHT EMITTING DIODES AND ASSOCIATED METHODS OF MANUFACTURING - Light emitting diodes and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode (LED) includes a substrate, a semiconductor material carried by the substrate, and an active region proximate to the semiconductor material. The semiconductor material has a first surface proximate to the substrate and a second surface opposite the first surface. The second surface of the semiconductor material is generally non-planar, and the active region generally conforms to the non-planar second surface of the semiconductor material. | 01-29-2015 |
| 20150034957 | NORMALLY-OFF ENHANCEMENT-MODE MISFET - The present disclosure relates to an enhancement mode MISFET device. In some embodiments, the MISFET device has an electron supply layer located on top of a layer of semiconductor material. A multi-dielectric layer, having two or more stacked dielectric materials sharing an interface having negative fixed charges, is disposed above the electron supply layer. A metal gate structure is disposed above the multi-dielectric layer, such that the metal gate structure is separated from the electron supply layer by the multi-dielectric layer. The multi-dielectric layer provides fixed charges at interfaces between the separate dielectric materials, which cause the transistor device to achieve a normally off disposition. | 02-05-2015 |
| 20150034958 | HEMT-COMPATIBLE LATERAL RECTIFIER STRUCTURE - The present disclosure relates to a high electron mobility transistor compatible power lateral field-effect rectifier device. In some embodiments, the rectifier device has an electron supply layer located over a layer of semiconductor material at a position between an anode terminal and a cathode terminal. A layer of doped III-N semiconductor material is disposed over the electron supply layer. A layer of gate isolation material is located over the layer of doped III-N semiconductor material. A gate structure is disposed over layer of gate isolation material, such that the gate structure is separated from the electron supply layer by the layer of gate isolation material and the layer of doped III-N semiconductor material. The layer of doped III-N semiconductor material modulates the threshold voltage of the rectifier device, while the layer of gate isolation material provides a barrier that gives the rectifier device a low leakage. | 02-05-2015 |
| 20150034959 | PATTERNED SUBSTRATE AND LIGHT EMITTING DIODE STRUCTURE HAVING THE SAME - A light emitting diode structure includes a patterned substrate, an N-type semiconductor layer, a light emitting layer, and a P-type semiconductor layer. Plural protruding portions are formed on a surface of the substrate. A horizontal projection of each of the protruding portions on the surface of the substrate has a projection width W | 02-05-2015 |
| 20150034960 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided as a semiconductor device manufacturing method that permits an opening to be formed in a good shape in a resist film. This manufacturing method is a semiconductor device manufacturing method having: a step of forming an insulating film | 02-05-2015 |
| 20150034961 | AlN SINGLE CRYSTAL SCHOTTKY BARRIER DIODE AND METHOD OF PRODUCING THE SAME - An AlN single crystal Schottky barrier diode including: an AlN single crystal substrate having a defect density of 10 | 02-05-2015 |
| 20150034962 | INTEGRATED CIRCUIT WITH MATCHING THRESHOLD VOLTAGES AND METHOD FOR MAKING SAME - An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess. | 02-05-2015 |
| 20150034963 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element in which changes in light distribution characteristics due to inclination angle of side surfaces are suppressed. The semiconductor light emitting element includes a semiconductor structure having a light extracting surface as its upper surface; a reflecting layer disposed on side surfaces of the semiconductor structure; and a positive electrode and a negative electrode disposed on a lower surface of the semiconductor structure. Side surfaces of the semiconductor structure are inclined, expanding upward from the lower surface to the upper surface. At least a portion of each side surface includes a plurality of protrusions, a plurality of recesses, or a combination thereof. | 02-05-2015 |
| 20150034964 | GALLIUM NITRIDE-BASED DIODE AND METHOD OF FABRICATING THE SAME - A GaN-based diode may include an intrinsic GaN-based semiconductor layer, GaN-based semiconductor layers configured to have a first conductivity type and bonded to the intrinsic GaN-based semiconductor layer. A first electrode made of metal is placed on a surface opposite a surface bonded to the GaN-based semiconductor layers of the intrinsic GaN-based semiconductor layer; a second electrode is placed on a surface opposite to a surface bonded to the intrinsic GaN-based semiconductor layer of the GaN-based semiconductor layers of the first conductivity type. Voltage-resistant layers configured to have a second conductivity type are formed in regions of the intrinsic GaN-based semiconductor layer that come in contact with edges of the first electrode. | 02-05-2015 |
| 20150034965 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING SAME - An LED includes a substrate and a semiconductor structure mounted on the substrate. A plurality of first holes and a plurality of second holes are defined in the semiconductor structure. The second holes are located above the first holes and communicate with the first holes. A method for manufacturing the LED is also provided. | 02-05-2015 |
| 20150034966 | NITRIDE-BASED FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME - Disclosed herein is a GaN-based transistor. The GaN-based transistor includes source electrodes, first switching semiconductor layers of a first conductivity type formed under the respective source electrodes, second switching semiconductor layers of a second conductivity type formed under the respective first switching semiconductor layers, and third switching semiconductor layers of the first conductivity type surrounding lower parts of the second switching semiconductor layers and sides of the first switching semiconductor layers and the second switching semiconductor layers. Gates are formed each having vertical faces or inclined faces in which a channel is formed on sides of the first switching semiconductor layer and the second switching semiconductor layer. Gate insulating layers are formed under the gates, and a drain electrode electrically is coupled to the source electrodes along a flow of charges in a vertical direction that passes through the channels. | 02-05-2015 |
| 20150034967 | SEMICONDUCTOR DEVICE - A semiconductor device including a high resistance layer formed on a substrate, the high resistance layer being formed with a semiconductor material doped with as impurity element that makes the semiconductor material highly resistant; a multilayer intermediate layer formed on the high resistance layer; an electron transit layer formed with a semiconductor material on the multilayer intermediate layer; and an electron supply layer formed with a semiconductor material on the electron transit layer, wherein the multilayer intermediate layer is formed with a multilayer film in which a GaN layer and an AlN layer are alternately laminated. | 02-05-2015 |
| 20150034968 | PHOTOELECTRIC CONVERSION ELEMENT, PHOTOELECTRIC CONVERSION SYSTEM, AND METHOD FOR PRODUCTION OF PHOTOELECTRIC CONVERSION ELEMENT - A photoelectric conversion element of an embodiment is a photoelectric conversion element which performs photoelectric conversion by receiving illumination light having n light emission peaks having a peak energy Ap (eV) (where 1≦p≦n and 2≦n) of 1.59≦Ap≦3.26 and a full width at half maximum Fp (eV) (where 1≦p≦n and 2≦n), wherein the photoelectric conversion element includes m photoelectric conversion layers having a band gap energy Bq (eV) (where 1≦q≦m and 2≦m≦n), and the m photoelectric conversion layers each satisfy the relationship of Ap−Fp| 02-05-2015 | |
| 20150041820 | COMPLEMENTARY GALLIUM NITRIDE INTEGRATED CIRCUITS AND METHODS OF THEIR FABRICATION - An embodiment of a complementary GaN integrated circuit includes a GaN layer with a first bandgap. A second layer with a second bandgap is formed on the GaN layer, resulting in a 2DEG in a contact region between the GaN layer and the second layer. The second layer has a relatively thin portion and a relatively thick portion. A third layer is formed over the relatively thick portion of the second layer. The third layer has a third bandgap that is different from the second bandgap, resulting in a 2DHG in a contact region between the second layer and the third layer. A transistor of a first conductivity type includes the 2DHG, the relatively thick portion of the second layer, and the third layer, and a transistor of a second conductivity type includes the 2DEG and the relatively thin portion of the second layer. | 02-12-2015 |
| 20150041821 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An electrode comes in ohmic contact with an AlGaN layer. A semiconductor device SD has a nitride semiconductor layer GN | 02-12-2015 |
| 20150041822 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a substrate, a reflective layer and a light emitting structure. The reflective layer includes at least two porous layers alternately disposed on the substrate and having different porosities. The light emitting structure is disposed on the reflective layer and includes a first conductivity-type semiconductor layer, an active layer and a second conductivity-type semiconductor layer. | 02-12-2015 |
| 20150041823 | LED DIE AND METHOD OF MANUFACTURING THE SAME - An LED die includes a substrate, a first buffer layer, a second buffer layer, a plurality of nanospheres, a first semiconductor layer, an active layer and a second semiconductor layer. The first buffer layer, the second buffer layer, the first semiconductor layer, the active layer and the second semiconductor layer are formed successively on the substrate. The substrate has a plurality of protrusions formed on a surface thereof. The nanospheres are located on the first buffer layer formed on the protrusions and covered by the second buffer layer. The present disclosure also provides a method of manufacturing an LED die. | 02-12-2015 |
| 20150048378 | IMAGE PICKUP ELEMENT AND IMAGE PICKUP DEVICE - Provided is an image pickup element that includes a photoelectric conversion section provided on a semiconductor substrate and including a chalcopyrite-based compound. The photoelectric conversion section has a band gap that is relatively wide on a light incident surface side. | 02-19-2015 |
| 20150048379 | Light Emitting Diode and Manufacturing Method Therefor - Disclosed are a light emitting diode having an n-doped ohm contact buffer layer and a manufacturing method therefor. In the present invention, a highly n-doped ohm contact buffer layer with an electronic concentration up to 1×10 | 02-19-2015 |
| 20150048380 | OPTICAL SUBSTRATE, SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING ELEMENT - In an optical substrate ( | 02-19-2015 |
| 20150048381 | METHOD FOR THE REUSE OF GALLIUM NITRIDE EPITAXIAL SUBSTRATES - A method for the reuse of gallium nitride (GaN) epitaxial substrates uses band-gap-selective photoelectrochemical (PEC) etching to remove one or more epitaxial layers from bulk or free-standing GaN substrates without damaging the substrate, allowing the substrate to be reused for further growth of additional epitaxial layers. The method facilitates a significant cost reduction in device production by permitting the reuse of expensive bulk or free-standing GaN substrates. | 02-19-2015 |
| 20150053990 | TRANSISTOR HAVING AN OHMIC CONTACT BY SCREEN LAYER AND METHOD OF MAKING THE SAME - A transistor includes a substrate, a channel layer over the substrate and an active layer over the channel layer. The active layer includes a first portion and a screen layer over the first portion. The transistor includes a metal layer over the screen layer. | 02-26-2015 |
| 20150053991 | TRANSISTOR HAVING AN OHMIC CONTACT BY GRADIENT LAYER AND METHOD OF MAKING THE SAME - A transistor includes a substrate, a channel layer over the substrate and an active layer over the channel layer. The active layer includes a gradient having a first concentration of a first material at an interface with the channel layer and a second concentration of the first material at a surface opposite the channel layer, and the first concentration is higher than the second concentration. | 02-26-2015 |
| 20150053992 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, a gate structure over the active layer, and a barrier layer between the gate structure and the active layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The gate structure is configured to deplete the 2DEG under the gate structure. The gate structure includes a dopant. The barrier layer is configured to block diffusion of the dopant from the gate structure into the active layer. | 02-26-2015 |
| 20150053993 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light-emitting device includes a substrate, a semiconductor light-emitting element, and a transparent resin. The substrate is configured to have an opening portion. The opening portion includes a lower portion and an upper portion narrower than the lower portion. The semiconductor light-emitting element is placed in a central portion of the substrate. The transparent resin covers the semiconductor light-emitting element and is provided to the opening portion. | 02-26-2015 |
| 20150053994 | DIODE CIRCUIT AND DC TO DC CONVERTER - A diode circuit includes a switching element having a first terminal and a second terminal. The switching element includes a control electrode for controlling electrical conductance between the first and second terminals. A diode has a cathode electrode connected to the first terminal of the switching element and an anode electrode connected to the control electrode of the switching element. An impedance element is connected in parallel to the diode. The switching element and the diode each comprise a gallium nitride-based semiconductor component. The switching element and the diode may optionally be disposed on the same semiconductor substrate. The diode circuit may optionally be included in a direct current to direct current converter device or other devices. | 02-26-2015 |
| 20150053995 | HORIZONTAL POWER LED DEVICE AND METHOD FOR MANUFACTURING SAME - The present invention relates to a horizontal LED device and a method of manufacturing the same. More particularly, the present invention relates to a high-power and high-efficiency horizontal LED device manufactured using the advantages of conventional horizontal and vertical LEDs, and a method of manufacturing the same. | 02-26-2015 |
| 20150053996 | LAYERED SUBSTRATE WITH A MISCUT ANGLE COMPRISING A SILICON SINGLE CRYSTAL SUBSTRATE AND A GROUP-III NITRIDE SINGLE CRYSTAL LAYER - A step-flow growth of a group-III nitride single crystal on a silicon single crystal substrate is promoted. A layer of oxide oriented to a <111> axis of silicon single crystal is formed on a surface of a silicon single crystal substrate, and group-III nitride single crystal is crystallized on a surface of the layer of oxide. Thereupon, a <0001> axis of the group-III nitride single crystal undergoing crystal growth is oriented to a c-axis of the oxide. When the silicon single crystal substrate is provided with a miscut angle, step-flow growth of the group-III nitride single crystal occurs. By deoxidizing a silicon oxide layer formed at an interface of the silicon single crystal and the oxide, orientation of the oxide is improved. | 02-26-2015 |
| 20150053997 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A compound semiconductor device and method of fabricating the same according to the present invention is disclosed. The compound semiconductor device comprises a substrate having at least a first doped region and at least a second doped region, and a semiconductor layer disposed on the substrate, wherein doping conditions of said first doped region and said second doped region may be different from each other. | 02-26-2015 |
| 20150060872 | Encapsulated Semiconductor Device - A semiconductor device includes a carrier and a semiconductor chip disposed over the carrier. The semiconductor chip has a first surface and a second surface opposite to the first surface, wherein the second surface faces the carrier. Further, the semiconductor device includes a pre-encapsulant covering at least partially the second surface of the semiconductor chip and at least partially a side wall surface of the semiconductor chip. The pre-encapsulant has a thermal conductivity of equal to or greater than 10 W/(m·K) and a specific heat capacity of equal to or greater than 0.2 J/(g·K). | 03-05-2015 |
| 20150060873 | Crystalline Layer for Passivation of III-N Surface - Some embodiments of the present disclosure relates to a crystalline passivation layer for effectively passivating III-N surfaces. Surface passivation of HEMTs reduces or eliminates the surface effects that can otherwise degrade device performance. The crystalline passivation layer reduces the degrading effects of surface traps and provides a good interface between a III-nitride surface and an insulator (e.g., gate dielectric formed over the passivation layer). | 03-05-2015 |
| 20150060874 | FLEXIBLE ELECTRIC DEVICE AND METHOD OF MANUFACTURING THE SAME - A flexible electric device includes a first electrode on a flexible member, at least one semiconductor element on the first electrode, at least one filling region adjacent to the semiconductor element and a second electrode on the semiconductor element. | 03-05-2015 |
| 20150060875 | SEMICONDUCTOR DEVICE - To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×10 | 03-05-2015 |
| 20150060876 | POLARIZATION INDUCED DOPED TRANSISTOR - A nitride-based field effect transistor (FET) comprises a compositionally graded and polarization induced doped p-layer underlying at least one gate contact and a compositionally graded and doped n-channel underlying a source contact. The n-channel is converted from the p-layer to the n-channel by ion implementation, a buffer underlies the doped p-layer and the re-channel, and a drain underlies the buffer. | 03-05-2015 |
| 20150060877 | OPTOELECTRONIC SEMICONDUCTOR DEVICE WITH BARRIER LAYER - An optoelectronic semiconductor device comprises a barrier layer, a first semiconductor layer on the barrier layer, the first semiconductor layer comprising a first dopant and a second dopant, and a second semiconductor layer beneath the barrier layer, the second semiconductor comprising the second dopant, wherein, in the first semiconductor layer, a concentration of the first dopant is larger than a concentration of the second dopant, and the concentration of the second dopant in the second semiconductor layer is larger than that in the first semiconductor layer. | 03-05-2015 |
| 20150060878 | Semiconductor Packages Having Multiple Lead Frames and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads. | 03-05-2015 |
| 20150060879 | GaN-Based LED - A GaN-based LED includes a substrate; an epitaxial layer over the substrate; a current spreading layer over a P-type layer; and a P electrode over the current spreading layer. The epitaxial layer includes the P-type layer, a light-emitting area, and an N-type layer. An annular reflecting layer and a metal reflecting layer are formed between the P electrode and the epitaxial layer. The geometric center vertically corresponds to the P electrode; the annular reflecting layer is formed between the current spreading layer and the P-type layer; the metal reflecting layer is formed between the current spreading layer and the P electrode; and a preset distance is arranged between the annular reflecting layer and the metal reflecting layer. The annular reflecting layer and the metal reflecting layer reduce light absorption of the P electrode and improve light extraction efficiency. | 03-05-2015 |
| 20150060880 | GaN-Based LED - A GaN-based LED includes: a substrate with front and back sides; an epitaxial layer formed over the front side of the substrate and including, from top down, a P-type layer, a light-emitting area, and an N-type layer; a current spreading layer formed over the P-type layer; a P electrode formed over the current spreading layer; a first reflecting layer between the current spreading layer and the epitaxial layer, disposed at a peripheral area of the epitaxial layer in a band-shaped distribution; and a second reflecting layer over the back side the substrate. The band-shaped or annular distribution can increase a probability light extraction of the LED sideways. By controlling the ratio of lights extracted upwards and sideways, the light-emitting distribution evenness can be adjusted and the uneven heat dissipation can be improved. | 03-05-2015 |
| 20150069404 | SEMICONDUCTOR DEVICE - A semiconductor device includes an active layer, at least one source electrode, at least one drain electrode, at least one gate electrode, a first insulating layer, a first source pad, a first drain pad, at least one source plug, and at least one drain plug. The source electrode and the drain electrode are both disposed on the active layer. Projections of the source electrode and the drain electrode on the active layer form a source region and a drain region, respectively. The first source pad and the first drain pad are both disposed on the first insulating layer. A projection of the first source pad on the active layer forms a source pad region. An area of an overlapping region between the source pad region and the drain region is smaller than or equal to 40% of an area of the drain region. | 03-12-2015 |
| 20150069405 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to one embodiment includes an n-type first GaN-based semiconductor layer, a p-type second GaN-based semiconductor layer on the first GaN-based semiconductor layer. The second GaN-based semiconductor layer includes a low impurity concentration region and a high impurity concentration region. An n-type third GaN-based semiconductor layer is provided on the second GaN-based semiconductor layer. The device includes a gate electrode being located adjacent to the third GaN-based semiconductor layer, the low impurity concentration region, and the first GaN-based semiconductor layer intervening a gate insulating film. The device includes a first electrode on the third GaN-based semiconductor layer, a second electrode on the high impurity concentration region, and a third electrode on the opposite side of the first GaN-based semiconductor layer from the second GaN-based semiconductor layer. | 03-12-2015 |
| 20150069406 | LIGHT EMITTING DIODE STRUCTURE - A light emitting diode structure comprising a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, a current resisting layer, a current spreading layer, a first electrode and a second electrode is provided. The first semiconductor layer is formed on the substrate. The active layer covers a portion of the first semiconductor layer, and exposes another portion of the first semiconductor layer. The second semiconductor layer is formed on the active layer. The current resisting layer covers a portion of the second semiconductor layer, and exposes another portion of the second semiconductor layer. The current spreading layer covers the second semiconductor layer and the current resisting layer. The current spreading layer is formed with a reverse trapezoidal concave over the current resisting layer. The first electrode is disposed on the first semiconductor layer. The second electrode is disposed within the reverse trapezoidal concave. | 03-12-2015 |
| 20150069407 | GROUP III NITRIDE SEMICONDUCTOR MULTILAYER SUBSTRATE AND GROUP III NITRIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR - A group III nitride semiconductor multilayer substrate ( | 03-12-2015 |
| 20150069408 | HETEROJUNCTION FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A laminate includes a surface on which a gate electrode is provided, and is made of a nitride semiconductor. The laminate includes a first layer having a first band gap, and a second layer provided between the first layer and the surface and having a second band gap which is larger than the first band gap. The first and second layers and form a joint surface by a hetero junction. The surface includes a surface defect density equal to or smaller than 1.7×10 | 03-12-2015 |
| 20150069409 | HETEROSTRUCTURE WITH CARRIER CONCENTRATION ENHANCED BY SINGLE CRYSTAL REO INDUCED STRAINS - A heterostructure grown on a silicon substrate includes a single crystal rare earth oxide template positioned on a silicon substrate, the template being substantially crystal lattice matched to the surface of the silicon substrate. A heterostructure is positioned on the template and defines at least one heterojunction at an interface between a III-N layer and a III-III-N layer. The template and the heterostructure are crystal matched to induce an engineered predetermined tensile strain at the at least one heterojunction. A single crystal rare earth oxide dielectric layer is grown on the heterostructure so as to induce an engineered predetermined compressive stress in the single crystal rare earth oxide dielectric layer and a tensile strain in the III-III-N layer. The tensile strain in the III-III-N layer and the compressive stress in the REO layer combining to induce a piezoelectric field leading to higher carrier concentration in 2DEG at the heterojunction. | 03-12-2015 |
| 20150069410 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, SCHOTTKY BARRIER DIODE, AND FIELD EFFECT TRANSISTOR - A semiconductor device includes: a base; an electron transit layer layered on the base; an electron-supplying layer being configured by layering a plurality of AlN layers and GaN layers alternately on the electron transit layer and having an average Al composition x; an etching sacrificial layer layered on the electron-supplying layer and made of Al | 03-12-2015 |
| 20150076505 | PATTERNED OPTO-ELECTRICAL SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a patterned opto-electrical substrate, comprising a substrate, the substrate has a first patterned structure, a spacer region and a second patterned structure, wherein the second patterned structure is formed on one or both of the first patterned structure and the spacer region, and the first patterned structure is a micron-scale protruding structure or a micron-scale recessing structure, while the second patterned structure is a submicron-scale recessing structure. The present invention also relates to a method for manufacturing the aforementioned patterned opto-electrical substrate and light emitting diodes having the aforementioned patterned opto-electrical substrate. | 03-19-2015 |
| 20150076506 | SEMICONDUCTOR DEVICE - This disclosure provides a semiconductor device which includes a GaN-based semiconductor layer having a surface with an angle of not less than 0 degree and not more than 5 degrees with respect to an m-plane or an a-plane, a first electrode provided above the surface and having a first end, and a second electrode provided above the surface to space apart from the first electrode, having a second end facing the first end, and a direction of a segment connecting an arbitrary point of the first end and an arbitrary point of the second end is different from a c-axis direction of the GaN-based semiconductor layer. | 03-19-2015 |
| 20150076507 | EPITAXY SUBSTRATE, METHOD FOR PRODUCING AN EPITAXY SUBSTRATE AND OPTOELECTRONIC SEMICONDUCTOR CHIP COMPRISING AN EPITAXY SUBSTRATE - An epitaxy substrate ( | 03-19-2015 |
| 20150076508 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a first semiconductor layer of a first GaN based semiconductor, a second semiconductor layer of a second GaN based semiconductor having a band gap narrower than the first GaN based semiconductor, a third semiconductor layer of a third GaN based semiconductor having a band gap wider than the second GaN based semiconductor, a fourth semiconductor layer of a fourth GaN based semiconductor having a band gap narrower than the third GaN based semiconductor, a fifth semiconductor layer of a fifth GaN based semiconductor having a band gap wider than the fourth GaN based semiconductor, a gate dielectric provided directly on the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer, a gate electrode provided on the gate dielectric, a source and drain electrodes provided above the fifth semiconductor layer. | 03-19-2015 |
| 20150076509 | SEMICONDUCTOR DEVICE WITH BUFFER LAYER MADE OF NITRIDE SEMICONDUCTOR - A semiconductor device includes a buffer layer made of nitride semiconductor on a substrate, a first semiconductor layer made of nitride semiconductor on the buffer layer, a second semiconductor layer made of nitride semiconductor on the first semiconductor layer, and a gate electrode, a source electrode, and a drain electrode formed on the second semiconductor layer, wherein the buffer layer has elements doped therein that include both an element selected from a group consisting of C, Mg, Fe, and Co and an element selected from a group consisting of Si, Ge, Sn, and O. | 03-19-2015 |
| 20150076510 | Heterostructure Power Transistor with AlSiN Passivation Layer - A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts. | 03-19-2015 |
| 20150076511 | SEMICONDUCTOR DEVICE - A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In | 03-19-2015 |
| 20150076512 | SEMICONDUCTOR SUBSTRATE AND METHOD OF FORMING - A method of forming a semiconductive substrate material for an electronic device including forming a plurality of semiconductive layers on a substrate during a continuous growth process in a reaction chamber, wherein during the continuous growth process, a release layer is formed between a base layer and an epitaxial layer by altering at least one growth process parameter during the continuous growth process. The method also including separating the plurality of semiconductive layers from the substrate. | 03-19-2015 |
| 20150076513 | Field Effect Transistor with Conduction Band Electron Channel and Uni-Terminal Response - A uni-terminal transistor device is described. In one embodiment, an n-channel transistor comprises a first semiconductor layer having a discrete hole level H | 03-19-2015 |
| 20150084057 | METHOD AND STRUCTURE FOR REDUCING THE PROPAGATION OF CRACKS IN EPITAXIAL FILMS FORMED ON SEMICONDUCTOR WAFERS - A method for reducing the effects of cracks in an epitaxial film. The method includes; providing a semiconductor wafer with an epitaxial film thereon; inspecting the epitaxial film to determine outer peripheral edge regions of the epitaxial film having cracks therein; and selectively removing the determined outer peripheral edge regions of the epitaxial film while leaving portions of the semiconductor wafer underlying the removed determined outer peripheral regions of the epitaxial film. | 03-26-2015 |
| 20150084058 | LIGHT EMITTING DEVICE GROWN ON A SILICON SUBSTRATE - A method according embodiments of the invention includes growing a semiconductor structure on a substrate including silicon. The semiconductor substrate includes an aluminum-containing layer in direct contact with the substrate, and a III-nitride light emitting layer disposed between an n-type region and a p-type region. The method further includes removing the substrate. After removing the substrate, a transparent material is formed in direct contact with the aluminum-containing layer. The transparent material is textured. | 03-26-2015 |
| 20150084059 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes a first GaN based semiconductor layer of a first conductive type, a second GaN based semiconductor layer of the first conductive type provided above the first GaN based semiconductor layer, a third GaN based semiconductor layer of a second conductive type provided above a part of the second GaN based semiconductor layer, a epitaxially grown fourth GaN based semiconductor layer of the first conductive type provided above the third GaN based semiconductor layer, a gate insulating film provided on the second, third, and fourth GaN based semiconductor layer, a gate electrode provided on the gate insulating film, a first electrode provided on the fourth GaN based semiconductor layer, a second electrode provided at the side of the first GaN based semiconductor layer opposite to the second GaN based semiconductor layer, and a third electrode provided on the second GaN based semiconductor layer. | 03-26-2015 |
| 20150084060 | INSULATED GATE BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF - The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel. | 03-26-2015 |
| 20150084061 | SEMICONDUCTOR PHOTO-DETECTING DEVICE - A photo-detecting device includes a first nitride layer, a low-current blocking layer disposed on the first nitride layer, a light absorption layer disposed on the low-current blocking layer, and a Schottky junction layer disposed on the light-absorption layer. The low-current blocking layer includes a multilayer structure. | 03-26-2015 |
| 20150097193 | ROOM TEMPERATURE TUNNELING SWITCHES AND METHODS OF MAKING AND USING THE SAME - The tunneling channel of a field effect transistor comprising a plurality of tunneling elements contacting a channel substrate. Applying a source-drain voltage of greater than a turn-on voltage produces a source-drain current of greater than about 10 pA. Applying a source-drain voltage of less than a turn-on voltage produces a source-drain current of less than about 10 pA. The turn-on voltage at room temperature is between about 0.1V and about 40V. | 04-09-2015 |
| 20150097194 | ENHANCED DEVICE AND MANUFACTURING METHOD THEREFOR - An enhancement-mode device comprises: a substrate, an epitaxial multilayer structure formed on the substrate, and a gate region formed on the epitaxial multilayer structure, where the epitaxial multilayer structure sequentially comprises from the substrate: a nucleation layer, a buffer layer, a heterojunction structure layer, a second gallium nitride layer, a nitride transition layer and a dielectric layer, where the heterojunction structure layer comprises a gallium nitride channel layer and a barrier layer which has a sandwich structure, and a middle layer of the sandwich structure is a first gallium nitride layer; and the gate region comprises a gate metal layer and a p-type nitride layer located under the gate metal layer, wherein the p-type nitride layer is embedded into the epitaxial multilayer structure, a bottom of the p-type nitride layer is in contact with the first gallium nitride layer of the sandwich structure. | 04-09-2015 |
| 20150097195 | Light Emitting Device - A light emitting device includes a double-sided electrode type semiconductor light emitting element that has a first electrode formed on a front side of the double-sided type semiconductor light emitting element and a second electrode formed on a rear side of the double sided type semiconductor light emitting element and is configured to emit light from a side wall surface of the double-sided electrode type semiconductor light emitting element, a first lead frame that is bonded to a whole area of one face of the first electrode, a second lead frame that is bonded to a whole area of one face of the second electrode, and a case in which a portion of the first lead frame and a portion of the second lead frame is embedded, | 04-09-2015 |
| 20150097196 | Integrated Device Including Silicon and III-Nitride Semiconductor Devices - A semiconductor device that includes one semiconductor device formed in one semiconductor material and a second semiconductor device formed in another semiconductor material on a common substrate, and a method of fabricating the semiconductor device. | 04-09-2015 |
| 20150102357 | GaN-containing semiconductor structure - A method for forming a GaN-containing semiconductor structure is provided. The method comprises a substrate is provided, a nucleation layer is formed above the substrate, a diffusion blocking layer is formed above the nucleation layer, a strain relief layer is formed above the diffusion blocking layer, and a semiconductor layer is formed above the strain relief layer, in which the diffusion blocking layer is deposited on the nucleation layer such that the diffusion blocking layer can prevent the impurities out-diffusion from the substrate. | 04-16-2015 |
| 20150102358 | NITRIDE SEMICONDUCTOR MULTILAYER STRUCTURE, SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR MULTILAYER STRUCTURE - A nitride semiconductor multilayer structure includes a sapphire substrate having an m-plane principal surface with an off-angle φ, and a mask layer including first and second side surface portions that sandwich each exposed region. In a cross section parallel to the m- and c-axes, points at which the first and second side surface portions meet the principal surface are respectively points A and B, a point at which the first side surface portion intersects a line passing through point B and forming an angle of 58°−φ with the principal surface is C, a distance between a line passing through point C and perpendicular to the principal surface and a line passing through point B and perpendicular to the principal surface is W, and a height of the first side surface portion is H. Then H≧W·tan(58°−φ)). | 04-16-2015 |
| 20150102359 | INTEGRATING ACTIVE MATRIX INORGANIC LIGHT EMITTING DIODES FOR DISPLAY DEVICES - A method of forming an active matrix, light emitting diode (LED) array includes removing, from a base substrate, a layer of inorganic LED material originally grown thereupon; and bonding the removed layer of inorganic LED material to an active matrix, thin film transistor (TFT) backplane array. | 04-16-2015 |
| 20150102360 | BONDABLE TOP METAL CONTACTS FOR GALLIUM NITRIDE POWER DEVICES - An embodiment of a semiconductor device includes a gallium nitride (GaN) substrate having a first surface and a second surface. The second surface is substantially opposite the first surface, at least one device layer is coupled to the first surface, and a backside metal is coupled to the second surface. A top metal stack is coupled to the at least one device layer. The top metal stack includes a contact metal coupled to a surface of the at least one device layer, a protection layer coupled to the contact metal, a diffusion barrier coupled to the protection layer, and a pad metal coupled to the diffusion barrier. The semiconductor device is configured to conduct electricity between the top metal stack and the backside metal. | 04-16-2015 |
| 20150108491 | LIGHT EMITTING DIODE PACKAGE - A light emitting diode package includes a lead frame, a light emitting diode chip, a wavelength conversion structure, and a filter. The light emitting diode chip is disposed on and electrically connected to the lead frame for providing a first light beam with a first wavelength. The light emitting diode chip is configured to provide a first light beam with a first wavelength. The wavelength conversion structure is disposed on the light emitting diode chip, and is configured to convert the first light beam into a second light beam with a second wavelength. The filter is disposed between the light emitting diode chip and the wavelength conversion structure. The filter allows the first light beam from the light emitting diode chip to pass therethrough to enter the wavelength conversion structure, and reflects the second light beam from the wavelength conversion structure back to the wavelength conversion structure. | 04-23-2015 |
| 20150108492 | LIGHT-EMITTING DIODE - A light-emitting diode (LED), including a first semiconductor layer defining several light-emitting regions and non-light-emitting regions; an active layer and a second semiconductor layer sequentially formed over the first semiconductor layer in the light-emitting regions; a transparent conductive layer formed over the second semiconductor layer; a Bragg reflector structure formed over the transparent conductive layer and including several first via holes; a metal layer formed over the Bragg reflector structure and connected to the transparent conductive layer through the first via holes; a passivation layer covering the metal layer and including several second via holes; several third via holes exposing the first semiconductor layer in the non-light-emitting regions; several first electrodes filling the third via holes and connected to the first semiconductor layer; and several second electrodes filling the second via holes and connected to the metal layer. | 04-23-2015 |
| 20150108493 | SILICON CARBIDE EPITAXIAL WAFER, AND PREPARATION METHOD THEREOF - According to an embodiment, there is provided a method of fabricating an epitaxial wafer, which includes preparing a wafer in a susceptor; and growing an epitaxial layer on the wafer, wherein the growing of the epitaxial layer on the wafer includes supplying a raw material into the susceptor; growing the epitaxial layer on the wafer at a first growth rate; and growing the epitaxial layer on the wafer at a second growth rate higher than the first growth rate. According to an embodiment, there is provided a silicon carbide epitaxial wafer which includes a silicon carbide wafer; and a silicon carbide epitaxial layer on the silicon carbide wafer wherein a surface defect formed on the silicon carbide epitaxial layer is 1 ea/cm | 04-23-2015 |
| 20150108494 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a light-emitting device and manufacturing method thereof. The light-emitting device comprising: a light-emitting stack; and a semiconductor layer having a first surface connecting to the light-emitting stack, a second surface opposite to the first surface, and a void; wherein the void comprises a bottom part near the first surface and an opening on the second surface, and a dimension of the bottom part is larger than the dimension of the opening. | 04-23-2015 |
| 20150108495 | Gallium Nitride Devices with Discontinuously Graded Transition Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 04-23-2015 |
| 20150108496 | GROUP III-N TRANSISTOR ON NANOSCALE TEMPLATE STRUCTURES - A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin. | 04-23-2015 |
| 20150108497 | LIGHT-EMITTING DEVICE HAVING LIGHT-EMITTING ELEMENTS - A light-emitting device including a substrate, a first electrode pad and a second electrode pad disposed on the substrate and spaced apart each other, and at least two arrays connected in parallel between the first and the second electrode pads. The at least two arrays include a first array and a second array, each of the at least two arrays include GaN-based light-emitting elements connected in series, the first electrode pad and the second electrode pad are disposed on a non-light-emitting first region of the substrate spaced apart from a light-emitting second region of the substrate, and the first electrode pad and the second electrode pad surround at least a portion of outer edges comprising a circumference of the at least two arrays. | 04-23-2015 |
| 20150108498 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a semiconductor light emitting device includes a first nitride semiconductor layer, a nitride semiconductor light emitting layer, a second nitride semiconductor layer, a p-side electrode, and an n-side electrode. The nitride semiconductor light emitting layer is provided on the p-side region of the second face of the first nitride semiconductor layer. The second nitride semiconductor layer is provided on the nitride semiconductor light emitting layer. The p-side electrode is provided on the second nitride semiconductor layer. The n-side electrode is provided on the n-side region of the second face of the first nitride semiconductor layer. The nitride semiconductor light emitting layer has a first concave-convex face in a side of the first nitride semiconductor layer, and a second concave-convex face in a side of the second nitride semiconductor layer. | 04-23-2015 |
| 20150115276 | LIGHT-EMITTING DIODE - The disclosure provides a light-emitting diode which includes a first semiconductor layer, a light-emitting layer, a second semiconductor layer, a reflective layer, a current blocking layer and a current spreading layer. The light-emitting layer is positioned on the first semiconductor layer, and the second semiconductor layer is positioned on the light-emitting layer. The reflective layer is positioned on a part of the second semiconductor layer, so as to expose another part of the second semiconductor layer. The current blocking layer covers the reflective layer, and the current spreading layer covers the exposed second semiconductor layer and current blocking layer. | 04-30-2015 |
| 20150115277 | Episubstrates for Selective Area Growth of Group III-V Material and a Method for Fabricating a Group III-V Material on a Silicon Substrate - The embodiments disclose a silicon substrate with a group III-V material and a method for fabricating a group III-V material on a silicon substrate. The method involves providing a silicon substrate. A first layer formed atop the silicon substrate, is subsequently patterned to expose the underlying silicon substrate. A group III-V material layer is formed over the patterned first layer and also on the exposed silicon substrate. The group III-V material layer is subjected to chemical mechanical polishing (CMP) to expose the first layer resulting in the formation of a plurality of areas suitable for growing a device layer on the silicon substrate. | 04-30-2015 |
| 20150115278 | LIGHT EMITTING DEVICE, AND METHOD FOR MANUFACTURING THEREOF - Provided is a light emitting device comprising an optical member provided on a light extracting surface side of a semiconductor light emitting element via a first light transmissive layer, wherein bonding surfaces of the semiconductor light emitting element and the first light transmissive layer are roughened surfaces, bonding surfaces of the first light transmissive layer and the optical member are flat, and the first light transmissive layer and the optical member are directly bonded. | 04-30-2015 |
| 20150115279 | METHOD FOR CONTROLLING CONCENTRATION OF DONOR IN GA2O3-BASED SINGLE CRYSTAL - A β-Ga2O3-based single crystal, including a first region that has side and bottom surfaces and is controlled so as to have a first donor concentration; and a second region that surrounds the side and bottom surfaces of the first region and is controlled so as to have a second donor concentration lower than the first donor concentration. | 04-30-2015 |
| 20150115280 | METHODS OF GROWING NITRIDE SEMICONDUCTORS AND METHODS OF MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATES - Methods of growing nitride semiconductor layers including forming nitride semiconductor dots on a substrate and growing a nitride semiconductor layer on the nitride semiconductor dots. The nitride semiconductor layer may be separated from the substrate to be used as a nitride semiconductor substrate. | 04-30-2015 |
| 20150115281 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor light-emitting device, and a method of manufacturing the same. The semiconductor light-emitting device includes a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked on a substrate, a first contact that passes through the substrate to be electrically connected to the first electrode layer, and a second contact that passes through the substrate, the first electrode layer, and the insulating layer to communicate with the second electrode layer. The first electrode layer is electrically connected to the first semiconductor layer by filling a contact hole that passes through the second electrode layer, the second semiconductor layer, and the active layer, and the insulating layer surrounds an inner circumferential surface of the contact hole to insulate the first electrode layer from the second electrode layer. | 04-30-2015 |
| 20150123138 | HIGH POWER GALLIUM NITRIDE ELECTRONICS USING MISCUT SUBSTRATES - An electronic device includes a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The electronic device also includes a first epitaxial layer coupled to the III-V substrate and a second epitaxial layer coupled to the first epitaxial layer. The electronic device further includes a first contact in electrical contact with the substrate and a second contact in electrical contact with the second epitaxial layer. | 05-07-2015 |
| 20150123139 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - Provided are a high electron mobility transistor and/or a method of manufacturing the same. The high electron mobility transistor includes a channel layer, a channel supply layer formed on the channel layer to generate a two-dimensional electron gas (2DEG), a depletion forming layer formed on the channel supply layer, a gate electrode formed on the depletion forming layer, and a barrier layer formed between the depletion forming layer and the gate electrode. Holes may be prevented from being injected into the depletion forming layer from the gate electrode, thereby reducing a gate forward current. | 05-07-2015 |
| 20150123140 | SEMIPOLAR NITRIDE SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - Provided are a semipolar nitride semiconductor structure and a method of manufacturing the same. The semipolar nitride semiconductor structure includes a silicon substrate having an Si(11k) surface satisfying 7≦k≦13; and a nitride semiconductor layer formed on the silicon substrate. The nitride semiconductor layer has a semipolar characteristic in which a polarization field is approximately 0. | 05-07-2015 |
| 20150123141 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a third electrode, a first insulating film and a second insulating film. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer is provided on the first layer, includes a nitride semiconductor, and includes a hole. The first electrode is provided in the hole. The second electrode is provided on the second layer. The third electrode is provided on the second layer so that the first electrode is disposed between the third and second electrodes. The first insulating film is provided between the first electrode and an inner wall of the hole and between the first and second electrodes, and is provided spaced from the third electrode. The second insulating film is provided in contact with the second layer between the first and third electrodes. | 05-07-2015 |
| 20150123142 | POWER SEMICONDUCTOR DEVICE INCLUDING A COOLING MATERIAL - A power semiconductor device includes a wiring structure adjoining at least one side of a semiconductor body and comprising at least one electrically conductive compound. The power semiconductor device further includes a cooling material in the wiring structure. The cooling material is characterized by a change in structure by means of absorption of energy at a temperature T | 05-07-2015 |
| 20150123143 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device of an embodiment includes a semiconductor layer formed of a III-V group nitride semiconductor, a first silicon nitride film formed on the semiconductor layer, a gate electrode formed on the first silicon nitride film, a source electrode and a drain electrode formed on the semiconductor layer such that the gate electrode is interposed between the source electrode and the drain electrode, and a second silicon nitride film formed between the source electrode and the gate electrode and between the drain electrode and the gate electrode and having an oxygen atom density lower than that of the first silicon nitride film. | 05-07-2015 |
| 20150123144 | Semiconductor Structures and Methods with High Mobility and High Energy Bandgap Materials - An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin. | 05-07-2015 |
| 20150129886 | GALLIUM NITRIDE FIELD EFFECT TRANSISTOR WITH BURIED FIELD PLATE PROTECTED LATERAL CHANNEL - A method for fabricating a lateral gallium nitride (GaN) field-effect transistor includes forming a first and second GaN layer coupled to a substrate, removing a first portion of the second GaN layer to expose a portion of the first GaN layer, and forming a third GaN layer coupled to the second GaN layer and the exposed portion of the first GaN layer. The method also includes removing a portion of the third GaN layer to expose a portion of the second GaN layer, forming a source structure coupled to the third GaN layer. A first portion of the second GaN layer is disposed between the source structure and the second GaN layer. A drain structure is formed that is coupled to the third GaN layer or alternatively to the substrate. The method also includes forming a gate structure coupled to the third GaN layer such that a second portion of the third GaN layer is disposed between the gate structure and the second GaN layer. | 05-14-2015 |
| 20150129887 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a substrate; nitride semiconductor layers disposed over the substrate; a source electrode and a drain electrode disposed over the nitride semiconductor layers; a first insulating layer disposed over the nitride semiconductor layers, the source electrode and the drain electrode; a second insulating layer disposed over the first insulating layer; a first opening disposed in the second insulating layer and the first insulating layer and between the source electrode and the drain electrode, a portion of the nitride semiconductor layer being exposed in the first opening; a second opening disposed in the second insulating layer and between the source electrode and the drain electrode, a portion of the first insulating layer being exposed in the second opening; and a gate electrode disposed over the second insulating layer to bury the first opening and at least a portion of the second opening. | 05-14-2015 |
| 20150129888 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a first nitride semiconductor layer formed over a substrate; a second nitride semiconductor layer formed over the first nitride semiconductor layer; element isolation regions formed in a part of the second nitride semiconductor layer and the first nitride semiconductor layer; a gate electrode, source electrodes, and a drain electrode formed over the second semiconductor layer and the element isolation regions; and a drain field plate formed in such a manner as to project from upper portions of side surfaces of the drain electrode. | 05-14-2015 |
| 20150129889 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SUBSTRATE - A semiconductor device is provided, which includes a barrier layer | 05-14-2015 |
| 20150129890 | TRANSISTOR - A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate. | 05-14-2015 |
| 20150137134 | METHOD AND SYSTEM FOR INTERLEAVED BOOST CONVERTER WITH CO-PACKAGED GALLIUM NITRIDE POWER DEVICES - An electronic package includes a leadframe and a plurality of pins. The electronic package also includes a first gallium nitride (GaN) transistor comprising a source, gate, and drain and a second GaN transistor comprising a source, gate, and drain. The source of the first GaN transistor is electrically connected to the leadframe and the drain of the second GaN transistor is electrically connected to the leadframe. The electronic package further includes a first GaN diode comprising an anode and cathode and a second GaN diode comprising an anode and cathode. The anode of the first GaN diode is electrically connected to the leadframe and the anode of the second GaN diode is electrically connected to the leadframe. | 05-21-2015 |
| 20150137135 | SEMICONDUCTOR DEVICES WITH INTEGRATED SCHOTKY DIODES AND METHODS OF FABRICATION - An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and a Schottky metal layer disposed over the substrate adjacent the gate electrode. The Schottky metal layer includes a Schottky contact electrically coupled to the channel which provides a Schottky junction and at least one alignment mark disposed over the semiconductor substrate. A method for fabricating the semiconductor device includes creating an isolation region that defines an active region along an upper surface of a semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and forming a Schottky metal layer over the semiconductor substrate. Forming the Schottky metal layer includes forming at least one Schottky contact electrically coupled to the channel and providing a Schottky junction, and forming an alignment mark in the isolation region. | 05-21-2015 |
| 20150137136 | GALLIUM NITRIDE SEMICONDUCTOR SUBSTRATE WITH SEMICONDUCTOR FILM FORMED THEREIN - A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more signal crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis. Each predetermined plane is inclined to the predetermined axis. Each substrate has a minor polished primary surface. The primary surface has a first area and a second area. The first area is between an edge of the substrate and a line 3 millimeter away from the edge. The first area surrounds the second area. An axis perpendicular to the primary surface forms an off-angle with c-axis of the substrate. The off-angle takes a minimum value at a first position in the first area of the primary surface. | 05-21-2015 |
| 20150137137 | CURRENT APERTURE VERTICAL ELECTRON TRANSISTORS WITH AMMONIA MOLECULAR BEAM EPITAXY GROWN P-TYPE GALLIUM NITRIDE AS A CURRENT BLOCKING LAYER - A current aperture vertical electron transistor (CAVET) with ammonia (NH | 05-21-2015 |
| 20150137138 | TRANSISTOR AND METHOD FOR PRODUCING TRANSISTOR - A transistor that offers a high dielectric breakdown voltage of a gate insulating film with limited reduction of the current flowing between drain and source electrodes. The transistor has a semiconductor layer, a gate insulating film on the semiconductor layer, a gate electrode on the gate insulating film, and a source electrode and a drain electrode disposed on the semiconductor layer with the gate electrode therebetween. The concentration of the impurities contained in the gate insulating film is on a downward gradient starting at the surface of the gate insulating film on the semiconductor layer side and ending at the surface of the gate insulating film on the gate electrode side. | 05-21-2015 |
| 20150137139 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. In one embodiment, the semiconductor device includes two different semiconductor materials. The two semiconductor materials are arranged adjacent one another in a common plane. | 05-21-2015 |
| 20150137140 | VERTICAL GALLIUM NITRIDE JFET WITH GATE AND SOURCE ELECTRODES ON REGROWN GATE - A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure. | 05-21-2015 |
| 20150137141 | Gallium Nitride Devices - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. | 05-21-2015 |
| 20150144953 | TRANSISTORS WITH FIELD PLATES RESISTANT TO FIELD PLATE MATERIAL MIGRATION AND METHODS OF THEIR FABRICATION - An embodiment of a transistor includes a semiconductor substrate, spaced-apart source and drain electrodes coupled to the semiconductor substrate, a gate electrode coupled to the semiconductor substrate between the source and drain electrodes, a dielectric layer over the gate electrode and at least a portion of the semiconductor substrate, and a field plate structure over the dielectric layer, wherein the field plate structure includes a gold-containing material and one or more migration inhibiting materials. | 05-28-2015 |
| 20150144954 | METHOD FOR HETEROEPITAXIAL GROWTH OF III METAL-FACE POLARITY III-NITRIDES ON SUBSTRATES WITH DIAMOND CRYSTAL STRUCTURE AND III-NITRIDE SEMICONDUCTORS - The present invention discloses a method of heteroepitaxial growth enabling the successful growth of thin films of GaN and III-nitride semiconductor heterostructures of (0001) orientation with III metal-face polarity on diamond substrates being either polycrystalline or single crystal with various crystallographic orientations. The method uses a thin AlN nucleation layer on the diamond substrate with thickness equal or less than 5 nm, grown by Molecular Beam Epitaxy (MBE) using a nitrogen plasma source. The invention enables the development of very high power metal-face III-nitride devices, such as High Electron Mobility Transistors, on single crystal or polycrystalline diamond substrates. The method is also applicable for other element IV substrates with diamond crystal structure. | 05-28-2015 |
| 20150144955 | Isolated Gate Field Effect Transistor and Manufacture Method Thereof - An isolated gate field effect transistor and the manufacture method thereof. The isolated gate field effect transistor includes a substrate; a nitride transistor structure arranged on the substrate; a dielectric layer on the nitride transistor structure, where the dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer and material of the second dielectric layer includes metal; a groove formed in a gate region and at least partially through the dielectric layer; a metal gate formed in the groove; and a source electrode and a drain electrode located at two ohmic contact regions. | 05-28-2015 |
| 20150144956 | GALLIUM NITRIDE SELF-SUPPORTED SUBSTRATE, LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREFOR - Provided is a self-supporting gallium nitride substrate useful as an alternative material for a gallium nitride single crystal substrate, which is inexpensive and also suitable for having a large area. This substrate is composed of a plate composed of gallium nitride-based single crystal grains, wherein the plate has a single crystal structure in the approximately normal direction. This substrate can be manufactured by a method comprising providing an oriented polycrystalline sintered body; forming a seed crystal layer composed of gallium nitride on the sintered body so that the seed crystal layer has crystal orientation mostly in conformity with the crystal orientation of the sintered body; forming a layer with a thickness of 20 μm or greater composed of gallium nitride-based crystals on the seed crystal layer so that the layer has crystal orientation mostly in conformity with crystal orientation of the seed crystal layer; and removing the sintered body. | 05-28-2015 |
| 20150144957 | ELECTRIC FIELD MANAGEMENT FOR A GROUP III-NITRIDE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a first active layer, a second active layer, at least first and second electrodes, an E-field management layer, and at least one injection electrode. The first active layer is disposed over the substrate. The second active layer is disposed on the first active layer such that a laterally extending conductive channel arises which extends in a lateral direction. The laterally extending conductive channel is located between the first active layer and the second active layer. The first and second electrodes are electrically connected to the first active layer. The E-field management layer, which reduces the electric-field gradients arising in the first and second active layers, is disposed over the second active layer. The injection electrode is electrically connected to the E-field management layer. | 05-28-2015 |
| 20150144958 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING III-V SEMICONDUCTOR MATERIAL USING SUBSTRATES COMPRISING MOLYBDENUM, AND STRUCTURES FORMED BY SUCH METHODS - Methods of fabricating semiconductor structures include the formation of molybdenum nitride at one or more surfaces of a substrate comprising molybdenum, and providing a layer of III-V semiconductor material, such as GaN, over the substrate. Semiconductor structures formed by methods described herein may include a substrate comprising molybdenum, molybdenum nitride at one or more surfaces of the substrate, and a layer of GaN bonded to the molybdenum nitride. | 05-28-2015 |
| 20150144959 | LIGHT-EMITTING DEVICE - Disclosed is a light-emitting device ( | 05-28-2015 |
| 20150294857 | COMPOSITE SUBSTRATE, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - The invention provides a composite substrate, a semiconductor device including such composite substrate, and a method of making the same. In particular, the composite substrate of the invention includes a nitride-based single crystal layer transformed from a nitride-based poly-crystal layer, which has a specific thickness of approximately between 2 nm and 100 nm. | 10-15-2015 |
| 20150294919 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device which can improve its reliability and a method for manufacturing the same are provided. A semiconductor device ( | 10-15-2015 |
| 20150294921 | SEMICONDUCTOR DEVICES WITH A THERMALLY CONDUCTIVE LAYER AND METHODS OF THEIR FABRICATION - An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel. | 10-15-2015 |
| 20150295051 | SEMICONDUCTOR DEVICE - A semiconductor device ( | 10-15-2015 |
| 20150295052 | SUBSTRATE ARRANGEMENT - A substrate arrangement comprising a substrate having a surface configured to receive, by epitaxy, an epitaxial layer of semiconducting material, the substrate comprising a laminate having a handle layer and a seed layer, the seed layer having a crystal orientation arranged to receive the epitaxial layer and the handle layer having a crystal orientation different to the seed layer. | 10-15-2015 |
| 20150295073 | SWITCHING DEVICE - A switching device provided herewith includes first to fourth semiconductor layers and a gate electrode. The second semiconductor layer is of a first conductive type or an un-dope type and located on the first semiconductor layer. A hetero junction is formed between the first and the second semiconductor layers. The third semiconductor layer is of a second conductive type and located on the second semiconductor layer. The fourth semiconductor layer is of a second conductive type and located on the third semiconductor layer. A hetero junction is formed between the third and the fourth semiconductor layers. The gate electrode electrically connected to the fourth semiconductor layer. | 10-15-2015 |
| 20150295075 | High Speed Gallium Nitride Transistor Devices - A low leakage current switch device ( | 10-15-2015 |
| 20150295096 | Semiconductor Device And Manufacturing Method Thereof - A technique of suppressing leak current in a semiconductor device is provided. A semiconductor device, comprises: a semiconductor layer made of a semiconductor; an insulating layer configured to have electric insulation property and formed to cover part of the semiconductor layer; a first electrode layer formed on the semiconductor layer, configured to have a work function of not less than 0.5 eV relative to electron affinity of the semiconductor layer and extended to surface of the insulating layer to form a field plate structure; and a second electrode layer configured to have electrical conductivity and formed to cover at least part of the first electrode layer. A distance between an edge of a part of the first electrode layer that is in contact with the semiconductor layer and the second electrode layer is equal to or greater than 0.2 μm. | 10-15-2015 |
| 20150295127 | Composite Substrate - A composite substrate configured for epitaxial growth of a semiconductor layer thereon is provided. The composite substrate includes multiple substrate layers formed of different materials having different thermal expansion coefficients. The thermal expansion coefficient of the material of the semiconductor layer can be between the thermal coefficients of the substrate layer materials. The composite substrate can have a composite thermal expansion coefficient configured to reduce an amount of tensile stress within the semiconductor layer at room temperature and/or an operating temperature for a device fabricated using the heterostructure. | 10-15-2015 |
| 20150295131 | SEMICONDUCTOR OPTICAL DEVICE AND ITS MANUFACTURE - The semiconductor optical device has a chip of semiconductor lamination having a first semiconductor layer of a first conductivity type having a first surface, a second semiconductor layer of a second conductivity type opposite to the first conductivity type having a second surface, and an active layer sandwiched between the first semiconductor layer and the second semiconductor layer, the chip having side surface including a first side surface which is contiguous to the second surface, forms an obtuse angle with the second surface, extends across the second semiconductor layer and the active layer, and enters the first semiconductor layer, and a cracked surface which is contiguous to the first side surface, a first conductivity type side electrode formed on the first surface, and a second conductivity type side electrode formed on the second surface, wherein in-plane size of the semiconductor lamination is 50 μm or less. | 10-15-2015 |
| 20150295132 | EPITAXIAL LAYER WAFER HAVING VOID FOR SEPARATING GROWTH SUBSTRATE THEREFROM AND SEMICONDUCTOR DEVICE FABRICATED USING THE SAME - An epitaxial wafer includes a growth substrate, a mask pattern disposed on the growth substrate and comprising a masking region and an opening region, and an epitaxial layer covering the mask pattern and including a first void disposed on the masking region. The first void includes a lower void disposed between a lower surface of the epitaxial layer and the masking region, and an upper void extending from the lower void into the epitaxial layer, the lower void having a greater width than the upper void. | 10-15-2015 |
| 20150303058 | CVD SILICON MONOLAYER FORMATION METHOD AND GATE OXIDE ALD FORMATION ON III-V MATERIALS - Methods for depositing silicon include cycling dosing between 1 and 100 cycles of one or more first chlorosilane precursors on a III-V surface at a temperature between 300° C. and 500° C. to form a first layer. Methods may include desorbing chlorine from the first layer by treating the first layer with atomic hydrogen to form a second layer. Methods may include forming a silicon multilayer on the second layer by cycling dosing between 1 and 100 cycles of one or more second chlorosilane precursors and atomic hydrogen at a temperature between 300° C. and 500° C. A layered composition includes a first layer selected from the group consisting of In | 10-22-2015 |
| 20150303066 | Substrates Including Gallium Nitride Layers and a Method of Producing the Same - In a substrate having a gallium nitride layer, surface damage after surface treatment of the gallium nitride layer is reduced and quality of a functional device formed thereon is improved. A substrate | 10-22-2015 |
| 20150303251 | BONDED EPITAXIAL OXIDE STRUCTURES FOR COMPOUND SEMICONDUCTOR ON SILICON SUBSTRATES - A structure includes a handle substrate and an epitaxial oxide layer. The epitaxial oxide layer is bonded directly or indirectly to the handle substrate. Also included is a compound semiconductor layer adjoining and lattice matched to the epitaxial oxide layer. | 10-22-2015 |
| 20150303291 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer made of a nitride semiconductor and formed on a substrate, a second semiconductor layer made of a material including InAlN and formed on the first semiconductor layer, an insulator layer formed by an oxidized surface part of the second semiconductor layer, a gate electrode formed on the insulator layer, and a source electrode and a drain electrode respectively formed on the first or second semiconductor layer. | 10-22-2015 |
| 20150303292 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a substrate; a buffer layer formed on the substrate; a laminated body formed by two or more cycles of semiconductor layers each including a first nitride semiconductor layer, and a second nitride semiconductor layer having a larger band gap than a band gap of the first nitride semiconductor layer, the first and second nitride semiconductor layers being laminated in this order on the buffer layer; a first electrode; and a second electrode. A channel layer is formed in each of the semiconductor layers at an interface between the first nitride semiconductor layer and the second nitride semiconductor layer. A carrier concentration of the channel layer in the uppermost semiconductor layer is lower than a carrier concentration of each of the channel layers of the other semiconductor layers. | 10-22-2015 |
| 20150303293 | FIELD-EFFECT TRANSISTOR - A field-effect transistor includes a codoped layer made of Al | 10-22-2015 |
| 20150311329 | FIELD EFFECT TRANSISTOR - Provided is a field-effect transistor (FET) that achieves compatibility between a higher current density and lower contact resistance and exhibits excellent properties, and a method for producing the FET. The FET includes: a channel layer above a substrate; an InAlN layer above the channel layer; an In | 10-29-2015 |
| 20150311330 | FET TRANSISTOR ON A III-V MATERIAL STRUCTURE WITH SUBSTRATE TRANSFER - A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material. | 10-29-2015 |
| 20150311331 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device of the present invention has a source-electrode-side insulator protection film layer disposed between a source electrode and a drain electrode on a second nitride semiconductor layer and formed at least partially covering the source electrode, a drain-electrode-side insulator protection film layer disposed separately from the source-electrode-side insulator protection film layer and formed at least partially covering the drain electrode, and a gate layer formed in contact with the second nitride semiconductor layer between the source-electrode-side insulator protection film layer and the drain-electrode-side insulator protection film layer and made of a p-type metal oxide semiconductor, and the gate layer has regions opposite to the second nitride semiconductor layer across each of the source-electrode-side insulator protection film layer and the drain-electrode-side insulator protection film layer and a region in contact with the second nitride semiconductor layer. | 10-29-2015 |
| 20150311332 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a substrate having a rear side on which a grounded electrode is disposed; a semiconductor layer disposed on a front side of the substrate and including an active region and an inactive region; a plurality of source electrodes disposed in the active region; a drain electrode including a plurality of first portions disposed in the active region and a second portion disposed in the inactive region; a gate electrode including a plurality of first portions disposed in the active region and a second portion disposed in the inactive region; and a plurality of source electrode pads having the same number as the plurality of source electrodes and disposed in the inactive region and each being connected to a corresponding source electrode directly. A plurality of through holes electrically connecting the plurality of source electrodes and the grounded electrode respectively are disposed in the plurality of source electrode pads. | 10-29-2015 |
| 20150311333 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device may form a nitride semiconductor layer on a substrate, form a first insulator layer on the nitride semiconductor layer by steam oxidation of ALD, form a second insulator layer on the first insulator layer by oxygen plasma oxidation of ALD, form a gate electrode on the second insulator layer, and form a source and drain electrodes on the nitride semiconductor layer. The nitride semiconductor layer may include a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer. | 10-29-2015 |
| 20150311381 | Multi-Color Light Emitting Devices with Compositionally Graded Cladding Group III-Nitride Layers Grown on Substrates - A light emitting device includes a substrate, multiple n-type layers, and multiple p-type layers. The n-type layers and the p-type layers each include a group III nitride alloy. At least one of the n-type layers is a compositionally graded n-type group III nitride, and at least one of the p-type layers is a compositionally graded p-type group III nitride. A first ohmic contact for injecting current is formed on the substrate, and a second ohmic contact is formed on a surface of at least one of the p-type layers. Utilizing the disclosed structure and methods, a device capable of emitting light over a wide spectrum may be made without the use of phosphor materials. | 10-29-2015 |
| 20150311397 | Zinc Stannate Ohmic Contacts for P-Type Gallium Nitride - Transparent ohmic contacts to p-GaN and other high-work-function (≧4.2 eV) semiconductors are fabricated from zinc stannate (e.g., ZnSnO | 10-29-2015 |
| 20150318272 | Semiconductor Device Including a Phase Change Material - A semiconductor device includes a transistor having a plurality of transistor cells in a semiconductor body. Each transistor cell includes a control terminal and first and second load terminals. The transistor further includes a phase change material exhibiting a solid-solid phase change at a phase transition temperature T | 11-05-2015 |
| 20150318353 | GALLIUM NITRIDE POWER DEVICES USING ISLAND TOPOGRAPHY - A semiconductor device in provided having a substrate and a semiconductor layer formed on a main surface of the substrate. A plurality of first island electrodes and a plurality of second island electrodes are placed over the semiconductor layer. The plurality of first island electrodes and second island electrodes are spaced apart from each other so as to be alternatively arranged to produce two-dimensional active regions in all feasible areas of the semiconductor layer. Each side of the first island electrodes is opposite a side of the second island electrodes. The semiconductor device can also include a plurality of strip electrodes that are formed in the regions between the first island electrodes and the second island electrodes. The strip electrodes serve as the gate electrodes of a multi-island transistor. The first island electrodes serve as the source electrodes of the multi-island transistor. The second island electrodes serve as the drain electrodes of the multi-island transistor. A plurality of connections to the gate electrodes are provided at each interstice defined by corners of the first island electrodes and the second island electrodes. | 11-05-2015 |
| 20150318374 | ENHANCEMENT MODE III-NITRIDE DEVICE AND METHOD FOR MANUFACTURING THEREOF - Enhancement mode III-nitride HEMT and method for manufacturing an enhancement mode III-nitride HEMT are disclosed. In one aspect, the method includes providing a substrate having a stack of layers on the substrate, each layer including a III-nitride material, and a passivation layer having high temperature silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the HT silicon nitride is formed by MOCVD or LPCVD or any equivalent technique at a temperature higher than about 450° C. The method also includes forming a recessed gate region by removing the passivation layer only in the gate region, thereby exposing the underlying upper layer. The method also includes forming a p-doped GaN layer at least in the recessed gate region, thereby filling at least partially the recessed gate region, and forming a gate contact and source/drain contacts. | 11-05-2015 |
| 20150318387 | Sidewall Passivation for HEMT Devices - Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material. | 11-05-2015 |
| 20150318388 | DEVICES, SYSTEMS, AND METHODS RELATED TO REMOVING PARASITIC CONDUCTION IN SEMICONDUCTOR DEVICES - Semiconductor devices and methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stack of semiconductor materials from an epitaxial substrate, where the stack of semiconductor materials defines a heterojunction, and where the stack of semiconductor materials and the epitaxial substrate further define a bulk region that includes a portion of the semiconductor stack adjacent the epitaxial substrate. The method further includes attaching the stack of semiconductor materials to a carrier, where the carrier is configured to provide a signal path to the heterojunction. The method also includes exposing the bulk region by removing the epitaxial substrate. | 11-05-2015 |
| 20150318441 | P-TYPE DOPING LAYERS FOR USE WITH LIGHT EMITTING DEVICES - A light emitting diode (LED) comprises an n-type Group III-V semiconductor layer, an active layer adjacent to the n-type Group III-V semiconductor layer, and a p-type Group III-V semiconductor layer adjacent to the active layer. The active layer includes one or more V-pits. A portion of the p-type Group III-V semiconductor layer is in the V-pits. A p-type dopant injection layer provided during the formation of the p-type Group III-V layer aids in providing a predetermined concentration, distribution and/or uniformity of the p-type dopant in the V-pits. | 11-05-2015 |
| 20150318443 | LED CHIP RESISTANT TO ELECTROSTATIC DISCHARGE AND LED PACKAGE INCLUDING THE SAME - A light emitting diode chip and a light emitting diode package including the same. The light emitting diode chip includes a substrate, a light emitting diode section disposed on the substrate, an inverse parallel diode section disposed on the substrate and connected inversely parallel to the light emitting diode section. In the light emitting diode chip, the light emitting diode section is disposed together with the inverse parallel diode section. | 11-05-2015 |
| 20150318446 | Low-Temperature Fabrication of Transparent Conductive Contacts for p-GaN and n-GaN - A ternary transparent conductive oxide, indium zinc oxide (IZO), is formed as a thin film by co-sputtering zinc oxide with indium oxide at a deposition temperature between 25 and 200 C. Optionally, up to 1-2% Al may be added by various methods. The layers may be annealed at temperatures between 200 and 400 C. Measurements of IZO with 75-85 wt % In | 11-05-2015 |
| 20150318449 | A hermetically sealed optoelectronic component - This invention provides inexpensively hermetically packaged optoelectronic chips. Multiple similar or dissimilar optoelectronic chips can be produced according to the present methods. Additionally, the chips may include a heat sink for efficient thermal management and elements for wavelength conversion without compromising their efficiency or quality. Furthermore, optical structures are provided to allow optimization of optical performance. | 11-05-2015 |
| 20150325658 | THIN FILM STRUCTURE AND METHOD OF FABRICATING THE SAME - Provided are a thin film structure capable of remarkably reducing the defect density of gallium nitride (GaN), and a method of fabricating the same. The thin film structure includes a supporting substrate including sapphire, and an epilayer disposed on the supporting substrate and including gallium nitride (GaN). An upper part of the supporting substrate facing the epilayer includes a layer of sapphire into which silicon (Si) is diffused or ion-implanted through a top surface of the supporting substrate. | 11-12-2015 |
| 20150325689 | III-V TRANSISTOR AND METHOD FOR MANUFACTURING SAME - Disclosed are a group III-V based transistor and a method for manufacturing same. The group III-V based transistor includes a laminated semiconductor structure having an upper surface and a lower surface and including a group III-V based semiconductor layer, and at least one 2DEG region extending from the upper surface of the laminated semiconductor structure to the lower surface thereof. A vertical-type GaN-based transistor using 2DEG can be provided by adopting the 2DEG region. | 11-12-2015 |
| 20150325741 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - A nitride semiconductor light emitting device is provided with a substrate having depression and projection, a base layer, and a structure of a stack of layers of nitride semiconductor at least having a light emitting layer sequentially. A cavity is provided in the base layer over a projection included in the depression and projection. | 11-12-2015 |
| 20150325746 | METHODS AND APPARATUS FOR IMPROVING MICRO-LED DEVICES - A μLED device comprising: a substrate and an epitaxial layer grown on the substrate and comprising a semiconductor material, wherein at least a portion of the substrate and the epitaxial layer define a mesa; an active layer within the mesa and configured, on application of an electrical current, to generate light for emission through a light emitting surface of the substrate opposite the mesa, wherein the crystal lattice structure of the substrate and the epitaxial layer is arranged such that a c-plane of the crystal lattice structure is misaligned with respect to the light emitting surface. | 11-12-2015 |
| 20150325764 | LED chip-on-board component and lighting module - An object of the present invention is to provide a Light Emitting Diode (LED) lamp construction comprising at least one light emitter component, a primary heat sink, and a secondary heat sink. The primary heat sink is in direct contact with the light emitter component and the primary heat sink is electrically insulated from the environment. Significant advantage is obtained by having a primary heat sink in direct contact with a light emitter component, such as a light emitting diode, and simultaneously electrically insulated from the environment. Direct contact between the die or diode and the primary heat sink allows for the most efficient heat transfer, thus more effectively cooling the element. This effect is particularly effective when the primary heat sink is a good thermal and even good electrical conductor. This direct contact between an electrical component such as the light emitting element and a good thermal and electrical conductor such as the primary heat sink is made possible by the electrically insulated nature of the primary heat sink. Thus, shorts are able to be eliminated and an effective heat dissipating construction is made possible. | 11-12-2015 |
| 20150332914 | SEMICONDUCTOR SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE - A semiconductor substrate according to embodiments includes a silicon substrate, a silicon nitride layer on the silicon substrate, the silicon nitride layer having a thickness of 1 nm or thicker, single-crystal aluminum nitride layer on the silicon nitride layer, and a single-crystal layer on the aluminum nitride layer, the single-crystal layer containing gallium (Ga). | 11-19-2015 |
| 20150332918 | SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SAME - Provided is a semiconductor substrate including a growth substrate, one or more compound semiconductor layers disposed on the growth substrate, and one or more control layers disposed between the compound semiconductor layers. Each control layer includes multiple nitride semiconductor layers including at least Al. | 11-19-2015 |
| 20150333141 | A HIGH ELECTRON MOBILITY DEVICE BASED ON THE GATE-FIRST PROCESS AND THE PRODUCTION METHOD THEREOF - The present disclosure belongs to the technical field of radio frequency power devices, and more specifically, to a high electron mobility device based on the gate-first process and the production method thereof. The high electro mobility device is made by adopting the gate-first process according to the present disclosure, wherein gate dielectric sidewalls are utilized to implement the self-alignment of the gate and source; besides, the source and drain of the device can be formed directly by use of the alloying process, the iron implanting process or epitaxy process after formation of the gate since the gate is protected by the passivating layer, featuring a simple technological process while reducing parameter shift of products and enhancing the electrical properties of high electron mobility devices. | 11-19-2015 |
| 20150333165 | Enhancement Mode III-Nitride Transistor - According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge. | 11-19-2015 |
| 20150333166 | Semiconductor Device and Method - A semiconductor device includes a first compound semiconductor material including a first doping concentration and a second compound semiconductor material on the first compound semiconductor material, the second compound semiconductor material including a different material than the first compound semiconductor material. The semiconductor device further includes a control electrode and at least one buried semiconductor material region including a second doping concentration different from the first doping concentration. The at least one buried semiconductor material region is disposed in the first compound semiconductor material in a region other than a region of the first compound semiconductor material being covered by the control electrode. | 11-19-2015 |
| 20150333220 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a silicon substrate, a buffer layer, a nitride-based epitaxial structure layer and multiple discontinuous strain-releasing layers. The buffer layer is disposed on the silicon substrate. The nitride-based epitaxial structure layer is disposed on the buffer layer. The discontinuous strain-releasing layers are disposed between the silicon substrate and the nitride-based epitaxial structure layer, wherein a material of the discontinuous strain-releasing layers is silicon nitride. | 11-19-2015 |
| 20150340230 | III NITRIDE EPITAXIAL SUBSTRATE AND METHOD OF PRODUCING THE SAME - A III nitride epitaxial substrate with reduced warp after the formation of a main laminate and improved vertical breakdown voltage, and a method of producing the same, a III nitride epitaxial substrate includes: a Si substrate; an initial layer in contact with the Si substrate; and a superlattice laminate formed on the initial layer, the superlattice laminate including first layers made of Al | 11-26-2015 |
| 20150340271 | GAN POWER DEVICE WITH SOLDERABLE BACK METAL - A method for fabricating a vertical gallium nitride (GaN) power device can include providing a GaN substrate with a top surface and a bottom surface, forming a device layer coupled to the top surface of the GaN substrate, and forming a metal contact on a top surface of the vertical GaN power device. The method can further include forming a backside metal by forming an adhesion layer coupled to the bottom surface of the GaN substrate, forming a diffusion barrier coupled to the adhesion layer, and forming a protection layer coupled to the diffusion barrier. The vertical GaN power device can be configured to conduct electricity between the metal contact and the backside metal. | 11-26-2015 |
| 20150340449 | GALLIUM NITRIDE FIELD EFFECT TRANSISTOR WITH BURIED FIELD PLATE PROTECTED LATERAL CHANNEL - A method for fabricating a lateral gallium nitride (GaN) field-effect transistor includes forming a first and second GaN layer coupled to a substrate, removing a first portion of the second GaN layer to expose a portion of the first GaN layer, and forming a third GaN layer coupled to the second GaN layer and the exposed portion of the first GaN layer. The method also includes removing a portion of the third GaN layer to expose a portion of the second GaN layer, forming a source structure coupled to the third GaN layer. A first portion of the second GaN layer is disposed between the source structure and the second GaN layer. A drain structure is formed that is coupled to the third GaN layer or alternatively to the substrate. The method also includes forming a gate structure coupled to the third GaN layer such that a second portion of the third GaN layer is disposed between the gate structure and the second GaN layer. | 11-26-2015 |
| 20150340482 | HIGH ELECTRON MOBILITY SEMICONDUCTOR DEVICE AND METHOD THEREFOR - In one embodiment, Group III-nitride materials are used to form a semiconductor device. A fin structure is formed in the Group III-nitride material, and a gate structure, source electrodes and drain electrodes are formed in spaced relationship to the fin structure. The fin structure provides both polar and semi-polar 2DEG regions. In one embodiment, the gate structure is configured to control current flow in the polar 2DEG region. Shield conductor layers are included above the gate structure and in spaced relationship with drain regions of the semiconductor device. | 11-26-2015 |
| 20150340485 | High-voltage Nitride Device and Manufacturing Method Thereof - A high-voltage nitride device which can avoid vertical breakdown and has a high breakdown voltage includes: a silicon substrate; a nitride epitaxial layer, prepared on the silicon substrate; a source electrode and a drain electrode, both of which are contacted with the nitride epitaxial layer; a gate electrode, prepared between the source electrode and the drain electrode; and, at least one spatial isolation area, formed in a region between the silicon substrate and the nitride epitaxial layer vertically and between the source electrode and the drain electrode horizontally. | 11-26-2015 |
| 20150340514 | METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL JFET WITH SELF-ALIGNED SOURCE AND GATE - A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure. | 11-26-2015 |
| 20150340554 | SERIES CONNECTED SEGMENTED LED - A light source and method for making the same are disclosed. The light source includes a conducting substrate, and a light emitting structure that is divided into segments. The light emitting structure includes a first layer of semiconductor material of a first conductivity type deposited on the substrate, an active layer overlying the first layer, and a second layer of semiconductor material of an opposite conductivity type from the first conductivity type overlying the active layer. A barrier divides the light emitting structure into first and second segments that are electrically isolated from one another. A serial connection electrode connects the first layer in the first segment to the second layer in the second segment. A power contact is electrically connected to the second layer in the first segment, and a second power contact electrically connected to the first layer in the second segment. | 11-26-2015 |
| 20150340555 | LIGHT EMITTING DEVICES HAVING DISLOCATION DENSITY MAINTAINING BUFFER LAYERS - A method for forming a light emitting device comprises forming a buffer layer having a plurality of layers comprising a substrate, an aluminum gallium nitride layer adjacent to the substrate, and a gallium nitride layer adjacent to the aluminum gallium nitride layer. During the formation of each of the plurality of layers, one or more process parameters are selected such that an individual layer of the plurality of layers is strained. | 11-26-2015 |
| 20150340562 | LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - Embodiments provide a method of growing a p-type nitride semiconductor, and a light emitting device fabricated using the same. The method of growing a p-type nitride semiconductor includes growing a p-type nitride semiconductor layer on a growth substrate by introducing a group III element source, a group V element source, and a p-type dopant into a chamber at a first temperature; and cooling the interior of the chamber from the first temperature to a second temperature, wherein the p-type dopant is introduced into the chamber for at least some part of the cooling of the interior of the chamber from the first temperature to the second temperature. According to the present disclosed technology, it is possible to prevent diffusion of the p-type dopant from a p-type nitride semiconductor layer into the chamber. | 11-26-2015 |
| 20150348885 | OVER-MOLD PACKAGING FOR WIDE BAND-GAP SEMICONDUCTOR DEVICES - A transistor package includes a lead frame and a gallium nitride (GaN) transistor attached to the lead frame. The lead frame and the GaN transistor are surrounded by an over-mold with a glass transition temperature greater than about 135° C. and a flexural modulus less than about 20 GPa. Using an over-mold with a glass transition temperature greater than about 135° C. and a flexural modulus less than about 20 GPa allows the over-mold to handle the heat produced by the GaN transistor while preventing damage to the GaN transistor due to thermal expansion and/or contraction of the over-mold. | 12-03-2015 |
| 20150348886 | OVER-MOLD PLASTIC PACKAGED WIDE BAND-GAP POWER TRANSISTORS AND MMICS - A transistor package includes a lead frame, a wide band-gap transistor attached to the lead frame, and an over-mold surrounding the lead frame and the wide band-gap transistor. The wide band-gap transistor has a peak output power greater than 150 W when operated at a frequency up to 3.8 GHz. Using an over-mold along with a wide band-gap transistor in the transistor package allows the transistor package to achieve an exceptionally high efficiency, gain, and bandwidth, while keeping the manufacturing cost of the transistor package low. | 12-03-2015 |
| 20150349064 | NUCLEATION AND BUFFER LAYERS FOR GROUP III-NITRIDE BASED SEMICONDUCTOR DEVICES - A semiconductor wafer includes a substrate and at least one nucleation layer overlying the substrate. The nucleation layer includes a Al | 12-03-2015 |
| 20150349105 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region. | 12-03-2015 |
| 20150349106 | SEMICONDUCTOR STRUCTURE HAVING SETS OF III-V COMPOUND LAYERS AND METHOD OF FORMING THE SAME - A semiconductor structure includes a substrate; and a graded III-V layer over the substrate. The semiconductor structure further includes a p-doped gallium nitride (GaN) layer over the graded III-V layer. The semiconductor structure further includes one or more sets of GaN layers over the p-doped GaN layer. Each set of the one or more sets of GaN layers includes a lower GaN layer, wherein the lower GaN layer is undoped, unintentionally doped having N-type doping, or N-type doped. Each set of the one or more sets of GaN layers includes an upper GaN layer on the lower GaN layer, wherein the upper GaN layer is P-type doped. The semiconductor structure includes a second GaN layer over the one or more sets of GaN layers, the second GaN layer being either undoped or unintentionally doped having the N-type doping. The semiconductor structure includes an active layer over the second GaN layer. | 12-03-2015 |
| 20150349108 | ELECTRODE STRUCTURE FOR NITRIDE SEMICONDUCTOR DEVICE, AND NITRIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR - An electrode structure for nitride semiconductor device according to an embodiment of the invention includes a source electrode and a drain electrode provided from recesses of a nitride semiconductor multilayer structure to a surface of an insulating film so as to be in contact with the surface of the nitride semiconductor multilayer structure between the insulating film and the opening edges of the recesses. According to the structure of the ohmic electrodes, ON-state maximum electric field at ends of the source electrode and the drain electrode adjacent to the nitride semiconductor multilayer structure can be reduced so that the ON-state withstand voltage can be improved, as compared with an electrode structure in which end edge portions of ohmic electrodes are sandwiched between a nitride semiconductor multilayer structure and an insulating film. | 12-03-2015 |
| 20150349204 | EPITAXIAL DEVICES - Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride. | 12-03-2015 |
| 20150349215 | Optoelectronic Semiconductor Chip - An optoelectronic semiconductor chip includes a number of active elements arranged at a distance from one another. A carrier is arranged transversely of the active elements. The active elements each have a main axis that extends perpendicularly to the carrier and are oriented parallel to one another. A converter material surrounds the active elements on circumferential faces. The converter material includes a conversion substance or a conversion substance and a matrix material. The active elements each have a central core region that is enclosed by at least two layers such that an active layer encloses the core region and a cover layer encloses the active layer. The core region is formed with a first semiconductor material. The active layer includes a light-emitting material. The cover layer is formed with a second semiconductor material and can have a layer thickness between 0.1 nm and 100 n. | 12-03-2015 |
| 20150357290 | LAMINAR STRUCTURE OF SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF - A laminar structure of semiconductors comprises a substrate, an epitaxial layer, a protective layer, a first layer and a second layer. The epitaxial layer is arranged above the substrate and the protective layer is arranged below the substrate. Thermal expansion coefficients of the epitaxial layer and the protective layer are simultaneously greater than or less than that of the substrate. The first layer is arranged between the substrate and the protective layer; and the second layer is arranged between the substrate and the epitaxial layer, wherein the band gap of the first layer and the second layer are both greater than 3 eV. By a protective layer arranged below the substrate, stress generated between the substrate and the epitaxial layer can be reduced to prevent occurrence of bending or crack. Therefore, yield can be promoted and costs can be reduced. A manufacturing method thereof is also herein provided. | 12-10-2015 |
| 20150357321 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes a normally-off transistor having a first source electrically connected to a source terminal, a first drain, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second source electrically connected to the first drain, a second drain electrically connected to a drain terminal, and a second gate, a capacitor having one end electrically connected to the gate terminal and the other end electrically connected to the second gate; and a first diode having a first anode electrically connected to the capacitor and the second gate and a first cathode electrically connected to the first source. | 12-10-2015 |
| 20150357416 | METAL CHLORIDE GAS GENERATOR, HYDRIDE VAPOR PHASE EPITAXY GROWTH APPARATUS, AND NITRIDE SEMICONDUCTOR TEMPLATE - A nitride semiconductor template includes a substrate, and a chlorine-containing nitride semiconductor layer. The chlorine-containing nitride semiconductor layer contains an iron concentration of not higher than 1×10 | 12-10-2015 |
| 20150357418 | SEMICONDUCTOR SUBSTRATE - Provided is a semiconductor substrate including a seed layer disposed on a substrate, a buffer layer disposed on the seed layer, a plurality of nitride semiconductor layers disposed on the buffer layer, and at least one stress control layer between the plurality of nitride semiconductor layers. The buffer layer includes a plurality of step regions and at least one heterogeneous region. The plurality of step regions includes the same nitride semiconductor material. The heterogeneous region includes a different nitride semiconductor material from the step regions. | 12-10-2015 |
| 20150357420 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor stacked structure including at least an electron transit layer and an electron supply layer over a substrate. The electron supply layer includes a first portion and second portions sandwiching the first portion, and the first portion has a higher energy of a conduction band than that of the second portion, and includes a doped portion doped with an n-type impurity and undoped portions that sandwich the doped portion and are not doped with an impurity. | 12-10-2015 |
| 20150357422 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate, an active layer, a source electrode, a drain electrode, a p-type doped layer, a gate electrode, a passivation layer, and a field plate. The active layer is disposed on the substrate. The source electrode, the drain electrode and the p-type doped layer are disposed on the active layer. The p-type doped layer is disposed between the source electrode and the drain electrode, and has a first thickness. The gate electrode is disposed on the p-type doped layer. The passivation layer covers the gate electrode and the active layer. The field plate is disposed on the passivation layer and is electrically connected to the source electrode. The field plate includes a field dispersion portion disposed between the gate electrode and the drain electrode. The passivation layer between the field dispersion portion and the active layer has a second thickness smaller than the first thickness. | 12-10-2015 |
| 20150357451 | SEMICONDUCTOR DEVICE FOR HIGH-POWER APPLICATIONS - Contemplated is a semiconductor device comprising: a substrate; a group (III)-nitride layer; a metal-group (III)-nitride layer deposited between the substrate and group (III)-nitride layer; and a metal-nitride layer deposited between the substrate and the metal-group (III)-nitride layer. Also a method for making a semiconductor device with the above mentioned structure is contemplated. Furthermore, the substrate can be a silicon on insulator (SOI) substrate; the metal-nitride layer can be an aluminium nitride layer; the metal-group (III)-nitride layer can be an aluminium gallium nitride layer; and the group (III)-nitride layer can be a gallium nitride layer. | 12-10-2015 |
| 20150357453 | CIRCUIT STRUCTURE, TRANSISTOR AND SEMICONDUCTOR DEVICE - A circuit structure includes a substrate, a III-V semiconductor compound over the substrate, a Al | 12-10-2015 |
| 20150357454 | LAYER STRUCTURE FOR A GROUP-III-NITRIDE NORMALLY-OFF TRANSISTOR - A layer structure for a normally-off transistor has an electron-supply layer made of a group-III-nitride material, a back-barrier layer made of a group-III-nitride material, a channel layer between the electron-supply layer and the back-barrier layer, made of a group-III-nitride material having a band-gap energy that is lower than the band-gap energies of the other layer mentioned. The material of the back-barrier layer is of p-type conductivity, while the material of the electron-supply layer and the material of the channel layer are not of p-type conductivity, the band-gap energy of the electron-supply layer is smaller than the band-gap energy of the back-barrier layer. In absence of an external voltage a lower conduction-band-edge of the third group-III-nitride material in the channel layer is higher in energy than a Fermi level of the material in the channel layer. | 12-10-2015 |
| 20150357456 | SEMICONDUCTOR HETEROJUNCTION DEVICE - In an example embodiment, a heterojunction device comprises a substrate, a multilayer structure disposed on the substrate. The multilayer structure has a first layer having a first semiconductor disposed on top of the substrate; a second layer has a second semiconductor is disposed on top of the first layer defining an interface between them. The second semiconductor differs from the first semiconductor such that a 2D Electron Gas forms adjacent to the interface. A first terminal couples to a first area of the interface between the first and second layers and a second terminal couples to a second area of the interface between the first and second layers; an electrically conducting channel comprises a metal or a region of the first layer with a higher defect density than another region of the first layer. The channel connects the second terminal and a region of the first layer such that electric charge can flow between them. | 12-10-2015 |
| 20150357457 | SCHOTTKY GATED TRANSISTOR WITH INTERFACIAL LAYER - A Schottky gated transistor having reduced gate leakage current is disclosed. The Schottky gated transistor includes a substrate and a plurality of epitaxial layers disposed on the substrate. Further included is a gate contact having an interfacial layer disposed on a surface of the plurality of epitaxial layers and having a thickness that is between about 5 Angstroms (Å) and 40 Å. The interfacial layer can be made up of non-native materials in contrast to a native insulator such as silicon dioxide (SiO | 12-10-2015 |
| 20150357458 | III-Nitride Device with Improved Transconductance - A III-Nitride device has a back-gate disposed in a trench and under and in close proximity to the 2 DEG layer and in lateral alignment with the main gate of the device. A laterally disposed trench is also disposed in a trench and under and in close proximity to the drift region between the gate and drain electrodes of the device. The back-gate is connected to the main gate and the field plate is connected to the source electrode. The back-gate can consist of a highly conductive silicon substrate. | 12-10-2015 |
| 20150357533 | ENGINEERED-PHOSPHOR LED PACKAGES AND RELATED METHODS - In accordance with certain embodiments, regions of spatially varying wavelength-conversion particle concentration are formed over light-emitting dies. | 12-10-2015 |
| 20150364330 | TA BASED AU-FREE OHMIC CONTACTS IN ADVANCED AIGAN/GAN BASED HFETS AND/OR MOSHFETS FOR POWER SWITCH APPLICATIONS - A method of forming an Ohmic contact including forming a Ta layer in a contact area of a barrier layer by evaporation at an evaporation rate of 1 Å/second, forming a Ti layer on the first Ta layer, and forming an Al layer on the Ti layer, wherein the barrier layer comprises AlGaN having a 25% Al composition and a thickness in a range between 30 Å to 100 Å, and wherein the barrier layer is on a channel layer comprising GaN. | 12-17-2015 |
| 20150364467 | SEMICONDUCTOR DEVICE - A transistor SEL is formed by using a compound semiconductor layer (channel layer CNL). The channel layer CNL is formed over a buffer layer BUF. In a first direction where a drain electrode DRE, a gate electrode GE, and a source electrode SOE of the transistor SEL are arranged, at least a portion of the buried electrode BE is situated on the side opposing the source electrode SOE with reference to the gate electrode GE. The buried electrode BE is connected to the source electrode SOE of the transistor SEL. The top end of the buried electrode BE intrudes into the buffer layer BUF. | 12-17-2015 |
| 20150364552 | HIGH-QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON - A GaN HFET includes a silicon substrate with an Al | 12-17-2015 |
| 20150364599 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type, and a second semiconductor layer of a second conductivity type provided on the first semiconductor layer. The device further includes a third semiconductor layer of the first conductivity type or an intrinsic type provided on the second semiconductor layer. The device further includes a control electrode and a first electrode provided on a side portion of the first, second or third semiconductor layer through at least one insulating layer, and a second electrode provided on the third semiconductor layer. | 12-17-2015 |
| 20150364612 | METHOD OF FABRICATING A GAN P-I-N DIODE USING IMPLANTATION - A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region | 12-17-2015 |
| 20150364641 | Semiconductor Layer Sequence and Method for Producing a Semiconductor Layer Sequence - A semiconductor layer sequence includes a first nitridic compound semiconductor layer, a second nitridic compound semiconductor layer, and an intermediate layer arranged between the first and second nitridic compound semiconductor layers. Beginning with the first nitridic compound semiconductor layer, the intermediate layer and the second nitridic compound semiconductor layer are arranged one after the other in a direction of growth of the semiconductor layer sequence and are adjacent to each other in direct succession. The intermediate layer has a lattice constant different from the lattice constant of the first nitridic compound semiconductor layer at least at some points. The second nitridic compound semiconductor layer is lattice-adapted to the intermediate layer at least at some points. | 12-17-2015 |
| 20150364646 | CRYSTAL LAYERED STRUCTURE AND LIGHT EMITTING ELEMENT - A crystal layered structure includes a Ga | 12-17-2015 |
| 20150364647 | A LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING A LIGHT EMITTING DEVICE - The present invention relates to a light emitting device ( | 12-17-2015 |
| 20150364669 | RESONANT BODY HIGH ELECTRON MOBILITY TRANSISTOR - A resonant body high electron mobility transistor is described with resonance frequencies in gigahertz regime, limited by the cutoff frequency of the readout transistor. Piezoelectric materials form the resonating membrane of the device. Different modes of acoustic resonance, such as a thickness-mode, can be excited and amplified by applying an AC signal to the transducer electrode and proper biasing of all electrodes. The drain electrode reads out the acoustic resonance and amplifies it. The drain electrode is placed at or near where the piezoelectric charge pickup is maximum; whereas, the source electrode is placed at a nodal point with minimum displacement. | 12-17-2015 |
| 20150368832 | GaN SUBSTRATE, AND METHOD FOR MANUFACTURING GaN SUBSTRATE - Provided is a technology capable of simply manufacturing a GaN substrate, which is constituted by a GaN crystal having a substantially uniform dislocation density distribution, without using a complicated process, at low cost and at a high yield ratio. | 12-24-2015 |
| 20150371987 | Group III-V HEMT Having a Diode Controlled Substrate - There are disclosed herein various implementations of a group III-V high electron mobility transistor (HEMT) having a diode controlled substrate. Such a group III-V HEMT is situated over a substrate, and includes a diode having an anode provided by the substrate. The diode is configured to ground the substrate when the group III-V HEMT is in an off-state and to cause the substrate to float when the group III-V HEMT is in an on-state. | 12-24-2015 |
| 20150372081 | IMPROVING LINEARITY IN SEMICONDUCTOR DEVICES - A field effect transistor that has a source, a drain, a gate and a semiconductor region. The semiconductor region has a source access region between the gate and the source, a drain access region between the gate and the drain, and a channel region under the gate. The channel region under the gate has a maximum current-carrying capability that is lower than a maximum current-carrying capability of the source access region. | 12-24-2015 |
| 20150372124 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first nitride semiconductor layer including carbon and having a first side and an opposing second side. The semiconductor device further includes an intrinsic nitride semiconductor layer on the first nitride semiconductor layer. A first side of the intrinsic semiconductor layer faces the second side of the first nitride semiconductor layer. The semiconductor device further includes a second nitride semiconductor layer including aluminum and disposed on a second side of the intrinsic nitride semiconductor layer opposite to the first nitride semiconductor layer. The first nitride semiconductor layer has a carbon distribution in which a concentration of carbon changes between a high concentration region and a low concentration region. In some embodiments, the high concentration region has a carbon concentration at least 100 times higher than the carbon concentration in the low concentration region. | 12-24-2015 |
| 20150372192 | METHOD AND APPARATUS FOR CREATING A PORUS REFLECTIVE CONTACT - A light emitting device includes a semiconductor structure having a light emitting region ( | 12-24-2015 |
| 20150380238 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device having a nitride-based semiconductor layer includes forming an aluminum nitride layer on a surface of the nitride-based semiconductor layer at a forming temperature and in a growth atmosphere for aluminum nitride; and performing a thermal treatment on the nitride-based semiconductor layer and the aluminum nitride layer, at a treatment temperature that is higher than the forming temperature and in the growth atmosphere for aluminum nitride. For example, an n-GaN layer is formed on an n-GaN substrate, and thereafter the n-GaN layer is doped with an impurity. A cap layer of an epitaxial film made up of AlN is formed, by MOCVD, on the surface of the n-GaN layer. Thermal treatment for activation annealing activates the impurity in the n-GaN layer in an atmosphere that causes AlN to grow, or in an atmosphere in which growth and decomposition of AlN are substantially balanced. | 12-31-2015 |
| 20150380482 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode. | 12-31-2015 |
| 20150380498 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE PRODUCED THEREBY - A method for producing a semiconductor device having a nitride-based semiconductor layer includes forming a first nitride-based semiconductor layer of Al | 12-31-2015 |
| 20150380605 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a substrate, a first un-doped semiconductor layer, a second un-doped semiconductor layer and at least one doped insertion layer. The first un-doped semiconductor layer is disposed on the substrate. The second un-doped semiconductor layer is disposed on the first un-doped semiconductor layer. | 12-31-2015 |
| 20160005725 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a normally off transistor having a first source, a first drain, a first gate connected to a common gate terminal, and a body diode, a normally on transistor having a second source connected to the first drain, a second drain, and a second gate, a capacitor provided between the common gate terminal and the second gate, a first diode having a first anode connected to between the capacitor and the second gate and a first cathode connected to the first source, and a second diode having a second anode connected to the first source and a second cathode connected to the second drain. | 01-07-2016 |
| 20160005823 | HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE AND METHOD OF MAKING THE SAME - A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view. | 01-07-2016 |
| 20160005826 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A trench has first to third side surfaces respectively constituted of first to third semiconductor layers. A first side wall portion included in a first insulating film has first to third regions respectively located on the first to third side surfaces. A second insulating film has a second side wall portion located on the first side wall portion. The second side wall portion has one end and the other end, the one end being connected to the second bottom portion of the second insulating film, the other end being located on one of the first and second regions, the other end being separated from the third region. | 01-07-2016 |
| 20160005846 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a gate insulating film contacting the second semiconductor layer, and a gate electrode facing the second semiconductor layer via the gate insulating film. The first semiconductor layer includes an Al | 01-07-2016 |
| 20160005847 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus invention includes a substrate ( | 01-07-2016 |
| 20160005848 | SEMICONDUCTOR DEVICE - A transistor which includes an electron transit layer and an electron supply layer which are stacked in a thickness direction of a substrate; an electron transit layer formed over the substrate in parallel to the electron transit layer and the electron supply layer; an anode electrode which forms a Schottky junction with the electron transit layer; and a cathode electrode which forms an ohmic junction with the electron transit layer are provided. The anode electrode is connected to a source of the transistor, and the cathode electrode is connected to a drain of the transistor. | 01-07-2016 |
| 20160005917 | LIGHT EMITTING DEVICE - Embodiments provide a light emitting device including a substrate, a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer, disposed on the substrate, a first electrode disposed on the first conductivity-type semiconductor layer, and a second electrode disposed on the second conductivity-type semiconductor layer. The first electrode includes an ohmic contact layer disposed on the first conductivity-type semiconductor layer and formed of a transparent conductive oxide and a reflective layer disposed on the ohmic contact layer, and the thickness of the ohmic contact layer is 1 nm or more and less than 60 nm. | 01-07-2016 |
| 20160005924 | Composite Substrates and Functional Device - In the case that a functional layer, made of a nitride of a group 13 element, is formed on a composite substrate including a sapphire body and a gallium nitride crystal layer disposed over the sapphire body, the deviation of the function is prevented. The composite substrate | 01-07-2016 |
| 20160005925 | VERTICAL TYPE LIGHT EMITTING DEVICE HAVING TRANSPARENT ELECTRODE AND METHOD OF MANUFACTURING THE SAME - Provided is a vertical type light emitting device and a method of manufacturing the same. A transparent electrode having high transmittance with respect to light in the entire range and constructed by using a resistance change material of which resistance state is to be changed from a high resistance state to a low resistance state if a voltage exceeding a threshold voltage inherent in a material is applied so that conducting filaments are formed is formed between an electrode pad and a semiconductor layer of a light emitting device. The transparent electrode has high transmittance with respect to the light in a UV wavelength range as well as in a visible wavelength range generated in the light emitting device. Since the conductivity of the transparent electrode is heightened due to the formation of the conducting filaments, the transparent electrode has good ohmic contact characteristic with respect to a semiconductor layer. | 01-07-2016 |
| 20160013169 | PASSIVE COMPONENT INTEGRATED WITH SEMICONDUCTOR DEVICE IN SEMICONDUCTOR PACKAGE | 01-14-2016 |
| 20160013282 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME | 01-14-2016 |
| 20160013304 | A RADIO FREQUENCY POWER DEVICE FOR IMPLEMENTING ASYMMETRIC SELF-ALIGNMENT OF THE SOURCE, DRAIN AND GATE AND THE PRODUCTION METHOD THEREOF | 01-14-2016 |
| 20160013305 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE | 01-14-2016 |
| 20160013327 | NITRIDE SEMICONDUCTOR DIODE | 01-14-2016 |
| 20160013351 | LIGHT DETECTION DEVICE | 01-14-2016 |
| 20160013367 | Oxides with Thin Metallic Layers as Transparent Ohmic Contacts for P-Type and N-Type Gallium Nitride | 01-14-2016 |
| 20160020248 | ACTIVE LED MODULE WITH LED AND TRANSISTOR FORMED ON SAME SUBSTRATE - An LED module is disclosed containing an integrated driver transistor (e.g, a MOSFET) in series with an LED. In one embodiment, LED layers are grown over a substrate. The transistor regions are formed over the same substrate. After the LED layers, such as GaN layers, are grown to form the LED portion, a central area of the LED is etched away to expose a semiconductor surface in which the transistor regions are formed. A conductor connects the transistor in series with the LED. Another node of the transistor is electrically coupled to an electrode on the bottom surface of the substrate. In one embodiment, an anode of the LED is connected to one terminal of the module, one current carrying node of the transistor is connected to a second terminal of the module, and the control terminal of the transistor is connected to a third terminal of the module. | 01-21-2016 |
| 20160020283 | HETERO-INTEGRATION OF III-N MATERIAL ON SILICON - A hetero-integrated device includes a monocrystalline Si substrate and a trench formed in the substrate to expose a crystal surface at a bottom of the trench. Sidewall dielectric spacers are formed on sidewalls of the trench, and a III-V material layer is formed on the crystal surface at the bottom of the trench and is isolated from the sidewalls of the trench by the sidewall dielectric spacers. | 01-21-2016 |
| 20160020285 | METHOD FOR PRODUCING GROUP III NITRIDE SEMICONDUCTOR AND TEMPLATE SUBSTRATE - A semiconductor substrate includes a sapphire substrate including a c-plane main surface and a groove in a surface thereof, the groove including side surfaces and a bottom surface, and a Group III nitride semiconductor layer formed on the sapphire substrate. The side surfaces of the groove are an a-plane of sapphire. An axis of the Group III nitride semiconductor layer, perpendicular to one of the side surface of the groove, is a c-axis of Group III nitride semiconductor. A plane of the Group III nitride semiconductor, parallel to the main surface of the sapphire substrate, is an a-plane of Group III nitride semiconductor. | 01-21-2016 |
| 20160020314 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a first semiconductor layer of a first GaN based semiconductor, a second semiconductor layer of a second GaN based semiconductor having a band gap narrower than the first GaN based semiconductor, a third semiconductor layer of a third GaN based semiconductor having a band gap wider than the second GaN based semiconductor, a fourth semiconductor layer of a fourth GaN based semiconductor having a band gap narrower than the third GaN based semiconductor, a fifth semiconductor layer of a fifth GaN based semiconductor having a band gap wider than the fourth GaN based semiconductor, a gate dielectric provided directly on the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer, a gate electrode provided on the gate dielectric, a source and drain electrodes provided above the fifth semiconductor layer. | 01-21-2016 |
| 20160027656 | DEFECT FREE SINGLE CRYSTAL THIN LAYER - A gallium nitride film can be a dislocation free single crystal, which can be prepared by irradiating a surface of a substrate and contacting the surface with an etching solution that can selectively etch at dislocations. | 01-28-2016 |
| 20160027909 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to one embodiment includes an n-type first GaN-based semiconductor layer, a p-type second GaN-based semiconductor layer on the first GaN-based semiconductor layer. The second GaN-based semiconductor layer includes a low impurity concentration region and a high impurity concentration region. An n-type third GaN-based semiconductor layer is provided on the second GaN-based semiconductor layer. The device includes a gate electrode being located adjacent to the third GaN-based semiconductor layer, the low impurity concentration region, and the first GaN-based semiconductor layer intervening a gate insulating film. The device includes a first electrode on the third GaN-based semiconductor layer, a second electrode on the high impurity concentration region, and a third electrode on the opposite side of the first GaN-based semiconductor layer from the second GaN-based semiconductor layer. | 01-28-2016 |
| 20160027959 | Method for Producing an Optoelectronic Semiconductor Chip and Optoelectronic Semiconductor Chip - In at least one embodiment, a method is designed to produce optoelectronic semiconductor chips. A carrier assembly, which is a sapphire wafer, is produced. A semiconductor layer sequence is applied to the carrier assembly. The carrier assembly and the semiconductor layer sequence are divided into the individual semiconductor chips. The dividing is implemented by producing a multiplicity of selectively etchable material modifications in the carrier assembly in separation region(s) by focused, pulsed laser radiation. The laser radiation has a wavelength at which the carrier assembly is transparent. The dividing includes wet chemically etching the material modifications, such that the carrier assembly is singulated into individual carriers for the semiconductor chips solely by the wet chemical etching or in combination with a further material removal method. | 01-28-2016 |
| 20160027976 | Optoelectronic Semiconductor Device and Method for Producing an Optoelectronic Semiconductor Device - An optoelectronic semiconductor component has at least one semiconductor chip for emitting electromagnetic radiation. The semiconductor chip has at least one side surface and wherein a part of the electromagnetic radiation exits through the side surface during operation of the semiconductor chip. The semiconductor component additionally has at least one deflecting element that is formed to be transmissive to radiation. The deflecting element and the semiconductor chip are arranged one alongside another. The deflecting element is arranged at the side surface of the semiconductor chip. The deflecting element has a material, the index of refraction of which is greater than an average index of refraction of a semiconductor material of the semiconductor chip. | 01-28-2016 |
| 20160035847 | GATE WITH SELF-ALIGNED LEDGED FOR ENHANCEMENT MODE GaN TRANSISTORS - An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively. | 02-04-2016 |
| 20160035931 | GALNASSB SOLID SOLUTION-BASED HETEROSTRUCTURE, METHOD FOR PRODUCING SAME AND LIGHT EMITTING DIODE BASED ON SAID HETEROSTRUCTURE - The provided heterostructure includes a substrate containing GaSb, a buffer layer which contains a GaInAsSb solid solution, the buffer layer being disposed over the substrate; an active layer which contains a GaInAsSb solid solution, the active layer being disposed over the buffer layer; a confining layer for localizing major carriers, the confining layer containing a AlGaAsSb solid solution and being disposed over the active layer; a contact layer containing GaSb, the contact layer being disposed over the confining layer, wherein the buffer layer contains less indium (In) than the active layer. The provided heterostructure is characterized by increased quantum efficiency. Also a method of producing the heterostructure and a light emitting diode based on the heterostructure are provided. Light emitting diodes on the basis of the provided heterostructure emit in a mid-infrared spectral range of 1.8-2.4 μm. | 02-04-2016 |
| 20160035938 | SEMICONDUCTOR LIGHT EMITTING DEVICE, NITRIDE SEMICONDUCTOR LAYER, AND METHOD FOR FORMING NITRIDE SEMICONDUCTOR LAYER - According to an embodiment, a semiconductor light emitting device includes a foundation layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer. The foundation layer has an unevenness having recesses, side portions, and protrusions. A first major surface of the foundation layer has an overlay-region. The foundation layer has a plurality of dislocations including first dislocations whose one ends reaching the recess and second dislocations whose one ends reaching the protrusion. A proportion of a number of the second dislocations reaching the first major surface to a number of all of the second dislocations is smaller than a proportion of a number of the first dislocations reaching the first major surface to a number of all of the first dislocations. A number of the dislocations reaching the overlay-region of the first major surface is smaller than a number of all of the first dislocations. | 02-04-2016 |
| 20160035945 | WHITE LED CHIP AND METHOD OF MANUFACTURE - The present invention discloses a white LED chip and method of manufacturing the same. The white LED chip includes a flip blue LED chip and a preformed conversion layer for light conversion, the method of manufacturing the white LED chip includes the steps of preparing for a preformed conversion layer for light conversion, setting up at least one cavity on the conversion layer, for receiving a blue LED chip(s), attaching the blue LED chip into the cavity; and cutting the conversion layer into a single white LED chip based on each cavity that received a blue LED chip. The invention not only enhance the luminous efficiency of the white LED chip, but also avoid the pollution to bottom electrode of the LED chip, making easier manufacture and higher binning yield. | 02-04-2016 |
| 20160043178 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In accordance with an embodiment, a method for manufacturing a semiconductor component includes providing a semiconductor material having a surface, forming an epitaxial layer of carbon doped semiconductor material on the semiconductor substrate, the epitaxial layer having a surface, forming a nucleation layer on the epitaxial layer; and forming a layer of III-nitride material on the nucleation layer. In accordance with another embodiment, the semiconductor component includes a silicon semiconductor substrate of a first conductivity type; a carbon doped epitaxial layer on the silicon semiconductor substrate; a buffer layer over the carbon doped buffer layer; and a channel layer on the buffer layer. | 02-11-2016 |
| 20160043181 | ELECTRONIC DEVICE INCLUDING A CHANNEL LAYER INCLUDING A COMPOUND SEMICONDUCTOR MATERIAL - An electronic device can transistor having a channel layer that includes a compound semiconductor material. In an embodiment, the channel layer overlies a semiconductor layer that includes a carrier barrier region and a carrier accumulation region. The charge barrier region can help to reduce the likelihood that de-trapped carriers from the channel layer will enter the charge barrier region, and the charge accumulation region can help to repel carriers in the channel layer away from the charge barrier layer. In another embodiment, a barrier layer overlies the channel layer. Embodiments described herein may help to produce lower dynamic on-resistance, lower leakage current, another beneficial effect, or any combination thereof. | 02-11-2016 |
| 20160043182 | METHOD AND SYSTEM FOR FORMATION OF P-N JUNCTIONS IN GALLIUM NITRIDE BASED ELECTRONICS - A semiconductor device includes a III-nitride substrate having a first conductivity type and a first electrode electrically coupled to the III-nitride substrate. The semiconductor device also includes a III-nitride material having a second conductivity type coupled to the III-nitride substrate at a regrowth interface and a p-n junction disposed between the III-nitride substrate and the regrowth interface. | 02-11-2016 |
| 20160043183 | SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAYER - According to one embodiment, a semiconductor wafer includes a substrate, an AlN buffer layer, a foundation layer, a first high Ga composition layer, a high Al composition layer, a low Al composition layer, an intermediate unit and a second high Ga composition layer. The first layer is provided on the foundation layer. The high Al composition layer is provided on the first layer. The low Al composition layer is provided on the high Al composition layer. The intermediate unit is provided on the low Al composition layer. The second layer is provided on the intermediate unit. The first layer has a first tensile strain and the second layer has a second tensile strain larger than the first tensile strain. Alternatively, the first layer has a first compressive strain and the second layer has a second compressive strain smaller than the first compressive strain. | 02-11-2016 |
| 20160043187 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer and having a wider band gap than the first semiconductor layer, a source electrode and a drain electrode provided on the second semiconductor layer, wherein at least one of the source electrode and the drain electrode includes a plurality of protrusions on a side in contact with the second semiconductor layer, and a gate electrode provided between the source electrode and the drain electrode. | 02-11-2016 |
| 20160043210 | Compound Semiconductor Device - A semiconductor device includes a first compound semiconductor material and a second compound semiconductor material on the first compound semiconductor material. The second compound semiconductor material comprises a different material than the first compound semiconductor material such that the first compound semiconductor material has a two-dimensional electron gas (2DEG). The semiconductor device further includes a buried field plate disposed in the first compound semiconductor material and electrically connected to a terminal of the semiconductor device. The 2DEG is interposed between the buried field plate and the second compound semiconductor material. | 02-11-2016 |
| 20160043211 | ELECTRODES FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A III-N semiconductor HEMT device includes an electrode-defining layer on a III-N material structure. The electrode-defining layer has a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, each sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a larger width than a portion of the recess proximal to the III-N material structure. An electrode is in the recess, the electrode including an extending portion over the first sidewall. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle. | 02-11-2016 |
| 20160049351 | High-Power Electronic Device Packages and Methods - A high power electronic device package constructed to include a high power electronic device having an epitaxial surface attached to a thermally conductive submount by a thermally conductive interface layer having a eutectic metal contact therein. A gallium nitride high electron mobility transistor (GaN HEMT) having a transistor structure formed of a GaN thin film layer bonded to a thermally conductive host substrate via a thermally conductive interface layer disposed therebetween, and a method of forming the GaN HEMT. The GaN HEMTs can be used in such applications as, for example, power amplifiers with x-band radio frequency (RF) power outputs for micro-radar applications. | 02-18-2016 |
| 20160049375 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate which includes a first face. The device also includes a buffer layer, a semiconductor layer, source and drain electrodes, and a gate electrode. A trench is formed on the semiconductor layer so that the trench surrounds the source electrode, the drain electrode, and the gate electrode in a plan view, the trench passes through the semiconductor layer and the buffer layer, and a bottom of the trench reaches at least an inside of the substrate. A distance from the first face of the substrate to the bottom of the trench is 100 nm or more in a thickness direction of the substrate. | 02-18-2016 |
| 20160049549 | SOLID STATE LIGHTING DEVICES WITH SELECTED THERMAL EXPANSION AND/OR SURFACE CHARACTERISTICS, AND ASSOCIATED METHODS - Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods are disclosed. A method in accordance with a particular embodiment includes forming an SSL (solid state lighting) formation structure having a formation structure coefficient of thermal expansion (CTE), selecting a first material of an interlayer structure to have a first material CTE greater than the substrate CTE, and selecting a second material of the interlayer structure based at least in part on the second material having a second material CTE less than the first material CTE. The method can further include forming the interlayer structure over the SSL formation structure by disposing (at least) a first layer of the first material over the SSL formation structure, a portion of the second material over the first material, and a second layer of the first material over the second material. The SSL formation structure supports an SSL emitter material, and the method further includes counteracting a force placed on the formation structure by the first material, by virtue of the difference between the second material CTE and the first material CTE. In other embodiments, the SSL formation structure can have an off-cut angle with a non-zero value of up to about 4.5 degrees. | 02-18-2016 |
| 20160049554 | Gallium Nitride Substrates and Functional Devices - The maximum value of peak intensities of cathode luminescence of a wavelength corresponding to a band gap of gallium nitride and in a measured visual field of 0.1 mm×0.1 mm is 140 percent or higher of an average value of the peak intensities of the cathode luminescence, provided that the peak intensities of the cathode luminescence are measured on a surface of the gallium nitride substrate. | 02-18-2016 |
| 20160056145 | SEMICONDUCTOR DEVICE - Performance of a semiconductor device is improved. The semiconductor device includes a substrate composed of silicon, a semiconductor layer composed of p-type nitride semiconductor provided on the substrate, and a transistor including a channel layer provided on the semiconductor layer. The semiconductor device further includes an n-type source region provided in the channel layer, and an n-type drain region provided in the channel layer separately from the source region in a plan view. | 02-25-2016 |
| 20160056150 | POWER SEMICONDUCTOR ELEMENT - A power semiconductor element includes: a main transistor including a first gate electrode, a first drain electrode, and a first source electrode; a sensor transistor including a second gate electrode, a second drain electrode, and a second source electrode; and a gate switch transistor including a third gate electrode, and a third drain electrode, a third source electrode. The first gate electrode, the second gate electrode, and the third drain electrode are connected, the first drain electrode and the second drain electrode are connected, the first source electrode and the second source electrode are connected via a sensor resistor, the first source electrode and the third source electrode are connected, the second source electrode and the third gate electrode are connected via a switch resistor, and the main transistor, the sensor transistor, and the gate switch transistor are formed with a nitride semiconductor. | 02-25-2016 |
| 20160056151 | POWER SEMICONDUCTOR DEVICE WITH OVER-CURRENT PROTECTION - A power semiconductor device has an upper transistor and a lower transistor that is coupled in cascode with the upper transistor. The upper transistor comprises an upper drain, upper gate, and an upper source. The lower transistor comprises a lower drain that is coupled to the upper source, a lower gate, and a lower source that is coupled to the upper gate. The upper transistor is a depletion mode device and has a first saturation current. The lower transistor is an enhancement mode device and has a second saturation current, which is lower than the first saturation current. | 02-25-2016 |
| 20160056245 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a channel layer which is made of In | 02-25-2016 |
| 20160056275 | FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR DEVICE - A field effect transistor includes multi-finger electrodes, a gate terminal electrode, a drain terminal electrode, a source terminal and a source terminal electrode. Each of the multi-finger electrodes includes two finger gate electrodes, a finger drain electrode, and at least two finger source electrodes. Finger electrodes are arranged so as to intersect with the first straight line at an angle of approximately +45 degrees and approximately −45 degrees alternately. The gate terminal electrode commonly bundles and connects the finger gate electrodes of two adjacent cell regions. The drain terminal electrode commonly bundles and connects the finger drain electrodes of two adjacent cell regions. And the source terminal electrode commonly bundles and connects the finger source electrodes of two adjacent cell regions. The gate terminal electrodes and the drain terminal electrodes are alternately provided in a connecting region of the multi-finger electrodes of two adjacent cell regions. | 02-25-2016 |
| 20160056333 | NITRIDE SEMICONDUCTOR MULTILAYER FILM REFLECTOR AND LIGHT-EMITTING DEVICE USING THE SAME - Achieving resistance reduction of a nitride semiconductor multilayer film reflector. In the nitride semiconductor multilayer film reflector, a first semiconductor layer ( | 02-25-2016 |
| 20160056339 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF PRODUCING THE SAME - The invention is a semiconductor light emitting device successively including a conductive support substrate, a metal layer, and a light emitting part successively including an n-type current spreading layer, an n-type cladding layer, an active layer, a p-type cladding layer, and a p-type current spreading layer, which are made of an AlGaInP-based semiconductor layer. This device also includes a first thin ohmic electrode partially covering the p-type current spreading layer and a second thin ohmic electrode partially provided between the metal and n-type current spreading layers. The first and second thin ohmic electrodes are disposed so as not to overlap when seen from above. The lattice constant of the n-type current spreading layer matches that of the n-type cladding layer. The invention provides a P-side-up metal reflection type of semiconductor light emitting device having high luminance that inhibits increase in thickness of semiconductor layers and keeps current from locally concentrating. | 02-25-2016 |
| 20160056347 | WHITE LIGHT EMITTING DIODE WITH SINGLE CRYSTAL PHOSPHOR AND THE MANNER OF PRODUCTION - According to the invention, the diode with a single crystal phosphor placed over the chip comprises the fact that the single crystal phosphor, created by LnYAG and/or YAP and/or GGAG hosts, doped with the atoms selected from the Ce | 02-25-2016 |
| 20160064271 | Inverted Trapezoidal Recess for Epitaxial Growth - A semiconductor device having an epitaxial layer a method of manufacture thereof is provided. The semiconductor device has a substrate with a trench formed therein and a recess formed below the trench. The recess has sidewalls with a (111) crystal orientation. The depth of the trench is such that the depth is greater than or equal to one-half a length of sidewalls of the recess. An epitaxial layer is formed in the recess and the trench. The depth of the trench is sufficient to cause dislocations formed between the interface of the semiconductor substrate and the epitaxial layer to terminate along sidewalls of the trench. | 03-03-2016 |
| 20160064491 | GROUP III-N TRANSISTORS ON NANOSCALE TEMPLATE STRUCTURES - A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin. | 03-03-2016 |
| 20160064539 | SEMICONDUCTOR STRUCTURE AND RECESS FORMATION ETCH TECHNIQUE - A semiconductor structure has a first layer that includes a first semiconductor material and a second layer that includes a second semiconductor material. The first semiconductor material is selectively etchable over the second semiconductor material using a first etching process. The first layer is disposed over the second layer. A recess is disposed at least in the first layer. Also described is a method of forming a semiconductor structure that includes a recess. The method includes etching a region in a first layer using a first etching process. The first layer includes a first semiconductor material. The first etching process stops at a second layer beneath the first layer. The second layer includes a second semiconductor material. | 03-03-2016 |
| 20160064540 | III-N MATERIAL STRUCTURE FOR GATE-RECESSED TRANSISTORS - III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack. | 03-03-2016 |
| 20160064555 | III-NITRIDE TRANSISTOR WITH ENHANCED DOPING IN BASE LAYER - A vertical trench MOSFET comprising: a N-doped substrate of a III-N material; and an epitaxial layer of the III-N material grown on a top surface of the substrate, a N-doped drift region being formed in said epitaxial layer; a P-doped base layer of said III-N material, formed on top of at least a portion of the drift region; a N-doped source region of said III-N material; formed on at least a portion of the base layer; and a gate trench having at least one vertical wall extending along at least a portion of the source region and at least a portion of the base layer; wherein at least a portion of the P-doped base layer along the gate trench is a layer of said P-doped III-N material that additionally comprises a percentage of aluminum. | 03-03-2016 |
| 20160064606 | EPITAXIAL SUBSTRATE, METHOD OF MANUFACTURING THE EPITAXIAL SUBSTRATE AND LIGHT EMITTING DIODE HAVING EPITAXIAL SUBSTRATE - An epitaxial substrate for growing a lighting emitting structure of a light emitting diode, includes a transparent base, a first buffer layer and a second buffer layer formed on the transparent base. The transparent base includes a first surface and a second surface opposite to the first surface. Plural protrusions are formed on the first surface of the transparent base. Each first buffer layer is formed on the outer surfaces of the plural protrusions. The second buffer layer fills in the recesses defined between two adjacent protrusions, and covers the first buffer layer. The refractive index of the first buffer layer is larger than that of the transparent base, and is less than that of the second buffer layer. This disclosure also relates a method for manufacturing the epitaxial substrate and a light emitting diode having the same. | 03-03-2016 |
| 20160071958 | HIGH RESISTIVITY SILICON-ON-INSULATOR WAFER MANUFACTURING METHOD FOR REDUCING SUBSTRATE LOSS - A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a semiconductor nitride layer in contact with the semiconductor handle substrate, the semiconductor nitride layer selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof; a dielectric layer in contact with the semiconductor nitride layer; and a semiconductor device layer in contact with the dielectric layer. | 03-10-2016 |
| 20160071967 | High-Electron-Mobility Transistor Having a Buried Field Plate - A high-electron-mobility field effect transistor is formed with a buffer region having a stepped lateral profile, the stepped lateral profile having first, second and third cross-sections of the buffer region, the first cross-section being thicker than the third cross-section and including a buried field plate, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections. A barrier region is formed along the stepped lateral profile. The barrier region is separated from the buried field plate by a portion of the buffer region. The buffer region is formed from a first semiconductor material and the barrier region is formed from a second semiconductor material. The first and second semiconductor materials have different band-gaps such that an electrically conductive channel of a two-dimensional charge carrier gas arises at an interface between the buffer and barrier regions. | 03-10-2016 |
| 20160071969 | HIGH ELECTRON MOBILITY TRANSISTOR WITH INDIUM NITRIDE LAYER - A semiconductor device includes a substrate, a first layer over the substrate, a second layer over the first layer, and a third layer over the second layer. The third layer has a first portion and a second portion. The first portion of the third layer is separated from the second portion of the third layer. The semiconductor device also includes a first blended region beneath the first portion of the third layer. The first blended region includes aluminum atoms drawn from the first layer into at least the second layer. The semiconductor device further includes a second blended region beneath the second portion of the third layer. The second blended region includes aluminum atoms drawn from the first layer into at least the second layer. The semiconductor device also includes a source contact and a drain contact. | 03-10-2016 |
| 20160072016 | SOLID-STATE LIGHT EMITTERS HAVING SUBSTRATES WITH THERMAL AND ELECTRICAL CONDUCTIVITY ENHANCEMENTS AND METHOD OF MANUFACTURE - Solid-state lighting devices (SSLDs) including a carrier substrate with conductors and methods of manufacturing SSLDs. The conductors can provide (a) improved thermal conductivity between a solid-state light emitter (SSLE) and a package substrate and (b) improved electrical conductivity for the SSLE. In one embodiment, the conductors have higher thermal and electrical conductivities than the carrier substrate supporting the SSLE. | 03-10-2016 |
| 20160072017 | VERTICAL TOPOLOGY LIGHT EMITTING DEVICE - A vertical topology light emitting device comprises a metal support structure; an adhesion structure on the metal support structure, wherein the adhesion structure comprises a first adhesion layer and a second adhesion layer on the first adhesion layer; a metal layer on the adhesion structure, wherein the adhesion structure is thicker than the metal layer; a GaN-based semiconductor structure on the metal layer, wherein the GaN-based semiconductor structure has a thickness less than 5 micrometers; a multi-layered electrode structure on the GaN-based semiconductor structure; and a protective layer on a side surface and a top surface of the GaN-based semiconductor structure, wherein the protective layer is further disposed on the multi-layered electrode structure. | 03-10-2016 |
| 20160079120 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate that has a first surface and a second surface opposite to the first surface, and has a groove or trench extending from the first surface toward the second surface, a bottom of the groove being situated between the first surface and the second surface, and a gallium nitride-containing layer on the first surface of the semiconductor substrate having a trench tapering inwardly along a direction toward the first surface of the semiconductor substrate and connected to the groove. | 03-17-2016 |
| 20160079370 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a nitride semiconductor device including a first semiconductor layer and a second semiconductor layer is provided. The first semiconductor layer is provided on a base, and includes a nitride semiconductor. The first semiconductor layer includes a first region, and a second region which is provided on the first region, has a concentration of Si lower than a concentration of Si in the first region, and is thicker than the first region. The second semiconductor layer is provided on the first semiconductor layer. | 03-17-2016 |
| 20160079371 | SEMICONDUCTOR DEVICE - According to one embodiment, there is provided a semiconductor device including a first semiconductor layer, a second semiconductor layer, a first insulating film, a first electrode, and a second insulting film. The first semiconductor layer includes a compound semiconductor. The second semiconductor layer is provided on the first semiconductor layer and includes a compound semiconductor. The first insulating film is provided on the second semiconductor layer. The first electrode is provided on the first insulating film. The second insulting film covers at least a portion of the first electrode and has a higher hydrogen concentration than the hydrogen concentration of the first insulating film. | 03-17-2016 |
| 20160079403 | FIELD EFFECT TRANSISTOR - A field effect transistor includes a multilayer body, a finger source electrode, a finger drain electrode, a finger gate electrode, an insulating layer, and a source field plate. A finger gate electrode includes a bottom part. The bottom part has a first side surface and a second side surface. A source field plate includes a finger part and an interconnect part. A side surface of the finger part is provided between the second side surface of the finger gate electrode and the finger drain electrode. A source terminal electrode covers the finger source electrode and a tip part of the interconnect part. A side surface of the finger source electrode has an opening recessed from the first side surface. And the tip part is extended to a part of the insulating layer exposed in the opening. | 03-17-2016 |
| 20160079404 | HETEROJUNCTION FIELD EFFECT TRANSISTOR - A heterojunction field effect transistor includes a first contact portion and a second contact portion. A length of the first contact portion in a longitudinal direction is smaller than a length of source electrodes in the longitudinal direction, and a length of the second contact portion in the longitudinal direction is smaller than a length of drain electrodes in the longitudinal direction. For each drain electrode, a distance from ends of the second contact portion to ends of the drain electrode, the ends being outside of the second contact portion, is greater than a distance from ends of the first contact portion to ends of the source electrode, the ends being outside of the first contact portion. | 03-17-2016 |
| 20160079405 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, and a first insulating film. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer is provided over the first semiconductor layer, includes a nitride semiconductor, and contains composition different from the composition of the first semiconductor layer. The first insulating film is provided over the second semiconductor layer, covers at least a part of the first electrode, and contains silicon nitride. The hydrogen concentration in the first insulating film is greater than or equal to 5.0×10 | 03-17-2016 |
| 20160079406 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, source and drain electrodes over the second semiconductor layer, a gate electrode, and a first field plate electrode. The second semiconductor layer includes a first semiconductor portion and a second semiconductor portion thinner than the first semiconductor portion. The source and drain electrodes are electrically connected to the second semiconductor layer. The gate electrode is provided over the second semiconductor layer between the source electrode and the drain electrode. The first field plate electrode is provided over the second semiconductor layer and includes a portion that extends from a location over the gate electrode toward the drain electrode and has an end portion that is positioned over the second semiconductor portion. | 03-17-2016 |
| 20160079407 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer, a first insulation layer, and a first electrode. The first electrode includes a titanium layer and a titanium nitride layer. The first insulation layer is provided on the first semiconductor layer. The first insulation layer contains silicon nitride. The titanium nitride layer is provided on the first insulation layer. The titanium layer is provided on at least a portion of the titanium nitride layer. | 03-17-2016 |
| 20160079409 | SEMICONDUCTOR DEVICE - A semiconductor device including a field effect transistor including a substrate, a lower barrier layer provided on the substrate, a channel layer provided on the lower barrier layer, an electron supplying layer provided on the channel layer, a source electrode and a drain electrode provided on the electron layer, and a gate electrode provided between the source electrode and the drain electrode. The lower barrier layer includes a composition of In | 03-17-2016 |
| 20160079410 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first electrode, a second electrode, a third electrode, and a nitride semiconductor layer. The first electrode has a first surface. The second electrode has a second surface. The second surface is provided with a plurality of convex portions and concave portions. The second electrode is spaced from the first electrode in a first direction. The third electrode is spaced from the first electrode in a second direction intersecting the first direction. The nitride semiconductor layer is provided between the first surface and the second surface, and between the third electrode and the second surface. | 03-17-2016 |
| 20160079426 | SEMICONDUCTOR DEVICE - To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×10 | 03-17-2016 |
| 20160079467 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND PRODUCTION METHOD THEREFOR - The present invention provides a Group III nitride semiconductor light-emitting device in which the production method is simplified while migration of at least one of Ag atoms and Al atoms is suppressed, and a production method therefor. The production method comprises steps of forming a first electrode, forming a second electrode, and forming a second electrode side barrier metal layer on the second electrode. Moreover, the second electrode has an electrode layer containing at least one of Ag and Al. In forming the first electrode and the second electrode side barrier metal layer, the second electrode side barrier metal layer is formed on the second electrode while the first electrode to be electrically connected to the first semiconductor layer is formed. The first electrode and the second electrode side barrier metal layer are deposited are deposited in the same layered structure. | 03-17-2016 |
| 20160079473 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND MANUFACTURING METHOD THEREOF - A semiconductor light emitting element includes a first layer, a second layer, an intermediate layer, and a third layer. The first layer has a first surface having roughness including concave portions of which side surfaces are inclined and a second surface on an opposite side to the first surface. The first layer includes a first conductive-type first semiconductor layer. The second layer includes a second conductive-type second semiconductor layer. The intermediate layer is provided between the second surface and the second layer. The third layer is provided in the concave portions. | 03-17-2016 |
| 20160079475 | LIGHT-EMITTING DEVICE - A light-emitting device of an embodiment of the present disclosure comprises a substrate; a semiconductor stack comprising a first type semiconductor layer, a second type semiconductor layer and an active layer formed between the first type semiconductor layer and the second type semiconductor layer, wherein the first type semiconductor layer comprises a non-planar roughened surface; a bonding layer formed between the substrate and the semiconductor stack; and multiple recesses each comprising a bottom surface lower than the non-planar roughened surface; and multiple buried electrodes physically buried in the first type semiconductor layer, wherein the multiple buried electrodes are formed in the multiple recesses respectively, and one of the multiple buried electrodes comprises an upper surface higher than the non-planar roughened surface of the first type semiconductor layer. | 03-17-2016 |
| 20160079476 | SEMICONDUCTOR COMPONENT COMPRISING AN INTERLAYER - An optoelectronic semiconductor component includes a layer sequence including a p-doped layer, an n-doped layer and an active zone that generates electromagnetic radiation arranged between the n-doped layer and the p-doped layer, wherein the n-doped layer includes at least GaN, an interlayer is arranged in the n-doped layer, wherein the interlayer includes Al | 03-17-2016 |
| 20160079482 | VERTICAL STRUCTURE LEDS - A vertical structure light-emitting device includes a conductive support, a light-emitting semiconductor structure disposed on the conductive support structure, the semiconductor structure having a first semiconductor surface, a side semiconductor surface and a second semiconductor surface, a first electrode electrically connected to the first-type semiconductor layer, a second electrode electrically connected to the second-type semiconductor layer, wherein the second electrode has a first electrode surface, a side electrode surface and a second electrode surface, wherein the first electrode surface, relative to the second electrode surface, is proximate to the semiconductor structure; and wherein the second electrode surface is opposite to the first electrode surface, and a passivation layer disposed on the side semiconductor surface and the second semiconductor surface. | 03-17-2016 |
| 20160086881 | Electronic Component - In an embodiment, an electronic component includes a dielectric core layer having a first major surface, a semiconductor die embedded in the dielectric core layer, and a first conductive layer. The semiconductor die includes a first major surface and at least two conductive fingers arranged on the first major surface which are coupled to a common potential. The first conductive layer is arranged on, and electrically coupled to, the at least two conductive fingers and extends from the at least two conductive fingers over the first major surface of the dielectric core layer. | 03-24-2016 |
| 20160086938 | GaN STRUCTURES - A semiconductor device is disclosed. The device includes a substrate including GaN, a two dimensional electron gas (2DEG) inducing layer on the substrate, and a lateral transistor on the 2DEG inducing layer. The lateral transistor includes source and drain contacts to the 2DEG inducing layer, a gate stack between the source and drain contacts, and a field plate between the gate and the drain contact. The device also includes one or more insulation layers on the 2DEG inducing layer, where the field plate is spaced apart from the 2DEG inducing layer by the insulation layers, and a conductor on the insulation layers, where a first portion of the conductor is spaced apart from the 2DEG inducing layer by the insulation layers by a distance less than 200 nm. | 03-24-2016 |
| 20160087048 | GALLIUM NITRIDE SEMICONDUCTOR SUBSTRATE WITH SEMICONDUCTOR FILM FORMED THEREIN - A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more signal crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis. Each predetermined plane is inclined to the predetermined axis. Each substrate has a minor polished primary surface. The primary surface has a first area and a second area. The first area is between an edge of the substrate and a line 3 millimeter away from the edge. The first area surrounds the second area. An qaxis perpendicular to the primary surface forms an off-angle with c-axis of the substrate. The off-angle takes a minimum value at a first position in the first area of the primary surface. | 03-24-2016 |
| 20160087051 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A manufacturing method of a semiconductor device, includes: a stacking process of forming an electrode by stacking a plurality of electrode layers on a semiconductor layer; and a anneal treatment process of treating the electrode. The stacking process including processes of forming a first electrode layer mainly made of aluminum (Al) as one of the plurality of electrode layers; forming a second electrode layer mainly made of a conductive material that has a higher melting point than that of aluminum (Al) and reacts with aluminum (Al) at 450° C. or higher temperature, as one of the plurality of electrode layers, on the first electrode layer; and forming a third electrode layer mainly made of palladium (Pd) as an electrode layer most distant from the semiconductor layer among the plurality of electrode layers, on the second electrode layer. | 03-24-2016 |
| 20160087089 | Non-Planar Normally Off Compound Semiconductor Device - A normally-off compound semiconductor device includes a first III-nitride semiconductor having a first sloped transition region in which the first III-nitride semiconductor transitions at an angle from a first level to a second level different than the first level, and a second III-nitride semiconductor on the first III-nitride semiconductor and having a different band gap than the first III-nitride semiconductor so that a two-dimensional charge carrier gas arises along an interface between the first and second III-nitride semiconductors. The normally-off compound semiconductor device further includes a gate on the second III-nitride semiconductor and a doped semiconductor over the first sloped transition region and interposed between the gate and the second III-nitride semiconductor. The two-dimensional charge carrier gas is disrupted along the first sloped transition region due solely to the slope of the first sloped transition region if steep enough, or also due to the presence of the doped semiconductor. | 03-24-2016 |
| 20160087090 | RF POWER TRANSISTOR - A radio frequency (RF) power transistor includes: a semiconductor heterostructure that includes an undoped barrier layer and an active layer and that is formed with a continuous two dimensional electron gas (2DEG) channel having an ohmic source-aligned region, an ohmic drain-aligned region and a Schottky-aligned region; agate electrode; and source and drain electrodes. One of the source and drain electrodes includes an ohmic contact and a Schottky contact that extends from the ohmic contact toward the gate electrode. The 2DEG channel is normally on and extends continuously from the ohmic source-aligned region to the ohmic drain-aligned region. The Schottky contact overlaps and is capacitively coupled to the Schottky-aligned region of the 2DEG channel. | 03-24-2016 |
| 20160087152 | EPITAXIAL FORMATION SUPPORT STRUCTURES AND ASSOCIATED METHODS - Epitaxial formation support structures and associated methods of manufacturing epitaxial formation support structures and solid state lighting devices are disclosed herein. In several embodiments, a method of manufacturing an epitaxial formation support substrate can include forming an uncured support substrate that has a first side, a second side opposite the first side, and coefficient of thermal expansion substantially similar to N-type gallium nitride. The method can further include positioning the first side of the uncured support substrate on a first surface of a first reference plate and positioning a second surface of a second reference plate on the second side to form a stack. The first and second surfaces can include uniformly flat portions. The method can also include firing the stack to sinter the uncured support substrate. At least side of the support substrate can form a planar surface that is substantially uniformly flat. | 03-24-2016 |
| 20160087169 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate, a light emitting device and a sealing resin member. The substrate includes a flexible base, a plurality of wiring portions, a groove portion and a pair of terminal portions. The flexible base extends in a first direction corresponding to a longitudinal direction of the substrate and the plurality of wiring portions are arranged on the flexible base. The groove portion is formed between the plurality of wiring portions spaced apart from each other. The pair of terminal portions is arranged along the first direction at the both sides of the plurality of wiring portions. The light emitting element is disposed on the substrate and electrically connected to the plurality of wiring portions. The sealing resin member seals the light emitting element and a part of the substrate. The light emitting element is mounted on the substrate in a flip-chip manner. | 03-24-2016 |
| 20160093689 | THIN FILM TRANSITION METAL DICHALCOGENIDES AND METHODS - A coated substrate including a thin film of a transition metal dichalcogenide and associated methods are shown. In one example, the substrate is a semiconductor wafer. In one example, the thin film is atomically thin, and the substrate is a number of centimeters in diameter. In one example a crystalline structure of the thin film is substantially 2H hexagonal. | 03-31-2016 |
| 20160093691 | SEMICONDUCTOR DEVICE, ELECTRIC EQUIPMENT, BIDIRECTIONAL FIELD EFFECT TRANSISTOR, AND MOUNTED STRUCTURE BODY - Provided are a semiconductor device and a bidirectional field effect transistor which can easily overcome the tradeoff relation between the high voltage resistance and high speed in the semiconductor device using a polarization super junction, realize both the high voltage resistance and elimination of the occurrence of current collapse, operate at a high speed, and further the loss is low. | 03-31-2016 |
| 20160093703 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor layer; a first electrode that is in ohmic contact with part of the semiconductor layer; an insulating film that is formed over from the semiconductor layer to the first electrode and has an opening area on an inner side of a first edge of the first electrode; a second electrode that is located at a position different from the first electrode and is formed on at least one of the insulating film and the semiconductor layer; and a third electrode that is made of an identical component with a component of the second electrode and is formed on the first electrode through the opening area and is also formed over from the first electrode to an inner side of the first edge on the insulating film. | 03-31-2016 |
| 20160093768 | LIGHT EMITTING DIODE CONSTRUCTIONS AND METHOD OF MAKING THE SAME - Flip chip LEDs comprise a transparent substrate or carrier having an active material attached thereto and having a number of electrodes disposed along a common surface of the active material. The substrate may include a number of surface features disposed along a first surface adjacent the active material for improving light extraction from the active material, and includes a number of surface features along a second surface opposite the first surface for minimizing internal reflection of light through the substrate, thereby improving light extraction from the transparent substrate. The surface features on both surfaces may be arranged having a random or ordered orientation relative to one another. A plurality of such flip chip LEDs may be physically packaged together in a manner providing electrical connection with the same for a lighting end-use application. | 03-31-2016 |
| 20160093772 | Methods for Reducing Interface Contact Resistivity - Provided are methods of forming low resistivity contacts. Also provided are devices having such low resistive contacts. A method may include doping the surface of a structure, such as a gallium nitride layer. Specifically, a dopant containing layer is formed on the surface of the structure using, for example, atomic layer deposition (ALD). The dopant may magnesium. In some embodiments, the dopant containing layer also includes nitrogen. A capping layer may be then formed over the dopant containing layer to prevent dopant desorption. The stack including the structure with the dopant containing layer disposed on its surface is then annealed to transfer dopant from the dopant containing layer into the surface. After annealing, any remaining dopant containing layer is removed. When another component is later formed over the surface, a low resistivity contact is created between this other component and the doped structure. | 03-31-2016 |
| 20160099318 | STRUCTURE AND METHOD FOR TRANSIENT VOLTAGE SUPPRESSION DEVICES WITH A TWO-REGION BASE - A transient voltage suppression (TVS) device and a method of forming the device are provided. The TVS device includes a first layer of wide band-gap semiconductor material formed of a first conductivity type material, a second layer of wide band-gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, the second layer including a first concentration of dopant. The TVS device further including a third layer of wide band-gap semiconductor material formed of the second conductivity type material over at least a portion of the second layer, the third layer including a second concentration of dopant, the second concentration of dopant being different than the first concentration of dopant. The TVS device further including a fourth layer of wide band-gap semiconductor material formed of the first conductivity type material over at least a portion of the third layer. | 04-07-2016 |
| 20160099319 | SEMICONDUCTOR WAFER INCLUDING A MONOCRYSTALLINE SEMICONDUCTOR LAYER SPACED APART FROM A POLY TEMPLATE LAYER - A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate. | 04-07-2016 |
| 20160099345 | High Electron Mobility Transistor with Periodically Carbon Doped Gallium Nitride - A method for forming a high electron mobility transistor (HEMT) device with a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN), and an HEMT device formed by the method is disclosed. In one embodiment, the method includes forming a channel layer stack on a substrate, the channel layer stack having a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN). The method further includes forming a barrier layer on the channel layer stack. In one embodiment, the channel layer stack is formed by growing each of the one or more undoped gallium nitride (GaN) layers in growth conditions that suppress the incorporation of carbon in gallium nitride, and growing each of the one or more carbon doped gallium nitride (c-GaN) layers in growth conditions that promote the incorporation of carbon in gallium nitride. | 04-07-2016 |
| 20160104688 | Robust and Reliable Power Semiconductor Package - In one implementation, a semiconductor package includes a patterned conductive carrier including a support segment having a partially etched recess. The semiconductor package also includes an integrated circuit (IC) situated on the support segment, and an electrical connector coupling the IC to the partially etched recess. In addition, the semiconductor package includes a packaging dielectric formed over the patterned conductive carrier and the IC. The packaging dielectric interfaces with and mechanically engages the partially etched recess so as to prevent delamination of the electrical connector. | 04-14-2016 |
| 20160104703 | INTEGRATED ENHANCEMENT MODE AND DEPLETION MODE DEVICE STRUCTURE AND METHOD OF MAKING THE SAME - A circuit is provided that includes a castellated channel device that comprises a heterostructure overlying a substrate structure, a castellated channel device area formed in the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, and a three-sided castellated conductive gate contact that extends across the castellated channel device area. The three-sided gate contact substantially surrounds each ridge channel around their tops and their sides to overlap a channel interface of heterostructure of each of the plurality of ridge channels. The three-sided castellated conductive gate contact extends along at least a portion of a length of each ridge channel. | 04-14-2016 |
| 20160104780 | Semiconductor Devices and Methods of Manufacturing Thereof - In one embodiment, a method of forming a semiconductor device includes forming a first porous semiconductor layer over a top surface of a substrate. A first epitaxial layer is formed over the first porous semiconductor layer. A circuitry is formed within and over the first epitaxial layer. The circuitry is formed without completely oxidizing the first epitaxial layer. | 04-14-2016 |
| 20160111416 | INTEGRATED CIRCUIT WITH MATCHING THRESHOLD VOLTAGES AND METHOD FOR MAKING SAME - An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess. | 04-21-2016 |
| 20160111500 | TECHNIQUES FOR FORMING OPTOELECTRONIC DEVICES - Embodiments relate to use of a particle accelerator beam to form thin films of material from a bulk substrate are described. In particular embodiments, a bulk substrate having a top surface is exposed to a beam of accelerated particles. In certain embodiments, this bulk substrate may comprise GaN; in other embodiments this bulk substrate may comprise (111) single crystal silicon. Then, a thin film or wafer of material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. In certain embodiments this separated material is incorporated directly into an optoelectronic device, for example a GaN film cleaved from GaN bulk material. In some embodiments, this separated material may be employed as a template for further growth of semiconductor materials (e.g. GaN) that are useful for optoelectronic devices. | 04-21-2016 |
| 20160111503 | SEMICONDUCTOR DEVICE WITH IMPROVED FIELD PLATE - A transistor device includes a semiconductor body, a spacer layer, and a field plate. The spacer layer is over at least a portion of a surface of the semiconductor body. The field plate is over at least a portion of the spacer layer, and includes a first current carrying layer, a refractory metal interposer layer over the first current carrying layer, and a second current carrying layer over the refractory metal interposer layer. By including the refractory metal interposer layer between the first current carrying layer and the second current carrying layer, the electromigration of metals in the field plate is significantly reduced. Since electromigration of metals in the field plate is a common cause of transistor device failures, reducing the electromigration of metals in the field plate improves the reliability and lifetime of the transistor device. | 04-21-2016 |
| 20160111603 | Indium Zinc Oxide for Transparent Conductive Oxide Layer and Methods of Forming Thereof - Provided are light emitting diodes (LEDs) and methods of fabricating such LEDs. Specifically, an LED has an epitaxial stack and current distribution layer disposed on and interfacing the epitaxial stack. The current distribution layer includes indium oxide and zinc oxide such that the concentration of indium oxide is between about 5% and 15% by weight. During fabrication, the current distribution layer is annealed at a temperature of less than about 500° C. or even at less than about 400° C. These low anneal temperature helps preserving the overall thermal budget of the LED while still yielding a current distribution layer having a low resistivity and low adsorption. A particular composition and method of forming the current distribution layer allows using lower annealing temperatures. In some embodiments, the current distribution layer is sputtered using indium oxide and zinc oxide targets at a pressure of less than 5 mTorr. | 04-21-2016 |
| 20160118377 | METHOD OF FORMING A HIGH ELECTRON MOBILITY SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In one embodiment, a method of forming a semiconductor device can comprise; forming a HEM device on a semiconductor substrate. The semiconductor substrate provides a current carrying electrode for the semiconductor device and one or more internal conductor structures provide a vertical current path between the semiconductor substrate and regions of the HEM device. | 04-28-2016 |
| 20160118486 | SEMICONDUCTOR DEVICE - Semiconductor device including: silicon-based substrate; first buffer layer on silicon-based substrate and is formed of first layer containing Al composition and second layer containing less Al than the first layer, the first and second layers being alternately stacked; second buffer layer on the first buffer layer and is formed of third layer containing Al composition and fourth layer containing less Al than the third layer, the third and fourth layers being alternately stacked; and third buffer layer on the second buffer layer and is formed of fifth layer containing Al composition and sixth layer containing less Al than the fifth layer, the fifth and sixth layers being alternately stacked, wherein the second buffer layer contains more Al than the first and third buffer layers. Thus, the semiconductor device leakage can be suppressed while reducing stress which is applied to buffer layer and can improve flatness of active layer upper face. | 04-28-2016 |
| 20160118488 | FIELD EFFECT TRANSISTOR - In a field effect transistor, a carbon concentration in a buffer layer at the side closer to a high resistance layer is not less than 0.8×10 | 04-28-2016 |
| 20160118545 | LIGHT EMITTING DEVICE WITH ANTI-TOTAL-INTERNAL-REFLECTION CAPABILITY - A light emitting device includes: a light emitting layered structure; an electrode unit connected to the light emitting layered structure and including a transparent electrode layer of a primary metal oxide which is stacked on the light emitting layered structure along a stacking direction; and a total-internal-reflection suppression material dispersed in the transparent electrode layer and containing a secondary metal oxide that is different from the primary metal oxide. The secondary metal oxide has a concentration gradient within the transparent electrode layer along the stacking direction. The light output power of the light emitting device may be increased by about 44% as compared to a conventional light emitting device. | 04-28-2016 |
| 20160126206 | THICK-SILVER LAYER INTERFACE - A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer. | 05-05-2016 |
| 20160126312 | SEMICONDUCTOR STRUCTURE INCLUDING A DOPED BUFFER LAYER AND A CHANNEL LAYER AND A PROCESS OF FORMING THE SAME - A semiconductor structure can include a substrate, a high-voltage blocking layer overlying the substrate, a doped buffer layer overlying the high-voltage layer, and a channel layer overlying the doped buffer layer, wherein the doped buffer layer and the channel layer include a same compound semiconductor material, and the doped buffer layer has a carrier impurity type at a first carrier impurity concentration, the channel buffer layer has the carrier impurity type at a second carrier impurity concentration that is less than the first carrier impurity concentration. In an embodiment, the channel layer has a thickness of at least 650 nm. In another embodiment, the high-voltage blocking includes a proximal region that is 1000 nm thick and adjacent to the doped buffer layer, and each of the proximal region, the doped buffer layer, and the channel layer has an Fe impurity concentration less than 5×10 | 05-05-2016 |
| 20160126330 | THERMAL TREATED SEMICONDUCTOR/GATE DIELECTRIC INTERFACE FOR GROUP IIIA-N DEVICES - A method of fabricating a gate stack for a power transistor device includes thermally oxidizing a surface of a Group IIIA-N layer on a substrate to form a first dielectric layer of an oxide material that is >5 A thick. A second dielectric layer being silicon nitride or silicon oxynitride is deposited on the first dielectric layer. A metal gate electrode is formed on the second dielectric layer. | 05-05-2016 |
| 20160126342 | CARBON DOPING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device can include forming a III-N semiconductor layer in a reactor and injecting a hydrocarbon precursor into the reactor, thereby carbon doping the III-N semiconductor layer and causing the III-N semiconductor layer to be insulating or semi-insulating. A semiconductor device can include a substrate and a carbon doped insulating or semi-insulating III-N semiconductor layer on the substrate. The carbon doping density in the III-N semiconductor layer is greater than 5×10 | 05-05-2016 |
| 20160126419 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor light-emitting device including a base layer formed of a first conductivity-type semiconductor material, and a plurality of light-emitting nanostructures disposed on the base layer to be spaced apart from each other, and including first conductivity-type semiconductor cores, active layers, and second conductivity-type semiconductor layers. The first conductivity-type semiconductor cores include rod layers extending upwardly from the base layer, and capping layers disposed on the rod layers. Heights of the rod layers are different in at least a portion of the plurality of light-emitting nanostructures, and heights of the capping layers are different in at least a portion of the plurality of light-emitting nanostructures. | 05-05-2016 |
| 20160133612 | LED MODULE WITH LED CHIPS - Various embodiments may relate to an LED module, including a number of first inherently unpackaged LED chips, which are in each case designed to emit light of a first color at a respective light emission area, and a number of second inherently unpackaged LED chips, which are in each case designed to emit light of a second color, different than the first color, at a respective light emission area. The LED chips are provided jointly in a housing, and the respective light emission area of a second LED chip is at least 25% smaller than the respective light emission area of a first LED chip. The sum of the light emission areas of the first LED chips is at least 50% greater than the sum of the light emission areas of the second LED chips. | 05-12-2016 |
| 20160133708 | STRAIN COMPENSATED REO BUFFER FOR III-N ON SILICON - A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer. | 05-12-2016 |
| 20160133715 | SEMICONDUCTOR DEVICE - The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved. | 05-12-2016 |
| 20160133738 | HIGH ELECTRON MOBILITY TRANSISTOR AND MANUFACTURING METHOD THEREOF - A high electron mobility transistor is realized in the present invention by a gate recessed structure, a high permittivity oxide layer and a nitride-based interfacial passivation layer, featuring high threshold voltage, high transconductance, highly stable drain output current, and high reliability. | 05-12-2016 |
| 20160133785 | DEEP ULTRAVIOLET LED AND METHOD FOR MANUFACTURING THE SAME - A deep ultraviolet LED with a design wavelength of λ is provided that includes a reflecting electrode layer, a metal layer, a p-type GaN contact layer, and a p-type AlGaN layer that are sequentially stacked from a side opposite to a substrate, the p-type AlGaN layer being transparent to light with the wavelength of λ; and a photonic crystal periodic structure that penetrates at least the p-type GaN contact layer and the p-type AlGaN layer. The photonic crystal periodic structure has a photonic band gap. | 05-12-2016 |
| 20160133792 | SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME - A semiconductor substrate includes a substrate including a plurality of semispherical protrusions disposed at an interval on a first plane of the substrate, and a first semiconductor layer disposed on the first plane of the substrate. | 05-12-2016 |
| 20160133807 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE PACKAGE, AND LIGHTNING APPARATUS - A semiconductor device includes a light emitting structure, and an interconnection bump including an under bump metallurgy (UBM) layer disposed on an electrode of at least one of the first and second conductivity-type semiconductor layers, and having a first surface disposed opposite to a surface of the electrode and a second surface extending from an edge of the first surface to be connected to the electrode, an intermetallic compound (IMC) disposed on the first surface of the UBM layer, a solder bump bonded to the UBM layer with the IMC therebetween, and a barrier layer disposed on the second surface of the UBM layer and substantially preventing the solder bump from being diffused into the second surface of the UBM layer. | 05-12-2016 |
| 20160141354 | Patterned Back-Barrier for III-Nitride Semiconductor Devices - A compound semiconductor device includes a III-nitride buffer and a III-nitride barrier on the III-nitride buffer. The III-nitride barrier has a different band gap than the III-nitride buffer so that a two-dimensional charge carrier gas channel arises along an interface between the III-nitride buffer and the III-nitride barrier. The compound semiconductor device further includes a source and a drain spaced apart from one another and electrically connected to the two-dimensional charge carrier gas channel, a gate for controlling the two-dimensional charge carrier gas channel between the source and the drain, and a patterned III-nitride back-barrier buried in the III-nitride buffer. The patterned III-nitride back-barrier extends laterally beyond the gate towards the drain and terminates prior to the drain so that the patterned III-nitride back-barrier is laterally spaced apart from the drain by a region of the III-nitride buffer. | 05-19-2016 |
| 20160141404 | STRUCTURE FOR A GALLIUM NITRIDE (GaN) HIGH ELECTRON MOBILITY TRANSISTOR - A high-electron mobility transistor (HEMT) device employing a gate protection layer is provided. A substrate has a channel layer arranged over the substrate and has a barrier layer arranged over the channel layer. The channel and barrier layers define a heterojunction, and a gate structure is arranged over a gate region of the barrier layer. The gate structure includes a gate arranged over a cap, where the cap is disposed on the barrier layer. The gate protection layer is arranged along sidewalls of the cap and arranged below the gate between opposing surfaces of the gate and the cap. Advantageously, the gate protection layer passivates the gate, reduces leakage current along sidewalls of the cap, and improves device reliability and threshold voltage uniformity. A method for manufacturing the HEMT device is also provided. | 05-19-2016 |
| 20160141405 | Semiconductor Field Plate for Compound Semiconductor Devices - A transistor includes a source, a drain spaced apart from the source, and a heterostructure body having a two-dimensional charge carrier gas channel for connecting the source and the drain. The transistor further includes a semiconductor field plate disposed between the source and the drain. The semiconductor field plate is configured to at least partly counterbalance charges in the drain when the transistor is in an off state in which the channel is interrupted and a blocking voltage is applied to the drain. The counterbalance charge provided by the semiconductor field plate is evenly distributed over a plane or volume of the semiconductor field plate. Various semiconductor field plate configurations and corresponding manufacturing methods are described herein. | 05-19-2016 |
| 20160141447 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A method for producing a nitride semiconductor device. The method comprises providing a substrate made of a material other than a nitride semiconductor. The material has a hexagonal crystal structure. An upper face of the substrate has at least one flat section. The method further comprises growing a first nitride semiconductor layer on the upper face of the substrate. The first nitride semiconductor layer is made of monocrystalline AlN. The first nitride semiconductor layer has an upper face that is a +c plane. The first nitride semiconductor layer has a thickness in a range of 10 nm to 100 nm. The method further comprises growing a second nitride semiconductor layer on the upper face of the first nitride semiconductor layer. The second nitride semiconductor layer is made of In | 05-19-2016 |
| 20160141453 | LATTICE-MATCHED LIGHT EMITTING ELEMENT - A light emitting element and its manufacturing method are disclosed. A larger end face of a gallium nitride pyramid contacts with a mounting face of a gallium nitride layer disposed on a substrate, with c-axes of the gallium nitride layer and the gallium nitride pyramid coaxial to each other, and with M-planes of the gallium nitride layer and the gallium nitride pyramid parallel to each other. Broken bonds at contact faces of the gallium nitride pyramid and of the gallium nitride layer weld with each other after heating and cooling. A portion of an insulating layer coated on the gallium nitride pyramid and is removed to form an electrically conductive portion on which a first electrode is disposed. A portion of the insulating layer coated on the gallium nitride layer is removed to form another electrically conductive portion on which a second electrode is disposed. | 05-19-2016 |
| 20160148855 | PACKAGING DEVICE AND MANUFACTURING METHOD THEREOF - A packaging device including a first semiconductor device, a thermal dissipating component, an encapsulation layer, a via, and a pad. The first semiconductor device includes a substrate, an active region, and an electrode. The active region is disposed between the substrate and the electrode. The substrate has a first surface opposite to the active region, and the electrode has a second surface opposite to the active region. The thermal dissipating component is disposed on the first surface of the substrate. The encapsulation layer encloses the second surface of the electrode and a part of the thermal dissipating component, such that another part of the thermal dissipating component is exposed by the encapsulation layer. The pad is disposed on the encapsulation layer. The via is disposed in the encapsulation layer and connects the pad to the electrode. | 05-26-2016 |
| 20160148973 | LIGHT-EMITTING ELEMENT HAVING AN OPTICAL FUNCTION FILM INCLUDING A REFLECTION LAYER - A light-emitting element includes a light-emitting layer, and an optical function film. The light-emitting layer is configured to include a first plane with a first electrode, a second plane with a second electrode, and a circumferential plane connecting the first and second planes, the second plane being opposing to the first plane, and the light-emitting layer being made of a semiconductor. The optical function film is configured to include a reflection layer being able to reflect light coming from the light-emitting layer, the reflection layer being provided with first and second regions, the first region covering the second plane and the circumferential plane, the second region protruding from the first region to an outside of the light-emitting layer to expose an end plane thereof. | 05-26-2016 |
| 20160149024 | HIGH-ELECTRON MOBILITY TRANSISTOR AND PROCESS TO FORM THE SAME - An electron device formed by primarily nitrides semiconductor materials and a method to form the electron device are disclosed. The electron device includes, on the SiC substrate, a buffer layer of AlN, a channel layer of GaN, and an electron supplying layer of AlGaN. The AlGaN layer has the oxygen concentration higher than the carbon concentration in the whole thereof. The AlGaN layer is grown on the channel layer under conditions of: a ratio of the flow rate of the ammonia gas against the flow rate of the gases for Al and Ga is 5000 to 20000; and/or the growth, rate of the AlGaN layer is slower than 0.2 nm/sec. | 05-26-2016 |
| 20160149083 | SEMICONDUCTOR MATERIAL INCLUDING DIFFERENT CRYSTALLINE ORIENTATION ZONES AND RELATED PRODUCTION PROCESS - The invention relates to a manufacturing process of semiconductor material of element III nitride from a starting substrate, the process comprising:
| 05-26-2016 |
| 20160149096 | PROX REACTION APPARATUS FOR FUEL CELL - Provided is a white light emitting diode, which has excellent characteristics by using a UV chip of a specific wavelength band, and red, green blue and yellow phosphors. | 05-26-2016 |
| 20160155834 | III-Nitride Device Having a Buried Insulating Region | 06-02-2016 |
| 20160155835 | SEMICONDUCTOR DEVICE | 06-02-2016 |
| 20160163653 | SEMICONDUCTOR DEVICE - A semiconductor device and a method of making the same. The semiconductor device includes a semiconductor substrate mounted on a carrier. The semiconductor substrate includes a Schottky diode. The Schottky diode has an anode and a cathode. The semiconductor device also includes one or more bond wires connecting the cathode to a first electrically conductive portion of the carrier. The semiconductor device further includes one or more bond wires connecting the anode to a second electrically conductive portion of the carrier. The first electrically conductive portion of the carrier is electrically isolated from the second electrically conductive portion of the carrier. The first electrically conductive portion of the carrier is configured to provide shielding against electromagnetic interference associated with switching of the anode during operation of the device. Both the cathode and the first electrically conductive portion of the carrier are electrically isolated from a backside of the semiconductor substrate. | 06-09-2016 |
| 20160163802 | HIGH RESISTANCE LAYER FOR III-V CHANNEL DEPOSITED ON GROUP IV SUBSTRATES FOR MOS TRANSISTORS - Techniques are disclosed for using a high resistance layer between a III-V channel layer and a group IV substrate for semiconducting devices, such as metal-oxide-semiconductor (MOS) transistors. The high resistance layer can be used to minimize (or eliminate) current flow from source to drain that follows a path other than directly through the channel. In some cases, the high resistance layer may be a III-V wide bandgap layer. In some such cases, the wide bandgap layer may have a bandgap greater than 1.4 electron volts (eV), and may even have a bandgap greater than 2.0 eV. In other cases, the wide bandgap layer may be partially or completely converted to an insulator through oxidation or nitridation, for example. The resulting structures may be used with planar, finned, or nanowire/nanoribbon transistor architectures to help prevent substrate leakage problems. | 06-09-2016 |
| 20160163803 | NITRIDE SEMICONDUCTOR ELEMENT AND NITRIDE SEMICONDUCTOR WAFER - According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of Al | 06-09-2016 |
| 20160163846 | METALORGANIC CHEMICAL VAPOR DEPOSITION OF OXIDE DIELECTRICS ON N-POLAR III-NITRIDE SEMICONDUCTORS WITH HIGH INTERFACE QUALITY AND TUNABLE FIXED INTERFACE CHARGE - A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor. | 06-09-2016 |
| 20160163925 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor light-emitting device includes a light-emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer, microstructures regularly arranged on the first conductivity-type semiconductor layer around the light-emitting structure, and a gradient refractive layer on at least a portion of the microstructures, the gradient refractive layer having a lower refractive index than the first conductivity-type semiconductor layer. | 06-09-2016 |
| 20160172279 | Integrated Power Assembly with Reduced Form Factor and Enhanced Thermal Dissipation | 06-16-2016 |
| 20160172283 | Power Semiconductor Package Having Reduced Form Factor and Increased Current Carrying Capability | 06-16-2016 |
| 20160172284 | Integrated Power Assembly with Stacked Individually Packaged Power Devices | 06-16-2016 |
| 20160172353 | III-Nitride Switching Device with an Emulated Diode | 06-16-2016 |
| 20160172455 | RECESSED OHMIC CONTACTS IN A III-N DEVICE | 06-16-2016 |
| 20160172465 | PLANAR III-V FIELD EFFECT TRANSISTOR (FET) ON DIELECTRIC LAYER | 06-16-2016 |
| 20160172474 | Semiconductor Device and Method of Manufacturing Semiconductor Device | 06-16-2016 |
| 20160172475 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE | 06-16-2016 |
| 20160172535 | GaN BASE LIGHT-EMITTING DIODE AND MANUFACTURING METHOD THEREFOR USING MECHANICAL POST-PROCESSING | 06-16-2016 |
| 20160172541 | GALLIUM NITRIDE SELF-SUPPORTED SUBSTRATE, LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREFOR | 06-16-2016 |
| 20160181085 | INTEGRATION OF III-V DEVICES ON SI WAFERS | 06-23-2016 |
| 20160181232 | SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE | 06-23-2016 |
| 20160181411 | SEMICONDUCTOR DEVICE | 06-23-2016 |
| 20160181469 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF | 06-23-2016 |
| 20160181475 | SEMICONDUCTOR LIGHT-EMITTING DEVICE | 06-23-2016 |
| 20160190105 | DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE - A display device according to an embodiment of the present disclosure may include a lower substrate disposed with a line electrode at an upper portion thereof, a plurality of semiconductor light emitting devices electrically connected to the line electrode to generate light, a wavelength converter disposed on the semiconductor light emitting device to convert a wavelength of light generated from the semiconductor light emitting device, and a conductive adhesive layer comprising conductors configured to electrically connect the lower substrate to the semiconductor light emitting device and a body configured to surround the conductors, wherein the semiconductor light emitting device has a composition formula of In | 06-30-2016 |
| 20160190114 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device comprises a substrate, a patterned conductive layer, a first transistor structure and a second transistor structure. The patterned conductive layer is formed on the substrate. The first transistor structure includes a first source, a first gate and a first drain and is electrically connected to the patterned conductive layer by flip-chip bonding. The second transistor structure includes a second source, a second gate and a second drain and is electrically connected to the patterned conductive layer by flip-chip bonding. The first gate is electrically connected to the second source through the patterned conductive layer, and the first source is electrically connected to the second drain through the patterned conductive layer. | 06-30-2016 |
| 20160190259 | EPITAXIAL STRUCTURE AND GROWTH THEREOF - The invention provides an epitaxial growth structure and a growth method thereof. The epitaxial growth structure comprises a substrate, a plurality of seeds, a plurality of nanorods and a film. The seeds arranged in an array are disposed on a surface of the substrate. The nanorods are disposed longitudinally on the seeds, respectively. The film covers horizontally on upper surfaces of the nanorods to form a substantial plane. | 06-30-2016 |
| 20160190296 | GALLIUM NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR INCLUDING AN ALUMINUM GALLIUM NITRIDE BARRIER LAYER - A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure. | 06-30-2016 |
| 20160190297 | HIGH-ELECTRON-MOBILITY TRANSISTORS - High-electron-mobility transistors that include field plates are described. In a first implementation, a HEMT includes a first and a second semiconductor material disposed to form a heterojunction at which a two-dimensional electron gas arises and source, a drain, and gate electrodes. The gate electrode is disposed to regulate conduction in the heterojunction between the source electrode and the drain electrode. The gate has a drain-side edge. A gate-connected field plate is disposed above a drain-side edge of the gate electrode and extends laterally toward the drain. A second field plate is disposed above a drain-side edge of the gate-connected field plate and extends laterally toward the drain. | 06-30-2016 |
| 20160190298 | FORMING ENHANCEMENT MODE III-NITRIDE DEVICES - A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device. | 06-30-2016 |
| 20160190299 | SEMICONDUCTOR DEVICE HAVING VIA HOLE COATED IN SIDE SURFACES WITH HEAT TREATED NITRIDE METAL AND METHOD TO FORM THE SAME - A semiconductor device having a via hole whose side surface is covered with nitride metals is disclosed. The via hole is formed within an insulating region that surrounds a conductive region, where both regions are made of nitride semiconductor materials. The via hole is filled with a back metal and in side surfaces thereof is covered with a nitride metal which is heat treated at a preset temperature for a preset period. Nitrogen atoms in the nitride metal diffuse into the nitride semiconductor materials in the insulating regions and compensate nitride vacancies therein. The interface between the nitride metal and the nitride semiconductor material is converted into an altered region that shows high resistivity enough to suppress currents leaking from the via hole metal to the conductive region of the nitride semiconductor material. | 06-30-2016 |
| 20160190930 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including: a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected town input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode. | 06-30-2016 |
| 20160197027 | SEMICONDUCTOR DEVICE STRUCTURES COMPRISING POLYCRYSTALLINE CVD DIAMOND WITH IMPROVED NEAR-SUBSTRATE THERMAL CONDUCTIVITY | 07-07-2016 |
| 20160197151 | METHOD TO MAKE BURIED, HIGHLY CONDUCTIVE P-TYPE III-NITRIDE LAYERS | 07-07-2016 |
| 20160197203 | Group III-N lateral schottky barrier diode and method for manufacturing thereof | 07-07-2016 |
| 20160197235 | LIGHT-EMITTING ELEMENT | 07-07-2016 |
| 20160197246 | WHITE EMITTING LIGHT SOURCE AND LUMINESCENT MATERIAL | 07-07-2016 |
| 20160203972 | METHOD AND APPARATUS FOR FORMING DEVICE QUALITY GALLIUM NITRIDE LAYERS ON SILICON SUBSTRATES | 07-14-2016 |
| 20160204074 | DICING METHOD FOR POWER TRANSISTORS | 07-14-2016 |
| 20160204207 | Composite High-K Metal Gate Stack for Enhancement Mode GaN Semiconductor Devices | 07-14-2016 |
| 20160204241 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 07-14-2016 |
| 20160204242 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME | 07-14-2016 |
| 20160204254 | SEMICONDUCTOR DEVICE | 07-14-2016 |
| 20160204263 | IMPROVED CLADDING LAYER EPITAXY VIA TEMPLATE ENGINEERING FOR HETEROGENEOUS INTEGRATION ON SILICON | 07-14-2016 |
| 20160204276 | FORMING III-V DEVICE STRUCTURES ON (111) PLANES OF SILICON FINS | 07-14-2016 |
| 20160204308 | POWER LIGHT EMITTING DIODE AND METHOD WITH UNIFORM CURRENT DENSITY OPERATION | 07-14-2016 |
| 20160254377 | HETEROJUNCTION-BASED HEMT TRANSISTOR | 09-01-2016 |
| 20160254391 | N-TYPE ALUMINUM NITRIDE SINGLE-CRYSTAL SUBSTRATE AND VERTICAL NITRIDE SEMICONDUCTOR DEVICE | 09-01-2016 |
| 20160254395 | SUBSTRATES HAVING AN ANTIREFLECTION LAYER AND METHODS OF FORMING AN ANTIREFLECTION LAYER | 09-01-2016 |
| 20160254411 | SUBSTRATE HAVING ANNEALED ALUMINUM NITRIDE LAYER FORMED THEREON AND METHOD FOR MANUFACTURING THE SAME | 09-01-2016 |
| 20160380046 | III-Nitride Power Semiconductor Device - A power semiconductor device includes a III-nitride heterojunction body including a first III-nitride body and a second III-nitride body having a different band gap than that of the first III-nitride body, a first power electrode coupled to the second III-nitride body, a second power electrode coupled to the second III-nitride body, a gate arrangement disposed between the first and second power electrodes, and a conductive channel that includes a two-dimensional electron gas that in a conductive state includes a reduced charge region under the gate arrangement that is less conductive than its adjacent regions. The reduced charge region extends beyond an edge of the gate arrangement toward one of the power electrodes only. | 12-29-2016 |
| 20160380068 | SEMICONDUCTOR DEVICE - An emitter electrode includes a first electrode layer, a second electrode layer, and a third electrode layer. The first to third electrode layers are laid in this order on an emitter layer. A solder layer is further laid on the third electrode layer. The first electrode layer covers the emitter layer and a gate oxide film in a front surface of a semiconductor chip. A first electroconductive material forming the first electrode layer has AlSi as its main component. A second electroconductive material forming the second electrode layer has a linear expansion coefficient different from that of the first electroconductive material and is lower in mechanical strength than the first electroconductive material. A third electroconductive material constituting the third electrode layer has a linear expansion coefficient different from that of the first electroconductive material and has solder wettability higher than that of the first electrode layer. | 12-29-2016 |
| 20160380090 | GaN SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF FABRICATION BY SUBSTRATE REPLACEMENT - Devices and systems comprising high current/high voltage GaN semiconductor devices are disclosed. A GaN die, comprising a lateral GaN transistor, is sandwiched between an overlying header and an underlying composite thermal dielectric layer. Fabrication comprises providing a conventional GaN device structure fabricated on a low cost silicon substrate (GaN-on-Si die), mechanically and electrically attaching source, drain and gate contact pads of the GaN-on-Si die to corresponding contact areas of conductive tracks of the header, then entirely removing the silicon substrate. The exposed substrate-surface of the epi-layer stack is coated with the composite dielectric thermal layer. Preferably, the header comprises a ceramic dielectric support layer having a CTE matched to the GaN epi-layer stack. The thermal dielectric layer comprises a high dielectric strength thermoplastic polymer and a dielectric filler having a high thermal conductivity. This structure offers improved electrical breakdown resistance and effective thermal dissipation compared to conventional GaN-on-Si device structures. | 12-29-2016 |
| 20160380092 | III-Nitride Power Semiconductor Device - A power semiconductor device includes a III-nitride heterojunction body including a first III-nitride body and a second III-nitride body having a different band gap than that of the first III-nitride body, a first power electrode coupled to the second III-nitride body, a second power electrode coupled to the second III-nitride body, a gate array arrangement disposed between the first and second power electrodes, and a conductive channel that includes a two-dimensional electron gas that in a conductive state includes a reduced charge region under the gate arrangement that is less conductive than its adjacent regions. The reduced charge region extends beyond an edge of the gate arrangement toward one of the power electrodes only. | 12-29-2016 |
| 20160380104 | III-V GATE-ALL-AROUND FIELD EFFECT TRANSISTOR USING ASPECT RATIO TRAPPING - Embodiments of the invention provide methods for forming III-V gate-all-around field effect transistors on silicon substrates that utilize Aspect-Ratio Trapping to reduce or eliminate dislocation defects associated with lattice mismatches. A field dielectric material defining a trench is formed on a crystalline silicon substrate. A channel feature comprising III-V material is subsequently formed inside the trench. Source/drain features are then formed at both ends of the channel feature inside the trench. Lastly, gate dielectric layers and a gate feature are formed surrounding a portion of the channel feature. | 12-29-2016 |
| 20160380119 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first nitride semiconductor layer of a semiconductor device is provided on a substrate, a second nitride semiconductor layer is provided on the first nitride semiconductor layer, a first ohmic metal and a second ohmic metal are provided on the second nitride semiconductor layer, a recess region is provided in the second nitride semiconductor layer between the first ohmic metal and the second ohmic metal, a passivation layer covers side of the first ohmic metal and a bottom surface and sides of the recess region, and a Schottky electrode is provided on the first ohmic metal and extends into the recess region. | 12-29-2016 |
| 20160380152 | NITRIDE SEMICONDUCTOR TEMPLATE AND ULTRAVIOLET LED - A nitride semiconductor template includes a Ga | 12-29-2016 |
| 20160380153 | SUBSTRATE, METHOD OF PREPARING THE SAME, AND LIGHT-EMITTING DIODE USING THE SUBSTRATE - The present invention relates to a gallium nitride substrate, a method of preparing the gallium nitride substrate, and a double-sided light-emitting diode using the gallium nitride substrate. The gallium nitride substrate has a first face having a Ga-polar face and a second face having an N-polar face. Protrusions with semi-polar surfaces are formed on the second face. A light-emitting body may be formed on the first face, and a separate light-emitting body may be formed through the surfaces of the protrusions. | 12-29-2016 |
| 20170236704 | WURTZITE HETEROEPITAXIAL STRUCTURES WITH INCLINED SIDEWALL FACETS FOR DEFECT PROPAGATION CONTROL IN SILICON CMOS-COMPATIBLE SEMICONDUCTOR DEVICES | 08-17-2017 |
| 20170236909 | HIGH ELECTRON MOBILITY TRANSISTOR AND FABRICATION METHOD THEREOF | 08-17-2017 |
| 20170236912 | Spatial terahertz wave phase modulator based on high electron mobility transistor | 08-17-2017 |
| 20170236928 | LOW SHEET RESISTANCE GaN CHANNEL ON Si SUBSTRATE USING InAlN AND AlGaN BI-LAYER CAPPING STACK | 08-17-2017 |
| 20170236936 | WIDE BAND GAP TRANSISTOR ON NON-NATIVE SEMICONDUCTOR SUBSTRATES AND METHODS OF MANUFACTURE THEREOF | 08-17-2017 |
| 20170236951 | STRUCTURES FOR NITRIDE VERTICAL TRANSISTORS | 08-17-2017 |
| 20180026106 | Enhancement Mode Field-Effect Transistor with a Gate Dielectric Layer Recessed on a Composite Barrier Layer for High Static Performance | 01-25-2018 |
| 20180026107 | SEMICONDUCTOR DEVICE, POWER CIRCUIT, COMPUTER, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 01-25-2018 |
| 20180026108 | SEMICONDUCTOR DEVICE, POWER CIRCUIT, AND COMPUTER | 01-25-2018 |
| 20180026123 | BOND-OVER-ACTIVE CIRCUITY GALLIUM NITRIDE DEVICES | 01-25-2018 |
| 20180026124 | SEMICONDUCTOR DEVICE, POWER CIRCUIT, AND COMPUTER | 01-25-2018 |
| 20180026126 | Heterostructure Power Transistor with AlSiN Passivation Layer | 01-25-2018 |
| 20180026156 | Light Emitting Diode and Fabrication Method Thereof | 01-25-2018 |
| 20190148332 | REINFORCEMENT FOR ELECTRICAL CONNECTORS | 05-16-2019 |
| 20190148498 | Passivation Structure For GaN Field Effect Transistor | 05-16-2019 |
| 20190148533 | SEMICONDUCTOR DEVICES WITH RAISED DOPED CRYSTALLINE STRUCTURES | 05-16-2019 |
| 20190148594 | SEMICONDUCTOR OPTICAL DEVICE | 05-16-2019 |
| 20220139709 | CONFINED GALLIUM NITRIDE EPITAXIAL LAYERS - A method of manufacturing an electronic device is provided. The method includes forming a dielectric layer on a Si-based substrate, etching away portions of the dielectric layer to form a crisscrossing grid pattern of remaining portions of the dielectric layer and to expose the substrate in areas where the dielectric layer is removed, forming GaN-based layers on the substrate in growth areas between sidewalls of the remaining portions of the dielectric layer, and forming a semiconductor device on the GaN-based layers. | 05-05-2022 |
| 20220140089 | PARASITIC CHANNEL MITIGATION USING SILICON CARBIDE DIFFUSION BARRIER REGIONS - Semiconductor structures and methods of forming semiconductor structures that inhibit the conductivity of parasitic channels are described. In one example, a semiconductor structure includes a semiconductor substrate and a III-nitride material region over a top surface of the semiconductor substrate. The semiconductor substrate includes a bulk region below the top surface and a parasitic channel that extends to a depth from the top surface toward the bulk region of the semiconductor substrate. The parasitic channel comprises a first region and a second region. The first region of the parasitic channel comprises an implanted species having a relative atomic mass of less than 5, and the second region of the parasitic channel is free from the implanted species or the implanted species is present in the second region at a concentration that is less than in the first region. | 05-05-2022 |
| 20220140130 | VERTICAL FIELD EFFECT TRANSISTOR DEVICE AND METHOD OF FABRICATION - A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p− type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n− type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region. | 05-05-2022 |
| 20220140201 | MOLECULAR COATINGS OF NITRIDE SEMICONDUCTORS FOR OPTOELECTRONICS, ELECTRONICS, AND SOLAR ENERGY HARVESTING - Gallium nitride based semiconductors are provided having one or more passivated surfaces. The surfaces can have a plurality of thiol compounds attached thereto for enhancement of optoelectronic properties and/or solar water splitting properties. The surfaces can also include wherein the surface has been treated with chemical solution for native oxide removal and/or wherein the surface has attached thereto a plurality of nitrides, oxides, insulating compounds, thiol compounds, or a combination thereof to create a treated surface for enhancement of optoelectronic properties and/or solar water splitting properties. Methods of making the gallium nitride based semiconductors are also provided. Methods can include cleaning a native surface of a gallium nitride semiconductor to produce a cleaned surface, etching the cleaned surface to remove oxide layers on the surface, and applying single or multiple coatings of nitrides, oxides, insulating compounds, thiol compounds, or a combination thereof attached to the surface. | 05-05-2022 |
