Class / Patent application number | Description | Number of patent applications / Date published |
205125000 | Product is circuit board or printed circuit | 56 |
20080251386 | Manufacturing Method Of Non-Etched Circuit Board - A manufacturing method of a non-etched circuit board is disclosed herein, which employs a metal substrate having a metal barrier layer and an electroplated copper layer to transmit an electrical current to form a circuit layer. A patterned photoresist layer is formed on the electroplated copper layer to define the location of the circuit layer and form circuits or conductive via on the board by electroplating. An electroplated nickel layer or an electroplated gold layer is further formed on the circuit layer for protecting the circuits and improving the fine line capability. During or after the process, the metal substrate, the metal barrier layer, and the electroplated copper layer are removed to enlarge the wiring space, so that a high-density circuit board can be obtained. | 10-16-2008 |
20080251387 | Wiring Board and Production Method Thereof - It is an object of the present invention to provide a wiring board having high-density wiring with a controlled shape without masking by a resist film and a production method thereof. In the present invention, the production method of a wiring board having copper wiring on an insulating substrate includes the steps of forming a metal seed layer on the insulating substrate, the metal seed layer having a roughened shape in a portion on which the copper wiring or a bump is to be formed, and forming an electroplated film of copper or an alloy of copper through electroplating on the portion of the metal seed layer having the roughened shape. A substance for suppressing the plating reaction is added to a plating bath to provide an angle of 90 degrees or smaller between a surface of the insulating substrate and a side of the electroplated film. | 10-16-2008 |
20090000951 | Method for Forming Electroconductive Circuit - An electroconductive circuit, in which a masking material and a substrate both have low dielectric loss tangent to high-frequency signal and have excellent adhesion to each other, can be formed in a simple and low-cost manner. A cycloolefin resin with a flexible polymer mixed and dispersed therein is injection molded to form a primary substrate | 01-01-2009 |
20090078578 | PRE-PLATING SOLUTIONS FOR MAKING PRINTED CIRCUIT BOARDS AND METHODS FOR PREPARING THE SAME - A pre-plating solution for making a printed circuit board includes carbon nanotubes of 0.01-3 wt %, a surfactant of 0.01-4 wt %, an alkaline substance of 0.01-l wt % and a solvent. A method for preparing a pre-plating solution comprising the steps of: providing a plurality of carbon nanotubes; purifying the carbon nanotubes; treating the purified carbon nanotubes with an acid; mixing the treated carbon nanotubes, an alkaline substance and a solvent to form suspension; and adding surfactant into suspension. | 03-26-2009 |
20090101510 | High density printed circuit board and method of manufacturing the same - The present invention relates to a high density printed circuit board and a method of manufacturing the same which enable a thin printed circuit board to be manufactured and can overcome problems occurring in a conventional method of manufacturing a printed circuit board because a conventional CCL is not used as a raw material. The high density printed circuit board includes a first insulating layer having a constant thickness, and a pair of first circuit layers embedded in two sides of the first insulating layer, respectively. | 04-23-2009 |
20090242411 | POLYIMIDE-METAL LAMINATED BODY AND POLYIMIDE CIRCUIT BOARD - A process for producing a polyimide-metal laminated body includes forming a metal conductive layer on a polyimide film having a ceramic-modified or pseudoceramic-modified surface with a wet plating process which includes forming at least a ground treatment layer by electroless plating, conducting electroless metal plating and conducting electrolytic copper plating. | 10-01-2009 |
20090294294 | Acid-resistance promoting composition - A composition for providing acid resistance to copper surfaces in the production of multilayered printed circuit boards. The composition comprises an acid, an oxidizer, a five-membered heterocyclic compound and a thiophosphate or a phosphorous sulfide compound. In a preferred embodiment, the phosphorous compound is phosphorus pentasulfide. The composition is applied to a copper or copper alloy substrate and the copper substrate is thereafter bonded to a polymeric material. | 12-03-2009 |
20090301891 | DEVICE AND METHOD FOR ELECTROPLATING - The invention relates to a device for the electrolytic coating of a structured or full-surface base layer ( | 12-10-2009 |
20090321266 | METHOD FOR MANUFACTURING PRINTED-CIRCUIT BOARD - There is provided a method for manufacturing a printed circuit board having an insulative board and a plurality of electroconductive pads arranged in a grid shape on the insulative board, the method comprising: a step for forming an electroconductive film on the insulative board; a step for forming a pattern on the electroconductive film so as to form the electroconductive pads, a lead wire connected to at least one of the electroconductive pads, and inter-pad wiring for electrically connecting each of the electroconductive pads not connected to the lead wire to any of the electroconductive pads connected to the lead wire, the inter-pad wiring being disposed between mutually adjacent electroconductive pads; a step for plating each of the electroconductive pads by immersing the insulative board in a plating bath and energizing each of the electroconductive pads through the lead wire; and a step for removing the inter-pad wiring. | 12-31-2009 |
20100006446 | Method for manufacturing package on package with cavity - A method for manufacturing a printed circuit board with an inner via hole, the method including applying a first current to both surfaces of a core layer having the inner via hole, so that a first plating layer grows centerwardly in an equal rate from all the directions of an inner wall of the inner via hole to close one entrance of the inner via hole, leaving a remaining space the inner via hole unfilled; and applying a second current to fill the remaining space of the inner via hole. Also, the manufacturing method does not require filling an inner via hole with an insulating ink, and forming a conductive layer on the insulating ink. Therefore, the method increases productive capacity and reduces manufacturing cost by simplifying the manufacturing process and reducing the lead time. | 01-14-2010 |
20100044237 | METHOD FOR MANUFACTURING PRINTED CIRCUIT BOARDS - A method for manufacturing a PCB is related. The method includes providing a substrate with two opposite conductive layers and defining a through hole passing through the two conductive layers; forming a first electrically conductive metal layer on an inner surface of the substrate in the through hole using an electro-less plating process; forming a second electrically conductive metal layer on the first electrically conductive metal layer using an electro-plating process till the through hole being filled. | 02-25-2010 |
20100140100 | MANUFACTURING METHOD OF PRINTED CIRCUIT BOARD - Disclosed is a method of manufacturing a printed circuit board. The method can include providing a carrier formed with a release layer, performing a roughening treatment on the release layer such that the release layer has surface roughness, forming a circuit pattern on the release layer, stacking the carrier on an insulating layer such that the circuit pattern is buried in the insulating layer, and separating the release layer and the carrier from the insulating layer and the circuit pattern. | 06-10-2010 |
20100243461 | METHOD OF FABRICATING CIRCUIT BOARD - A method of fabricating a circuit board includes: forming an adhesion auxiliary layer on a surface of an insulating base board; forming an adhesion layer on a surface of the adhesion auxiliary layer, the adhesion layer comprising a polymer compound having a polymerizable group and a functional group capable of interacting with a plating catalyst or a precursor thereof; fixing the adhesion layer to the adhesion auxiliary layer by applying energy to the adhesion layer; applying a plating catalyst or a precursor thereof to the adhesion layer; forming a first metal film by electroless plating on the adhesion layer; and performing electroplating by using the first metal film; and the method further includes partly removing, by irradiating a laser beam, an area corresponding to a non-circuit portion in any of the adhesion auxiliary layer, the adhesion layer, or the first metal film. | 09-30-2010 |
20110011746 | Aqueous, Acid Bath and Method for the Electrolytic Deposition of Copper - To generate a very uniform copper deposit in particular in blind micro vias (BMVs) and trenches, an aqueous, acid bath for the electrolytic deposition of copper is provided, said bath containing at least one copper ion source, at least one acid ion source, at least one brightener compound and at least one leveler compound, wherein at least one leveler compound is selected from the group comprising synthetically produced non-functionalized peptides and synthetically produced functionalized peptides and synthetically produced functionalized amino acids. | 01-20-2011 |
20110056838 | METHOD OF MANUFACTURING PRINTED WIRING BOARD - A printed wiring board is manufactured by a method in which an opening is formed in a substrate, and a seed layer for electrolytic plating is formed on an inner wall of the opening and a surface of the substrate. The substrate with the seed layer is placed in an electrolytic plating solution, and an insulative body is placed in the electrolytic plating solution. The substrate and the insulative body are moved relative to each other to form an electrolytic plated film on the substrate and fill the opening with the electrolytic plated film. A conductive circuit is formed on the substrate. The electrolytic plating solution includes copper sulfate, sulfuric acid, and iron ions. | 03-10-2011 |
20110062029 | ELECTROLYTIC COPPER PLATING BATH AND METHOD FOR ELECTROPLATING USING THE ELECTROLYTIC COPPER PLATING BATH - For use for a circuit board where a through hole and a blind via hole co-exist, an electrolytic copper plating bath in which the covering power for the through hole and the plugging performance for the blind via hole are sufficient, and an electroplating method that uses the electrolytic copper plating bath, are disclosed. The electrolytic copper plating bath is mainly composed of a water-soluble copper salt, sulfuric acid and chloride ions. A polyamide polyamine, obtained on processing by heating of an epichlorohydrin modified product of a polycondensation product of diethylene triamine, adipic acid and ε-caprolactam, is contained in the bath as a leveler. | 03-17-2011 |
20110073482 | PLATING APPARATUS - A plating apparatus for use in forming a plated film in trenches, via holes, or resist openings that are defined in a surface of a semiconductor wafer, and forming bumps to be electrically connected to electrodes of a package, on a surface of a semiconductor wafer. The plating apparatus has a plating tank for holding a plating solution, a holder for holding a workpiece and bringing a surface to be plated of the workpiece into contact with the plating solution in the plating tank, and a ring-shaped nozzle pipe disposed in the plating tank and having a plurality of plating solution injection nozzles for injecting the plating solution to the surface to be plated of the workpiece held by the holder to supply the plating solution into the plating tank. | 03-31-2011 |
20110266156 | METHOD OF FORMING SOLID BLIND VIAS THROUGH THE DIELECTRIC COATING ON HIGH DENSITY INTERCONNECT (HDI) SUBSTRATE MATERIALS - A method includes forming a first substrate by (a) applying an electrodepositable dielectric coating onto a conductive surface; (b) curing the dielectric coating; (c) depositing an adhesion layer and a seed layer onto the dielectric coating; (d) applying a layer of a first removable material to the seed layer; (e) forming openings in the first removable material to expose areas of the seed layer; (f) electroplating a first conductive material to the exposed areas of the seed layer; (g) applying a layer of a second removable material; (h) forming openings in the second removable material to expose areas of the first conductive material; (i) plating a second conductive material to the exposed areas of the first conductive material; (j) removing the first and second removable materials; (k) removing unplated portions of the seed layer; repeating steps (a) through (k) to form a second substrate; and laminating the first and second substrates together with a layer of dielectric material between the first and second substrates to form at least one interconnect between the first and second substrates. | 11-03-2011 |
20110272286 | METHOD OF MANUFACTURING MULTILAYER PRINTED WIRING BOARD - A method of manufacturing a multilayer printed wiring board includes forming a first interlaminar resin insulating layer, a first conductor circuit on the first interlaminar resin insulating layer, a second interlaminar resin insulating layer, opening portions in the second interlaminar resin insulating layer to expose a face of the first conductor circuit, an electroless plating film on the second interlaminar resin insulating layer and the exposed face, and a plating resist on the electroless plating film. The method further includes substituting the electroless plating film with a thin film conductor layer, having a lower ion tendency than the electroless plating film, and a metal of the exposed face, forming an electroplating film including the metal on a portion of the electroless plating film and the thin film conductor layer, stripping the plating resist, and removing the electroless plating film exposed by the stripping. | 11-10-2011 |
20120012464 | PRINTED WIRING BOARD AND A METHOD OF PRODUCTION THEREOF - A method for manufacturing a printed wiring board including providing an insulating resin substrate having first and second surfaces, irradiating laser upon the first surface such that a first opening portion having an opening on the first surface and tapering inward is formed, irradiating laser upon the second surface such that a second opening portion having an opening on the second surface, tapering inward and communicated to the first opening portion is formed and that a penetrating-hole having the first and second opening portions is formed, forming an electroless plated film on an inner wall surface of the penetrating-hole, and forming an electrolytic plated film on the electroless plated film such that a through hole conductor structure is formed in the penetrating-hole. The opening of the first portion has an axis of the center of gravity offset with respect to that of the opening of the second opening portion. | 01-19-2012 |
20120055800 | METHOD FOR FORMING PLATING LAYER OF PRINTED CIRCUIT BOARD - Disclosed herein is a method for forming a plating layer of a printed circuit board. A deviation in plating thickness of a copper plating layer filled in a circuit pattern part and a through-hole part in a SIP product group having a narrow through-hole pitch and a large through-hole volume may be reduced. To this end, there is provided a method for forming a plating layer of a printed circuit board, the method including: processing a though-hole in a copper clad lamination (CCL); forming a seed plating layer in the through hole; applying a resist on the CCL and the seed plating layer and exposing and developing the resist; forming a primary plating layer on the seed plating layer; forming a copper plating layer on the primary plating layer; and removing the resist remaining on the primary plating layer and the seed plating layer to thereby form patterns. | 03-08-2012 |
20120085655 | INTERPOSER AND MANUFACTURING METHOD FOR THE SAME - In a manufacturing method for an interposer, a seed layer is formed at an opening portion in a through hole on back surface side of a substrate, an electrode layer for electroplated coating is formed based on the seed layer, and an electroplated coating layer is formed to fill the through hole from the electrode layer for electroplated coating layer to a front surface side. As a result, a manufacturing method for an interposer is provided in which the manufacturing process is simple and the void is not generated inside of the through hole. | 04-12-2012 |
20120132530 | TIN PLATING SOLUTION - To provide a tin plating solution having uniformity of through-hole plating, uniformity of film thickness distribution and no burn deposits even. The tin plating solution include a tin ion source, at least one non-ionic surfactant, imidazoline dicarboxylate and 1,10-phenanthroline. | 05-31-2012 |
20120132531 | Process and Apparatus for Producing a Metal Covered Polyimide Composite - A metal covered polyimide composite comprising a tie-coat layer and a metal seed layer formed on a surface of a polyimide film by electroless plating or a drying method is provided. A copper layer or a copper alloy layer is formed thereon by electroplating. The copper plated layer or copper alloy plated layer includes three layers to one layer of the copper layer or copper alloy layer. The metal covered polyimide composite effectively prevents peeling in a non-adhesive flexible laminate (especially a two-layer flexible laminate), and more particularly, effectively inhibits peeling from the interface of a copper layer and tin plating. A method of producing the composite and apparatus for producing the composite are also provided. | 05-31-2012 |
20120152753 | METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD - Disclosed herein is a method of manufacturing a printed circuit board that simultaneously forms a via and an embedding land and thus improves the matching value of the via and the embedding land to secure interlayer conduction reliability, and further simultaneously forms the via and the embedding land to reduce manufacturing costs. In addition, the embedding land is formed to be embedded in the second insulating layer to implement high-density/high-integration of the printed circuit board and a via is formed in less time as compared to a method of forming a via hole using laser to reduce a process time. | 06-21-2012 |
20120175265 | CIRCUIT BOARD SURFACE STRUCTURE AND FABRICATION METHOD THEREOF - A circuit board surface structure and a fabrication method thereof are proposed. The circuit board surface structure includes: a circuit board having a plurality of electrically connecting pads formed on at least one surface thereof; a first and a second insulating protective layers formed on the surface of the circuit board in sequence; first and a second openings respectively formed in the first and second insulating protective layers to expose the electrically connecting pads on the surface of the circuit board, wherein the first and second openings have narrow top and wide bottom and the diameter of the first openings is bigger than that of the second openings; and conductive elements formed in the first and second openings on surfaces of the electrically connecting pads. The present structure facilitates to strengthen the bonding between the conductive elements and the corresponding electrically connecting pads. | 07-12-2012 |
20120279865 | Touch Fingerprint Sensor Using 1-3 Piezo Composites and Acoustic Impediography Principle - Provided herein is a method of making an integrated circuit device using copper metallization on 1-3 PZT composite. The method includes providing an overlay of electroplated immersion of gold (Au) to cover copper metal traces, the overlay preventing oxidation on 1:3 PZT composite with material. Also included is the formation of immersion Au nickel electrodes on the 1-3 PZT composite to achieve pad metallization for external connections. | 11-08-2012 |
20120298517 | METHOD OF MAKING WEAR-RESISTANT PRINTED WIRING MEMBER - A method for making a printed wiring member including wire-bondable contact pads and wear-resistant connector pads, the method includes a) providing a blank printed wiring member comprising a copper foil laminated to a dielectric substrate; b) masking the blank printed wiring member to protect regions of the copper foil; c) removing copper in unprotected regions of the blank printed wiring member to form a patterned printed wiring member including contact pads and connector pads; d) depositing a nickel coating on the patterned printed wiring member; e) electrolytically depositing a hard gold layer on the nickel coating; and f) depositing palladium on a surface of the hard gold layer to improve bondability of the contact pads while preserving wear resistance of the connector pads. | 11-29-2012 |
20130032485 | METHOD OF FABRICATING CIRCUIT BOARD - A method of fabricating a circuit board including at least one insulation layer and at least one wiring layer, the method including a first step of forming a wiring trench in a surface of the insulation layer, a second step of forming a conductor layer serving as the wiring layer in the wiring trench such that at least a portion of the conductor layer is embedded in the wiring trench, and a third step of cutting a surface of the conductor layer with a cutting tool to form the wiring layer. | 02-07-2013 |
20130056362 | MANUFACTURE METHOD OF BUILDUP CIRCUIT BOARD - A manufacturing method of a buildup circuit board includes forming a wiring layer on an organic polymer insulating layer by copper electroplating and building up other organic polymer insulating layer on the wiring layer, wherein in a final step of the copper electroplating, a surface of the wiring layer is roughened by copper electroplating and the organic polymer insulating layer is formed directly on the roughened surface of the wiring layer. According to the invention, a specific etching step that is essential for enhancing adhesion between the organic polymer insulating layer and the wiring layer can be omitted and no expensive etching apparatus is necessary, thus being good in economy. In addition, if various types of copper sulfate plating baths containing different types of additives used for via fill plating are used as they are, irregularities on the surface can be made in various forms and roughnesses. Thus, it is necessary to select a specific type of etching solution depending on film characteristics ascribed to types of additives. Moreover, it is easy to form surface irregularities in conformity with the type of material and physical properties of the organic polymer insulating layer being built up. | 03-07-2013 |
20130105329 | METHOD TO FORM SOLDER DEPOSITS AND NON-MELTING BUMP STRUCTURES ON SUBSTRATES | 05-02-2013 |
20130112566 | METHOD FOR ETCHING OF COPPER AND COPPER ALLOYS - The present invention is concerned with improved means for etching circuit structures on printed circuit board or wafer substrates of copper or copper alloys in a manner effectively removing unwanted copper from such circuit structures leaving behind a smooth copper surface applying an etching solution containing an Fe(II)/Fe(III) redox system and sulfur containing organic additives. It is an advantage of the present invention that the solution can also applied for plating of copper prior to etching. | 05-09-2013 |
20140014521 | FLEXIBLE CIRCUIT BOARD AND METHOD FOR MANUFACTURING SAME - An object of the present invention is to provide a flexible circuit board that maintains high insulation reliability, exhibits high wiring adhesion, has low thermal expansion, and allows the formation of a fine circuit thereon. Specifically, the present invention provides a flexible circuit board, wherein at least a nickel plating layer is laminated on a polyimide film to form a polyimide film provided with a nickel plating layer and a wiring pattern is applied to the nickel plating layer thereof. The polyimide film has a thermal expansion coefficient of 0 to 8 ppm/° C. in the temperature range from 100 to 200° C., and the nickel plating layer has a thickness of 0.03 to 0.3 μm. | 01-16-2014 |
20140116885 | NON-DELETERIOUS TECHNIQUE FOR CREATING CONTINUOUS CONDUCTIVE CIRCUITS UPON THE SURFACES OF A NON-CONDUCTIVE SUBSTRATE - A non-deleterious method for producing a continuous conductive circuit upon a non-conductive substrate can begin with the application of a metallic base layer upon a surface of a non-conductive substrate. A circuit pattern can be created within the metallic base layer based upon a circuit design. The metallic base layer comprising the circuit pattern can be physically separated from the remainder of the metallic base layer on the non-conductive substrate. The region of the non-conductive substrate surface that encloses the circuit pattern can be called the plating region. The remainder of the non-conductive substrate surface can be called the non-plating region. A first metal layer can be added upon the metallic base layer. A second metal layer can be added upon the first metal layer of the plating region. The second metal layer can be electrically conductive and restricted from forming on the first metal layer of the non-plating region. | 05-01-2014 |
20140166495 | SUBSTRATE FOR PRINTED WIRING BOARD, PRINTED WIRING BOARD, AND METHODS FOR PRODUCING SAME - Provided are a substrate for a printed wiring board, and a printed wiring board, which are not limited in size because vacuum equipment is not necessary for the production, in which an organic adhesive is not used, and which can include a conductive layer (copper foil layer) having a sufficiently small thickness. Also provided are a method for producing the substrate for a printed wiring board, and a method for producing the printed wiring board. A substrate | 06-19-2014 |
20140174940 | HEAT-DISSIPATING SUBSTRATE AND FABRICATING METHOD THEREOF - Embodiments of the invention provide a heat-dissipating substrate and a fabricating method of the heat-dissipating substrate. According to various embodiments, the heat-dissipating substrate includes a plating layer divided by a first insulator formed in a division area. A metal plate is formed on an upper surface of the plating layer and filled with a second insulator at a position corresponding to the division area, with an anodized layer formed on a surface of the metal plate. A circuit layer is formed on the anodized layer which is formed on an upper surface of the metal plate. The heat-dissipating substrate and fabricating method thereof achieves thermal isolation by a first insulator formed in a division area and a second insulator. | 06-26-2014 |
20140197037 | TREATMENT METHOD OF ELECTRODEPOSITED COPPER FOR WAFER-LEVEL-PACKAGING PROCESS FLOW - A method of treating a copper containing structure on a substrate is disclosed. The method includes electrodepositing the copper containing structure on a substrate, annealing the copper containing structure, and forming an interface between a pad of the copper containing structure and a solder structure after anneal. The interface can have improved resistance to interfacial voiding. The copper containing structure is configured to deliver current between one or more ports and one or more solder structures in the integrated circuit package. Annealing the copper containing structure can move impurities and vacancies to the surface of the copper containing structure for subsequent removal. | 07-17-2014 |
20140284217 | MINIMIZING PLATING STUB REFLECTIONS IN A CHIP PACKAGE USING CAPACITANCE - The present invention is directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a method including capacitively coupling a plating stub to ground so that the resonant frequency caused by the plating stub in a semiconductor package is shifted away from an operational frequency. | 09-25-2014 |
20140339094 | PRODUCTION METHOD AND DEVICE OF SURFACE ROUGHENED COPPER PLATE, AND SURFACE ROUGHENED COPPER PLATE - PROBLEMS TO BE SOLVED: To provide a process for roughening both sides of a copper plate by forming a protrusion with a fine bump shape on the both sides of the copper plate, and then to provide a process for a deterioration of an electroplating solution for plating copper to become hard to progress therein. | 11-20-2014 |
20150108003 | METHOD FOR PRODUCING CERAMIC CIRCUIT BOARDS FROM CERAMIC SUBSTRATES HAVING METAL-FILLED VIAS - A method for producing ceramic circuit boards from ceramic substrates having metal-filled vias. In order to be able to fill the vias by means of a single filling process, either a planar copper metallization is applied on one side to the ceramic substrate having vias by means of scren printing, or a copper film of 100-300 μm is bonded on one side to the ceramic substrate having vias in a DCB/DBC process and the vias are filled from the ceramic side by means of an electrogalvanic process in a copper bath by the deposition of copper. | 04-23-2015 |
20150303074 | PROCESS FOR FABRICATING THE SAME - A process for fabricating a circuit substrate is provided. The process includes the following steps. A carrier is provided. A conductive layer and a dielectric layer are placed on the carrier, and the conductive layer is located between the carrier and the dielectric layer. The dielectric layer is patterned to form a patterned-dielectric layer having first openings partially exposing the conductive layer. Arc-shaped grooves are formed on the exposed part of the conductive layer. A first-patterned-photoresist layer having second openings respectively connecting the first openings is formed. Conductive structures are formed, wherein each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part; the second openings, the first openings and the arc-shaped grooves are respectively filled with the pad parts, the connection parts and the protruding parts. The first patterned photoresist layer, the carrier and the conductive layer are removed. | 10-22-2015 |
20150351257 | METHOD FOR PRODUCING WIRING BOARD - A method for producing a wiring board includes the steps of forming an upper insulating layer on a lower insulating layer having a lower wiring conductor on its upper surface; forming a via-hole in the upper insulating layer; depositing a first base metal layer in the via-hole and on an upper surface of the upper insulating layer; forming a first plating resist layer on the first base metal layer; depositing a first electrolytically plated layer to completely fill at least the via-hole; forming a via conductor, and depositing a second base metal layer; forming a second plating resist layer on the second base metal layer; depositing a second electrolytically plated layer; and forming a wiring pattern. | 12-03-2015 |
20160014908 | FUSION BONDED LIQUID CRYSTAL POLYMER CIRCUIT STRUCTURE | 01-14-2016 |
20160044792 | WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A wiring substrate includes an insulating layer, a connection pad buried in the insulating layer in a state that an upper surface of the connection pad is exposed from an upper surface of the insulating layer and a lower surface and at least a part of a side surface of the connection pad contact the insulating layer, and a concave level difference portion formed in the insulating layer around an outer periphery part of the connection pad, wherein an upper surface of the connection pad and an upper surface of the insulating layer are arranged at a same height. | 02-11-2016 |
20160102413 | TIN OR TIN ALLOY PLATING LIQUID - Tin or tin alloy plating liquid with a sufficient plated deposit can be formed in the opening without causing burns on the plated film surface or abnormal deposits, and which has a good via filling effect. When a specific α, β-unsaturated carbonyl compound is added into the tin or tin alloy plating liquid, the plating liquid with good via filling performance can be obtained, and the deposit which is substantially free of voids and burns or abnormal deposits on the deposit surface are reduced. | 04-14-2016 |
20160108535 | MANUFATURING METHOD OF CASING OF ELECTROING DEVICE - A manufacturing method of a casing of an electronic device including the following steps is provided. First, a casing body is formed by an injection molding technology, and the casing body includes a button portion. Thereafter, a sensing assembly is electroplated on an inner surface of the casing body. The sensing assembly includes a first conductive line and two first contacts. The first conductive line forms a strain sensing pattern on the button portion, and the two first contacts connect to two ends of the first conductive line, respectively. | 04-21-2016 |
20160128202 | BOTTOM-UP ELECTROLYTIC VIA PLATING METHOD - Disclosed herein is a bottom-up electrolytic via plating method wherein a first carrier substrate and a second substrate having at least one through-via are temporarily bonded together. The method includes applying a seed layer on a surface of the first substrate, forming a surface modification layer on the seed layer or the second substrate, bonding the second substrate to the first substrate with the surface modification layer to create an assembly wherein the seed layer and the surface modification layer are disposed between the first and second substrates, applying conductive material to the through-via, removing the second substrate having the through-via containing conductive material from the assembly. | 05-05-2016 |
20160130712 | ELECTROPLATING SOLUTION FOR TIN OR TIN ALLOY, AND USE FOR SAME - An object of the present invention is to solve a problem in filling of a blind via or a through-hole with a conventionally used plating solution for tin or tin alloy plating where the filling itself cannot be achieved well, or even if the filling itself could be achieved, it takes an extremely long time. The electroplating solution for tin or tin alloy capable of solving the problem includes the following components (a) and (b):
| 05-12-2016 |
20160149294 | INTENNA MANUFACTURING METHOD HAVING CAPABILITY TO IMPROVE PLATING RELIABILITY - The present invention relates to a method for manufacturing an internal antenna (intenna) and, in particular, to a method for manufacturing an intenna, which allows a resin molded product to be smoothly and securely plated with a metal by applying a primer paint on the surface of the resin molded product, and thereby improves the reliability of the metal plating formed on the resin molded product. | 05-26-2016 |
20160168737 | ADDITIVE C CAPABLE OF CHANGING MICROVIA-FILLING METHOD BY TSV COPPER PLATING, AND ELECTROPLATING SOLUTION CONTAINING SAME | 06-16-2016 |
20160255729 | POLYMERS CONTAINING BENZIMIDAZOLE MOIETIES AS LEVELERS | 09-01-2016 |
205126000 | Electroless coating from bath containing metal ions and reducing agent prior to electrolytic coating | 5 |
20080257742 | Method of manufacturing printed circuit board for semiconductor package - Disclosed is a method of manufacturing a printed circuit board for a semiconductor package, which minimizes or completely obviates masking work upon the plating of each pad for the surface treatment of a printed circuit board for a semiconductor package, thereby simplifying the overall process and increasing the mounting reliability. | 10-23-2008 |
20110308956 | SYSTEMS AND METHODS FOR REDUCING OVERHANG ON ELECTROPLATED SURFACES OF PRINTED CIRCUIT BOARDS - Systems and methods for reducing overhang on electroplated surfaces of printed circuit boards are described. One such method includes applying a first resist layer on a substrate having a first copper layer, applying a first image to the first resist layer, developing the first resist layer in accordance with the first image, applying a second copper layer on the first copper layer, electroplating a first metallic layer on the second copper layer, removing the first resist layer, etching a portion of the first copper layer, removing the first metallic layer, depositing a third copper layer on a surface of the assembly, applying a second resist layer on the third copper layer, applying a second image to the second resist layer, developing the second resist layer in accordance with the second image, electroplating a preselected metal layer on the third copper layer, removing the second resist layer, and etching a portion of the third copper layer. | 12-22-2011 |
20120118753 | Method of Manufacturing a Circuit Carrier Layer and a Use of Said Method for Manufacturing a Circuit Carrier - In order to be able to produce high density circuits on a dielectric substrate wherein the conductor lines of said circuit have a good adhesion to the dielectric substrate surface, a method is provided which comprises the following method steps: a) providing an auxiliary substrate having two sides, at least one of said sides having an electrically conductive surface; b) treating at least one of the at least one electrically conductive surface with at least one release layer forming compound, the at least one release layer forming compound being a heterocyclic compound having at least one thiol group, c) forming a patterned resist coating on at least one of said at least one electrically conductive surface which has been treated with said at least one release layer forming compound, the patterned resist coating having at least one resist opening thereby exposing the electrically conductive surface; d) forming an electrically conductive pattern in the at least one resist opening by electrodepositing a metal on the exposed electrically conductive surface; e) embedding each electrically conductive pattern into a dielectric material by forming a respective dielectric material layer on the respective side of the auxiliary substrate; and f) separating each dielectric material layer comprising the respective embedded electrically conductive pattern and the auxiliary substrate from each other. | 05-17-2012 |
20150083602 | METHOD FOR MANUFACTURE OF FINE LINE CIRCUITRY - The present invention relates to a method for manufacture of fine line circuitry in the manufacture of printed circuit boards, IC substrates and the like. The method utilizes a first conductive layer on the smooth surface of a build-up layer and a second conductive layer selected from electrically conductive polymers, colloidal noble metals and electrically conductive carbon particles on the roughened walls of at least one opening which are formed after depositing the first conductive layer. | 03-26-2015 |
20170238427 | METHOD OF FILLING THROUGH-HOLES TO REDUCE VOIDS AND OTHER DEFECTS | 08-17-2017 |