Zuzin
Alex Zuzin, San Francisco, CA US
Patent application number | Description | Published |
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20130080385 | Asynchronous Replication Of Databases Of Peer Networks - User data is shared among servers or server farms, referred to transaction nodes. A user is assigned to one of multiple transaction nodes as its home when the user enrolls in a web-based service. Each transaction nodes maintains records of the users assigned to it, including blocks which are formed when a specified number of new users are assigned. A block hash value is computed based on row hash values, where one row is provided for each user. A transaction node advertises its block identifiers when there is a changed full or partial block, or at other times, to allow other transaction nodes to request a block they do not have. Changed blocks can also be advertised with their recomputed block hash value. Advertisements can be provided to transaction nodes actively accepting new users, and to a subset of transaction nodes which are deactivated and not accepting new users. | 03-28-2013 |
20130080635 | Massively Scalable Electronic Gating System - Access by users to transaction servers is restricted or gated by an access-control network, in situations in which a large number of users need to access the servers in a short amount of time. A user's computing device establishes a place in a wait process by contacting a wait server in the access control network and receiving a cookie file with an arrival stamp. The user's computing device periodically contacts with the wait node with the cookie file to determine if the user's turn is up. Each wait server maintains a model of estimated arrival times of users to provide a dynamically updated estimated wait time, and increments a demarcation value which dictates when a user is allowed to access a transaction server. When the user's turn is up, the wait server provides a URL of a transaction server to the user's computing device. | 03-28-2013 |
Mikhail Zuzin, Moscow RU
Patent application number | Description | Published |
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20150193572 | TRACE ROUTING ACCORDING TO FREEFORM SKETCHES - Methods and apparatuses for routing traces in a layout design, such as for example a layout design for an integrated circuit, are disclosed. In various implementations, a group of netlines within a layout design and a freeform sketch are identified. Subsequently, the netlines are routed as traces according to the freeform sketch. More particularly, the geometry of the traces is determined by approximating the geometry of the freeform sketch. Various implementations of the invention provide for the netlines to be routed by an automated trace routing engine. With further implementations of the invention, ball grid array escapes and trace fanouts are additionally routed. For example, ball grid array escapes may be routed prior to netlines being routed according to the freeform sketch. In further implementations of the invention, the freeform sketch is deleted after the traces have been routed. With various implementations of the invention, the netlines are routed as traces by forming a container shape around the freeform sketch, approximating the geometry of the freeform sketch within the container shape, and routing traces within the container shape using the approximation of the freeform shape as a guide. | 07-09-2015 |
Mikhail Y. Zuzin, Moscow RU
Patent application number | Description | Published |
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20100199251 | Heuristic Routing For Electronic Device Layout Designs - Various implementations of the invention provide a method for dynamically determining a layer bias. In various implementations, the layer bias may be employed to determine placement locations for a trace within an electrical device layout design. The trace providing for the electrical connection of components or pins within the layout design. With various implementations of the invention, a layer within the layout design is partitioned into regions, selected regions having a bias. As events or alterations to the layout design occur, the corresponding bias for the selected regions is updated to reflect any changes in bias occurring due to the event or alteration. With other implementations of the invention, processes, machines, or manufactures are provided that dynamically determine a layer bias. The dynamically determined layer bias may be incorporated into a layer bias heuristic employed by for example, an automated trace routing tool. | 08-05-2010 |
20110010683 | Trace Routing According To Freeform Sketches - Methods and apparatuses for routing traces in a layout design, such as for example a layout design for an integrated circuit, are disclosed. In various implementations, a group of netlines within a layout design and a freeform sketch are identified. Subsequently, the netlines are routed as traces according to the freeform sketch. More particularly, the geometry of the traces is determined by approximating the geometry of the freeform sketch. Various implementations of the invention provide for the netlines to be routed by an automated trace routing engine. With further implementations of the invention, ball grid array escapes and trace fanouts are additionally routed. For example, ball grid array escapes may be routed prior to netlines being routed according to the freeform sketch. In further implementations of the invention, the freeform sketch is deleted after the traces have been routed. With various implementations of the invention, the netlines are routed as traces by forming a container shape around the freeform sketch, approximating the geometry of the freeform sketch within the container shape, and routing traces within the container shape using the approximation of the freeform shape as a guide. | 01-13-2011 |
Yuri V. Zuzin, Moscow RU
Patent application number | Description | Published |
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20100199251 | Heuristic Routing For Electronic Device Layout Designs - Various implementations of the invention provide a method for dynamically determining a layer bias. In various implementations, the layer bias may be employed to determine placement locations for a trace within an electrical device layout design. The trace providing for the electrical connection of components or pins within the layout design. With various implementations of the invention, a layer within the layout design is partitioned into regions, selected regions having a bias. As events or alterations to the layout design occur, the corresponding bias for the selected regions is updated to reflect any changes in bias occurring due to the event or alteration. With other implementations of the invention, processes, machines, or manufactures are provided that dynamically determine a layer bias. The dynamically determined layer bias may be incorporated into a layer bias heuristic employed by for example, an automated trace routing tool. | 08-05-2010 |