Patent application number | Description | Published |
20140175628 | COPPER WIRE BONDING STRUCTURE IN SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device comprises a first top electrode and a second top electrode at a front surface of the die, at least a Ni plating layer and an Au plating layer overlaying the Ni plating layer are formed on each of the first top electrode and the second top electrode. A copper clip attaches on the Au plating layer of the second top electrode. A gold (Au) stud bump is formed on the Au plating layer of the first top electrode with a copper wire connected on the stud bump. The Au stud bump is thicker than a thickness of the Au plating layer and thinner than a thickness of the copper clip to avoid copper wire NSOP (non-stick on pad) problem due to Ni plating layer diffusion during the solder reflow process in the copper clip attachment. | 06-26-2014 |
20140315350 | WAFER PROCESS FOR MOLDED CHIP SCALE PACKAGE (MCSP) WITH THICK BACKSIDE METALLIZATION - A wafer process for MCSP comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer covering metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer and a thick metal layer at bottom surface of wafer in recessed space in a sequence; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and the metal seed and metal layers along the scribe line. | 10-23-2014 |
20140361420 | HYBRID PACKAGING MULTI-CHIP SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF - A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure. | 12-11-2014 |
20150056752 | SUBSTRATELESS POWER DEVICE PACKAGES - A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer. | 02-26-2015 |
20150236005 | Method of Hybrid Packaging a Lead Frame Based Multi-Chip Semiconductor Device with Multiple Interconnecting Structures - A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure. | 08-20-2015 |
20150325559 | EMBEDDED PACKAGE AND METHOD THEREOF - The present invention discloses a new embedded package comprising: a pre-mold lead frame with a plurality of chips attached thereon, where the molding material fills the voids of the lead frame, so that the lead frame is entirely solid; a plurality of pins arranged around the lead frame; a metal clip attached on and electrically connecting the chips together; first laminate layer which covers the chips, the lead frame, a metal clip and pins; conductive plug and extension formed to connect an electrode of a chip to a corresponding pin or to connect the chips together. The new embedded package of the invention with a three-dimensional stack capacity improves the thickness, thermal and electrical properties and the flexible power and logic hybrid design. | 11-12-2015 |
20160035653 | MCSP POWER SEMICONDUCTOR DEVICES AND PREPARATION METHODS THEREOF - The present invention discloses the MCSP power semiconductor device and the preparation method thereof. In the present invention method, a metal foil layer is attached to the back of the wafer using a conductive adhesive layer and a composite tape is laminated on the metal foil layer. Thus, individual MCSP power semiconductor devices are separated by cutting the wafer, the conductive adhesive, the metal foil layer and the composite tape along the scribe lines between adjacent semiconductor chips formed on the front of the wafer. | 02-04-2016 |
20160079203 | WAFER PROCESS FOR MOLDED CHIP SCALE PACKAGE (MCSP) WITH THICK BACKSIDE METALLIZATION - A wafer process for molded chip scale package (MCSP) comprises: depositing metal bumps on bonding pads of chips on a wafer; forming a first packaging layer at a front surface of the wafer to cover the metal bumps; forming an un-covered ring at an edge of the wafer to expose two ends of each scribe line of a plurality of scribe lines; thinning the first packaging layer to expose metal bumps; forming cutting grooves; grinding a back surface of the wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer at a bottom surface of the wafer in the recessed space; cutting off an edge portion of the wafer; flipping and mounting the wafer on a substrate; depositing a metal layer covering the metal seed layer; removing the substrate from the wafer; and separating individual chips from the wafer by cutting through the first packaging layer, the wafer, the metal seed layers and the metal layers along the scribe lines. | 03-17-2016 |
20160099238 | EMBEDDED PACKAGE AND METHOD THEREOF - The present invention discloses anew embedded package comprising: a pre-mold lead frame with a plurality of chips attached thereon, where the molding material fills the voids of the lead frame, no that the lead frame is entirely solid; a plurality of pins arranged around the lead frame; a metal clip attached on and electrically connecting the chips together; first laminate layer which covers the chips, the lead frame, a metal clip and pins; conductive plug and extension formed to connect an electrode of a chip to a corresponding pin or to connect the chips together. The new embedded package of the invention with a three-dimensional stack capacity improves the thickness, thermal and electrical properties and the flexible power and logic hybrid design. | 04-07-2016 |