Patent application number | Description | Published |
20140070380 | BRIDGE INTERCONNECT WITH AIR GAP IN PACKAGE ASSEMBLY - Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed. | 03-13-2014 |
20140071646 | ROUTING DESIGN FOR HIGH SPEED INPUT/OUTPUT LINKS - Certain embodiments relate to routing structures and their formation. In one embodiment a routing structure includes a first region including a first layer comprising alternating signal traces and ground traces separated by a dielectric. The first region also includes a second layer including alternating signal traces and ground traces separated by a dielectric, wherein the second layer signal positioned over the first layer ground traces, and the second layer ground traces positioned over the first layer signal traces. The first region may also include additional layers of alternating signal and ground traces. The first region may also be formed with the ground traces having a width that is larger than that of the signal traces. The routing structure may also include a second region including pads to which the traces are coupled. Other embodiments are described and claimed. | 03-13-2014 |
20140117552 | X-LINE ROUTING FOR DENSE MULTI-CHIP-PACKAGE INTERCONNECTS - X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective. | 05-01-2014 |
20140160707 | NON-UNIFORM SUBSTRATE STACKUP - Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described. | 06-12-2014 |
20140217579 | HIGH DENSITY PACKAGE INTERCONNECTS - Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed. | 08-07-2014 |
20140268614 | COUPLED VIAS FOR CHANNEL CROSS-TALK REDUCTION - Capacitively coupled vertical transitions may be configured with a desired amount of mutual capacitance to at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent vertical transitions is achieved with overlapping metal surfaces within the vertical transitions. In embodiments, one or more of the overlapping metal surfaces are vias, via pads, or metal stub features extending off a vertical transition. In embodiments, signal paths with overlapped vertical transitions are utilized to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, capacitively coupled vertical transitions are implemented in a package substrate, an interposer, or a printed circuit board. | 09-18-2014 |
20150102477 | X-LINE ROUTING FOR DENSE MULTI-CHIP-PACKAGE INTERCONNECTS - X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective. | 04-16-2015 |
20160085899 | INTERCONNECT ROUTING CONFIGURATIONS AND ASSOCIATED TECHNIQUES - Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed. | 03-24-2016 |
20160104632 | NON-UNIFORM SUBSTRATE STACKUP - Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described. | 04-14-2016 |