Patent application number | Description | Published |
20100295014 | IMPROVEMENTS IN EXTERNAL LIGHT EFFICIENCY OF LIGHT EMITTING DIODES - A method to improve the external light efficiency of light emitting diodes, the method comprising etching an external surface of an n-type layer of the light emitting diode to form surface texturing, the surface texturing reducing internal light reflection to increase light output. A corresponding light emitting diode is also disclosed. | 11-25-2010 |
20150014761 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, wherein each of the gate stack layers includes a top surface and two side surfaces. A conductive material layer is deposited to conformally cover the top surface and the two side surfaces of each of the gate stack layers. Then, a cap layer is deposited to conformally cover the conductive material layer. Finally, the cap layer and the conductive material layer above the top surface of each of the gate stack layers are removed to leave the cap layer adjacent to the two side surfaces of each of the gate stack layers and covering a portion of the conductive material layer. | 01-15-2015 |
20150206894 | SEMICONDUCTOR STRUCTURE AND LAYOUT STRUCTURE FOR MEMORY DEVICES - A layout structure for memory devices includes a plurality of first gate patterns, a plurality of first landing pad patterns, a plurality of dummy patterns, a plurality of second landing pad patterns, and a plurality of second gate patterns. The first landing pad patterns are parallel with each other and electrically connected to the first gate patterns. The dummy patterns and the first landing pad patterns are alternately arranged, and the second landing pad patterns are respectively positioned in between one first landing pad pattern and one dummy pattern. The second gate patterns are electrically connected to the second landing pad patterns. | 07-23-2015 |
20150270277 | Memory Cell and Manufacturing Method Thereof - The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof. | 09-24-2015 |
20160042957 | SEMICONDUCTOR PROCESS - A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area. | 02-11-2016 |
20160049525 | FLASH MEMORY AND METHOD OF MANUFACTURING THE SAME - A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion. | 02-18-2016 |
Patent application number | Description | Published |
20090047379 | Benzamide Compounds Useful as High Potency Sweet Taste Enhancers - The present invention relates to novel benzamide compounds may be used to provide desirable property of sweetness and to a foodstuff, chewing gum, medicinal product, toothpaste, alcoholic beverage, aqueous beverage, snack, sauce, confection, baked good, dairy product or cereal. | 02-19-2009 |
20090143488 | Peptides imparting umami, salt, dairy and bitter flavor - The invention relates to compositions and methods of using the flavor active peptides, Lys-Ile-His-Pro-Phe (SEQ ID NO:1), Gly-Pro-Phe-Pro-Ile (SEQ ID NO:2), and Lys-Lys-Tyr-Lys-Val-Pro-Gln (SEQ ID NO:3), to impart a bitter, salt, dairy or umami flavor to food or pharmaceutical products. In particular embodiments, the Lys-Lys-Tyr-Lys-Val-Pro-Gln (SEQ ID NO:3) peptide further imparts a vegetable, brothy, or bready flavor. | 06-04-2009 |
20100111880 | NOVEL 1,3-OXATHIANE COMPOUNDS AND THEIR USE IN FLAVOR AND FRAGRANCE COMPOSITIONS - The present invention relates to novel 1,3-oxathiane compounds represented by Formula I: | 05-06-2010 |
20120183490 | NOVEL 1,3-OXATHIANE COMPOUNDS AND THEIR USE IN FLAVOR AND FRAGRANCE COMPOSITIONS - The present invention relates to novel 1,3-oxathiane compounds represented by Formula I: | 07-19-2012 |
20130144046 | METHOD FOR PURIFYING REBAUDIOSIDE C - The present invention is a method for purifying Rebaudioside C by subjecting “waste material,” generated during the Rebaudioside A manufacturing process, to liquid-liquid extraction and recrystallizing the Rebaudioside C. | 06-06-2013 |
20140171517 | 2-MERCAPTO-5-METHYL-4-HEPTANONE AND ITS USE IN FLAVOR AND FRAGRANCE COMPOSITIONS - The present invention is directed to a novel compound, 2-mercapto-5-methyl-4-heptanone, a process of augmenting, enhancing or imparting taste to a material selected from the group consisting of a foodstuff, a chewing gum, a medicinal product, and toothpaste comprising the step of incorporating an olfactory acceptable amount of 2-mercapto-5-methyl-4-heptanone, and a process of improving, enhancing or modifying a fragrance formulation through the addition of an olfactory acceptable amount of 2-mercapto-5-methyl-4-heptanone. | 06-19-2014 |
Patent application number | Description | Published |
20100055518 | HYDROGEN-PRODUCING ASSEMBLIES, FUEL CELL SYSTEMS INCLUDING THE SAME, METHODS OF PRODUCING HYDROGEN GAS, AND METHODS OF POWERING AN ENERGY-CONSUMING DEVICE - Hydrogen-producing assemblies, fuel cell systems including the same, methods of producing hydrogen gas, and methods of powering an energy-consuming device. Hydrogen-producing assemblies may include a monolithic body that defines at least a reforming conduit, in which a feed stream is catalyzed into a reformate gas stream containing hydrogen gas, and a burner conduit, in which a fuel-air stream is combusted. The monolithic body is constructed to conduct heat generated by the exothermic reaction of the combustion from the burner conduit to the reformer conduit. In some hydrogen-producing assemblies, the monolithic body further defines a vaporizer conduit, in which liquid portions of the feed stream are vaporized prior to being delivered to the reformer conduit. In such embodiments, the monolithic body is constructed to conduct heat from the burner conduit to the vaporizer conduit. Hydrogen-producing assemblies may be incorporated into a fuel cell system that is configured to power an energy-consuming device. | 03-04-2010 |
20110136027 | FUEL PROCESSING SYSTEMS WITH THERMALLY INTEGRATED COMPONENTRY - Hydrogen-producing assemblies, fuel cell systems including the same, methods of producing hydrogen gas, and methods of powering an energy-consuming device. Hydrogen-producing assemblies may include a monolithic body that defines at least a reforming conduit, and in some embodiments a plurality of reforming conduits, in which a feed stream is catalyzed into a reformate gas stream containing hydrogen gas, and a burner conduit, in which a fuel-air stream is combusted. The monolithic body is constructed to conduct heat generated by the exothermic reaction of the combustion from the burner conduit to the reformer conduit. In some hydrogen-producing assemblies, the monolithic body further defines a vaporizing conduit, in which liquid portions of the feed stream are vaporized prior to being delivered to the reformer conduit, and the monolithic body may be constructed to conduct heat from the burner conduit to the vaporizing conduit. | 06-09-2011 |
20120208099 | SYSTEMS AND METHODS FOR ACTIVELY CONTROLLING STEAM-TO-CARBON RATIO IN HYDROGEN-PRODUCING FUEL PROCESSING SYSTEMS - The present disclosure is directed to systems and methods for actively controlling the steam-to-carbon ratio in hydrogen-producing fuel processing systems that include a feedstock delivery system. The feedstock delivery system supplies a combined feedstock stream including steam and carbon-containing feedstock to a hydrogen-producing region, which produces a mixed gas stream including hydrogen gas as a majority component therefrom. The systems and methods may include measuring a thermodynamic property of a steam stream, a carbon-containing feedstock stream, and/or the combined feedstock stream and controlling the flow rate and/or pressure of a water stream, the steam stream, and/or the carbon-containing feedstock stream based on a desired steam-to-carbon ratio in the combined feedstock stream and/or a desired flow rate of the mixed gas stream and may include feedforward and/or feedback control strategies. | 08-16-2012 |
Patent application number | Description | Published |
20090281870 | RANKING PRODUCTS BY MINING COMPARISON SENTIMENT - A method of ranking a plurality of products includes obtaining a numerical user score for each of the plurality of products, calculating an opinion score for each of the plurality of products for which a written comparison sentiment applies, determining a final score by combining the numerical user rating and the opinion score for each of the plurality of products, and ranking the plurality of products based on the final score. The opinion score is derived from one or more written comparison sentiments containing a first product name and a second product name. In another aspect, a computer readable medium has instructions stored thereon which, when executed, cause a computer to perform a method of ranking a plurality of products including at least a first product and a second product. | 11-12-2009 |
20110130352 | THE USE OF THE EFFECTIVE FRACTION OF ALKALOIDS FROM MULBERRY TWIG IN PREPARING HYPOGLYCEMIC AGENTS - The present invention relates to an effective fraction of alkaloids and the effective fraction is prepared from mulberry twig and its active ingredients are a composition of alkaloids. Determined by HPLC, the percentage of the total alkaloids are 50% or more by weight in the effective fraction and the percentage of the compound 1-deoxynojirimycin is 30% or more by weight in the total alkaloids. The effective fraction of the invention is prepared as the following steps: the mulberry twig is extracted by solvents, and the extract is precipitated by alcohol precipitation or flocculation to remove the impurities, and then concentrated, purified by resin chromatography. The present invention also relates to a pharmaceutical composition containing the said effective fraction of alkaloids and to the use of the effective fraction of alkaloids according to claim | 06-02-2011 |
20140147092 | METHOD AND DEVICE FOR RECORDING INFORMATION - A method for a mobile terminal to record information, including: detecting an acceleration of the mobile terminal; determining whether the detected acceleration is higher than or equal to a preset acceleration threshold; and initiating a recording function of the mobile terminal to record information if it is determined that the detected acceleration is higher than or equal to the preset acceleration threshold. | 05-29-2014 |
Patent application number | Description | Published |
20110304013 | INTEGRATED INDUCTOR - A method of fabricating an integrated inductor device includes providing a silicon substrate and forming a thickness of an insulating layer overlying the silicon substrate. The insulating layer includes a dummy structure within a portion of the thickness. The method includes forming an inductor having a first portion and a second portion. The first portion includes a spiral coil of conductor lines. The method also includes exposing the dummy structure by forming an opening in the insulating layer and removing the dummy structure to form a cavity underlying the inductor to reduce a dielectric constant and to increase a Q value of the inductor. The method includes using aluminum or copper for the dummy structures. The method includes dry etching the insulator and wet etching the dummy structure. The method also includes forming the inductors using aluminum or copper. | 12-15-2011 |
20120112315 | METHOD AND SYSTEM FOR MANUFACTURING COPPER-BASED CAPACITOR - Embodiments of the present invention provide a method and system for manufacturing copper-based capacitor on an integrated circuit. For example, the integrated circuit is associated with a channel length of less than 0.13 um. It is to be appreciated that, depending upon application, the present invention provides a more improved method for manufacturing capacitors and thus allow MIM capacitors to be manufactured at smaller dimensions. The method includes a step for providing a substrate. The method also includes a step for providing a layer of inter-metal dielectric overlaying the substrate. The method additionally includes a step for providing a bottom layer. The bottom layer includes a first portion and a second portion. The first portion can be characterized as electrically conductive. In addition, the method includes a step for providing a first insulating layer overlaying the bottom layer. | 05-10-2012 |
20120139020 | METHOD AND STRUCTURE FOR HIGH Q VARACTOR - A method for forming a variable capacitor includes providing a semiconductor substrate of a first conductivity type and forming an active region of a second conductivity type within the substrate. The method forms a first dielectric layer overlying the active region. The method provides a conductive gate layer over the first dielectric layer and selectively patterns the conductive gate layer to form a plurality of holes in the conductive gate layer. A perimeter of the holes and a spacing between a first and a second holes are selective to provide a high quality factor (Q) of the capacitor. The method implants impurities of the second conductivity type into the active region through the plurality of holes in the conductive layer. The method also includes providing a second dielectric layer and patterning the second dielectric layer to form contacts to the active region and the gate. | 06-07-2012 |
20130094571 | LOW LATENCY VIDEO COMPRESSION - A method and system are described for low-latency video. In the method a frame, selected from a group of frames, is divided into P-regions and an I-region based on an assigned refresh pattern in a refresh loop. An I-region bit budget and a P-region bit budget are determined. Quantization parameters are determined using the I-region bit budget and the P-region bit budget. Macroblocks of the selected frame are encoded based on the quantization parameters. The I-complexity and P-complexity are updated and a new frame bit budget is determined. The dividing, determining of the I-region bit budget, determining of the P-region bit budget, determining of quantization parameters and encoding are repeated for each remaining frame in the group of frames. | 04-18-2013 |
20140103904 | Apparatus and Method of Power Measurement for Pulsed Terahertz Quantum-Cascade Laser - The present invention provides a power measurement apparatus and method for a pulsed terahertz quantum-cascade laser (THz QCL). The apparatus includes a light source part, a light path part, and a detection part. Terahertz light emitted by a THz QCL reaches a terahertz quantum-well photodetector (THz QWP) through the measurement apparatus, and is absorbed to generate a corresponding current signal. A signal processing circuit extracts a voltage signal from the current signal, amplifies the voltage signal, and inputs the amplified voltage signal to an oscilloscope for reading and displaying. According to a responsivity of the THz QWP at a lasing frequency of the laser, the measurement of the output power of the pulsed THz QCL is acquired. The present invention avoids integration estimation when a thermal detector is used to measure output power of a THz QCL in a pulse operating mode, and can directly acquire the power value of a pulsed output from the laser according to the amplitude of the detector responding to the pulsed terahertz light. | 04-17-2014 |
20140146883 | BANDWIDTH SAVING ARCHITECTURE FOR SCALABLE VIDEO CODING SPATIAL MODE - A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth. | 05-29-2014 |
Patent application number | Description | Published |
20130009130 | LATERALLY CONTACTED BLUE LED WITH SUPERLATTICE CURRENT SPREADING LAYER - A laterally contacted blue LED device involves a PAN structure disposed over an insulating substrate. The substrate may be a sapphire substrate that has a template layer of GaN grown on it. The PAN structure includes an n-type GaN layer, a light-emitting active layer involving indium, and a p-type GaN layer. The n-type GaN layer has a thickness of at least 500 nm. A Low Resistance Layer (LRL) is disposed between the substrate and the PAN structure such that the LRL is in contact with the bottom of the n-layer. In one example, the LRL is an AlGaN/GaN superlattice structure whose sheet resistance is lower than the sheet resistance of the n-type GnA layer. The LRL reduces current crowding by conducting current laterally under the n-type GaN layer. The LRL reduces defect density by preventing dislocation threads in the underlying GaN template from extending up into the PAN structure. | 01-10-2013 |
20130032810 | LED ON SILICON SUBSTRATE USING ZINC-SULFIDE AS BUFFER LAYER - A vertical GaN-based blue LED has an n-type GaN layer that was grown over a ZnS layer that in turn was grown directly on a silicon substrate. In one example, the ZnS layer is a transitional buffer layer that is 50 nm thick, and the n-type GaN layer is at least 2000 nm thick. Growing the n-type GaN layer on the ZnS buffer layer reduces lattice defect density in the n-type layer. The ZnS buffer layer provides a good lattice constant match with the silicon substrate and provides a compound polar template for subsequent GaN growth. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate and the ZnS buffer layer are then removed. Electrodes are added and the structure is singulated to form finished LED devices. | 02-07-2013 |
20130032834 | LED HAVING A LOW DEFECT N-TYPE LAYER THAT HAS GROWN ON A SILICON SUBSTRATE - A vertical GaN-based blue LED has an n-type GaN layer that was grown directly on Low Resistance Layer (LRL) that in turn was grown over a silicon substrate. In one example, the LRL is a low sheet resistance GaN/AlGaN superlattice having periods that are less than 300 nm thick. Growing the n-type GaN layer on the superlattice reduces lattice defect density in the n-type layer. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate is then removed. Electrodes are added and the structure is singulated to form finished LED devices. In some examples, some or all of the LRL remains in the completed LED device such that the LRL also serves a current spreading function. In other examples, the LRL is entirely removed so that no portion of the LRL is present in the completed LED device. | 02-07-2013 |
20130032836 | N-TYPE GALLIUM-NITRIDE LAYER HAVING MULTIPLE CONDUCTIVE INTERVENING LAYERS - A vertical GaN-based blue LED has an n-type layer comprising multiple conductive intervening layers. The n-type layer contains a plurality of periods. Each period of the n-type layer includes a gallium-nitride (GaN) sublayer and a thin conductive aluminum-gallium-nitride (AlGaN:Si) intervening sublayer. In one example, each GaN sublayer has a thickness substantially more than 100 nm and less than 1000 nm, and each AlGaN:Si intervening sublayer has a thickness less than 25 nm. The entire n-type layer is at least 2000 nm thick. The AlGaN:Si intervening layer provides compressive strain to the GaN sublayer thereby preventing cracking. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate is then removed. Electrodes are added and the structure is singulated to form a finished LED device. Because the AlGaN:Si sublayers are conductive, the entire n-type layer can remain as part of the finished LED device. | 02-07-2013 |
20130056745 | Buffer Layer for GaN-on-Si LED - A buffer layer of zinc telluride (ZnTe) or titanium dioxide (TiO | 03-07-2013 |
20140131658 | LED THAT HAS BOUNDING SILICON-DOPED REGIONS ON EITHER SIDE OF A STRAIN RELEASE LAYER - A strain release layer adjoining the active layer in a blue LED is bounded on the bottom by a first relatively-highly silicon-doped region and is also bounded on the top by a second relatively-highly silicon-doped region. The second relatively-highly silicon-doped region is a sublayer of the active layer of the LED. The first relatively-highly silicon-doped region is a sublayer of the N-type layer of the LED. The first relatively-highly silicon-doped region is also separated from the remainder of the N-type layer by an intervening sublayer that is only lightly doped with silicon. The silicon doping profile promotes current spreading and high output power (lumens/watt). The LED has a low reverse leakage current and a high ESD breakdown voltage. The strain release layer has a concentration of indium that is between 5×10 | 05-15-2014 |
20140134765 | LED ON SILICON SUBSTRATE USING ZINC-SULFIDE AS BUFFER LAYER - A vertical GaN-based blue LED has an n-type GaN layer that was grown over a ZnS layer that in turn was grown directly on a silicon substrate. In one example, the ZnS layer is a transitional buffer layer that is 50 nm thick, and the n-type GaN layer is at least 2000 nm thick. Growing the n-type GaN layer on the ZnS buffer layer reduces lattice defect density in the n-type layer. The ZnS buffer layer provides a good lattice constant match with the silicon substrate and provides a compound polar template for subsequent GaN growth. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate and the ZnS buffer layer are then removed. Electrodes are added and the structure is singulated to form finished LED devices. | 05-15-2014 |
20150069324 | LED THAT HAS BOUNDING SILICON-DOPED REGIONS ON EITHER SIDE OF A STRAIN RELEASE LAYER - A strain release layer adjoining the active layer in a blue LED is bounded on the bottom by a first relatively-highly silicon-doped region and is also bounded on the top by a second relatively-highly silicon-doped region. The second relatively-highly silicon-doped region is a sublayer of the active layer of the LED. The first relatively-highly silicon-doped region is a sublayer of the N-type layer of the LED. The first relatively-highly silicon-doped region is also separated from the remainder of the N-type layer by an intervening sublayer that is only lightly doped with silicon. The silicon doping profile promotes current spreading and high output power (lumens/watt). The LED has a low reverse leakage current and a high ESD breakdown voltage. The strain release layer has a concentration of indium that is between 5×10 | 03-12-2015 |
Patent application number | Description | Published |
20140367759 | MULTI-LEVEL CONTACT TO A 3D MEMORY ARRAY AND METHOD OF MAKING - A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers. | 12-18-2014 |
20150179663 | MULTI-LEVEL CONTACT TO A 3D MEMORY ARRAY AND METHOD OF MAKING - A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers. | 06-25-2015 |
20150194380 | Trench Multilevel Contact to a 3D Memory Array and Method of Making Thereof - A multilevel device includes: at least one device region and at least one contact region having a stack of alternating plurality of continuous electrically conductive layers and plurality of electrically insulating layers located over a base. Each electrically conductive layer in the stack is electrically insulated from the other electrically conductive layers in the stack. The base may include a raised portion and a plurality of recesses in the raised portion, each recess in the plurality of recesses having a different lateral size from the other recesses in the plurality of recesses. The electrically conductive layers in the stack may be substantially conformal to the plurality of recesses in the base and expose one or more top surfaces of the raised portion of the base. A first electrically conductive layer in the stack may be a topmost layer in a laterally central portion of a first one of the plurality of recesses. A second electrically conductive layer in the stack different from the first electrically conductive layer may be a topmost layer in a laterally central portion of a second one of the plurality of recesses. | 07-09-2015 |