Patent application number | Description | Published |
20140246736 | High-K Film Apparatus and Method - Disclosed herein is a method forming a device comprising forming a high-k layer over a substrate and applying a dry plasma treatment to the high-k layer and removing at least a portion of one or more impurity types from the high-k layer. The dry plasma treatment may be chlorine, fluorine or oxygen plasma treatment. A cap layer may be applied on the high-k layer and a metal gate formed on the cap layer. An interfacial layer may optionally be formed on the substrate, with the high-k layer is formed on the interfacial layer. The high-k layer may have a dielectric constant greater than 3.9, and the cap layer may optionally be titanium nitride. The plasma treatment may be applied after the high-k layer is applied and before the cap layer is applied or after the cap layer is applied. | 09-04-2014 |
20140264589 | SEMICONDUCTOR STRUCTURE PROFILE - One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. In some embodiments, a semiconductor structure includes a substrate, a first lightly doped drain (LDD), a second LDD, an interface layer (IL), a high-k stack, a gate region, a dummy poly region, a first hard mask (HM) region, a second HM region, and a seal spacer region. The HK stack has a HK stack width and the gate region has a gate region width that is less than or substantially equal to the HK stack width. Because of the increased width of the HK stack, some of the HK stack likely overlaps some of the first LDD or the second LDD. In this manner, a saturation current and a threshold voltage associated with the semiconductor structure are improved. The increased width of the HK stack also protects more of the IL during LDD implanting. | 09-18-2014 |
20150024518 | METHOD OF FORMING A SELECTIVELY ADJUSTABLE GATE STRUCTURE - The present disclosure relates to a method of forming a gate structure that can be selectively adjusted to reduce critical-dimension (CD) variations. In some embodiments, the method is performed by forming a gate structure having a first length over a semiconductor substrate. The first length of the gate structure is measured and compared to a target length. If the first length differs from the target length by an amount that is greater than a threshold value, the first length is adjusted to converge upon the target length. By selectively adjusting the length of the gate structure, critical-dimension (CD) variations can be reduced, thereby increasing yield and reducing cost. | 01-22-2015 |
20150069466 | STRAINED SOURCE AND DRAIN (SSD) STRUCTURE AND METHOD FOR FORMING THE SAME - Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers. | 03-12-2015 |
20150069535 | SEMICONDUCTOR DEVICE WITH AN ANGLED SIDEWALL GATE STACK - A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided. | 03-12-2015 |