Patent application number | Description | Published |
20080225190 | SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF FOR LIQUID CRYSTAL DISPLAY DEVICE - A method for fabricating a semiconductor structure with a multi-layer storage capacitor is provided. A substrate having an active element area and a storage capacitor area is provided. By sequentially fabricating a semiconductor layer, a first inter-layer dielectric (ILD) layer, a gate and a first electrode, a source and a drain in the semiconductor layer in the active element area, a second ILD layer, a patterned conductive layer served as a pixel electrode, a patterned third ILD layer, a plurality of contact windows in the first, second and third ILD layers for exposing the source, the drain, parts of the patterned conductive layer and the first electrode, a second electrode and a source/drain conductive line, the semiconductor structure with the multi-layer storage is obtained in consequence. | 09-18-2008 |
20090090912 | STRUCTURE OF THIN FILM TRANSISTOR ARRAY - A substrate having a gate electrode layer, a gate insulating layer, and a silicon layer thereon is provided. These layers are patterned into a gate area, a gate line and a gate line wiring area. A passivation layer is formed on the entire substrate and patterned to form two contact holes in the passivation layer on the silicon layer at the gate area, and partions of the passivation layer at the gate line and at the gate line wiring areas are removed. An ion implanting layer and a metal layer are formed on the substrate and patterned to form a source region, a drain region, a data line, a data line wiring area and a second layer of the gate line wiring area. A pixel electrode is formed on the passivation layer and electrically coupled to the drain region. Therefore, the TFT array can be fabricated by only four masks. | 04-09-2009 |
20100163873 | PHOTO-VOLTAIC CELL DEVICE AND DISPLAY PANEL - A photo-voltaic cell device includes a first electrode, an N-type doped silicon-rich dielectric layer, a P-type doped silicon-rich dielectric layer, and a second electrode. The N-type doped silicon-rich dielectric layer is disposed on the first electrode, and the N-type doped silicon-rich dielectric layer is doped with an N-type dopant. The P-type doped silicon-rich dielectric layer is disposed on the N-type doped silicon-rich dielectric layer, and the P-type doped silicon-rich dielectric layer is doped with a P-type dopant. The second electrode is disposed on the P-type doped silicon-rich dielectric layer. A display panel including the photo-voltaic cell device is also provided. | 07-01-2010 |
20100230763 | ACTIVE DEVICE ARRAY SUBSTRATE AND METHOD FOR FABRICATING THE SAME - A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer. | 09-16-2010 |
20100267177 | METHOD FOR FABRICATING ACTIVE DEVICE ARRAY SUBSTRATE - A method for fabricating an active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is formed on the display area of the substrate. A gate insulator is formed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are formed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then formed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is formed on the passivation layer. | 10-21-2010 |
20110073862 | ARRAY STRUCTURE AND FABRICATING METHOD THEREOF - An array structure, which includes a TFT, a passivation layer, a pixel electrode, a first connecting layer and a first spacer is provided. The TFT includes a gate, a source and a drain. The passivation layer overlays the TFT. The pixel electrode is located on the passivation layer. The first connecting layer is located on the pixel electrode and electrically connected to the pixel electrode and the drain. The first spacer is located on the first connecting layer. | 03-31-2011 |
20110080388 | DISPLAY PANEL AND ACTIVE DEVICE ARRAY SUBSTRATE THEREOF - A display panel including an active device array substrate, an opposite substrate and a display medium is provided. The active device array substrate includes a substrate, scan lines, data lines, pixel units, and data signal transmission lines. The scan lines and data lines define a plurality of pixel regions on the substrate. Each pixel unit is disposed within one of the pixel regions respectively, and each pixel unit includes a plurality of sub-pixel units. The sub-pixel units within the same pixel unit are electrically connected with the same data line, and each sub-pixel unit within the same pixel unit is electrically connected with one of the scan lines respectively. Each data signal transmission line is electrically connected with one of the data lines, and an extending direction of the data signal transmission line is substantially parallel with an extending direction of the scan lines. | 04-07-2011 |
20110156038 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate including a substrate, scan lines, data lines, active devices, a first dielectric layer, a common line, a second dielectric layer, a patterned conductive layer, a third dielectric layer, and pixel electrodes is provided. At least a part of the active devices are electrically connected to the scan lines and the data lines. The first dielectric layer covers the scan lines, the data lines and the active devices. The common line is disposed on the first dielectric layer. The second dielectric layer covers the common line and the first dielectric layer. The patterned conductive layer is disposed on the second dielectric layer. The third dielectric layer covers the patterned conductive layer and the second dielectric layer. The pixel electrodes are disposed on the third dielectric layer and electrically connected to the patterned conductive layer and the active devices. | 06-30-2011 |
20110165742 | PIXEL STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a pixel structure includes providing a substrate having a pixel area. A first metal layer, a gate insulator and a semiconductor layer are formed on the substrate and patterned by using a first half-tone mask or a gray-tone mask to form a transistor pattern, a lower capacitance pattern and a lower circuit pattern. Next, a dielectric layer and an electrode layer both covering the three patterns are sequentially formed and patterned to expose a part of the lower circuit pattern, a part of the lower capacitance pattern and a source/drain region of the transistor pattern. A second metal layer formed on the electrode layer and the electrode layer are patterned by using a second half-tone mask or the gray-tone mask to form an upper circuit pattern, a source/drain pattern and an upper capacitance pattern. A portion of the electrode layer constructs a pixel electrode. | 07-07-2011 |
20110233567 | PIXEL ARRAY - A pixel array is located on a substrate and includes a plurality of pixel sets. Each of the pixel sets includes a first scan line, a second scan line, a data line, a data signal transmission line, a first pixel unit, and a second pixel unit. The data line is not parallel to the first and the second scan lines. The data signal transmission line is disposed parallel to the first and the second scan lines and electrically connected to the data line. Distance between the first and the second scan lines is smaller than distance between the data signal transmission line and one of the first and the second scan lines. The first pixel unit is electrically connected to the first scan line and the data line. The second pixel unit is electrically connected to the second scan line and the data line. | 09-29-2011 |
20110273654 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate includes a substrate, scan lines disposed on the substrate, data lines intersected with the scan lines, scan signal transmission lines, and pixel units. The scan signal transmission lines are intersected with the scan lines. Each scan signal transmission line connects one scan line through a node. The pixel unit electrically connects the corresponding data line and the corresponding scan line and includes an active device and a pixel electrode. The active device has a gate, a source, and a drain. The pixel electrode electrically connects the drain. In the pixel units not adjacent to the nodes, a gate-to-drain capacitance of each active device is Cgd | 11-10-2011 |
20110292331 | PIXEL STRUCTURE AND DISPLAY PANEL HAVING THE SAME - A pixel structure includes a first and a second scan lines, a data line, a first insulating layer covering the first and the second scan lines and a portion of the data line and having a recess, a second insulating layer covering the first insulating layer, a capacitor electrode line covering the data line and the recess, a third insulating layer on the capacitor electrode line, a first active device electrically connected to the second scan line and the data line, a second active device electrically connected to the first active device and the first scan line, and a first and a second pixel electrodes electrically connected to the first and the second active devices, respectively. The portion of the data line and the first and the second scan lines are in the same layer. The recess is located at two sides of the portion of the data line. | 12-01-2011 |
20120057090 | ACTIVE DEVICE, PIXEL STRUCTURE AND DISPLAY PANEL - An active device, a pixel structure, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a gate insulating layer, a pixel electrode, a capacitor electrode, and a capacitor dielectric layer. The active device includes a gate, a channel, a source, and a drain. The gate is electrically connected to the scan line. The source is electrically connected to the data line. The gate insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected to the drain. The capacitor electrode is located on the gate insulating layer. The capacitor dielectric layer is located between the capacitor electrode and the drain. | 03-08-2012 |
20120092240 | DRIVING CIRCUIT AND DISPLAY PANEL HAVING THE SAME - An active device, a pixel structure, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a first insulating layer, a pixel electrode, a capacitor electrode, and a second insulating layer. The active device includes a gate, a channel, a source, and a drain. The gate is electrically connected to the scan line. The source is electrically connected to the data line. The first insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected to the drain. The capacitor electrode is located on the first insulating layer. The second insulating layer is located between the capacitor electrode and the drain. | 04-19-2012 |
20120112214 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is disposed on the display area of the substrate. A gate insulator is disposed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are disposed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then disposed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is disposed on the passivation layer. | 05-10-2012 |
20120115288 | METHOD FOR FABRICATING ACTIVE DEVICE ARRAY SUBSTRATE - A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer. | 05-10-2012 |