Patent application number | Description | Published |
20090196492 | Method, medium, and system generating depth map of video image - A method, medium, and system generating a depth map of a video image are provided. The depth map generating method extracts the ground of a video image other than an object from the video image, classifies the video image as a long shot image or a non-long shot image based on a distribution value of the extracted ground, calculates a depth value gradually varied along a predetermined direction of the extracted ground when the video image corresponds to the long shot image and calculates a depth value based on the object when the video image corresponds to the non-long shot image. Accordingly, a sense of space and perspective can be effectively given to even a long shot image in which the ground occupies a large part of the image and a stereoscopic image recognizable by a viewer can be generated even if rapid object change is made between scenes in a video image. | 08-06-2009 |
20110179432 | OPTICAL DISC DRIVE - Disclosed is an optical disc drive. The optical disc drive may include a clamp unit for selectively chucking an optical disc, a moving force transfer unit for transferring a moving force, of moving the clamp unit in an axial direction of the clamp unit, to the clamp unit, the moving force transfer unit being formed of a first synthetic resin material at least in part, and a lifting projection coupling body formed of a second synthetic resin material, coupled to at least one lifting projection protruding from the clamp unit toward the moving force transfer unit, and contacting the moving force transfer unit. Accordingly, noise generation at a joined portion between the moving force transfer unit and the lifting projection coupling body can be suppressed. | 07-21-2011 |
20110179433 | OPTICAL DISC DRIVE - Disclosed is an optical disc drive. The optical disc drive may include a clamp unit for chucking an optical disc; at least one lifting projection protruding from the clamp unit; and a moving force transfer unit for transferring a moving force, of moving the clamp unit in an axial direction of the clamp unit, to the clamp unit through the lifting projection, wherein the moving force transfer unit includes a guide for moving the lifting projection in the axial direction by a movement in a direction perpendicular to the axial direction, and a protective part provided at least one of both ends of the guide and protecting the lifting projection. Accordingly, when an optical disc rotates at high speed, noise generation at a joined portion between the guide of the moving force transfer unit and the lifting projection can be suppressed. | 07-21-2011 |
20120027267 | MOBILE TERMINAL AND METHOD OF CONTROLLING OPERATION OF THE MOBILE TERMINAL - According to an embodiment of the present invention, a method of controlling the operation of a mobile terminal includes displaying, on a display module of the mobile terminal, a stereoscopic three-dimensional (3D) image using a disparity between left-eye and right-eye images, receiving a touch input within the stereoscopic 3D image, determining whether a position of the touch input is received within a first area, a second area or a third area, wherein the right-eye image is displayed in the first area, the left-eye image is displayed in the second area, and the third area is the overlapping area of the left-eye and right-eye images, and correcting a touch-sensing area on the display module according to the position of the received touch input, wherein the touch-sensing area receives a touch for selecting the stereoscopic 3D image. | 02-02-2012 |
20120327106 | MOBILE TERMINAL AND SCREEN PARTITIONING METHOD THEREOF - A mobile terminal and controlling method thereof are disclosed, by which various and convenient functions are provided through screen partition in consideration of a plurality of users. The present invention includes a touchscreen recognizing a touch input and a controller setting a reference line on the touchscreen to correspond to a 1 | 12-27-2012 |
20140035453 | Home Appliance Having Movable Door Handle - A home appliance having a door which may be opened and closed, and more particularly, a home appliance to assist a user in easily opening or closing a door is disclosed. The home appliance includes a cabinet having a chamber in which an object is received or retrieved, a door to open or close the chamber, and a handle assembly to be rotated relative to the door during opening or closing of the door, wherein rotation of the handle assembly causes the door to be rotated about a door rotating axis. | 02-06-2014 |
20140156269 | PORTABLE DEVICE AND METHOD FOR PROVIDING VOICE RECOGNITION SERVICE - A portable device and a method for providing a voice recognition service are disclosed. The portable device includes a mechanical vibration sensor configured to sense vibrations having a magnitude equal to or larger than a threshold and generate an electrical signal, a motion sensor configured to sense a motion of the portable device, an audio sensor configured to receive a voice command, a sensor hub configured to control a plurality of sensors including the motion sensor and the audio sensor, and a main processor configured to execute an application and control the portable device. When the portable device is placed in standby mode, upon receipt of the electrical signal from the mechanical vibration sensor, the sensor hub is configured to switch from inactive state to active state and activate the motion sensor. | 06-05-2014 |
20140195841 | PORTABLE DEVICE AND METHOD FOR PROVIDING VOICE RECOGNITION SERVICE - A portable device and a method for controlling the device are disclosed. The portable device includes sensors configured to sense user inputs; a sensor hub configured to activate a main processor and control the sensors including a touch sensor, the touch sensor sensing touch inputs while the portable device is in a standby mode; and the main processor configured to execute an application and control the portable device, wherein, when the portable device is in the standby mode, the touch sensor is in an active state and at least one of the sensors except the touch sensor is in an inactive state, and when the touch sensor detects a first touch input which corresponds to a pre-stored pattern, the sensor hub activates the main processor and switches the portable device from the standby mode to an active mode. | 07-10-2014 |
20150036906 | AUTOMATED MAMMOGRAPHIC DENSITY ESTIMATION AND DISPLAY METHOD USING PRIOR PROBABILITY INFORMATION, SYSTEM FOR THE SAME, AND MEDIA STORING COMPUTER PROGRAM FOR THE SAME - Disclosed is an automated mammographic density estimation method using statistical image information, the method including a preprocessing step of reading the mammogram, segmenting a breast area and shifting pixel values; a step of constructing a tissue probability map in which population-based probability information is extracted, and a probability map for glandular and adipose tissues is constructed; and a density estimation step in which a breast area is segmented based on the constructed tissue probability map and a mammographic density is calculated. | 02-05-2015 |
20150207924 | MOBILE TERMINAL AND CONTROLLING METHOD THEREOF - A mobile terminal and controlling method thereof are disclosed, by which the mobile terminal can operate based on a voice command. The present invention includes a wireless communication unit configured to perform a wireless communication, a microphone configured to receive sound, a touchscreen configured to receive a touch input, and a controller configured to if the touchscreen is touched with a pointer, control the microphone to be activated while the touchscreen is touched with the pointer, set a target indicated by a first user voice received via the microphone, and if the pointer is released from the touchscreen or dragged to move in a first direction, control the target to be processed on a specific application. | 07-23-2015 |
Patent application number | Description | Published |
20110085385 | Nonvolatile Memory Devices Having Dummy Cell and Bias Methods Thereof - Provided are nonvolatile memory devices and methods of operating thereof. The nonvolatile memory devices include: dummy cells connected to a dummy bit line; and a dummy bit line bias circuit providing a dummy bit line voltage to the dummy bit line during a program operation, wherein, due to the dummy bit line voltage, at least one of the dummy cells is programmed with a threshold voltage lower than the top programmed state and higher than an erased state during the program operation. | 04-14-2011 |
20120043673 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate. | 02-23-2012 |
20120068247 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - Provided are three-dimensional semiconductor devices. The devices may include gap-fill insulating patterns configured to upwardly extend from a substrate and an electrode structure defined by sidewalls of the gap-fill insulating patterns. Vertical structures may be provided between adjacent ones of the gap-fill insulating patterns to penetrate the electrode structure, and the vertical structures may include first and second rows of the vertical structures. A separation pattern may be provided between the first and second rows of vertical structures and include a separation semiconductor layer. The separation pattern extends along a direction parallel to the first and second rows of vertical structures. | 03-22-2012 |
20120119283 | METHODS FOR FORMING ETCH STOP LAYERS, SEMICONDUCTOR DEVICES HAVING THE SAME, AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion. | 05-17-2012 |
20120205722 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device. | 08-16-2012 |
20120280299 | Three-Dimensional Semiconductor Memory Devices and Method of Fabricating the Same - Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, and vertical active patterns penetrating the electrode structure. At least an uppermost electrode of the electrodes is divided into a plurality of physically isolated segments arranged in the first direction. The segments of the uppermost electrode are electrically connected to each other. | 11-08-2012 |
20130134377 | SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONALLY ARRANGED RESISTIVE MEMORY CELLS - Semiconductor memory devices are provided. The device may include may include first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other. | 05-30-2013 |
20130140623 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor memory device may include gap-fill insulating layers extending upward from a substrate, an electrode structure delimited by sidewalls of the gap-fill insulating layers, vertical structures provided between adjacent ones of the gap-fill insulating layers to penetrate the electrode structure, and at least one separation pattern extending along the gap-fill insulating layers and penetrating at least a portion of the electrode structure. The separation pattern may include at least one separation semiconductor layer. | 06-06-2013 |
20130153852 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF FORMING THE SAME - A variable resistance memory device comprises a bit line extended in a first direction, a vertical electrode extended vertically in a third direction and configured to be vertically aligned with the bit line in the third direction, a variable resistance layer disposed on a part of the vertical electrode, multiple word lines disposed on the variable resistance layer and stacked in the third direction, wherein each of multiple word lines are extended in a second direction, and a selection transistor including a first dopant injection region electrically connected to the vertical electrode, and a second dopant injection region electrically connected to the bit line. | 06-20-2013 |
20130223127 | VERTICAL RESISTANCE MEMORY DEVICE AND A READ METHOD THEREOF - A read method of a vertical resistance memory device including resistance memory cells arranged in a three-dimensional array includes selecting a block from a plurality of blocks, applying a read voltage to a word line selected from word lines of the block, applying a sensing reference voltage to bit lines sharing the plurality of blocks, applying a string selection voltage to a string selection transistor through a string selection line selected from a plurality of string selection lines of the block, wherein the string selection line is connected to a gate of the string selection transistor; and determining a memory state of a memory cell selected from the plurality of resistance memory cells by the word line and the string selection line based on a current flowing through the memory cell, wherein the word line is connected through a corresponding horizontal electrode to the memory cell. | 08-29-2013 |
20130285006 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A variable resistance memory device includes a selection transistor, which includes a first doped region and a second doped region, a vertical electrode coupled to the first doped region of the selection transistor, a bit line coupled to the second doped region of the selection transistor, a plurality of word lines stacked on the substrate along a sidewall of the vertical electrode, variable resistance patterns between the word lines and the vertical electrode, and an insulating isolation layer between the word lines. The variable resistance patterns are spaced apart from each other in a direction normal to a top surface of the substrate by the insulating isolation layer. | 10-31-2013 |
20130301340 | ERASING METHOD OF RESISTIVE RANDOM ACCESS MEMORY - An erase method of a resistive random access memory which includes a plurality of cell strings, each having a plurality of memory cells and a string selection transistor, includes applying a first voltage to bit lines connected with string selection transistors of the plurality of cell strings, applying a turn-on voltage to at least one string selection line selected from string selection lines connected with the string selection transistors, applying a turn-off voltage to unselected string selection lines of the string selection lines, applying a second voltage to at least one word line selected from word lines connected with memory cells of the plurality of cell strings, and floating unselected word lines of the word lines. | 11-14-2013 |
20140085961 | SEMICONDUCTOR MEMORY DEVICE - According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines. | 03-27-2014 |
20140151783 | NONVOLATILE MEMORY INCLUDING MEMORY CELL ARRAY HAVING THREE-DIMENSIONAL STRUCTURE - A nonvolatile memory is provided which includes a plurality of channel layers and a plurality of insulation layers alternately stacked on a substrate in a direction perpendicular to the substrate, each of the plurality of channel layers including a plurality of channel films extending along a first direction on a plane parallel with the substrate; a plurality of conductive materials extending from a top of the channel layers and the insulation layers up to a portion adjacent to the substrate in a direction perpendicular to the substrate through areas among channel films of each channel layer; a plurality of information storage films provided between the channel films of the channel layers and the conductive materials; and a plurality of bit lines connected to the channel layers, respectively, wherein the conductive materials, the information storage films, and the channel films of the channel layers form a three-dimensional memory cell array, wherein the conductive materials form a plurality of groups, and wherein a distance between the groups is longer than a distance between conductive materials in each other. | 06-05-2014 |
20140160828 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES - A three-dimensional semiconductor device includes bit lines provided on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel pipes connecting the bit lines to the common source line. Each of the channel pipes may include a pair of vertical portions extending through the gate structure and a horizontal portion connecting the vertical portions. The pair of vertical portions are provided under a pair of the bit lines arranged adjacent to each other, respectively. | 06-12-2014 |
20140197469 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES WITH CURRENT PATH SELECTION STRUCTURE AND METHODS OF OPERATING THE SAME - Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate. | 07-17-2014 |
20140197470 | METHODS FOR FORMING ETCH STOP LAYERS, SEMICONDUCTOR DEVICES HAVING THE SAME, AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion. | 07-17-2014 |
20140198552 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array. | 07-17-2014 |
20140231899 | METHODS OF MANUFACTURING THREE-DIMENSIONAL SEMICONDUCTOR DEVICES - Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer. | 08-21-2014 |
20140306279 | SEMICONDUCTOR DEVICES INCLUDING WORD LINE INTERCONNECTING STRUCTURES - A semiconductor memory device includes a substrate including a cell region and an interconnection region, adjacent first and second rows of vertical channels extending vertically from the substrate in the cell region, and layers of word lines stacked on the substrate. Each layer includes a first word line through which the first row of vertical channels passes and a second word line through which the second row of vertical channels passes, and the word lines include respective word line pads extending into the interconnection region. An isolation pattern separates the first and second word lines in the cell region and the interconnection region. First and second pluralities of contact plugs are disposed on opposite sides of the isolation pattern in the interconnection region and contact the word line pads. | 10-16-2014 |
20140367764 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating a semiconductor memory device includes forming a mold stack on a substrate and the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate. The method also includes forming a plurality of vertical channels that penetrate the mold stack and that contact the substrate, patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate, removing one of the first and second sacrificial layers to form recessed regions in the mold stack, forming a data storage layer, at least a portion of the data storage layer being formed between the vertical channels and the gates, forming gates in the recessed regions, forming air gaps between the gates by removing the other of the first and second sacrificial layers, and forming an insulation layer pattern in the word line cuts. | 12-18-2014 |
20150061155 | Semiconductor Devices and Methods of Fabricating the Same - The inventive concepts provide semiconductor devices and methods of fabricating the same. According to the method, sub-stack structures having a predetermined height and active holes are repeatedly stacked. Thus, cell dispersion may be improved, and various errors such as a not-open error caused in an etching process may be prevented. A grain size of an active pillar used as channels may be increased or maximized using a metal induced lateral crystallization method, so that a cell current may be improved. A formation position of a metal silicide layer including a crystallization inducing metal may be controlled such that a concentration grade of the crystallization inducing metal may be controlled depending on a position within the active pillar. | 03-05-2015 |
20150138862 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND FABRICATING METHODS THEREOF - A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure. | 05-21-2015 |
20150255386 | THREE-DIMENSIONAL (3D) SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING 3D SEMICONDUCTOR DEVICES - A three-dimensional (3D) semiconductor device includes a stack of conductive layers spaced from each other in a vertical direction, the stack having a staircase-shaped section in a connection region, and ends of the conductive layers constituting treads of the staircase-shaped section, respectively. The 3D semiconductor device further includes buffer patterns disposed on and protruding above the respective ends of the conductive layers, an interconnection structure disposed above the stack and including conductive lines, and contact plugs extending vertically between the conductive lines and the buffer patterns and electrically connected to the conductive layers of the stack via the buffer patterns. | 09-10-2015 |
20150262826 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND RELATED METHOD OF MANUFACTURE - A method of manufacturing a three-dimensional semiconductor memory device comprises forming a thin layer structure by alternately stacking first and second material layers on a substrate, forming a penetration dent penetrating the thin layer structure and exposing a top surface of the substrate recessed by the penetration dent, forming a vertical insulation layer penetrating the thin layer structure to cover an inner wall of the penetration dent, forming a semiconductor pattern penetrating the vertical insulation layer at the penetration dent to be inserted into the substrate, and forming an oxide layer between the thin layer structure and the substrate by oxidizing a sidewall of the penetration dent. | 09-17-2015 |
20150294980 | Semiconductor Memory Devices Including Fine Patterns and Methods of Fabricatring the Same - Semiconductor devices are provided including an active pillar protruding from a substrate; a first gate electrode and a second gate electrode adjacent to a sidewall of the active pillar and vertically overlapping with each other, the first and second gate electrodes being insulated from each other; a first intergate insulating layer covering a first surface of the first gate electrode; and a second intergate insulating layer covering a second surface, opposite the first surface, of the second gate electrode and spaced apart from the first intergate insulating layer. The first intergate insulating layer and the second intergate insulating layer define an air gap therebetween. | 10-15-2015 |
20150303209 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES INCLUDING A CONNECTION REGION - Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a peripheral circuit part that is disposed under a cell array circuit part. The peripheral circuit part may drive the cell array circuit part. The semiconductor devices may also include first conductive lines, which are connected to the peripheral circuit part, and second conductive lines, which are connected to the cell array circuit part. The first conductive lines and the second conductive lines may have substantially the same shape, and the first conductive lines may overlap with the second conductive lines in a connection region, respectively. | 10-22-2015 |
20150303213 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES INCLUDING A VERTICAL CHANNEL - Semiconductor memory devices and methods of forming the semiconductor devices may be provided. The semiconductor memory devices may include a channel portion of an active pillar that may be formed of a semiconductor material having a charge mobility greater than a charge mobility of silicon. The semiconductor devices may also include a non-channel portion of the active pillar including a semiconductor material having a high silicon content. | 10-22-2015 |
20150303215 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes. | 10-22-2015 |
20160005760 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a lower stack structure including lower gate electrodes and lower insulating layers that are alternately and repeatedly stacked on a substrate. The semiconductor device includes an upper stack structure including upper gate electrodes and upper insulating layers that are alternately and repeatedly stacked on the lower stack structure. A lower channel structure penetrates the lower stack structure. An upper channel structure penetrates and is connected to the upper stack structure. A lower vertical insulator is disposed between the lower stack structure and the lower channel structure. The lower channel structure includes a first vertical semiconductor pattern connected to the substrate, and a first connecting semiconductor pattern disposed on the first vertical semiconductor pattern. The upper channel structure includes a second vertical semiconductor pattern electrically connected to the first vertical semiconductor pattern with the first connecting semiconductor pattern disposed therebetween. | 01-07-2016 |
20160027514 | NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - According to example embodiments, a nonvolatile memory device includes a plurality of cell strings on a horizontal semiconductor layer. Each of the cell strings including a plurality of memory cells stacked in a direction perpendicular to the horizontal semiconductor layer. According to example embodiments, a programming method of the nonvolatile memory device includes setting up bitlines corresponding the cell strings, setting up a plurality of string select lines connected to the cell strings, and applying a negative voltage lower to a ground select line. The ground select line is connected to a plurality of ground select transistors between the memory cells and the semiconductor layer. The string select lines extend in a direction intersecting the bitlines. The negative voltage is lower than a ground voltage. | 01-28-2016 |
20160118399 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. | 04-28-2016 |