Patent application number | Description | Published |
20090289670 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A buffer circuit is provided between a gate terminal of a pull-down transistor and a threshold circuit receiving a gate signal as an input signal. A voltage applied to an output terminal of a power semiconductor element from an external battery power supply is supplied to the buffer circuit through a resistive element. The buffer circuit converts the level of an on-signal output from the threshold circuit into a voltage higher than the threshold of the pull-down transistor, so that the pull-down transistor operates surely to turn off the power semiconductor element even when the level of the gate signal is low. Thus, there is provided a semiconductor integrated circuit device having a power semiconductor element which can be turned off by sure operation of a pull-down semiconductor element. | 11-26-2009 |
20120299108 | SEMICONDUCTOR DEVICE - By connecting a protection diode ( | 11-29-2012 |
20130093053 | TRENCH TYPE PIP CAPACITOR, POWER INTEGRATED CIRCUIT DEVICE USING THE CAPACITOR, AND METHOD OF MANUFACTURING THE POWER INTEGRATED CIRCUIT DEVICE - A trench-type PIP capacitor having a small step at the end part of the capacitor without increasing manufacturing cost, and a power integrated circuit device that uses such a trench-type PIP capacitor are disclosed. A method of manufacturing the power integrated circuit device also is disclosed. A trench-type PIP capacitor has a construction, in the surface region of a semiconductor substrate, comprising an isolating insulation layer formed on an inner wall of a trench and a first polysilicon that fills the trench through the isolating insulation layer and becomes a lower electrode. Since this construction has a small step formed at the end region of the capacitor, a metal layer for wiring does not need to be made excessively thick, allowing a fine structure of the metal layer. Therefore, the power IC provided with such a trench-type PIP capacitor can have a fine structure. | 04-18-2013 |
20130126967 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A vertical super junction MOSFET and a lateral MOSFET are integrated on the same semiconductor substrate. The lateral MOSFET is electrically isolated from the vertical super junction MOSFET by an n-buried isolating layer and an n-diffused isolating layer. The lateral MOSFET is formed of a p-well region formed in an n | 05-23-2013 |
20130321094 | ISOLATOR AND ISOLATOR MANUFACTURING METHOD - In certain aspects of the invention, an isolator is configured by a reception circuit, a transmission circuit, and a transformer. In some aspects, the transmission circuit is disposed in an anterior surface of a semiconductor substrate. The transformer is disposed in a posterior surface of the semiconductor substrate and transmits in an electrically isolated state to the reception circuit, a signal input from the transmission circuit. The transformer is configured by a primary coil and a secondary coil. The primary coil can be configured by a metal film embedded in an oxide film inside a coil trench. The secondary coil can be disposed inside an insulating film covering the primary coil so as to oppose the primary coil and is insulated from the primary coil by the insulating film. | 12-05-2013 |
20140008718 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a vertical trench gate element portion and a lateral n-channel element portion for control which includes a well diffusion region, and a junction edge termination region which surrounds the vertical trench gate element portion and the lateral n-channel element portion for control. The junction edge termination region includes an oxide layer, a sustain region in contact with a trench provided at the end, and a diffusion region in contact with the sustain region. The diffusion region is deeper than the base region and has low concentration. The sustain region is shallower than the diffusion region and has high concentration. The well diffusion region is deeper than the base region and the sustain region and has low concentration. The breakdown voltage of the junction edge termination region and the well diffusion region is higher than that of the vertical trench gate element portion. | 01-09-2014 |
20140073102 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method of forming a device in each of vertical trench gate MOSFET region and control lateral planar gate MOSFET region of a semiconductor substrate is disclosed. A trench is formed in the substrate in the vertical trench gate MOSFET region, a first gate oxide film is formed along the internal wall of the trench, and the trench is filled with a polysilicon film. A LOCOS oxide film is formed in a region isolating the devices. A second gate oxide film is formed on the substrate in the lateral planar gate MOSFET region. Advantages are that number of steps is suppressed, the gate threshold voltage of an output stage MOSFET is higher than the gate threshold voltage of a control MOSFET, the thickness of the LOCOS oxide film does not decrease, and no foreign object residue remains inside the trench. | 03-13-2014 |
20140253078 | LOAD DRIVE CIRCUIT - An open load and a supply fault are differentiated between and detected with a simple configuration. A switching element (Q | 09-11-2014 |
20140306750 | SEMICONDUCTOR DEVICE - A low cost, small scale semiconductor device including a trimming circuit having a fuse resistor is disclosed. By a trimming circuit being configured of a MOSFET, a protection circuit, and a fuse resistor, it is possible to carry out a change from an open circuit state to a short circuit state by fusing the fuse resistor. Also, by the protection circuit and fuse resistor configuring the trimming circuit being formed in a two layer structure, it is possible to reduce the size of the trimming circuit, and thus it is possible to provide a low cost, small scale semiconductor device having a trimming circuit that occupies a small area. | 10-16-2014 |
20140370674 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A vertical super junction MOSFET and a lateral MOSFET are integrated on the same semiconductor substrate. The lateral MOSFET is electrically isolated from the vertical super junction MOSFET by an n-buried isolating layer and an n-diffused isolating layer. The lateral MOSFET is formed of a p-well region formed in an n | 12-18-2014 |