Patent application number | Description | Published |
20120181519 | Organic Semiconductor Device And Method Of Manufacturing The Same - An organic semiconductor device includes an organic semiconductor, an electrode electrically connected to the organic semiconductor, and a self-assembled monolayer positioned between the organic semiconductor and the electrode, the self-assembled monolayer including a monomer having an anchor group at one end and an ionic functional group at another end. | 07-19-2012 |
20120291857 | Organic Passivation Layer Composition, Transistor And/Or Electronic Device Including Organic Passivation Layer Fabricated Therefrom - According to example embodiments, an organic passivation layer composition includes a cross-linking agent and an oligomer or a polymer including structural units represented by the following Chemical Formulae 1 and 2: | 11-22-2012 |
20150295516 | ENERGY CONVERSION DEVICE USING CHANGE OF CONTACT SURFACE WITH LIQUID - The present invention relates to an energy conversion device using a change of a contact surface with liquid and, more specifically, to a method and a device for converting mechanical energy into electrical energy by applying an opposite phenomenon to an electrowetting phenomenon. The energy conversion device having a simplified structure and reduced manufacturing costs with minimal malfunctions by changing a contact surface with liquid between a pair of electrodes and using the change of the contact surface with the liquid to generate electrical energy such that channel blocking can be prevented or a lubricating layer or electrodes complicatedly patterned on a channel are not required. | 10-15-2015 |
20150303831 | ENERGY CONVERSION DEVICE USING LIQUID - The present invention relates to an energy conversion device using a liquid and, more specifically, to a method and a device for converting mechanical energy into electrical energy by applying an opposite phenomenon to an electrowetting phenomenon. The contact surface with liquid is being changed within a pair of electrodes, and the resulting change in the contact surface with liquid is being utilized for generating electrical energy. The device can be simplified and the manufacturing cost thereof is being reduced, furthermore it is effective in implementing an energy conversion device that is less faulty, by preventing channel blocking phenomenon and not requiring a lubricating layer or an electrode complicatedly patterned on a channel. Besides, it is advantageous in that a flexible device can be realized and a large area application is facilitated by simplifying the device structure. | 10-22-2015 |
Patent application number | Description | Published |
20110233648 | Three-Dimensional Semiconductor Memory Devices And Methods Of Fabricating The Same - Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns. | 09-29-2011 |
20120001345 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern. | 01-05-2012 |
20120135583 | METHODS OF MANUFACTURING THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES USING SUB-PLATES - A method of manufacturing a Three Dimensional (3D) semiconductor memory device can be provided by forming at least one trench in a plate stack structure to divide the plate stack structure into a plurality of sub-plate stack structures between forming a plurality of vertical active patterns in the plate stack structure and forming pads of a stepped structure from the plate stack structure. | 05-31-2012 |
20120295409 | METHODS OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers stacked alternatingly on a substrate, forming first and second trenches separating the plate stack structure into a plurality of mold structures, the first trench being between the second trenches, forming first vertical insulating separators in the first and second trenches, forming semiconductor patterns penetrating the mold structure and being spaced apart from the first and second trenches, removing the first vertical insulating separator from the second trench to expose the sacrificial layers, removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separator, and forming conductive patterns in the recess regions. | 11-22-2012 |
20130270643 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A three-dimensional (3D) semiconductor memory device includes an electrode separation pattern, a stack structure, a data storage layer, and a channel structure. The electrode separation pattern is disposed on a substrate. A stack structure is disposed on a sidewall of the electrode separation pattern. The stack structure includes a corrugated sidewall opposite to the sidewall of the electrode separation pattern. The sidewall of the electrode separation pattern is vertical to the substrate. A data storage layer is disposed on the corrugated sidewall. A channel structure is disposed on the charge storage layer. | 10-17-2013 |
20140070302 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures. | 03-13-2014 |
20150279857 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. A first vertical channel pattern is disposed in a lower portion of each vertical channel structure. A gate oxide layer is formed on a sidewall of the first vertical channel pattern. A recess region is formed in the substrate between the vertical channel structures. A buffer oxide layer is formed in the recess region. An oxidation inhibiting layer is provided in the substrate to surround the recess region. The oxidation inhibiting layer is in contact with the buffer oxide layer and inhibits growth of the buffer oxide layer. | 10-01-2015 |
20150372005 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material. | 12-24-2015 |
20160049423 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region, a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate, a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate, and a semiconductor pattern provided in the channel hole but not in the dummy hole. | 02-18-2016 |
20160093634 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A three dimensional semiconductor memory device includes a vertical channel structure extending in a vertical direction on a substrate; interlayer insulating layers surrounding the vertical channel structure and being stacked in the vertical direction on the substrate, gate electrodes surrounding the vertical channel structure and being disposed between the interlayer insulating layers, corners of the gate electrodes adjacent to the vertical channel structure being rounded, and auxiliary gate insulating patterns disposed between the gate electrodes and the vertical channel structure, wherein a side surface of the auxiliary gate insulating pattern is substantially coplanar with a side surface of the interlayer insulating layer in the vertical direction on the substrate. | 03-31-2016 |
Patent application number | Description | Published |
20100200907 | Semiconductor Integrated Circuit Device and Method of Fabricating the Same - A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a plurality of isolation regions which are formed within a semiconductor substrate and define active regions. A tunnel layer and a trap seed layer are formed in each of the active regions and are sequentially stacked between the isolation regions. A trap layer is formed on the trap seed layer and protrudes further than a top surface of each of the isolation regions. A blocking layer is formed on the trap layer. A gate electrode is formed on the blocking layer. | 08-12-2010 |
20110001183 | Memory device and method of fabricating the same - A memory device and a method of fabricating the same are provided. The memory device includes a tunneling dielectric layer on a substrate, a charge storage layer on the tunneling dielectric layer, a blocking dielectric layer on the charge storage layer, the blocking dielectric layer including a first dielectric layer having silicon oxide, a second dielectric layer on the first dielectric layer and having aluminum silicate, and a third dielectric layer formed on the second dielectric layer and having aluminum oxide, and an upper electrode on the blocking dielectric layer. | 01-06-2011 |
20110101438 | Nonvolatile Memory Devices Having Gate Structures Therein with Improved Blocking Layers - Nonvolatile memory devices include a tunnel insulating layer on a substrate and a charge storing layer on the tunnel insulating layer. A charge transfer blocking layer is provided on the charge storing layer. The charge transfer blocking layer is formed as a composite of multiple layers, which include a first oxide layer having a thickness of about 1 Å to about 10 Å. This first oxide layer is formed directly on the charge storing layer. The charge transfer blocking layer includes a first dielectric layer on the first oxide layer. The charge transfer blocking layer also includes a second oxide layer on the first dielectric layer and a second dielectric layer on the second oxide layer. The first and second dielectric layers have a higher dielectric constant relative to the first and second oxide layers, respectively. The memory cell includes an electrically conductive electrode on the charge transfer blocking layer. | 05-05-2011 |
20110159680 | METHOD OF FORMING A DIELECTRIC LAYER AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - In a method of forming an aluminum oxide layer, an aluminum source gas and a dilution gas can be supplied into a chamber through a common gas supply nozzle so that the aluminum source gas may be adsorbed on a substrate in the chamber. A first purge gas can be supplied into the chamber to purge the physically adsorbed aluminum source gas from the substrate. An oxygen source gas may be supplied into the chamber to form an aluminum oxide layer on the substrate. A second purge gas may be supplied into the chamber to purge a reaction residue and the physically adsorbed remaining gas from the substrate. The operations can be performed repeatedly to form an aluminum oxide layer having a desired thickness. | 06-30-2011 |
20110281379 | METHODS OF FORMING CONDUCTIVE LAYER PATTERNS USING GAS PHASE CLEANING PROCESS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - Methods of forming conductive patterns include forming a conductive layer including a metal element on a substrate. The conductive layer is partially etched to generate a residue including an oxide of the metal element and to form a plurality of separately formed conductive layer patterns. A cleaning gas is inflowed onto the substrate including the conductive layer pattern. The metal compound is evaporated to remove the metal element contained in the residue and to form an insulating interface layer on the conductive layer pattern and a surface portion of the substrate through a reaction of a portion of the cleaning gas and oxygen. The residue may be removed from the conductive layer pattern to suppress generation of a leakage current. | 11-17-2011 |
20120037977 | SEMICONDUCTOR DEVICES INCLUDING VERTICAL CHANNEL PATTERN - An insulating pattern is disposed on a surface of a semiconductor substrate and includes a silicon oxynitride film. A conductive pattern is disposed on the insulating pattern. A data storage pattern and a vertical channel pattern are disposed within a channel hole formed to vertically penetrate the insulating pattern and the conductive pattern. The data storage pattern and the vertical channel pattern are conformally stacked along sidewalls of the insulating pattern and the conductive pattern. A concave portion is formed in the semiconductor substrate adjacent to the insulating pattern. The concave portion is recessed relative to a bottom surface of the insulating pattern. | 02-16-2012 |
20120098139 | Vertical Memory Devices And Methods Of Manufacturing The Same - A vertical memory device includes a channel, a ground selection line (GSL), word lines, a string selection line (SSL), and a contact. The channel includes a vertical portion and a horizontal portion. The vertical portion extends in a first direction substantially perpendicular to a top surface of a substrate, and the horizontal portion is connected to the vertical portion and parallel to the top surface of the substrate. The GSL, the word lines and the SSL are formed on a sidewall of the vertical portion of the channel sequentially in the first direction, and are spaced apart from each other. The contact is on the substrate and electrically connected to the horizontal portion of the channel. | 04-26-2012 |
20120149185 | Methods Of Manufacturing Semiconductor Devices - Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns. | 06-14-2012 |
20150145014 | VERTICAL MEMORY DEVICES - A vertical memory device includes a substrate, a first cell block and a second cell block. The substrate includes a central region and a peripheral region. At least one first cell block is on the central region. The first cell block includes a first channel and first gate lines. At least one second cell block is on the peripheral region. The second cell block includes a second channel and second gate lines. The second cell block has a width greater than a width of the first cell block. The first and second channel extend in a first direction vertical to a top surface of the substrate. The first gate lines surround the first channel and the first gate lines are spaced apart from each other in the first direction. The second gate lines surround the second channel and are spaced apart from each other in the first direction. | 05-28-2015 |
20150145021 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions. | 05-28-2015 |
20150155297 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING DOUBLE-LAYERED BLOCKING INSULATING LAYERS - Provided is a method of fabricating a semiconductor memory device. The method includes alternately stacking interlayer insulating layers and sacrificial layers on a substrate, forming a channel hole exposing the substrate through the interlayer insulating layers and the sacrificial layers, sequentially forming a blocking insulating layer, an electric charge storage layer and a channel layer on a substrate exposed on a sidewall of the channel hole and in the channel hole wherein the blocking insulating layer includes a first blocking insulating layer and a second blocking insulating layer, selectively removing the sacrificial layers to expose the first blocking insulating layer and then forming a gap, removing the first blocking insulating layer exposed in the gap, forming first blocking insulating patterns between the interlayer insulating layers and the second blocking insulating layer, and forming a gate electrode in the gap. | 06-04-2015 |
20150206900 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode. | 07-23-2015 |
20160043179 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a substrate including a channel region; a gate dielectric a tunneling layer, a charge storage layer, and a blocking layer sequentially disposed on the channel region; and a gate electrode disposed on the gate dielectric, wherein the tunneling layer has variations in nitrogen concentrations in a direction perpendicular to the channel region, and has a maximum nitrogen concentration in a position shifted from a center of the tunneling layer toward the charge storage layer. | 02-11-2016 |
Patent application number | Description | Published |
20130238877 | CORE SYSTEM FOR PROCESSING AN INTERRUPT AND METHOD FOR TRANSMISSION OF VECTOR REGISTER FILE DATA THEREFOR - Provided is a technique for improving the transfer latency of vector register file data when an interrupt is generated. According to an aspect, when interrupt occurs, a core determines whether to store vector register file data currently being executed in a first memory or in a second memory based on whether or not the first memory can store the vector register file data therein. In response to not being able to store the vector register file data in the first memory, a data transfer unit, which is implemented as hardware, is provided to store vector register file data in the second memory. | 09-12-2013 |
20140297992 | APPARATUS AND METHOD FOR GENERATING VECTOR CODE - An apparatus and method for generating vector code are provided. The apparatus and method generate vector code using scalar-type kernel code, without user's changing a code type or modifying data layout, thereby enhancing user's convenience of use and retaining the portability of OpenCL. | 10-02-2014 |
20140331216 | APPARATUS AND METHOD FOR TRANSLATING MULTITHREAD PROGRAM CODE - A method and apparatus for translating a multithread program code are provided. The method includes: dividing a multithread program code into a plurality of statements according to a synchronization point; generating at least one loop group by combining one or more adjacent statements based on a number of instructions included in the plurality of statements; expanding or renaming variables in each of the plurality of statements so that each statement included in the at least one loop group is executed with respect to a work item of a different work group; and enclosing each of the generated at least one loop group respectively with a work item coalescing loop. | 11-06-2014 |
20140344793 | APPARATUS AND METHOD FOR EXECUTING CODE - An apparatus and method for executing code are provided. The apparatus includes a memory manager that allocates a stack in memory to store processed data that needs to be retained; a loop generator that divides program code programmed to be processed in parallel into regions based on a barrier function, transforms a region that includes the processed data that needs to be retained in the stack into a first coalescing loop, and transforms a region that uses the processed data stored in the stack into a second coalescing loop such that the transformed program code may be serially processed; and a loop changer that reverses a processing order of the second coalescing loop in comparison to a processing order of the first coalescing loop. | 11-20-2014 |
20160055089 | CACHE CONTROL DEVICE FOR PREFETCHING AND PREFETCHING METHOD USING CACHE CONTROL DEVICE - The present examples relate to prefetching, and to a cache control device for prefetching and a prefetching method using the cache control device, wherein the cache control device analyzes a memory access pattern of program code, inserts, into the program code, a prefetching command generated by encoding the analyzed access pattern, and executes the prefetching command inserted into the program code in order to prefetch data into a cache, thereby maximizing prefetching efficiency. | 02-25-2016 |
Patent application number | Description | Published |
20130341658 | LIGHT-EMITTING DEVICE HAVING DIELECTRIC REFLECTOR AND METHOD OF MANUFACTURING THE SAME - A light-emitting device includes a first conductive semiconductor layer formed on a substrate, a mask layer formed on the first conductive semiconductor layer and having a plurality of holes, a plurality of vertical light-emitting structures vertically grown on the first conductive semiconductor layer through the plurality of holes, a current diffusion layer surrounding the plurality of vertical light-emitting structures on the first conductive semiconductor layer, and a dielectric reflector filling a space between the plurality of vertical light-emitting structures on the current diffusion layer. | 12-26-2013 |
20140124732 | NANO-STRUCTURED LIGHT-EMITTING DEVICE AND METHODS FOR MANUFACTURING THE SAME - A nano-structured light-emitting device including a first semiconductor layer; a nano structure formed on the first semiconductor layer. The nano structure includes a nanocore, and an active layer and a second semiconductor layer that are formed on a surface of the nanocore, and of which the surface is planarized. A conductive layer surrounds sides of the nano structure, a first electrode is electrically connected to the first semiconductor layer and a second electrode is electrically connected to the conductive layer. | 05-08-2014 |
20140166974 | NANO-STRUCTURED LIGHT-EMITTING DEVICES - A nano-structured light-emitting device includes a plurality of light-emitting nanostructures each having a resistant layer disposed thereon. The device includes a first semiconductor layer of a first conductivity type, and a plurality of nanostructures disposed on the first semiconductor layer. Each nanostructure includes a nanocore, and an active layer and a second semiconductor layer of a second conductivity type that enclose surfaces of the nanocores. An electrode layer encloses and covers the plurality of nanostructures A plurality of resistant layers are disposed on the electrode layer and each corresponds to a respective nanostructure of the plurality of nanostructures. | 06-19-2014 |
20140209859 | NANOSTRUCTURE SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a nanostructure semiconductor light emitting device including providing a base layer formed of a first conductivity type semiconductor. A mask including an etch stop layer is formed on the base layer. A plurality of openings are formed in the mask so as to expose regions of. A plurality of nanocores are formed by growing the first conductivity type semiconductor on the exposed regions of the base layer to fill the plurality of openings. The mask is partially removed by using the etch stop layer to expose side portions of the plurality of nanocores. An active layer and a second conductivity type semiconductor layer are sequentially grown on surfaces of the plurality of nanocores. | 07-31-2014 |
20140246647 | NANOSTRUCTURE LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A nanostructure semiconductor light emitting device includes a base layer, an insulating layer, and a plurality of light emitting nanostructures. The base layer includes a first conductivity type semiconductor. The insulating layer is disposed on the base layer and has a plurality of openings through which regions of the base layer are exposed. The light emitting nanostructures are respectively disposed on the exposed regions of the base layer and include a plurality of nanocores having a first conductivity type semiconductor and having side surfaces provided as the same crystal planes. The light emitting nanostructures include an active layer and a second conductivity type semiconductor layer sequentially disposed on surfaces of the nanocores. Upper surfaces of the nanocores are provided as portions of upper surfaces of the light emitting nanostructures, and the upper surfaces of the light emitting nanostructures are substantially planar with each other. | 09-04-2014 |
20140367727 | LIGHT-EMITTING DEVICE HAVING DIELECTRIC REFLECTOR AND METHOD OF MANUFACTURING THE SAME - A light-emitting device includes a first conductive semiconductor layer formed on a substrate, a mask layer formed on the first conductive semiconductor layer and having a plurality of holes, a plurality of vertical light-emitting structures vertically grown on the first conductive semiconductor layer through the plurality of holes, a current diffusion layer surrounding the plurality of vertical light-emitting structures on the first conductive semiconductor layer, and a dielectric reflector filling a space between the plurality of vertical light-emitting structures on the current diffusion layer. | 12-18-2014 |
20150144873 | NANOSTRUCTURE SEMICONDUCTOR LIGHT EMITTING DEVICE - A nanostructure semiconductor light emitting device includes a plurality of light emitting nanostructures, each of which including a nanocore formed of a first conductivity-type semiconductor material, and an active layer and a second conductivity-type semiconductor layer sequentially disposed on a surface of the nanocore, a contact electrode disposed on a surface of the second conductivity-type semiconductor layer and formed of a transparent conductive material, a first light transmissive portion filling space between the plurality of light emitting nanostructures and formed of a material having a first refractive index, and a second light transmissive portion disposed on an upper surface of the first light transmissive portion to cover the plurality of light emitting nanostructures and formed of a material having a second refractive index higher than the first refractive index. | 05-28-2015 |
20150155432 | NANO STRUCTURE SEMICONDUCTOR LIGHT EMITTING DEVICE, AND SYSTEM HAVING THE SAME - A nanostructure semiconductor light emitting device may include a substrate including a plurality of light emitting nanostructures comprising nanocores including a first conductivity type semiconductor, active layers and second conductivity type semiconductor layers sequentially formed on the nanocores. The light emitting region may include a first region and a second region. The interval between the light emitting nanostructures disposed in the first region may be different than the interval between the light emitting nanostructures disposed in the second region. The first region may be closer to a non-light emitting region than the second region and may have a smaller interval between the light emitting nanostructures than that of the second region. Systems implementing such a nanostructure semiconductor light emitting device and methods of manufacture are also disclosed. | 06-04-2015 |
20150207038 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a first conductive type semiconductor layer having a main surface, a plurality of vertical type light-emitting structures protruding upward from the first conductive type semiconductor layer; a transparent electrode layer covering the plurality of vertical type light-emitting structures; and an insulation-filling layer disposed on the transparent electrode layer. The insulation-filling layer extends parallel to the first conductive type semiconductor layer so as to cover the plurality of vertical type light-emitting structures. A selected one of the first conductive type semiconductor layer and the insulation-filling layer, which is disposed on a light transmission path through which light generated from the plurality of vertical type light-emitting structures is radiated externally, has an uneven outer surface. The uneven outer surface is opposite to an inner surface of the selected one, and the inner surface faces the plurality of vertical type light-emitting structures. | 07-23-2015 |
20150280062 | NANOSTRUCTURE SEMICONDUCTOR LIGHT EMITTING DEVICE - A nanostructure semiconductor light emitting device includes a base layer, an insulating layer, a plurality of light emitting nanostructures, and a contact electrode. The base layer is formed of a first conductivity-type semiconductor material. The insulating layer is disposed on the base layer. Each light emitting nanostructure is disposed in a respective opening of a plurality of openings in the base layer, and includes a nanocore formed of the first conductivity-type semiconductor material, and an active layer and a second conductivity-type semiconductor layer sequentially disposed on a surface of the nanocore. The contact electrode is spaced apart from the insulating layer and is disposed on a portion of the second conductivity-type semiconductor layer. A tip portion of the light emitting nanostructure has crystal planes different from those on side surfaces of the light emitting nanostructure. | 10-01-2015 |
20150364642 | METHOD FOR MANUFACTURING NANO-STRUCTURED SEMICONDUCTOR LIGHT-EMITTING ELEMENT - There is provided a method for manufacturing a nanostructure semiconductor light emitting device, including: forming a mask having a plurality of openings on a base layer; growing a first conductivity-type semiconductor layer on exposed regions of the base layer such that the plurality of openings are filled, to form a plurality of nanocores; partially removing the mask such that side surfaces of the plurality of nanocores are exposed; heat-treating the plurality of nanocores after partially removing the mask; sequentially growing an active layer and a second conductivity-type semiconductor layer on surfaces of the plurality of nanocores to form a plurality of light emitting nanostructures, after the heat treatment; and planarizing upper parts of the plurality of light emitting nanostructures such that upper surfaces of the nanocores are exposed. | 12-17-2015 |
20150372186 | METHOD FOR MANUFACTURING NANOSTRUCTURE SEMICONDUCTOR LIGHT EMITTING DEVICE - There is provided a method of manufacturing a nanostructure semiconductor light emitting device including providing a base layer formed of a first conductivity-type semiconductor, forming a mask including an etch stop layer on the base layer, forming a plurality of openings with regions of the base layer exposed therethrough, in the mask; forming a plurality of nanocores by growth of the first conductivity-type semiconductor on the exposed regions of the base layer to fill the plurality of openings, partially removing the mask using the etch stop layer to expose side portions of the plurality of nanocores, and sequentially growth of an active layer and a second conductivity-type semiconductor layer on surfaces of the plurality of nanocores. | 12-24-2015 |
20160020358 | SEMICONDUCTOR LIGHT EMITTING DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGE - There is provided a semiconductor light emitting device | 01-21-2016 |
20160035932 | NANO-STRUCTURED LIGHT-EMITTING DEVICE AND METHODS FOR MANUFACTURING THE SAME - A nano-structured light-emitting device including a first semiconductor layer; a nano structure formed on the first semiconductor layer. The nano structure includes a nanocore, and an active layer and a second semiconductor layer that are formed on a surface of the nanocore, and of which the surface is planarized. A conductive layer surrounds sides of the nano structure, a first electrode is electrically connected to the first semiconductor layer and a second electrode is electrically connected to the conductive layer. | 02-04-2016 |
20160049553 | NANOSTRUCTURE SEMICONDUCTOR LIGHT EMITTING DEVICE - A nanostructure semiconductor light emitting device may includes: a base layer having first and second regions and formed of a first conductivity-type semiconductor material; a plurality of light emitting nanostructures disposed on an upper surface of the base layer, each of which including a nanocore formed of the first conductivity-type semiconductor material, and an active layer and a second conductivity-type semiconductor layer sequentially disposed on the nanocore; and a contact electrode disposed on the plurality of light emitting nanostructures, wherein a tip portion of each of light emitting nanostructures disposed on the first region may not be covered with the contact electrode, and a tip portion of each of light emitting nanostructures disposed on the second region may be covered with the contact electrode. | 02-18-2016 |
20160064607 | NANOSTRUCTURE SEMICONDUCTOR LIGHT EMITTING DEVICE - A nanostructure semiconductor light emitting device may include: a base layer formed of a first conductivity-type semiconductor material; an insulating layer disposed on the base layer and having a plurality of openings exposing portions of the base layer; a plurality of nanocores disposed on the exposed portions of the base layer and formed of a first conductivity-type semiconductor material, each of which including a tip portion having a crystal plane different from that of a side surface thereof; a first high resistance layer disposed on the tip portion of the nanocore and formed of an oxide containing an element which is the same as at least one of elements constituting the nanocore; an active layer disposed on the first high resistance layer and the side surface of the nanocore; and a second conductivity-type semiconductor layer disposed on the active layer. | 03-03-2016 |
Patent application number | Description | Published |
20150193036 | USER TERMINAL APPARATUS AND CONTROL METHOD THEREOF - A user terminal apparatus includes a user interface that generates a sliding interaction status based on a sliding interaction of layered panels that can perform physical sliding, and a controller that transmits signals corresponding to the sliding interaction status to an external device, in which the signals corresponding to the sliding interaction status are control signals corresponding to one or more functions based on context of the external device. | 07-09-2015 |
20150279369 | DISPLAY APPARATUS AND USER INTERACTION METHOD THEREOF - A display apparatus and an interaction method thereof are provided. The display apparatus includes a microphone configured to receive speech from a user, a camera configured to capture an image of the user, a storage configured to store registered user information, and a controller configured to recognize whether the user is a registered user stored in the storage using at least one of the image of the user captured by the camera and speech of the user received by the microphone, and in response to recognizing the user is the registered user, perform a control operation that matches at least one of the speech of the user and a user motion included in the captured image of the user. | 10-01-2015 |
20150325254 | METHOD AND APPARATUS FOR DISPLAYING SPEECH RECOGNITION INFORMATION - A method and an apparatus for displaying speech recognition information are provided. The method includes acquiring at least one of speech recognition information based on speech recognized by performing speech recognition, and response information indicating a processing result of the speech recognition information, displaying a speech recognition history list including the acquired information, in a first window region, selecting at least one of the acquired information included in the speech recognition history list, and updating response information corresponding to the selected at least one piece of acquired information. | 11-12-2015 |
20150339026 | USER TERMINAL DEVICE, METHOD FOR CONTROLLING USER TERMINAL DEVICE, AND MULTIMEDIA SYSTEM THEREOF - A user terminal device, a controlling method thereof, and a multimedia system are provided. The method of controlling a user terminal device including a display includes displaying a first image content on the display, detecting a touch gesture with respect to the user terminal device, controlling the user terminal device in response to the touch gesture being a single-touch gesture, and transmitting data for controlling a first external apparatus to the first external apparatus in response to the touch gesture being a multi-touch gesture. | 11-26-2015 |
20150347461 | DISPLAY APPARATUS AND METHOD OF PROVIDING INFORMATION THEREOF - A display apparatus and a method of providing information thereof are provided. The information providing method of the display apparatus includes displaying image content, recognizing at least one of a user motion and a user voice to obtain information related to the image content while the image content is displayed, generating query data according to the recognized at least one of the user motion and the user voice, and transmitting the query data to an external server, and in response to receiving information related to the image content from the external server in response to transmitting the query data, providing the received related information. | 12-03-2015 |
20150350587 | METHOD OF CONTROLLING DISPLAY DEVICE AND REMOTE CONTROLLER THEREOF - According to one or more exemplary embodiments, a method of a remote controller for controlling a display device includes capturing an image of an object; detecting information about at least one of the shape, location, distance, and movement of the object based on the captured image; and transmitting the detected information to the display device. | 12-03-2015 |
Patent application number | Description | Published |
20090300442 | Field mounting-type test apparatus and method for testing memory component or module in actual PC environment - Provided are a field mounting-type test apparatus and method, which can enhance competitiveness of a product by simulating various test conditions including a mounting environment so as to improve quality reliability of a memory device and by minimizing overall loss due to change in a mounting environment so as to reduce testing time and cost. In accordance with example embodiments, the field mounting-type test apparatus may include a mass storage device configured to store logic data simulating a mounting environment of a device under test (DUT) and a tester main frame configured to test the DUT by using the logic data. | 12-03-2009 |
20100148753 | Method to predict phase current - A phase current prediction method is disclosed. The phase current prediction method predicts current representative of a PWM period using a motor model which receives current measured through a single current sensor as an input, instead of the measured current, and determines the predicted current to be phase current. | 06-17-2010 |
20110109318 | SIGNAL CAPTURE SYSTEM AND TEST APPARATUS INCLUDING THE SAME - A signal capture system for capturing a signal and storing the captured signal in a storage apparatus in real time, and a test apparatus including the signal capture system. The signal capture system includes a printed circuit board; a socket that is connected to the printed circuit board and on which a reference memory component is mounted; and an interposer that is mounted on the printed circuit board, is connected to the socket, an external apparatus, and a storage apparatus, receives first signals from the reference memory component and transmits the received first signals to the external apparatus and the storage apparatus, and receives second signals from the external apparatus and transmits the received second signals to the reference memory component and the storage apparatus, wherein a shape of the socket is defined according to a type of the reference memory component. | 05-12-2011 |
20120326738 | PATTERN SYNTHESIS APPARATUS AND SEMICONDUCTOR TEST SYSTEM HAVING THE SAME - A semiconductor test system includes a user device configured to operate a reference device in accordance with an interface signal based on a timing signal having a variable operating frequency, a pattern synthesis apparatus configured to measure an interval between adjacent edges of the timing signal transmitted from the user device, and extract a logic value of the interface signal in accordance with the timing signal so as to generate test pattern data, and a test device configured to receive the test pattern data, reconstruct the timing signal based on the measured interval, generate a test driving signal such that the logic value is extracted from a device under test (DUT) based on the reconstructed timing signal, and apply the test driving signal to the DUT so as to determine an operating state of the DUT. | 12-27-2012 |
20130249450 | SENSORLESS CONTROL APPARATUSES AND CONTROL METHODS THEREOF - A sensorless control apparatus may include: a speed command unit configured to output a speed command to an electric motor; a current detector unit configured to detect electric current flowing through the electric motor if a voltage being output according to the speed command is supplied to the electric motor; a rotor angle calculation unit configured to calculate a magnetic flux of a rotor of the electric motor based on the detected electric current and the voltage being output according to the speed command, and to calculate an angle of the rotor from the calculated magnetic flux; and/or an out-of-step sensing unit configured to sense an out-of-step of the rotor according to a comparison of the calculated angle of the rotor with an angle of the rotor estimated based on a sensorless control algorithm. | 09-26-2013 |
20130278295 | APPARATUSES FOR MEASURING HIGH SPEED SIGNALS AND METHODS THEREOF - An apparatus for measuring a high speed signal may comprise a plurality of Analog-Digital converters (AD converter) that are arranged in parallel to each other to sample an input signal at different frequencies; a plurality of frequency synthesizers configured to provide each AD converter with a different sampling frequency; a signal processor configured to receive an output of the plurality of AD converters to reconstruct the input signal; and/or a controller configured to receive and process a trigger signal. | 10-24-2013 |
Patent application number | Description | Published |
20100017657 | System and Method for Performance Test in Outside Channel Combination Environment - Provided are a system and method for a performance test in an outside channel combination environment. In an outside channel combination environment including first and second outside-affairs servers in an active-active form, first and second outside channel combination servers, and first and second network devices, a system for a performance test includes: a plurality of test lines connected to one another so that a closed circuit is formed at outputs of the first and second network devices; and at least one load generator for generating loads corresponding to outbound messages to be sent to a plurality of outside authorities, and measuring system performance, wherein: the loads generated by the load generator are sent to the second outside channel combination server via the first outside-affairs server, the first outside channel combination server, the first network device, the test lines, and the second network device, and the second outside channel combination server generates a response message corresponding to the received load, and then sends the response message to the load generator via the second network device, the test lines, the first network device, the first outside channel combination server, and the first outside-affairs server, so that system performance is measured. Thus, a performance test for transmit/receive message can be effectively performed in advance in a newly built outside channel combination environment. | 01-21-2010 |
20100122112 | System and Method for Communication Error Processing in Outside Channel Combination Environment - Provided are a system and method for processing communication errors in an outside channel combination environment. The system includes: first and second outside-affairs servers connected with a plurality of user terminals and having respective outside-affairs processing applications to perform outside affairs associated with a plurality of outside authorities; first and second outside channel combination servers for processing outside affairs associated with the outside authorities, the first and second outside channel combination servers having respective message relaying and communication applications to interwork with the first and second outside-affairs servers; first and second active and standby network devices respectively connected in parallel with the first and second outside channel combination servers, the first and second active network devices performing normal outside affairs, and the first and second standby network devices being activated when a communication error is generated to perform the normal outside affairs; and first and second switching devices respectively provided between the first and second active and standby network devices and the outside authorities to selectively connect the first and second active and standby network devices when the communication error is generated. Thus, communication errors can be minimized and system resources can be efficiently managed by distributing system loads. | 05-13-2010 |
Patent application number | Description | Published |
20130170209 | OPTICAL SEMICONDUCTOR LIGHTING APPARATUS - An optical semiconductor lighting apparatus having at least one or more clamping units are formed along a longitudinal direction of a race way. A first sealing unit finishes both ends of a housing attached to or detached from the clamping unit. A second sealing unit surrounds upper and lower portions of both edges of an optical member disposed on the bottom surface of the housing. A wireless communication unit receives a dimming signal through a wireless communication network, and outputs the received dimming signal to a power supply unit. The power supply unit supplies a DC voltage to the light emitting module to control the illuminance of the light emitting module according to the dimming signal input from the wireless communication unit. | 07-04-2013 |
20130200796 | HEAT SINK AND LED ILLUMINATING APPARATUS COMPRISING THE SAME - A light emitting diode (LED) illuminating apparatus including a heat sink, a light emitting module, a power connection portion, a translucent cover and a wiring path. The heat sink has a plurality of heat dissipation fins. The light emitting module is positioned on an upper portion of the heat sink. The power connection portion is positioned below a lower portion of the heat sink. The translucent cover is mounted to cover an upper portion of the light emitting module. The wiring path is formed in the heat sink so as to accommodate a wire for electrically connecting the power connection portion and the light emitting module. In the LED illuminating apparatus, the light emitting module emits light by directly receiving AC power supplied through the wire accommodated in the wiring path. | 08-08-2013 |
20130279166 | OPTICAL SEMICONDUCTOR BASED ILLUMINATING APPARATUS - An optical semiconductor based illuminating apparatus includes a first unit which is disposed on an upper side of a housing and includes protrusions formed on a lower outer side of an optical member surrounding a semiconductor optical device and having an inclined surface inclined upwards from a lower edge of an optical member; and a second unit which accommodates and holds the first unit, so that it can reduce defect rate, improve assembly efficiency, and has excellent durability. | 10-24-2013 |
20140111988 | OPTICAL SEMICONDUCTOR BASED ILLUMINATING APPARATUS - An optical semiconductor based illuminating apparatus includes a first unit which is disposed on an upper side of a housing and includes protrusions formed on a lower outer side of an optical member surrounding a semiconductor optical device and having an inclined surface inclined upwards from a lower edge of an optical member; and a second unit which accommodates and holds the first unit, so that it can reduce defect rate, improve assembly efficiency, and has excellent durability. | 04-24-2014 |
20140247598 | HEAT SINK AND LED ILLUMINATING APPARATUS COMPRISING THE SAME - A light emitting diode (LED) illuminating apparatus including a heat sink, a light emitting module, a power connection portion, a translucent cover and a wiring path. The heat sink has a plurality of heat dissipation fins. The light emitting module is positioned on an upper portion of the heat sink. The power connection portion is positioned below a lower portion of the heat sink. The translucent cover is mounted to cover an upper portion of the light emitting module. The wiring path is formed in the heat sink so as to accommodate a wire for electrically connecting the power connection portion and the light emitting module. In the LED illuminating apparatus, the light emitting module emits light by directly receiving AC power supplied through the wire accommodated in the wiring path. | 09-04-2014 |
20140306242 | OPTICAL SEMICONDUCTOR LIGHTING APPARATUS - An optical semiconductor lighting apparatus including: a substrate in which a single LED chip or a plurality of LED chips are disposed; a first mold portion disposed on the substrate to cover the plurality of LED chips; and a second mold portion extending from an edge of the first mold portion and disposed on the substrate. The respective LED chips can improve adhesive strength with respect to the substrate through the first and second mold portions. Peeling, surface cracking and damage caused by moisture permeation can be prevented by the first and second mold portions. A fluorescent material included in the second mold portion can improve a wavelength conversion rate. | 10-16-2014 |
20150029733 | OPTICAL SEMICONDUCTOR LIGHTING APPARATUS - A optical semiconductor lighting apparatus includes: a board; a drive IC which is disposed in a central portion of the board; a plurality of semiconductor optical devices which is disposed adjacent to and around the drive IC in the board in a grid shape in one or more rows and columns; a non-insulating heat sink in which the board is disposed; an insulating housing which accommodates the heat sink and protects the drive IC and the plurality of semiconductor optical devices from withstand voltages; and a first optical member which faces the plurality of semiconductor optical devices, transmits or reflects light irradiated from the semiconductor optical devices, and forms a vertical vent hole corresponding to the drive IC; and a second optical member which is connected to an upper side of the housing and forms light distribution by refracting light transmitted or reflected from the first optical member. | 01-29-2015 |
Patent application number | Description | Published |
20090083642 | METHOD FOR PROVIDING GRAPHIC USER INTERFACE (GUI) TO DISPLAY OTHER CONTENTS RELATED TO CONTENT BEING CURRENTLY GENERATED, AND A MULTIMEDIA APPARATUS APPLYING THE SAME - A method for providing a graphic user interface (GUI) and a multimedia apparatus incorporating the same. While a first content is being generated, other content related to the first content are searched for via a storage medium or a network and displayed concurrently. As a result, a user can view the related content conveniently while the user is generating or editing content. | 03-26-2009 |
20090122022 | METHOD FOR DISPLAYING CONTENT AND ELECTRONIC APPARATUS USING THE SAME - A method of displaying content and an electronic apparatus using the same, the method of displaying content of an electronic apparatus using an touchscreen including: dividing the touchscreen into a viewable area and an un-viewable area according to a touching of the touchscreen; and displaying the content on the viewable area. Accordingly, a user more conveniantly manipulates an electronic apparatus. | 05-14-2009 |
20090177399 | METHOD FOR ESTIMATING LOCATION AND APPARATUS USING THE SAME - A method for estimating location, and an apparatus using the same. The method for estimating location includes receiving information on the location of a plurality of external apparatuses from the plurality of external apparatuses; setting estimable areas for estimating an area wherein there is a possibility that the device is located based on the information on the location of the plurality of external apparatuses; and determining a predetermined area of the estimable areas to be an estimation area wherein there is the possibility that the device is located. If it is impossible to receive a GPS signal, the location information of a device is estimated using information on the location of an external apparatus communicable with the device. | 07-09-2009 |
20090177810 | METHOD OF OPTIMIZED-SHARING OF MULTIMEDIA CONTENT AND MOBILE TERMINAL EMPLOYING THE SAME - Provided are a method of optimized sharing of multimedia content that allows delivery of optimized multimedia content using device profiles shared between devices connected via a short-range wireless communication and a mobile terminal employing the same method. The method includes: exchanging, upon connecting with peripheral devices via one of a wired network having a predetermined wired communication protocol and a wireless network having a predetermined wireless communication protocol, profile information with the peripheral devices; displaying the received profile information about the peripheral devices in order of network distances of the peripheral devices; and arranging and displaying, if the displayed profile information about each of the peripheral devices is selected, a list of shareable and playable multimedia content items pertaining to each peripheral device in order of priority. | 07-09-2009 |
20090185763 | PORTABLE DEVICE,PHOTOGRAPHY PROCESSING METHOD, AND PHOTOGRAPHY PROCESSING SYSTEM HAVING THE SAME - A portable device, a photography processing method, and a photography processing system having the same, the method including capturing a photo image; collecting identification (ID) information from neighboring devices; confirming ID information corresponding to the collected ID information; displaying one or more graphical user interface (GUI) elements corresponding to the confirmed identification (ID) information; and transmitting the captured photo image to a device having ID information corresponding to a selected GUI element. Furthermore, the photography processing method tags the identification information of the GUI element selected by the photographer to the captured image, stores the tagged image, performs a photo transmission and a tagging, improves user convenience, data management, and search efficiency, and quickly transmits the photo image of the target person without using additional navigation operations. | 07-23-2009 |
20090199098 | APPARATUS AND METHOD FOR SERVING MULTIMEDIA CONTENTS, AND SYSTEM FOR PROVIDING MULTIMEDIA CONTENT SERVICE USING THE SAME - An apparatus and method for serving multimedia contents and a system for providing a multimedia content service using the same, the apparatus including: a display unit to display multimedia contents and supplementary information; and a controller to control the display unit to display the supplementary information appended to a section of the multimedia contents when the section is reproduced, to retrieve a section including selected supplementary information from the multimedia contents stored in the memory when the supplementary information is selected using the input unit, to display section information of the retrieved section, and to reproduce the section corresponding to selected section information when the section information is selected using the input unit. Thus, it is possible to easily perform movement to a scene in which the user is interested and provide manipulation convenience and usability to the user. | 08-06-2009 |
20110269400 | METHOD OF OPTIMIZED-SHARING OF MULTIMEDIA CONTENT AND MOBILE TERMINAL EMPLOYING THE SAME - An apparatus and method for displaying information using a mobile terminal connectable to peripheral devices through corresponding wireless communication is provided. The method includes receiving profile information from one or more of the peripheral devices connected through the corresponding wireless communication, each received profile information having identification information identifying the corresponding one or more peripheral devices and content information on the corresponding one or more peripheral devices, and listing the received profile information organized according to signal strength of the one or more peripheral devices from which the profile information is received. | 11-03-2011 |
20150019123 | METHOD FOR ESTIMATING LOCATION AND APPARATUS USING THE SAME - A method and apparatus for displaying a map are provided. The method includes receiving user input for displaying a map, receiving location information regarding surrounding apparatus from each of at least one of the surrounding apparatus using short range wireless communication, in response to the user input, and displaying a message indicating that map may not be viewed when the location information is not received from the surrounding apparatus, determining a position estimation area in which the mobile device may be located based on received location information regarding surrounding apparatus and displaying a map on which the position estimation area is indicated when the location information is received from the surrounding apparatus. | 01-15-2015 |
Patent application number | Description | Published |
20130326119 | STORAGE DEVICE HAVING NONVOLATILE MEMORY DEVICE AND WRITE METHOD - Disclosed is a method of writing data in a storage device including a nonvolatile memory device. The method includes receiving write data with a write request, detecting a number of free blocks, if the detected number of free blocks is less than a threshold value, allocating a log block only in accordance with a sub-block unit, but if the detected number of free blocks is not less than the threshold value, allocating the log block in accordance with one of the sub-block unit and a physical block unit, wherein the sub-block unit is smaller than the physical block unit. | 12-05-2013 |
20130326312 | STORAGE DEVICE INCLUDING NON-VOLATILE MEMORY DEVICE AND REPAIR METHOD - Disclosed is a storage device which includes a nonvolatile memory device including a memory block a program order of which is adjusted regardless of an arrangement of memory cells, and a memory controller that performs address mapping to replace a bad page of the memory block with a normal page of the memory block. | 12-05-2013 |
20140204672 | MEMORY SYSTEM - A memory system includes a flash memory including a block having first sub-blocks and second sub-blocks different from each other, the second sub-blocks including free pages only; and a controller configured to erase the flash memory in units of the sub-blocks, and in a garbage collection operation, the controller is configured to copy data of a valid page of the first sub-blocks to at least one of the second sub-blocks. | 07-24-2014 |
20150205540 | MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICES AND OPERATING METHOD - A memory system includes nonvolatile memory devices (NVM) connected to a controller via a channel and provided with data according to an interleaving approach. A controller respectively accesses the NVM and determines a number of program operations that may be simultaneously executed by the NVM in conjunction with an additional operation upon comparing a peak operating current associated with a sum of respective peak operating currents for the number of program operations and the at least one additional operation with a reference peak current. | 07-23-2015 |
Patent application number | Description | Published |
20100238738 | EEPROM Having Single Gate Structure and Method of Operating the Same - An electrically erasable programmable read-only memory (EEPROM) includes an access transistor having a floating gate and source/drain regions formed at opposite sides of the floating gate in a first well, a first well tap formed in the first well, a control gate located on a second region, first impurity regions formed at both sides of the control gate in the second region, and a second well tap formed in a third region. In order to erase information stored in a memory cell, a predetermined erasing voltage is applied to the source/drain regions of the access transistor and the first well tap, a ground voltage is applied to the first impurity regions in the second region, and a voltage, which is greater than 0V and less than a junction breakdown voltage between the active area and the first well, is applied to the second well tap. | 09-23-2010 |
20150037956 | MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE - Provided is a manufacturing method of a semiconductor device including providing a substrate including a first region and a second region, forming active fins in the first region and the second region, forming gate electrodes which intersect the active fins and have surfaces facing side surfaces of the active fins, forming an off-set zero (OZ) insulation layer covering the active fins, forming a first residual etch stop layer and a first hard mask pattern which cover the first region, injecting first impurities into the active fins of the second region, removing the first hard mask pattern and the first residual etch stop layer, forming second residual etch stop layer and a second hard mask pattern which cover the second region, injecting a second impurities into the active fins of the first region, and removing the second residual etch stop layer and the second hard mask pattern. | 02-05-2015 |
Patent application number | Description | Published |
20090174836 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes: a substrate; a pixel electrode disposed on the substrate and having a first subpixel electrode and a second subpixel electrode; and a common electrode facing the pixel electrode, wherein the first subpixel electrode has a pair of bent edges substantially parallel to each other, the second subpixel electrode has a pair of bent edges substantially parallel to each other, and the second subpixel electrode has a height greater than a height of the first subpixel electrode. | 07-09-2009 |
20100097537 | THIN FILM TRANSISTOR SUBSTRATE CAPABLE OF ENHANCING IMAGE CLARITY AND REDUCING RESIDUAL IMAGES - A thin film transistor substrate and a liquid crystal display capable of eliminating residual images and enhancing clarity are presented. The thin film transistor substrate includes a charge-up capacitor for increasing electric charge in a first pixel electrode of a first pixel capacitor and a charge-down capacitor decreasing electric charge in a second pixel electrode of a second pixel capacitor. An extension electrode portion of the charge-up capacitor is formed in the shape of a frame to reduce any variation in the overlapping area between the first pixel electrode and the extension electrode portion caused by an alignment error generated during the manufacturing process. | 04-22-2010 |
20100118247 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes a substrate, a pixel electrode disposed on the substrate and including a first subpixel electrode and a second subpixel electrode, and a common electrode facing the pixel electrode. The first subpixel electrode comprises a first edge, a second edge disposed opposite the first edge, and two first oblique edges substantially parallel to each other, the first oblique edges making an oblique angle with the first edge and the second edge and meeting the first edge. The second subpixel electrode comprises a first edge, a second edge disposed opposite the first edge, and two first oblique edges substantially parallel to or substantially perpendicular to the first oblique edges of the first subpixel electrode, the first oblique edges of the second subpixel electrode meeting the first edge of the second subpixel electrode. The first edge of the first subpixel electrode is adjacent to the first edge of the second subpixel electrode, and a length of the first edge of the first subpixel electrode is different from a length of the first edge of the second subpixel electrode. The first oblique edges of the first subpixel electrode are offset from the first oblique edges of the second subpixel electrode. | 05-13-2010 |
20110012941 | LIQUID CRYSTAL DISPLAY PANEL, METHOD FOR DRIVING THE SAME, AND LIQUID CRYSTAL DISPLAY APPARATUS USING THE SAME - The disclosure describes a liquid crystal display panel including a plurality of sub-pixels, a plurality of thin film transistors, a plurality of data lines, and a plurality of gate lines. Each of the sub-pixels has first and second gray scale regions which are split up and down and have different areas, first and second gray scale regions of one sub-pixel having a staggered arrangement with respect to those of an adjacent sub-pixel. Thin film transistors are connected to first and second gray scale regions so that first gray scale regions are driven when one of gate lines is driven and the second gray scale regions are driven when another gate line is driven. | 01-20-2011 |