Patent application number | Description | Published |
20100155826 | Non-volatile memory device and method of fabricating the same - Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a substrate and a plurality of semiconductor pillars on the substrate. A plurality of control gate electrodes may be stacked on the substrate and intersecting the plurality of semiconductor pillars. A plurality of dummy electrodes may be stacked adjacent to the plurality of control gate electrodes on the substrate, the plurality of dummy electrodes being spaced apart from the plurality of control gate electrodes. A plurality of via plugs may be connected to the plurality of control gate electrodes. A plurality of wordlines may be on the plurality of via plugs. Each of the plurality of via plugs may penetrate a corresponding one of the plurality of control gate electrodes and at least one of the plurality of dummy electrodes. | 06-24-2010 |
20130105863 | ELECTRODE STRUCTURES, GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICES INCLUDING THE SAME AND METHODS OF MANUFACTURING THE SAME | 05-02-2013 |
20130252410 | SELECTIVE LOW-TEMPERATURE OHMIC CONTACT FORMATION METHOD FOR GROUP III-NITRIDE HETEROJUNCTION STRUCTURED DEVICE - A method for forming a selective ohmic contact for a Group III-nitride heterojunction structured device may include forming a conductive layer and a capping layer on an epitaxial substrate including at least one Group III-nitride heterojunction layer and having a defined ohmic contact region, the capping layer being formed on the conductive layer or between the conductive layer and the Group III-nitride heterojunction layer in one of the ohmic contact region and non-ohmic contact region, and applying at least one of a laser annealing process and an induction annealing process on the substrate at a temperature of less than or equal to about 750° C. to complete the selective ohmic contact in the ohmic contact region. | 09-26-2013 |
20140110717 | STRUCTURE INCLUDING GALLIUM NITRIDE SUBSTRATE AND METHOD OF MANUFACTURING THE GALLIUM NITRIDE SUBSTRATE - A structure includes a silicon substrate, a plurality of silicon rods on the silicon substrate, a silicon layer on the plurality of silicon rods, and a GaN substrate on the silicon layer. | 04-24-2014 |
20140117349 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING METAL OXIDE - A method of manufacturing a semiconductor device using a metal oxide includes forming a metal oxide layer on a substrate, forming an amorphous semiconductor layer on the metal oxide layer, and forming a polycrystalline semiconductor layer by crystallizing the amorphous semiconductor layer using the metal oxide layer. | 05-01-2014 |
20140174640 | METHODS OF TRANSFERRING GRAPHENE AND MANUFACTURING DEVICE USING THE SAME - A method of transferring graphene includes forming a sacrificial layer and a graphene layer sequentially on a first substrate, bonding the graphene layer to a target layer, and removing the sacrificial layer using a laser and separating the first substrate from the graphene layer. | 06-26-2014 |
20150214037 | STRUCTURE INCLUDING GALLIUM NITRIDE SUBSTRATE AND METHOD OF MANUFACTURING THE GALLIUM NITRIDE SUBSTRATE - A structure includes a silicon substrate, a plurality of silicon rods on the silicon substrate, a silicon layer on the plurality of silicon rods, and a GaN substrate on the silicon layer. | 07-30-2015 |
20160035898 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING METAL OXIDE - A method of manufacturing a semiconductor device using a metal oxide includes forming a metal oxide layer on a substrate, forming an amorphous semiconductor layer on the metal oxide layer, and forming a polycrystalline semiconductor layer by crystallizing the amorphous semiconductor layer using the metal oxide layer. | 02-04-2016 |