Yong-Jik
Yong Jik Kim, Gyeonggi-Do KR
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20090281301 | Manufacturing Process of 2' ,2' - Difluoronucleoside and Intermediate - The present invention relates to more improved process for preparing 2′-deoxy-2′,2′-difluoronucleoside and its intermediate. The present invention provide a process for preparing an erythro enantiomer in greater than 98% purity, comprising forming a lactone ring by hydrolyzing ethyl (3RS)-2,2-difluoro-3-hydroxy-3-(2,2-dimethyloxolan-4-yl)propionate is hydrolyzed in the presence of hydrolysis reagents selected from acetic acid or chloroacetic acid, water and a mixture of organic solvents selected from the group comprising acetonilrile, dioxane, tetrahydrofuran or toluene, introducing a substituted benzoyl protecting group at the 3-position and 5-position, and recrys- tallizing said erythro enantiomer. Further, the present invention provides a process for selectively preparing, in greater than 99% purity, a beta-anomer 2′-deoxy-2′,2′-difluoronucleoside at the 3′-position and 5′-position that are protected by a substituted benzoyl in a 2:3 alpha/beta anomeric ratio. | 11-12-2009 |
20100113556 | NOVEL CRYSTAL FORMS OF PYRROLYLHEPTANOIC ACID DERIVATIVES - The present invention provides novel crystalline forms D1 and D2 of [R—(R*,R*)]-2-(4-fluorophenyl)-β,δ-dihydroxy-5-(1-methylethyl)-3-phenyl-4-[(phenylamino)carbonyl]-1H-pyrrole-1-heptanoic acid hemicalcium salt, and hydrates thereof. The crystalline forms D | 05-06-2010 |
Yong Jik Lee, Gyeongsangbuk-Do KR
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20150274772 | METHOD FOR SEPARATING AND PURIFYING PROTEIN FROM PLANTS USING CELLULOSE AND CELLULOSE BINDING DOMAIN - The present invention relates to a method of isolating a protein containing a cellulose binding domain from plants using various structures of cellulose and/or variants thereof. According to the method of isolating a protein, as a high affinity cellulose binding domain is used, a high purity recombinant protein is rapidly and effectively isolated in large quantities at low cost, and thus can be applied in various industrial fields. | 10-01-2015 |
Yong Jik Lee, Busan KR
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20160037646 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - The object of the present invention is to provide a printed circuit board formed with a cavity to mount a semiconductor chip. | 02-04-2016 |
Yong-Jik Lee, Seoul KR
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20090009489 | Portable Apparatus and Method for Inputing Data With Electronic Pen and Transmitting Data - Disclosed is a portable apparatus and a method for inputting data with an electronic pen and transmitting data. More particularly, there is provided a portable apparatus for creating image data with an electronic pen and transmitting the created image data, or inputting data with an electronic pen, which allows a user to input numerals, characters, etc. without a keypad, and transmitting the input data, and to a data input and transmission method using such a portable apparatus. | 01-08-2009 |
20100067674 | MESSENGER SYSTEM FOR TRANSMITTING HANDWRITING INSTANT MESSAGES THROUGH WIRE AND/OR WIRELESS NETWORK SYSTEM AND MESSENGER SERVICE METHOD THEREOF - Disclosed are a wire and/or wireless handwriting instant messenger system and a method for realizing the same. In the wire and/or wireless handwriting instant messenger system, handwritten input information created in a handwritten input information generator is transmitted from a transmission terminal through a wire/wireless network, and received in a reception terminal, thereby allowing users to make communication with each other. | 03-18-2010 |
Yong-Jik Park, Suwon-Si KR
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20110018051 | Integrated Circuit Memory Devices Having Vertical Transistor Arrays Therein and Methods of Forming Same - An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively. | 01-27-2011 |
20140015032 | INTEGRATED CIRCUIT MEMORY DEVICES HAVING VERTICAL TRANSISTOR ARRAYS THEREIN AND METHODS OF FORMING SAME - An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively. | 01-16-2014 |
Yong-Jik Park, Gyeonggi-Do KR
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20100308391 | SEMICONDUCTOR DEVICE - Provided are a semiconductor device and a method of fabricating the same. At least one mold structure defining at least one first opening is formed on a substrate, wherein the mold structure comprises first mold patterns and second mold patterns that are sequentially and alternatingly stacked. Thereafter, side surfaces of the first mold patterns are selectively etched to form undercut regions between the second mold patterns. Then, a semiconductor layer is formed to cover a surface of the mold structure where the undercut regions are formed, and gate patterns are formed, which fill respective undercut regions where the semiconductor layer is formed. | 12-09-2010 |
20120181593 | Semiconductor Device - Provided is a semiconductor device that can include a lower interconnection on a substrate and at least one upper interconnection disposed on the lower interconnection. At least one gate structure can be disposed between the upper interconnection and the lower interconnection, where the gate structure can include a plurality of gate lines that are vertically stacked so that each of the gate lines has a wiring portion that is substantially parallel to an upper surface of the substrate and a contact portion that extends from the wiring portion along a direction penetrating an upper surface of the substrate. At least one semiconductor pattern can connect the upper and lower interconnections. | 07-19-2012 |