Patent application number | Description | Published |
20080231790 | Active matrix type display device - An active matrix type display device is disclosed, to reduce a fabrication cost, which comprises first to third gate lines arranged at one direction; first and second data lines arranged orthogonally to the first to third gate lines; a first pixel cell connected to the first gate line and the first data line; a second pixel cell connected to the first gate line and the second data line; a third pixel cell connected to the second gate line and the first data line; a fourth pixel cell connected to the second gate line and the second data line; a fifth pixel cell connected to the third gate line and the first data line; and a sixth pixel cell connected to the third gate line and the second data line, wherein the three predetermined pixel cells of displaying the different colors among the first to sixth pixel cells constitute a first unit pixel for displaying a first unit image; and the three other pixel cells except the pixel cells included in the first unit pixel constitute a second unit pixel for displaying a second unit image. | 09-25-2008 |
20080252624 | Liquid crystal display device - Disclosed herein is a liquid crystal display device which is capable of reducing the number of data drive integrated circuits (ICs) to curtail a production cost. The liquid crystal display device includes a plurality of pixel cells formed respectively in areas defined by a plurality of gate lines and a plurality of data lines, a first unit pixel including at least three of the pixel cells, the at least three pixel cells being connected to different ones of the data lines, and a second unit pixel including at least three of the pixel cells other than the at least three pixel cells of the first unit pixel, the at least three pixel cells of the second unit pixel being connected respectively to the different data lines to which the at least three pixel cells of the first unit pixel are connected, wherein the first and second unit pixels are arranged in a direction of the data lines and connected to different ones of the gate lines. A plurality of adjacent pixel cells expressing the same colors or different colors on horizontal lines, among the pixel cells, are connected in common to the same data lines. | 10-16-2008 |
20100214279 | SHIFT REGISTER - A shift register which is capable of minimizing a spike voltage is disclosed. The shift register includes a plurality of stages, each including a plurality of nodes, a scan pulse output unit controlled according to voltages at the nodes for outputting a scan pulse and supplying it to a corresponding gate line through a scan output terminal, a carry pulse output unit controlled according to the voltages at the nodes for outputting a carry pulse and supplying it to an upstream stage and a downstream stage through a carry output terminal, a node controller for controlling voltage states of the nodes in response to a carry pulse from the upstream stage and a carry pulse from the downstream stage, and a discharging unit connected to any one of a plurality of clock transfer lines and the scan output terminal for discharging a spike voltage of the scan output terminal. | 08-26-2010 |
20120013585 | SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME AND DRIVING METHOD THEREOF - A shift register includes a plurality of first to n-numbered stages, where n is a positive integer. Each stage includes a node controller controlling respective voltages of a first node and a second node in accordance with an output signal from the (i−j | 01-19-2012 |
20120098808 | DISPLAY DEVICE AND DRIVING METHOD THEREOF - A display device and driving method are provided. A display device includes a display area that includes a plurality of pixel cells in respective pixel regions defined by a plurality of gate and data lines crossing each other. A data driver is operable to supply data signals to the pixel cells. The pixel cells are connected with the first data line and are divided into a plurality of pixel-cell groups. The data driver is operable to supply the data signal of first polarity to the pixel cells included in the odd-numbered pixel-cell groups, and to supply the data signal of second polarity to the pixel cells included in the even-numbered pixel-cell groups. The first polarity is opposite to the second polarity. A shift register that is operable to drive the gate lines to supply the scan pulses of different amplitudes to neighboring pixel cells included in the different pixel-cell groups. | 04-26-2012 |
20120100400 | INSTRUMENT CONNECTION TYPE UNIT PACK COMBINED CELL CARTRIDGE - The present invention relates to an instrument connection type unit pack combined cell cartridge assembled into a compound cell interconnection mesh, and to a combined cartridge electricity storage device assembled into a compound unit interconnection mesh in which a plurality of cell cartridges are electrically interconnected. The unit pack combined cell cartridge of the present invention is configured such that a plurality of cells are interconnected into a unit pack using a suitable device (bus bar), and a plurality of unit packs are interconnected into a unitary cartridge using a suitable device (intermediate conductor plate). The combined cartridge electricity storage device of the present invention is configured such that a plurality of unit pack combined cartridges are accommodated in an outer case and interconnected into a serial or parallel compound interconnection structure to form a unitary system. The present invention interconnects cells, unit packs and cartridges using an easily connectible or separable instrument, to thereby allow for ease of assembly and improve productivity. In addition, the number of cells used in a unit pack, the number of unit packs used in a cartridge, and the number of cartridges used in an electricity storage device can be adjusted and changed to change current capacity and voltage capacity with ease. | 04-26-2012 |
20130010916 | Gate Driving Circuit - Disclosed herein is a gate driving circuit including a first clock generator to sequentially output n output clock pulses, a second clock generator to sequentially output n output control clock pulses, and a shift register to receive the n output clock pulses and the n output control clock pulses and to sequentially output a plurality of scan pulses, wherein high sections of k-th to (k+s)-th output clock pulses output during adjacent periods overlap with one another, a k-th output control clock pulse rises before the k-th output clock pulse, the k-th output control clock pulse falls before a (k−a)-th output clock pulse, a high section of the output control clock pulses does not overlap with that of the k-th output clock pulse, and a (k+b)-th output clock pulse falls during the high section of the output control clock pulses not overlapping with that of the k-th output clock pulse. | 01-10-2013 |
20140044228 | Shift Register - Disclosed herein is a shift register which is capable of preventing leakage of charges at a set node which occurs when the duty ratio of a scan pulse is small, so as to normally output a scan pulse. The shift register includes a plurality of stages for sequentially generating outputs thereof. Each of the stages includes a carry output unit for outputting a carry pulse to drive at least one of a downstream stage and an upstream stage, and a scan output unit for outputting a scan pulse to drive a gate line. Each of the outputs generated from the stages includes the carry pulse and the scan pulse. The carry pulse and the scan pulse are paired to correspond to each other. The paired carry pulse and scan pulse have different durations. | 02-13-2014 |