Patent application number | Description | Published |
20120256276 | Metal Gate and Fabricating Method Thereof - A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O | 10-11-2012 |
20130095616 | METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE - A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer. | 04-18-2013 |
20130154012 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE - A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench. | 06-20-2013 |
20130200470 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures. | 08-08-2013 |
20130203230 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate is provided. An ozone saturated deionized water process is performed to form an oxide layer on the substrate. A dielectric layer is formed on the oxide layer. A post dielectric annealing (PDA) process is performed on the dielectric layer and the oxide layer. | 08-08-2013 |
20130302976 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench. | 11-14-2013 |
20140015056 | MULTI-GATE MOSFET AND PROCESS THEREOF - A multi-gate MOSFET includes a substrate, a dielectric layer and at least a fin-shaped structure. The substrate has a first area and a second area. The dielectric layer is only located in the substrate of the first area. At least a fin-shaped structure is located on the dielectric layer. Moreover, the present invention also provides a multi-gate MOSFET process forming said multi-gate MOSFET. | 01-16-2014 |
20140035066 | Non-Planar FET and Manufacturing Method Thereof - The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same. | 02-06-2014 |
20140077229 | SEMICONDUCTOR STRUCTURE - A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures. | 03-20-2014 |
20140106557 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE - A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench. | 04-17-2014 |
20140199817 | METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE - A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer. | 07-17-2014 |
20140295660 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally foamed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench. | 10-02-2014 |
20140339652 | SEMICONDUCTOR DEVICE WITH OXYGEN-CONTAINING METAL GATES - A semiconductor device with oxygen-containing metal gates includes a substrate, a gate dielectric layer and a multi-layered stack structure. The multi-layered stack structure is disposed on the substrate. At least one layer of the multi-layered stack structure includes a work function metal layer. The concentration of oxygen in the side of one layer of the multi-layered stack structure closer to the gate dielectric layer is less than that in the side of one layer of the multi-layered stack structure opposite to the gate dielectric layer. | 11-20-2014 |
Patent application number | Description | Published |
20130095644 | PLANARIZATION PROCESS FOR SEMICONDUCTOR DEVICE FABRICATION - The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature. | 04-18-2013 |
20130164930 | GATE HEIGHT LOSS IMPROVEMENT FOR A TRANSISTOR - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure over an iso region of a substrate and a second gate structure over a dense region of the substrate. The dense region has a greater pattern density than the iso region. The first and second gate structures each have a respective hard mask disposed thereon. The method includes removing the hard masks from the first and second gate structures. The removal of the hard mask from the second gate structure causes an opening to be formed in the second gate structure. The method includes performing a deposition process followed by a first polishing process to form a sacrificial component in the opening. The method includes performing a second polishing process to remove the sacrificial component and portions of the first and second gate structures. | 06-27-2013 |
20140370696 | MECHANISMS FOR FORMING OXIDE LAYER OVER EXPOSED POLYSILICON DURING A CHEMICAL MECHANICAL POLISHING (CMP) PROCESS - Embodiments of cleaning a surface of a polysilicon layer during a chemical mechanical polishing (CMP) process are provided. The method includes providing a substrate, and forming a gate structure on the substrate, and the gate structure includes a polysilicon layer. The method further includes forming an inter-layer dielectric layer (ILD) over the gate structure. The method also includes performing a CMP process to planarize the inter-layer dielectric layer (ILD) and to expose the polysilicon layer, and the CMP process includes: providing an oxidation solution to a surface of the substrate to perform an oxidation operation to form an oxide layer on the polysilicon layer; and providing a cleaning solution to the surface of the substrate to perform a cleaning operation. | 12-18-2014 |
20150099431 | CMP Slurry Particle Breakup - A method for breaking up Chemical Mechanical Polishing (CMP) slurry particles includes receiving a CMP slurry comprising particles suspended in a solution, placing the slurry into a first agitation tank, and agitating the slurry at a first frequency. The first frequency is selected to break up particles having a size within a specified range. | 04-09-2015 |
20150102456 | AMORPHORUS SILICON INSERTION FOR STI-CMP PLANARITY IMPROVEMENT - A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a first cushion layer, a second cushion layer and an insulating filler. The first cushion layer is peripherally enclosed by the semiconductor substrate, the second cushion layer is peripherally enclosed by the first cushion layer, and insulating filler is peripherally enclosed by the second cushion layer. A method for fabricating the semiconductor device is also provided herein. | 04-16-2015 |
20150187594 | Composite Structure for Gate Level Inter-Layer Dielectric - A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process. | 07-02-2015 |
20150279686 | SEMICONDUCTOR PROCESSING METHODS - One or more methods for semiconductor processing are provided. At least one of the methods include receiving information regarding a pre-etch back thickness of a first layer over a substrate, comparing the pre-etch back thickness to a desired thickness of the first layer, responsive to the pre-etch back thickness being greater than the desired thickness, determining parameters for an etch back process and performing the etch back process on the first layer to reduce the pre-etch back thickness to a first etch back thickness. The etch back process comprising performing a gas cluster ion beam etching process. In some embodiments, a second etch back process is performed. In some embodiments a wet clean process is performed on the first layer after the etch back process. | 10-01-2015 |