Patent application number | Description | Published |
20080315388 | VERTICAL CONTROLLED SIDE CHIP CONNECTION FOR 3D PROCESSOR PACKAGE - In some embodiments, vertical controlled side chip connection for 3D processor package is presented. In this regard, an apparatus is introduced having a substrate, a substantially horizontal, in relation to the substrate, integrated circuit device coupled to the substrate, and a substantially vertical, in relation of the substrate, integrated circuit device coupled to the substrate and adjacent to one side of the substantially horizontal integrated circuit device. Other embodiments are also disclosed and claimed. | 12-25-2008 |
20120237125 | Isolating Background and Foreground Objects in Video - In accordance with some embodiments, background subtraction can be performed by iteratively computing a new expected background image from an old background image using a plurality of consecutive frames. The new expected background image may be computed to be closer to a current frame's pixel value. In some embodiments, a new expected background image may be based on user supplied values so that a user may determine how fast a background image changes. | 09-20-2012 |
20130275639 | METHOD TO EMULATE MESSAGE SIGNALED INTERRUPTS WITH MULTIPLE INTERRUPT VECTORS - Methods to emulate a message signaled interrupt (MSI) with multiple interrupt vectors are described herein. An embodiment of the invention includes a memory decoder to monitor a predetermined memory location allocated to a device and to generate an emulated message signaled interrupt (MSI) signal in response to a posted write transaction to the predetermined memory location initiated from the device, and an interrupt controller, in response to the emulated MSI signal from the memory decoder, to invoke processing of a plurality of interrupts based on a plurality of interrupt vectors retrieved from the predetermined memory location, without receiving an actual MSI interrupt request from the device. | 10-17-2013 |
20140006668 | Performing Emulated Message Signaled Interrupt Handling | 01-02-2014 |
20140009378 | User Profile Based Gesture Recognition - An embodiment includes a system recognizing a first user via a camera, selecting a profile for the first user, and interpreting the first user's gestures according to that profile. For example, the embodiment identifies a first user, loads his gesture signature profile, and then interprets the first user forming his fist with his thumb projecting upwards as acceptance of a condition presented to the user (e.g., whether the user wishes to turn a tuner to a certain channel). The embodiment recognizes a second user, selects a profile for the second user, and interprets the second user's gestures according to that profile. For example, the embodiment identifies the second user, loads her profile, and then interprets the second user forming her fist with her thumb projecting upwards as the user pointing upwards. This moves an area of focus upwards on a graphical user interface. Other embodiments are described herein. | 01-09-2014 |
20140156950 | EMULATED MESSAGE SIGNALED INTERRUPTS IN MULTIPROCESSOR SYSTEMS - A processor with coherency-leveraged support for low latency message signaled interrupt handling includes multiple execution cores and their associated cache memories. A first cache memory associated a first of the execution cores includes a plurality of cache lines. The first cache memory has a cache controller including hardware logic, microcode, or both to identify a first cache line as an interrupt reserved cache line and map the first cache line to a selected memory address associated with an I/O device. The selected system address may be a portion of configuration data in persistent storage accessible to the processor. The controller may set a coherency state of the first cache line to shared and, in response to detecting an I/O transaction including I/O data from the I/O device and containing a reference to the selected memory address, emulate a first message signaled interrupt identifying the selected memory address. | 06-05-2014 |
20140168708 | COMBINING PRINT JOBS - A method and system for combining print jobs is described herein. The method includes loading a print surface containing a first print job and obtaining a second print job. The first print job and the second print job may be combined into a composite file, wherein the composite file is used to adjust the first print job and the second print job. | 06-19-2014 |
20140189182 | METHOD TO ACCELERATE MESSAGE SIGNALED INTERRUPT PROCESSING - Methods to accelerate a message signaled interrupt (MSI) are described herein. An embodiment of the invention includes an interrupt controller to receive a messaged signaled interrupt (MSI) request from a device over a bus, and an execution unit coupled to the interrupt controller to execute an interrupt service routine (ISR) associated with the device, the execution unit to retrieve interrupt data from a predetermined memory location specifically allocated to the device and to service the MSI using the interrupt data, without having to obtain the device interrupt data via an input output (IO) transaction. | 07-03-2014 |
20140192677 | NETWORK ROUTING PROTOCOL POWER SAVING METHOD FOR NETWORK ELEMENTS - Methods and apparatus relating to network routing protocols to support power savings in network elements. A most utilized link path network topology for a computer network is discovered using a routing protocol such as a Spanning Tree, link-state, or distance vector routing protocol. In view of the most utilized link path network topology, links are identified as candidates for power management under which a power state of the link and associated network ports are managed to save power under applicable link conditions, such as low utilization. Link power-state change conditions are detected, and in response a corresponding change to the power state of a link is effected by changing the power-state of the network ports at the ends of the link. Power state changes include putting a link into a reduced power state, taking a link offline, and powering a link back up. | 07-10-2014 |
20140195792 | HIDING BOOT LATENCY FROM SYSTEM USERS - Methods and systems may provide for identifying a proximity condition between a system and a potential user of the system. In addition, one or more boot components of the system can be activated in response to the proximity condition, wherein one or more peripheral devices associated with the system are maintained in an inactive state. In one example, at least one of the one or more peripheral devices is placed in an active state in response to detecting an activation condition of the system. | 07-10-2014 |
20140237144 | METHOD TO EMULATE MESSAGE SIGNALED INTERRUPTS WITH INTERRUPT DATA - Methods to emulate a message signaled interrupt (MSI) with interrupt data are described herein. An embodiment of the invention includes a memory decoder to monitor a predetermined memory block allocated to a device, an interrupt controller to receive an emulated messaged signaled interrupt (MSI) signal from the memory decoder in response to a posted write transaction to the predetermined memory block initiated from the device, and an execution unit to execute an interrupt service routine (ISR) associated with the device to service the MSI using interrupt data retrieved from the predetermined memory block, without having to obtain the interrupt data from the device via an input output (IO) transaction. | 08-21-2014 |
20140310721 | REDUCING THE NUMBER OF READ/WRITE OPERATIONS PERFORMED BY A CPU TO DUPLICATE SOURCE DATA TO ENABLE PARALLEL PROCESSING ON THE SOURCE DATA - Methods and apparatuses to reduce the number of read/write operations performed by a CPU may involve duplicating source data to enable parallel processing on the source data. A memory controller may be configured to duplicate data written to a first buffer to one or more duplicate buffers that are allocated to one or more processing threads, respectively. In some implementations, the one or more duplicate buffers are dedicated buffers, and the addresses of the first buffer and the one or more duplicate buffers are stored in a register of memory controller. | 10-16-2014 |