Patent application number | Description | Published |
20110215405 | PREVENTION OF OXYGEN ABSORPTION INTO HIGH-K GATE DIELECTRIC OF SILICON-ON-INSULATOR BASED FINFET DEVICES - A method of forming fin field effect transistor (finFET) devices includes forming a plurality of semiconductor fins over a buried oxide (BOX) layer; performing a nitrogen implant so as to formed nitrided regions in a upper portion of the BOX layer corresponding to regions between the plurality of semiconductor fins; forming a gate dielectric layer over the semiconductor fins and the nitrided regions of the upper portion of the BOX layer; and forming one or more gate electrode materials over the gate dielectric layer; wherein the presence of the nitrided regions of upper portion of the BOX layer prevents oxygen absorption into the gate dielectric layer as a result of thermal processing. | 09-08-2011 |
20120038007 | Field Effect Transistor Device With Self-Aligned Junction - A method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, the source extension portion extending from the source region into the first portion of the substrate, forming an ion doped drain extension portion in the substrate, the drain extension portion extending from the drain region into the first portion of the substrate, removing a portion of the dummy gate stack to expose an interfacial layer of the dummy gate stack, implanting ions in the source extension portion and the drain extension portion to form a channel region in the first portion of the substrate, removing the interfacial layer, and forming a gate stack on the channel region of the substrate. | 02-16-2012 |
20120038008 | Field Effect Transistor Device with Self-Aligned Junction and Spacer - In one aspect of the present invention, a method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, forming an ion doped drain extension portion in the substrate, forming a first spacer portion adjacent to the dummy gate stack, removing the dummy gate stack to expose a channel region of the substrate, a portion of the ion doped source extension portion, and a portion of the ion doped drain extension portion, forming a second spacer portion on the exposed portion of the ion doped source extension portion and on the exposed portion of the ion doped drain extension portion, and forming a gate stack on the exposed channel region of the substrate. | 02-16-2012 |
20120193712 | FinFET STRUCTURE HAVING FULLY SILICIDED FIN - A semiconductor device which includes fins of a semiconductor material formed on a semiconductor substrate and then a gate electrode formed over and in contact with the fins. An insulator layer is deposited over the gate electrode and the fins. A trench opening is then etched in the insulator layer. The trench opening exposes the fins and extends between the fins. The fins are then silicided through the trench opening. Then, the trench opening is filled with a metal in contact with the silicided fins to form a local interconnect connecting the fins. | 08-02-2012 |
20120220114 | TENSILE STRESS ENHANCEMENT OF NITRIDE FILM FOR STRESSED CHANNEL FIELD EFFECT TRANSISTOR FABRICATION - A method for inducing a tensile stress in a channel of a field effect transistor (FET) includes forming a nitride film over the FET; forming a contact hole to the FET through the nitride film; and performing ultraviolet (UV) curing of the nitride film after forming the contact hole to the FET through the nitride film, wherein the UV cured nitride film induces the tensile stress in the channel of the FET. | 08-30-2012 |
20120235247 | FIN FIELD EFFECT TRANSISTOR WITH VARIABLE CHANNEL THICKNESS FOR THRESHOLD VOLTAGE TUNING - A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers. | 09-20-2012 |
20120286360 | Field Effect Transistor Device with Self-Aligned Junction and Spacer - A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, a first spacer portion disposed on the source region, the drain region and a first portion of the source extension portion, and a first portion of the drain extension portion, a second spacer portion disposed on a second portion of the source extension portion, and a second portion of the drain extension portion, a gate stack portion disposed on the channel region. | 11-15-2012 |
20120286371 | Field Effect Transistor Device With Self-Aligned Junction - A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, wherein the channel region includes a source transition portion including n-type and p-type ions and a drain transition portion including n-type and p-type ions, and a gate stack portion disposed on the channel region. | 11-15-2012 |
20120286375 | PRESERVING STRESS BENEFITS OF UV CURING IN REPLACEMENT GATE TRANSISTOR FABRICATION - A method of forming a semiconductor structure includes forming a stress inducing layer over one or more partially completed field effect transistor (FET) devices disposed over a substrate, the one or more partially completed FET devices including sacrificial dummy gate structures; planarizing the stress inducing layer and removing the sacrificial dummy gate structures; and following the planarizing the stress inducing layer and removing the sacrificial dummy gate structures, performing an ultraviolet (UV) cure of the stress inducing layer so as to enhance a value of an initial applied stress by the stress inducing layer on channel regions of the one or more partially completed FET devices. | 11-15-2012 |
20130029488 | Single Liner Process to Achieve Dual Stress - Methods for imparting a dual stress property in a stress liner layer of a semiconductor device. The methods include depositing a metal layer over a compressive stress liner layer, applying a masking agent to a portion of the metal layer to produce a masked and unmasked region of the metal layer, etching the unmasked region of the metal layer to remove the metal layer in the unmasked region to thereby expose a corresponding portion of the compressive stress liner layer, removing the mask to expose the metal layer from the masked region, and irradiating the compressive stress liner layer to impart a tensile stress property to the exposed portion of the compressive stress liner layer. Methods are also provided for imparting a compressive-neutral dual stress property in a stress liner layer, as well as for imparting a neutral-tensile dual stress property in a stress liner layer. | 01-31-2013 |
20130082329 | MULTI-GATE FIELD-EFFECT TRANSISTORS WITH VARIABLE FIN HEIGHTS - Multi-gate devices and methods of their fabrication are disclosed. A multi-gate device can include a gate structure and a plurality of fins. The gate structure envelops a plurality of surfaces of the fins, which are directly on a substrate that is composed of a semiconducting material. Each of the fins provides a channel between a respective source and a respective drain, is composed of the semiconducting material and is doped. A first fin of the plurality of fins has a first height that is different from a second height of a second fin of the plurality of fins such that drive currents of the first and second fins are different. Further, the first and second fins form a respective cohesive structure of the semiconducting material with the substrate. In addition, surfaces of the substrate that border the fins are disposed at a same vertical position. | 04-04-2013 |
20130082333 | MULTI-GATE FIELD-EFFECT TRANSISTORS WITH VARIABLE FIN HEIGHTS - Multi-gate devices and methods of their fabrication are disclosed. A multi-gate device can include a gate structure and a plurality of fins. The gate structure envelops a plurality of surfaces of the fins, which are directly on a substrate that is composed of a semiconducting material. Each of the fins provides a channel between a respective source and a respective drain, is composed of the semiconducting material and is doped. A first fin of the plurality of fins has a first height that is different from a second height of a second fin of the plurality of fins such that drive currents of the first and second fins are different. Further, the first and second fins form a respective cohesive structure of the semiconducting material with the substrate. In addition, surfaces of the substrate that border the fins are disposed at a same vertical position. | 04-04-2013 |
20130105894 | THRESHOLD VOLTAGE ADJUSTMENT FOR THIN BODY MOSFETS | 05-02-2013 |
20130105896 | Threshold Voltage Adjustment For Thin Body Mosfets | 05-02-2013 |
20130154001 | EMBEDDED STRESSORS FOR MULTIGATE TRANSISTOR DEVICES - Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region. | 06-20-2013 |
20130154005 | SOI FINFET WITH RECESSED MERGED FINS AND LINER FOR ENHANCED STRESS COUPLING - FinFETS and methods for making FinFETs with a recessed stress liner. A method includes providing an SW substrate with fins, forming a gate over the fins, forming an off-set spacer on the gate, epitaxially growing a film to merge the fins, depositing a dummy spacer around the gate, and recessing the merged epi film. Silicide is then formed on the recessed merged epi film followed by deposition of a stress liner film over the FinFET. By using a recessed merged epi process, a MOSFET with a vertical silicide (i.e. perpendicular to the substrate) can be formed. The perpendicular silicide improves spreading resistance. | 06-20-2013 |
20130154006 | FINFET WITH VERTICAL SILICIDE STRUCTURE - FinFETS and methods for making FinFETs with a vertical silicide structure. A method includes providing a substrate with a plurality of fins, forming a gate stack above the substrate wherein the gate stack has at least one sidewall and forming an off-set spacer adjacent the gate stack sidewall. The method also includes growing an epitaxial film which merges the fins to form an epi-merge layer, forming a field oxide layer adjacent to at least a portion of the off-set spacer and removing a portion of the field oxide layer to expose a portion of the epi-merge-layer. The method further includes removing at least part of the exposed portion of the epi-merge-layer to form an epi-merge sidewall and an epi-merge spacer region and forming a silicide within the epi-merge sidewall to form a silicide layer and two silicide sidewalls. | 06-20-2013 |
20130154029 | EMBEDDED STRESSORS FOR MULTIGATE TRANSISTOR DEVICES - Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region. | 06-20-2013 |
20130161744 | FINFET WITH MERGED FINS AND VERTICAL SILICIDE - A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region. | 06-27-2013 |
20130164890 | METHOD FOR FABRICATING FINFET WITH MERGED FINS AND VERTICAL SILICIDE - A method is provided for fabricating a finFET device. Fin structures are formed over a BOX layer. The fin structures include a semiconductor layer and extend in a first direction. A gate stack is formed on the BOX layer over the fin structures and extending in a second direction. The gate stack includes a high-K dielectric layer and a metal gate. Gate spacers are formed on sidewalls of the gate stack, and an epi layer is deposited to merge the fin structures. Ions are implanted to form source and drain regions, and dummy spacers are formed on sidewalls of the gate spacers. The dummy spacers are used as a mask to recess or completely remove an exposed portion of the epi layer. Silicidation forms silicide regions that abut the source and drain regions and each include a vertical portion located on the vertical sidewall of the source or drain region. | 06-27-2013 |
20130175594 | INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC - An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region. | 07-11-2013 |
20130175620 | FINFET WITH FULLY SILICIDED GATE - A method is provided for fabricating a finFET device. Multiple fin structures are formed over a BOX layer, and a gate stack is formed on the BOX layer. The fin structures each include a semiconductor layer and extend in a first direction, and the gate stack is formed over the fin structures and extends in a second direction. The gate stack includes dielectric and polysilicon layers. Gate spacers are formed on vertical sidewalls of the gate stack, and an epi layer is deposited over the fin structures. Ions are implanted to form source and drain regions, and the gate spacers are etched so that their upper surface is below an upper surface of the gate stack. After etching the gate spacers, silicidation is performed to fully silicide the polysilicon layer of the gate stack and to form silicide regions in an upper surface of the source and drain regions. | 07-11-2013 |
20130175632 | REDUCTION OF CONTACT RESISTANCE AND JUNCTION LEAKAGE - A time clock clearly identifies where a user should position a time card therein. The clock and a printer platen are fixed relative to a base, and has the time card rests thereon. A printing mechanism moves relative to the base and has a target area, it is traversable between a print position and an idle position, and it impresses the time indicia onto the time card while in the print position. A ribbon shield is fixed relative to the base. A focused illuminated guide is fixed relative to the base, and in combination with the ribbon shield, guides the time card with respect to the printing mechanism to clearly identify where the user should position the time card in the time clock. | 07-11-2013 |
20130178020 | FINFET WITH FULLY SILICIDED GATE - A method is provided for fabricating a finFET device. Multiple fin structures are formed over a BOX layer, and a gate stack is formed on the BOX layer. The fin structures each include a semiconductor layer and extend in a first direction, and the gate stack is formed over the fin structures and extends in a second direction. The gate stack includes dielectric and polysilicon layers. Gate spacers are formed on vertical sidewalls of the gate stack, and an epi layer is deposited over the fin structures. Ions are implanted to form source and drain regions, and the gate spacers are etched so that their upper surface is below an upper surface of the gate stack. After etching the gate spacers, silicidation is performed to fully silicide the polysilicon layer of the gate stack and to form silicide regions in an upper surface of the source and drain regions. | 07-11-2013 |
20130200468 | Integration of SMT in Replacement Gate FINFET Process Flow - A method of fabricating a FINFET includes the following steps. A plurality of fins is patterned in a wafer. A dummy gate is formed covering a portion of the fins which serves as a channel region. Spacers are formed on opposite sides of the dummy gate. The dummy gate is removed thus forming a trench between the spacers that exposes the fins in the channel region. A nitride material is deposited into the trench so as to cover a top and sidewalls of each of the fins in the channel region. The wafer is annealed to induce strain in the nitride material thus forming a stressed nitride film that covers and induces strain in the top and the sidewalls of each of the fins in the channel region of the device. The stressed nitride film is removed. A replacement gate is formed covering the fins in the channel region. | 08-08-2013 |
20130207194 | TRANSISTORS WITH UNIAXIAL STRESS CHANNELS - A method for fabricating a transistor with uniaxial stress channels includes depositing an insulating layer onto a substrate, defining bars within the insulating layer, recessing a channel into the substrate, growing a first semiconducting material in the channel, defining a gate stack over the bars and semiconducting material, defining source and drain recesses and embedding a second semiconducting material into the source and drain recesses. | 08-15-2013 |
20130264653 | STRUCTURE AND METHOD OF HIGH-PERFORMANCE EXTREMELY THIN SILICON ON INSULATOR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTORS WITH DUAL STRESS BURIED INSULATORS - A method of forming a complementary metal oxide semiconductor (CMOS) device including an n-type field effect transistor (NFET) and an p-type field effect transistor (PFET) having fully silicided gates electrode in which an improved dual stress buried insulator is employed to incorporate and advantageous mechanical stress into the device channel of the NFET and PFET. The method can be imposed on a bulk substrate or extremely thin silicon on insulator (ETSOI) substrate. The device includes a semiconductor substrate, a plurality of shallow trench isolations structures formed in the ETSOI layer, NFET having a source and drain region and a gate formation, a PFET having a source and drain region, and a gate formation, an insulator layer, including a stressed oxide or nitride, deposited inside the substrate of the NFET, and a second insulator layer, including either an stressed oxide or nitride, deposited inside the substrate of the PFET. | 10-10-2013 |
20130285156 | FIN FIELD EFFECT TRANSISTOR WITH VARIABLE CHANNEL THICKNESS FOR THRESHOLD VOLTAGE TUNING - A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers. | 10-31-2013 |
20130307079 | ETCH RESISTANT BARRIER FOR REPLACEMENT GATE INTEGRATION - Semiconductor devices and methods of their fabrication are disclosed. One device includes a plurality of gates and a dielectric gap filling material with a pre-determined aspect ratio that is between the gates. The device further includes an etch resistant nitride layer that is configured to maintain the aspect ratio of the dielectric gap filling material during fabrication of the device and is disposed above the dielectric gap filling material and between the plurality of gates. | 11-21-2013 |
20130307121 | RETROGRADE SUBSTRATE FOR DEEP TRENCH CAPACITORS - A semiconductor device includes a substrate having a first doped portion to a first depth and a second doped portion below the first depth. A deep trench capacitor is formed in the substrate and extends below the first depth. The deep trench capacitor has a buried plate that includes a dopant type forming an electrically conductive connection with second doped portion of the substrate and being electrically insulated from the first doped portion. | 11-21-2013 |
20130309835 | RETROGRADE SUBSTRATE FOR DEEP TRENCH CAPACITORS - A method for forming a semiconductor device includes forming a deep trench in a substrate having a first doped portion to a first depth and a second doped portion below the first depth, the deep trench extending below the first depth. A region around the deep trench is doped to form a buried plate where the buried plate includes a dopant type forming an electrically conductive connection with the second doped portion of the substrate and being electrically insulated from the first doped portion. A deep trench capacitor is formed in the deep trench using the buried plate as one electrode of the capacitor. An access transistor is formed to charge or discharge the deep trench capacitor. A well is formed in the first doped portion. | 11-21-2013 |
20130309856 | ETCH RESISTANT BARRIER FOR REPLACEMENT GATE INTEGRATION - Semiconductor devices and methods of their fabrication are disclosed. One method includes forming a semiconductor device structure including a plurality of dummy gates and a dielectric gap filling material with a pre-determined aspect ratio that is between the dummy gates. An etch resistant nitride layer is applied above the dielectric gap filling material to maintain the aspect ratio of the gap filling material. In addition, the dummy gates are removed by implementing an etching process. Further, replacement gates are formed in regions of the device structure previously occupied by the dummy gates. | 11-21-2013 |
20130313649 | FIN ISOLATION FOR MULTIGATE TRANSISTORS - Multigate transistor devices and methods of their fabrication are disclosed. One such device includes a plurality of semiconductor fins that have source and drain regions and a gate structure overlaying the fins. The device further includes a dielectric layer that is beneath the gate structure and the fins. Here, the dielectric layer includes first dielectric regions that are disposed beneath the fins and second dielectric regions that are disposed between the fins. In addition, the first dielectric regions have a density that is greater than a density of the second dielectric regions. | 11-28-2013 |
20130316513 | FIN ISOLATION FOR MULTIGATE TRANSISTORS - Multigate transistor devices and methods of their fabrication are disclosed. In one method, a substrate including a semiconductor upper layer and a lower layer beneath the upper layer is provided. The lower layer has a rate of transformation into a dielectric that is higher than a rate of transformation into a dielectric of the upper layer when the upper and lower layers are subjected to dielectric transformation conditions. Fins are formed in the upper layer, and the lower layer beneath the fins is transformed into a dielectric material to electrically isolate the fins. In addition, a gate structure is formed over the fins to complete the multigate transistor device. | 11-28-2013 |
20130328135 | PREVENTING FULLY SILICIDED FORMATION IN HIGH-K METAL GATE PROCESSING - A gate stack structure for a transistor device includes a gate dielectric layer formed over a substrate; a first silicon gate layer formed over the gate dielectric layer; a dopant-rich monolayer formed over the first silicon gate layer; and a second silicon gate layer formed over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer. | 12-12-2013 |
20130330899 | PREVENTING FULLY SILICIDED FORMATION IN HIGH-K METAL GATE PROCESSING - A method of forming gate stack structure for a transistor device includes forming a gate dielectric layer over a substrate; forming a first silicon gate layer over the gate dielectric layer; forming a dopant-rich monolayer over the first silicon gate layer; and forming a second silicon gate layer over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer. | 12-12-2013 |
20140027831 | Method of eDRAM DT Strap Formation in FinFET Device Structure - The specification and drawings present a new method, device and computer/software related product (e.g., a computer readable memory) are presented for realizing eDRAM strap formation in Fin FET device structures. Semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer is provided. The (metal) strap formation is accomplished by depositing conductive layer on fins portion of the second semiconductor layer (Si) and a semiconductor material (polysilicon) in each DT capacitor extending to the second semiconductor layer. The metal strap is sealed by a nitride spacer to prevent the shorts between PWL and DT capacitors. | 01-30-2014 |
20140027878 | SELF-ALIGNED TRENCH OVER FIN - A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch. A dielectric material layer is conformally deposited and planarized. The dielectric material layer is etched employing an anisotropic etch that is selective to the first hard mask portion to form a dielectric material portion that laterally surrounds the first hard mask portion. After removal of the second and first hard mask portions, the semiconductor material layer is etched employing the dielectric material portion as an etch mask. Optionally, portions of the semiconductor material layer underneath the first and second hard mask portions can be undercut at a periphery. | 01-30-2014 |
20140027917 | NON-LITHOGRAPHIC LINE PATTERN FORMATION - A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions. | 01-30-2014 |
20140027923 | NON-LITHOGRAPHIC HOLE PATTERN FORMATION - A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation or nitridation. A hard mask portion is formed over the metal layer. A plasma impermeable spacer is formed on at least one first sidewall of the hard mask portion, while at least one second sidewall of the hard mask portion is physically exposed. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. A sequence of a surface pull back of the hard mask portion, cavity etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a hole pattern having a spacing that is not limited by lithographic minimum dimensions. | 01-30-2014 |
20140030864 | Method of eDRAM DT Strap Formation In FinFET Device Structure - The specification and drawings present a new method, device and computer/software related product (e.g., a computer readable memory) are presented for realizing eDRAM strap formation in Fin FET device structures. Semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer is provided. The (metal) strap formation is accomplished by depositing conductive layer on fins portion of the second semiconductor layer (Si) and a semiconductor material (polysilicon) in each DT capacitor extending to the second semiconductor layer. The metal strap is sealed by a nitride spacer to prevent the shorts between PWL and DT capacitors. | 01-30-2014 |
20140048804 | FIN STRUCTURE FORMATION INCLUDING PARTIAL SPACER REMOVAL - A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate. | 02-20-2014 |
20140051247 | FIN STRUCTURE FORMATION INCLUDING PARTIAL SPACER REMOVAL - A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate. | 02-20-2014 |
20140054705 | SILICON GERMANIUM CHANNEL WITH SILICON BUFFER REGIONS FOR FIN FIELD EFFECT TRANSISTOR DEVICE - A fin field effect transistor (finFET) device includes a substrate; first and second source/drain regions located on the substrate; and a fin located on the substrate between the first and second source/drain regions. The fin includes a silicon germanium channel region and first and second silicon buffer regions located in the fin adjacent to and on either side of the silicon germanium channel region. The first silicon buffer region is located between the first source/drain region and the silicon germanium channel region and the second silicon buffer region is located between the second source/drain region and the silicon germanium channel region. | 02-27-2014 |
20140084249 | STACKED NANOWIRE FIELD EFFECT TRANSISTOR - A nanowire field effect transistor device includes a first nanowire having a first distal end connected to a source region, a second distal end connected to a drain region, and a channel region therebetween, the source region and the drain region arranged on a substrate, and a second nanowire having a first distal end connected to the source region and a second distal end connected to the drain region, and a channel region therebetween, a longitudinal axis of the first nanowire and a longitudinal axis of the second nanowire defining a plane, the plane arranged substantially orthogonal to a plane defined by a planar surface of the substrate. | 03-27-2014 |
20140084371 | MULTI-GATE FIELD EFFECT TRANSISTOR DEVICES - A field effect transistor device includes a substrate, a substrate insulator layer arranged on the substrate, a semiconductor fin arranged on the substrate insulator layer, a source region arranged on a portion of the substrate insulator layer, a drain region arranged on a portion of the substrate insulator layer, a first insulator layer portion arranged on the source region, a second insulator layer portion arranged on the drain region, a gate stack arranged about a channel region of the semiconductor fin, and an insulator portion arranged on the gate stack, wherein the insulator portion arranged on the gate stack is disposed between the first insulator layer portion and the second insulator layer portion. | 03-27-2014 |
20140087523 | STACKED NANOWIRE FIELD EFFECT TRANSISTOR - A method for fabricating a nanowire field effect transistor device includes depositing a first sacrificial layer on a substrate, depositing a first layer of a semiconductor material on the first sacrificial layer, depositing a second sacrificial layer on the first layer of semiconductor material, depositing a second layer of the semiconductor material on the second sacrificial layer, pattering and removing portions of the first sacrificial layer, the first semiconductor layer, the second sacrificial layer, and the second semiconductor layer, patterning a dummy gate stack, removing the dummy gate stack, removing portions of the sacrificial layer to define a first nanowire including a portion of the first semiconductor layer and a second nanowire including a portion of the second semiconductor layer, and forming gate stacks about the first nanowire and the second nanowire. | 03-27-2014 |
20140087526 | MULTI-GATE FIELD EFFECT TRANSISTOR DEVICES - A method for fabricating a field effect transistor device includes patterning a semiconductor fin on a substrate insulator layer, the substrate insulator layer arranged on a substrate, patterning a dummy gate stack over a portion of the fin, forming spacers adjacent to the dummy gate stack, removing the dummy gate stack to form a cavity that exposes portions of the substrate insulator layer and the fin, removing exposed portions of the substrate insulator layer to increase a depth of the cavity, removing a region of the substrate insulator layer from beneath the fin to suspend a portion of the fin above the substrate insulator layer, forming a gate stack in the cavity, removing a portion of the gate stack in the cavity to expose a portion of a dielectric layer arranged on the fin, and depositing an insulator material in the cavity. | 03-27-2014 |
20140103435 | VERTICAL SOURCE/DRAIN JUNCTIONS FOR A FINFET INCLUDING A PLURALITY OF FINS - Fin-defining mask structures are formed over a semiconductor material layer. A semiconductor material portion is formed by patterning the semiconductor material layer, and a disposable gate structure is formed over the fin-defining mask structures. After formation of a disposable template layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed by etching center portions of the semiconductor material portion employing the combination of the disposable template layer and the fin-defining mask structures as an etch mask. A first pad region and a second pad region laterally contact the plurality of semiconductor fins. A replacement gate structure is formed on the plurality of semiconductor fins. The disposable template layer is removed, and the first pad region and the second pad regions are vertically recessed. Vertical source/drain junctions can be formed by introducing dopants through vertical sidewalls of the recessed source and second pad regions. | 04-17-2014 |
20140110784 | REPLACEMENT METAL GATE FINFET - A method for fabricating a field effect transistor device includes depositing a hardmask over a semiconductor layer depositing a metallic alloy layer over the hardmask, defining a semiconductor fin, depositing a dummy gate stack material layer conformally on exposed portions of the fin, patterning a dummy gate stack by removing portions of the dummy gate stack material using an etching process that selectively removes exposed portions of the dummy gate stack without appreciably removing portions of the metallic alloy layer, removing exposed portions of the metallic alloy layer, forming spacers adjacent to the dummy gate stack, forming source and drain regions on exposed regions of the semiconductor fin, removing the dummy gate stack, removing exposed portions of the metallic alloy layer, and forming a gate stack conformally over exposed portions of the insulator layer and the semiconductor fin. | 04-24-2014 |
20140110785 | REPLACEMENT METAL GATE FINFET - A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer. | 04-24-2014 |
20140117490 | SEMICONDUCTOR DEVICE INCLUDING ESD PROTECTION DEVICE - A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer and a buried insulator layer disposed between the bulk substrate layer and the active semiconductor layer. A trench is formed through the SOI substrate to expose the bulk substrate layer. A doped well is formed in an upper region of the bulk substrate layer adjacent trench. The semiconductor device further includes a first doped region different from the doped well that is formed in the trench. | 05-01-2014 |
20140124861 | TRANSISTORS WITH UNIAXIAL STRESS CHANNELS - A method for fabricating a transistor with uniaxial stress channels includes depositing an insulating layer onto a substrate, defining bars within the insulating layer, recessing a channel into the substrate, growing a first semiconducting material in the channel, defining a gate stack over the bars and semiconducting material, defining source and drain recesses and embedding a second semiconducting material into the source and drain recesses. | 05-08-2014 |
20140131802 | Structure and Method to Form Passive Devices in ETSOI Process Flow - Techniques for fabricating passive devices in an extremely-thin silicon-on-insulator (ETSOI) wafer are provided. In one aspect, a method for fabricating one or more passive devices in an ETSOI wafer is provided. The method includes the following steps. The ETSOI wafer having a substrate and an ETSOI layer separated from the substrate by a buried oxide (BOX) is provided. The ETSOI layer is coated with a protective layer. At least one trench is formed that extends through the protective layer, the ETSOI layer and the BOX, and wherein a portion of the substrate is exposed within the trench. Spacers are formed lining sidewalls of the trench. Epitaxial silicon templated from the substrate is grown in the trench. The protective layer is removed from the ETSOI layer. The passive devices are formed in the epitaxial silicon. | 05-15-2014 |
20140145295 | DOUBLE DENSITY SEMICONDUCTOR FINS AND METHOD OF FABRICATION - Methods and structures having increased fin density are disclosed. Structures with two sets of fins are provided. A lower set of fins is interleaved with an upper set of fins in a staggered manner, such that the lower set of fins and upper set of fins are horizontally and vertically non-overlapping. | 05-29-2014 |
20140151773 | FINFET eDRAM STRAP CONNECTION STRUCTURE - A method of forming a strap connection structure for connecting an embedded dynamic random access memory (eDRAM) to a transistor comprises forming a buried oxide layer in a substrate, the buried oxide layer defining an SOI layer on a surface of the substrate; forming a deep trench through the SOI layer and the buried oxide layer in the substrate; forming a storage capacitor in a lower portion of the deep trench; conformally doping a sidewall of an upper portion of the deep trench; depositing a metal strap on the conformally doped sidewall and on the storage capacitor; forming at least one fin in the SOI layer, the fin being in communication with the metal strap; forming a spacer over the metal strap and over a juncture of the fin and the metal strap; and depositing a passive word line on the spacer. | 06-05-2014 |
20140159166 | Preventing FIN Erosion and Limiting Epi Overburden in FinFET Structures by Composite Hardmask - A FinFET structure is formed by forming a hardmask layer on a substrate including a silicon-containing layer on an insulating layer. The hardmask layer includes first, second and third layers on the silicon-containing layer. An array of fins is formed from the hardmask layer and the silicon-containing layer. A gate is formed covering a portion but not all of a length of each of the array of fins. The portion covers each of the fins in the array. The gate defines source/drain regions on either side of the gate. A spacer is formed on each side of the gate, the forming of the spacer performed to remove the third layer from portions of the fins in the source/drain regions. The second layer of the hardmask layer is removed from the portions of the fins in the source/drain regions, and the fins in the source/drain regions are merged. | 06-12-2014 |
20140159167 | PREVENTING FIN EROSION AND LIMITING EPI OVERBURDEN IN FINFET STRUCTURES BY COMPOSITE HARDMASK - A FinFET structure is formed by forming a hardmask layer on a substrate including a silicon-containing layer on an insulating layer. The hardmask layer includes first, second and third layers on the silicon-containing layer. An array of fins is formed from the hardmask layer and the silicon-containing layer. A gate is formed covering a portion but not all of a length of each of the array of fins. The portion covers each of the fins in the array. The gate defines source/drain regions on either side of the gate. A spacer is formed on each side of the gate, the forming of the spacer performed to remove the third layer from portions of the fins in the source/drain regions. The second layer of the hardmask layer is removed from the portions of the fins in the source/drain regions, and the fins in the source/drain regions are merged. | 06-12-2014 |
20140167162 | FINFET WITH MERGE-FREE FINS - A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions. | 06-19-2014 |
20140170825 | FINFET WITH MERGE-FREE FINS - A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions. | 06-19-2014 |
20140231890 | MIM CAPACITOR IN FINFET STRUCTURE - A method of forming a FinFET structure having a metal-insulator-metal capacitor. Silicon fins are formed on a semiconductor substrate followed by formation of the metal-insulator-metal capacitor on the silicon fins by depositing sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium nitride. A polysilicon layer is deposited over the metal-insulator-metal capacitor followed by etching back the polysilicon layer and the metal-insulator-metal capacitor layers from ends of the silicon fins so that the first and second ends of the silicon fins protrude from the polysilicon layer. A spacer may be formed on surfaces facing the ends of the silicon fins followed by the formation of epitaxial silicon over the ends of the silicon fins. Also disclosed is a FinFET structure having a metal-insulator-metal capacitor. | 08-21-2014 |
20140231891 | MIM CAPACITOR IN FINFET STRUCTURE - A FinFET structure which includes: silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium nitride on the sides and horizontal surface of the silicon fins; a polysilicon gate layer over the second layer of titanium nitride on the silicon fins and over the semiconductor substrate such that first and second ends of the silicon fins protrude from the polysilicon layer; spacers adjacent to the polysilicon gate layer; epitaxial silicon over the first and second ends of the silicon fins to form sources and drains, wherein the combination of the first layer of titanium nitride, dielectric layer and second layer of titanium nitride forms a metal-insulator-metal capacitor situated between each silicon fin and the polysilicon layer. | 08-21-2014 |
20140239395 | CONTACT RESISTANCE REDUCTION IN FINFETS - A method for forming contacts in a semiconductor device includes forming a plurality of substantially parallel semiconductor fins on a dielectric layer of a substrate having a gate structure formed transversely to a longitudinal axis of the fins. The fins are merged by epitaxially growing a crystalline material between the fins. A field dielectric layer is deposited over the fins and the crystalline material. Trenches that run transversely to the longitudinal axis of the fins are formed to expose the fins in the trenches. An interface layer is formed over portions of the fins exposed in the trenches. Contact lines are formed in the trenches that contact a top surface of the interface layer on the fins and at least a portion of side surfaces of the interface layer on the fins. | 08-28-2014 |
20140239401 | SILICON NITRIDE GATE ENCAPSULATION BY IMPLANTATION - A FinFET structure which includes: silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; a gate wrapping around at least one of the silicon fins, the gate having a first surface and an opposing second surface facing the at least one of the silicon fins; a hard mask on a top surface of the gate; a silicon nitride layer formed in each of the first and second surfaces so as to be below and in direct contact with the hard mask on the top surface of the gate; spacers on the gate and in contact with the silicon nitride layer; and epitaxially deposited silicon on the at least one of the silicon fins so as to form a raised source/drain. | 08-28-2014 |
20140239415 | STRESS MEMORIZATION IN RMG FINFETS - Transistors with memorized stress and methods for making such transistors. The methods include forming a transistor structure having a channel region, a source and drain region, and a gate dielectric; depositing a stressor over the channel region of the transistor structure, wherein the stressor provides a stress to the channel region; removing the stressor metal after the stress is memorized within the channel region; and depositing a work function metal over the channel region of the transistor structure, where the work function metal applies less stress to the channel region than the stress applied by the stressor. A transistor with memorized stress includes a source and drain region on a substrate; a stress-memorized channel region on the substrate that retains an externally applied stress; and a gate structure including a work function gate metal that applies less stress to the stress-memorized channel region than the externally applied stress. | 08-28-2014 |
20140239420 | SILICON NITRIDE GATE ENCAPSULATION BY IMPLANTATION - A method of forming a FinFET structure which includes forming fins on a semiconductor substrate; forming a gate wrapping around at least one of the fins, the gate having a first surface and an opposing second surface facing the fins; depositing a hard mask on a top of the gate; angle implanting nitrogen into the first and second surfaces of the gate so as to form a nitrogen-containing layer in the gate that is below and in direct contact with the hard mask on top of the gate; forming spacers on the gate and in contact with the nitrogen-containing layer; and epitaxially depositing silicon on the at least one fin so as to form a raised source/drain. Also disclosed is a FinFET structure. | 08-28-2014 |
20140256139 | SELF-ALIGNED TRENCH OVER FIN - A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch. A dielectric material layer is conformally deposited and planarized. The dielectric material layer is etched employing an anisotropic etch that is selective to the first hard mask portion to form a dielectric material portion that laterally surrounds the first hard mask portion. After removal of the second and first hard mask portions, the semiconductor material layer is etched employing the dielectric material portion as an etch mask. Optionally, portions of the semiconductor material layer underneath the first and second hard mask portions can be undercut at a periphery. | 09-11-2014 |
20140264595 | FORMING STRAINED AND RELAXED SILICON AND SILICON GERMANIUM FINS ON THE SAME WAFER - Various embodiments form strained and relaxed silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is formed. The semiconductor wafer comprises a substrate, a dielectric layer, and a strained silicon germanium (SiGe) layer. At least one region of the strained SiGe layer is transformed into a relaxed SiGe region. At least one strained SiGe fin is formed from a first strained SiGe region of the strained SiGe layer. At least one relaxed SiGe fin is formed from a first portion of the relaxed SiGe region. Relaxed silicon is epitaxially grown on a second strained SiGe region of the strained SiGe layer. Strained silicon is epitaxially grown on a second portion of the relaxed SiGe region. At least one relaxed silicon fin is formed from the relaxed silicon. At least one strained silicon fin is formed from the strained silicon. | 09-18-2014 |
20140264596 | PARTIALLY ISOLATED FIN-SHAPED FIELD EFFECT TRANSISTORS - A transistor device and a method for forming a fin-shaped field effect transistor (FinFET) device, with the channel portion of the fins on buried silicon oxide, while the source and drain portions of the fins on silicon. An example method includes receiving a wafer with a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. The method further comprises implanting a well in the silicon substrate and forming vertical sources and drains over the well between dummy gates. The vertical sources and drains extend through the BOX layer, fins, and a portion of the dummy gates. | 09-18-2014 |
20140264601 | STRAINED SILICON NFET AND SILICON GERMANIUM PFET ON SAME WAFER - Various embodiments form silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is obtained. The semiconductor wafer comprises a substrate, a dielectric layer, and a semiconductor layer including silicon germanium (SiGe). At least one SiGe fin is formed from at least a first SiGe region of the semiconductor layer in at least one PFET region of the semiconductor wafer. Strained silicon is epitaxially grown on at least a second SiGe region of the semiconductor layer. At least one strained silicon fin is formed from the strained silicon in at least one NFET region of the semiconductor wafer. | 09-18-2014 |
20140264602 | FORMING STRAINED AND RELAXED SILICON AND SILICON GERMANIUM FINS ON THE SAME WAFER - Various embodiments form strained and relaxed silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is formed. The semiconductor wafer comprises a substrate, a dielectric layer, and a strained silicon germanium (SiGe) layer. At least one region of the strained SiGe layer is transformed into a relaxed SiGe region. At least one strained SiGe fin is formed from a first strained SiGe region of the strained SiGe layer. At least one relaxed SiGe fin is formed from a first portion of the relaxed SiGe region. Relaxed silicon is epitaxially grown on a second strained SiGe region of the strained SiGe layer. Strained silicon is epitaxially grown on a second portion of the relaxed SiGe region. At least one relaxed silicon fin is formed from the relaxed silicon. At least one strained silicon fin is formed from the strained silicon. | 09-18-2014 |
20140264603 | PARTIALLY ISOLATED FIN-SHAPED FIELD EFFECT TRANSISTORS - A transistor device and a method for forming a fin-shaped field effect transistor (FinFET) device, with the channel portion of the fins on buried silicon oxide, while the source and drain portions of the fins on silicon. An example method includes receiving a wafer with a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. The method further comprises implanting a well in the silicon substrate and forming vertical sources and drains over the well between dummy gates. The vertical sources and drains extend through the BOX layer, fins, and a portion of the dummy gates. | 09-18-2014 |
20140264755 | STRAINED SILICON NFET AND SILICON GERMANIUM PFET ON SAME WAFER - Various embodiments form silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is obtained. The semiconductor wafer comprises a substrate, a dielectric layer, and a semiconductor layer including silicon germanium (SiGe). At least one SiGe fin is formed from at least a first SiGe region of the semiconductor layer in at least one PFET region of the semiconductor wafer. Strained silicon is epitaxially grown on at least a second SiGe region of the semiconductor layer. At least one strained silicon fin is formed from the strained silicon in at least one NFET region of the semiconductor wafer. | 09-18-2014 |
20140306274 | SELF-ALIGNED STRUCTURE FOR BULK FinFET - A FinFET structure which includes a bulk semiconductor substrate; semiconductor fins extending from the bulk semiconductor substrate, each of the semiconductor fins having a top portion and a bottom portion such that the bottom portion of the semiconductor fins is doped and the top portion of the semiconductor fins is undoped; a portion of the bulk semiconductor substrate directly underneath the plurality of semiconductor fins being doped to form an n+ or p+ well; and an oxide formed between the bottom portions of the fins. | 10-16-2014 |
20140306289 | SELF-ALIGNED STRUCTURE FOR BULK FinFET - A FinFET structure which includes a bulk semiconductor substrate; semiconductor fins extending from the bulk semiconductor substrate, each of the semiconductor fins having a top portion and a bottom portion such that the bottom portion of the semiconductor fins is doped and the top portion of the semiconductor fins is undoped; a portion of the bulk semiconductor substrate directly underneath the plurality of semiconductor fins being doped to form an n+ or p+ well; and an oxide formed between the bottom portions of the fins. Also disclosed is a method for forming a FinFET device. | 10-16-2014 |
20140312433 | CONTACT STRUCTURE EMPLOYING A SELF-ALIGNED GATE CAP - After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion. | 10-23-2014 |
20140315379 | CONTACT STRUCTURE EMPLOYING A SELF-ALIGNED GATE CAP - After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion. | 10-23-2014 |
20140339640 | FINFET WITH VERTICAL SILICIDE STRUCTURE - FinFETS and methods for making FinFETs with a vertical silicide structure. A method includes providing a substrate with a plurality of fins, forming a gate stack above the substrate wherein the gate stack has at least one sidewall and forming an off-set spacer adjacent the gate stack sidewall. The method also includes growing an epitaxial film which merges the fins to form an epi-merge layer, forming a field oxide layer adjacent to at least a portion of the off-set spacer and removing a portion of the field oxide layer to expose a portion of the epi-merge-layer. The method further includes removing at least part of the exposed portion of the epi-merge-layer to form an epi-merge sidewall and an epi-merge spacer region and forming a silicide within the epi-merge sidewall to form a silicide layer and two silicide sidewalls. | 11-20-2014 |
20140346640 | NON-LITHOGRAPHIC HOLE PATTERN FORMATION - A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation or nitridation. A hard mask portion is formed over the metal layer. A plasma impermeable spacer is formed on at least one first sidewall of the hard mask portion, while at least one second sidewall of the hard mask portion is physically exposed. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. A sequence of a surface pull back of the hard mask portion, cavity etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a hole pattern having a spacing that is not limited by lithographic minimum dimensions. | 11-27-2014 |
20140349088 | NON-LITHOGRAPHIC LINE PATTERN FORMATION - A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions. | 11-27-2014 |
20140353735 | LOCALIZED FIN WIDTH SCALING USING A HYDROGEN ANNEAL - Transistors and methods for fabricating the same include forming one or more semiconductor fins on a substrate; covering source and drain regions of the one or more semiconductor fins with a protective layer; annealing uncovered channel portions of the one or more semiconductor fins in a gaseous environment to reduce fin width and round corners of the one or more semiconductor fins; and forming a dielectric layer and gate over the thinned fins. | 12-04-2014 |
20140367826 | MAKING AN EFUSE - A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of the chip. A voltage may be applied to burn out at least one of the first fuse and the second fuse. The first critical dimension of the first fuse may result from applying a first mask to the layer and applying light having a first property to the mask. The second critical dimension of the second fuse may result from applying a second mask to the layer and applying light having a second property to the mask. | 12-18-2014 |
20150021689 | ASYMMETRICAL REPLACEMENT METAL GATE FIELD EFFECT TRANSISTOR - An asymmetrical field effect transistor (FET) device includes a semiconductor substrate, a buried oxide layer disposed on the semiconductor substrate, an extended source region disposed on the buried oxide layer and a drain region disposed on the buried oxide layer. The asymmetrical FET device also includes a silicon on insulator region disposed between the extended source region and the drain region and a gate region disposed above the extended source region and the silicon on insulator region. | 01-22-2015 |
20150024558 | ASYMMETRICAL REPLACEMENT METAL GATE FIELD EFFECT TRANSISTOR - An asymmetrical field effect transistor (FET) device includes a semiconductor substrate, a buried oxide layer disposed on the semiconductor substrate, an extended source region disposed on the buried oxide layer and a drain region disposed on the buried oxide layer. The asymmetrical FET device also includes a silicon on insulator region disposed between the extended source region and the drain region and a gate region disposed above the extended source region and the silicon on insulator region. | 01-22-2015 |
20150041897 | ANCHORED STRESS-GENERATING ACTIVE SEMICONDUCTOR REGIONS FOR SEMICONDUCTOR-ON-INSULATOR FINFET - After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose semiconductor surfaces of an underlying semiconductor material layer from underneath a source region and a drain region. Each of the extended source region and the extended drain region includes an anchored single crystalline semiconductor material portion that is in epitaxial alignment to the single crystalline semiconductor structure of the underlying semiconductor material layer and laterally applying a stress to the semiconductor fin. Because each anchored single crystalline semiconductor material portion is in epitaxial alignment with the underlying semiconductor material layer, the channel of the fin field effect transistor is effectively stressed along the lengthwise direction of the semiconductor fin. | 02-12-2015 |
20150048429 | SIDEWALL IMAGE TRANSFER WITH A SPIN-ON HARDMASK - Semiconductor devices and sidewall image transfer methods with a spin on hardmask. Methods for forming fins include forming a trench through a stack of layers that includes a top and bottom insulator layer, and a layer to be patterned on a substrate; isotropically etching the top and bottom insulator layers; forming a hardmask material in the trench to the level of the bottom insulator layer; isotropically etching the top insulator layer; and etching the bottom insulator layer and the layer to be patterned down to the substrate to form fins from the layer to be patterned. | 02-19-2015 |
20150048430 | SIDEWALL IMAGE TRANSFER WITH A SPIN-ON HARDMASK - Semiconductor devices include a first and a second set of parallel fins, each set of fins having a same number of fins and a pitch between adjacent fins below a minimum pitch of an associated lithography process, where a spacing between the first and second set of fins is greater than the pitch between adjacent fins; a gate structure over the first and second sets of fins; a merged source region that connects the first and second sets of fins on a first side of the gate structure; and a merged drain region that connects the first and second sets of fins on a second side of the gate structure. | 02-19-2015 |
20150054077 | FINFET FORMED OVER DIELECTRIC - A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels. A thermal oxidation is performed to diffuse elements from the semiconductor layer into an upper portion of the one or more mandrels and concurrently oxidize a lower portion of the one or more mandrels to form the one or more mandrels on the dielectric material. | 02-26-2015 |
20150054121 | FINFET FORMED OVER DIELECTRIC - A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels. A thermal oxidation is performed to diffuse elements from the semiconductor layer into an upper portion of the one or more mandrels and concurrently oxidize a lower portion of the one or more mandrels to form the one or more mandrels on the dielectric material. | 02-26-2015 |
20150061015 | NON-MERGED EPITAXIALLY GROWN MOSFET DEVICES - Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins. | 03-05-2015 |
20150064853 | INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC - An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region. | 03-05-2015 |
20150076498 | TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS - A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact. | 03-19-2015 |
20150102453 | Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion - A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide. | 04-16-2015 |
20150137243 | REPLACEMENT METAL GATE FINFET - A method for fabricating a field effect transistor device includes depositing a hardmask over a semiconductor layer depositing a metallic alloy layer over the hardmask, defining a semiconductor fin, depositing a dummy gate stack material layer conformally on exposed portions of the fin, patterning a dummy gate stack by removing portions of the dummy gate stack material using an etching process that selectively removes exposed portions of the dummy gate stack without appreciably removing portions of the metallic alloy layer, removing exposed portions of the metallic alloy layer, forming spacers adjacent to the dummy gate stack, forming source and drain regions on exposed regions of the semiconductor fin, removing the dummy gate stack, removing exposed portions of the metallic alloy layer, and forming a gate stack conformally over exposed portions of the insulator layer and the semiconductor fin. | 05-21-2015 |
20150137244 | REPLACEMENT METAL GATE FINFET - A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer. | 05-21-2015 |
20150137245 | REPLACEMENT METAL GATE FINFET - A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer. | 05-21-2015 |
20150140697 | TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS - A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact. | 05-21-2015 |
20150140698 | TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS - A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact. | 05-21-2015 |
20150140762 | FINFET WITH MERGE-FREE FINS - A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions. | 05-21-2015 |
20150144886 | FINFET WITH MERGE-FREE FINS - A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions. | 05-28-2015 |
20150155238 | MAKING AN EFUSE - A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of the chip. A voltage may be applied to burn out at least one of the first fuse and the second fuse. The first critical dimension of the first fuse may result from applying a first mask to the layer and applying light having a first property to the mask. The second critical dimension of the second fuse may result from applying a second mask to the layer and applying light having a second property to the mask. | 06-04-2015 |
20150179766 | BURIED LOCAL INTERCONNECT IN FINFET STRUCTURE - A method for fabricating a finfet with a buried local interconnect and the resulting device are disclosed. Embodiments include forming a silicon fin on a BOX layer, forming a gate electrode perpendicular to the silicon fin over a portion of the silicon fin, forming a spacer on each of opposite sides of the gate electrode, forming source/drain regions on the silicon fin at opposite sides of the gate electrode, recessing the BOX layer, undercutting the silicon fin and source/drain regions, at opposite sides of the gate electrode, and forming a local interconnect on a recessed portion of the BOX layer. | 06-25-2015 |
20150187577 | METHOD AND STRUCTURE FOR MULTIGATE FINFET DEVICE EPI-EXTENSION JUNCTION CONTROL BY HYDROGEN TREATMENT - Embodiments are directed to forming a structure comprising at least one fin, a gate, and a spacer, applying an annealing process to the structure to create a gap between the at least one fin and the spacer, and growing an epitaxial semiconductor layer in the gap between the spacer and the at least one fin. | 07-02-2015 |
20150187766 | MULTI-GATE FINFET SEMICONDUCTOR DEVICE WITH FLEXIBLE DESIGN WIDTH - A semiconductor device includes a substrate extending in a first direction to define a substrate length and a second direction perpendicular to the first direction to define a substrate width. A first semiconductor fin is formed on an upper surface of the substrate. The first semiconductor fin extends along the second direction at a first distance to define a first fin width. A second semiconductor fin is formed on the upper surface of the substrate. The second semiconductor fin extends along the second direction at a second distance to define a second fin width. The second distance may be different with respect to the first distance such that the first and second fin widths are different with respect to one another. | 07-02-2015 |
20150187867 | INDEPENDENT GATE VERTICAL FINFET STRUCTURE - A semiconductor device includes a substrate extending in a first direction to define a substrate length and a second direction perpendicular to the first direction to define a substrate width. A first semiconductor fin is formed on an upper surface of the substrate. The first semiconductor fin extends along the second direction at a first distance to define a first fin width. A first gate channel is formed between a first source/drain junction formed in the substrate and a second source/drain junction formed in the first semiconductor fin. A first gate stack is formed on sidewalls of the first gate channel. A first spacer is interposed between the first gate stack and the first source/drain junction. | 07-02-2015 |
20150187881 | CONTACT RESISTANCE REDUCTION IN FINFETS - A semiconductor device having fin transistors includes a plurality of substantially parallel semiconductor fins formed over a substrate and a gate structure formed over the fins transversely to a longitudinal axis of the fins. Source and drain regions are formed on opposite sides of the gate structure and are merged with the fins by an epitaxially grown crystalline material between the fins in merged regions. Interface layers are formed on the fins in regions disposed apart from both sides of the gate structure. The interface layers are formed over a top and at least a portion of opposing sides of the fins. Contact lines are formed over the interface layers such that contact is made at the top surface of the interface layer on the fins and at least a portion of the sides of the interface layer on the fins. | 07-02-2015 |
20150187914 | FINFET INCLUDING IMPROVED EPITAXIAL TOPOLOGY - A semiconductor device includes a semiconductor substrate having a plurality of semiconductor fins formed on an upper surface thereof. An epitaxial material is formed on the upper surface of the semiconductor substrate and on an outer surface of the semiconductor fins. The epitaxial material includes an epi upper surface having a lower region that contacts the semiconductor fins and an upper region formed above the lower region. The upper region extends parallel with an upper surface of the semiconductor fins. | 07-02-2015 |
20150194334 | Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion - A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide. | 07-09-2015 |
20150194484 | Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion - A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide. | 07-09-2015 |
20150194496 | CONTACT RESISTANCE REDUCTION IN FINFETS - A semiconductor device having fin transistors includes a plurality of substantially parallel semiconductor fins formed over a substrate and a gate structure formed over the fins transversely to a longitudinal axis of the fins. Source and drain regions are formed on opposite sides of the gate structure and are merged with the fins by an epitaxially grown crystalline material between the fins in merged regions. Interface layers are formed on the fins in regions disposed apart from both sides of the gate structure. The interface layers are formed over a top and at least a portion of opposing sides of the fins. Contact lines are formed over the interface layers such that contact is made at the top surface of the interface layer on the fins and at least a portion of the sides of the interface layer on the fins. | 07-09-2015 |
20150194504 | NON-MERGED EPITAXIALLY GROWN MOSFET DEVICES - Methods for forming semiconductor devices having non-merged fin extensions. Methods for forming semiconductor devices include forming trenches in an insulator layer of a substrate. Fins are formed in the trenches and a dummy gate is formed over the fins, leaving a source and drain region exposed. The fins are etched below a surface level of a surrounding insulator layer. Fin extensions are epitaxially grown from the etched fins. | 07-09-2015 |
20150206877 | NON-MERGED EPITAXIALLY GROWN MOSFET DEVICES - Semiconductor devices having non-merged fin extensions. A semiconductor device includes fins formed in trenches in an insulator layer, each of the fins having a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another. | 07-23-2015 |
20150206953 | METHOD AND STRUCTURE TO ENHANCE GATE INDUCED STRAIN EFFECT IN MULTIGATE DEVICE - A FinFet formed by depositing a thin layer of polycrystalline silicon followed by depositing a stress containing material, including a high Ge percentage silicon germanium film and/or a high stress W film on top of a polycrystalline silicon film. Freeing space between fins allows stressor films to be deposited closer to the transistor channel, improving the proximity of the stress containing material to the transistor channel and enhancing the stress coupling efficiency by defining a ratio between stress level in the stressor film and stress transferred to the channel for a mobility enhancement. The stress level is enhanced by patterning by removing the n-type workfunction metal from the p-FinFET. After stripping off the soft or hard mask, the p-type workfunction metal is deposited in the n- and p-FinFET regions. The freed space specifically for p-FinFet between the fins achieves an even higher stressor coupling to further boost the carrier mobility. | 07-23-2015 |
20150214058 | DUAL SILICIDE REGIONS AND METHOD FOR FORMING THE SAME - A method for forming dual silicide regions includes forming semiconductor regions having a first thickness and a second thickness different from the first thickness and forming a dielectric layer over the semiconductor regions. Holes are opened up in the dielectric layer down to a first depth corresponding with the first or second thickness leaving a thickness of the dielectric layer over the other of the first or second thickness. A first silicide is formed at the first depth in the holes using a first deposited material. The holes are extended through the thickness of the dielectric layer to reach a second depth. A second silicide is formed at the second depth in the holes using a different material than the first deposited material. | 07-30-2015 |
20150214119 | FORMATION OF FINS HAVING DIFFERENT HEIGHTS IN FIN FIELD EFFECT TRANSISTORS - A method includes forming at least two fins of a fin field effect transistor (finFET) on a substrate and forming an insulator layer on the at least two fins. A portion of the insulator layer at a top of a first fin of the at least two fins is removed and a sacrificial layer is formed in a top end of the first fin. The method includes etching the sacrificial layer to remove the sacrificial layer to form the first fin having a different fin height than a second fin of the at least two fins. | 07-30-2015 |
20150214338 | FINFET WITH SILICON GERMANIUM STRESSOR AND METHOD OF FORMING - The present disclosure generally provides for a method of forming a FinFET with a silicon germanium (SiGe) stressor, in addition to a FinFET structure obtained from embodiments of the method. The method can include forming a semiconductor fin on a buried insulator layer; forming a gate structure on the semiconductor fin; forming a silicon germanium (SiGe) layer on the buried insulator layer, wherein the SiGe layer contacts the semiconductor fin; and heating the SiGe layer, wherein the heating diffuses germanium (Ge) into the semiconductor fin. | 07-30-2015 |
20150214351 | SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE SIGE/SI FIN STRUCTURE - A semiconductor device includes a semiconductor-on-insulator substrate having an insulator layer, and at least one silicon germanium (SiGe) fin having a superlattice structure. The SiGe fin is formed on an upper surface of the insulator layer. A gate stack is formed on an upper surface of the at least one silicon germanium fin. The gate stack includes first and second opposing spacers defining a gate length therebetween. First and second epitaxial source/drain structures are formed on the insulator layer. The first and second epitaxial source/drain structures extend beneath the spacer to define a silicon germanium gate channel beneath the gate stack. | 07-30-2015 |
20150228762 | GATE STRUCTURE INTEGRATION SCHEME FOR FIN FIELD EFFECT TRANSISTORS - In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence. | 08-13-2015 |
20150228789 | STRESSED CHANNEL BULK FIN FIELD EFFECT TRANSISTOR - Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins. A gate structure is formed across the semiconductor fins, and the dielectric material layer is patterned employing the gate structure as an etch mask. A gate spacer is formed around the gate stack, and physically exposed portions of the semiconductor fins are removed by an etch. Stress-generating active semiconductor regions are formed by selective epitaxy from physically exposed top surfaces of the semiconductor layer, and apply stress to remaining portions of the semiconductor fins that include channels. | 08-13-2015 |
20150236021 | Structure to Enhance Gate Induced Strain Effect in Multigate Devices - A FinFet device structure provided with a thin layer of polycrystalline silicon having stress containing material, including a high Ge percentage silicon germanium film and/or a high stress W film on top of a polycrystalline silicon film. Space between the fins enables the stressor films to be positioned closer to the transistor channel. The improved proximity of the stress containing material to the transistor channel and the enhanced stress couple the efficiency defines a ratio between the stress level in the stressor film and stress transfer to the channel for mobility enhancement. The stress level is further enhanced by patterning by removal of the n-type workfunction metal from the p-FinFET. Following the stripping off the soft or hard mask, the p-type workfunction metal ends positioned in the n- and p-FinFET regions. The freed space specifically for p-FinFet between the fins achieves an even higher stressor coupling to further boost the carrier mobility. | 08-20-2015 |
20150243660 | CMOS STRUCTURE HAVING LOW RESISTANCE CONTACTS AND FABRICATION METHOD - A method for fabricating a CMOS integrated circuit structure and the CMOS integrated circuit structure. The method includes creating one or more n-type wells, creating one or more p-type wells, creating one or more pFET source-drains embedded in each of the one or more n-type wells, creating one or more nFET source-drains embedded in each of the one or more p-type wells, creating a pFET contact overlaying each of the one or more pFET source-drains, and creating an nFET contact overlaying each of the one or more nFET source-drains. A material of each of the one or more pFET source-drains includes silicon doped with a p-type material; a material of each of the one or more nFET source-drains includes silicon doped with an n-type material; a material of each pFET contact includes nickel silicide; and a material of each nFET contact comprises titanium silicide. | 08-27-2015 |
20150243760 | LOW-K SPACER FOR RMG FINFET FORMATION - A method for semiconductor fabrication includes providing mask layers on opposite sides of a substrate, the substrate having one or more mandrels. Dummy spacers are formed along a periphery of the mask layers. A dummy gate structure is formed between the dummy spacers. The dummy spacers are removed to provide a recess. Low-k spacers are formed in the recess. | 08-27-2015 |
20150255300 | DENSELY SPACED FINS FOR SEMICONDUCTOR FIN FIELD EFFECT TRANSISTORS - A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins. | 09-10-2015 |
20150270158 | SHALLOW TRENCH ISOLATION FOR END FIN VARIATION CONTROL - A method of fabricating a fin field effect transistor (FinFET) device and the device are described. The method includes forming a deep STI region adjacent to a first side of an end fin among a plurality of fins and lining the deep STI region, including the first side of the end fin, with a passivation layer. The method also includes depositing an STI oxide into the deep STI region, the passivation layer separating the STI oxide and the first side of the end fin, etching back the passivation layer separating the STI oxide and the first side of the end fin to a specified depth to create a gap, and depositing gate material, the gate material covering the gap. | 09-24-2015 |
20150270264 | SHALLOW TRENCH ISOLATION FOR END FIN VARIATION CONTROL - A method of fabricating a fin field effect transistor (FinFET) device and the device are described. The method includes forming a deep STI region adjacent to a first side of an end fin among a plurality of fins and lining the deep STI region, including the first side of the end fin, with a passivation layer. The method also includes depositing an STI oxide into the deep STI region, the passivation layer separating the STI oxide and the first side of the end fin, etching back the passivation layer separating the STI oxide and the first side of the end fin to a specified depth to create a gap, and depositing gate material, the gate material covering the gap. | 09-24-2015 |
20150270348 | SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE SIGE/SI FIN STRUCTURE - A semiconductor device includes a semiconductor-on-insulator substrate having an insulator layer, and at least one silicon germanium (SiGe) fin having a superlattice structure. The SiGe fin is formed on an upper surface of the insulator layer. A gate stack is formed on an upper surface of the at least one silicon germanium fin. The gate stack includes first and second opposing spacers defining a gate length therebetween. First and second epitaxial source/drain structures are formed on the insulator layer. The first and second epitaxial source/drain structures extend beneath the spacer to define a silicon germanium gate channel beneath the gate stack. | 09-24-2015 |
20150279839 | SEMICONDUCTOR DEVICE INCLUDING MERGED-UNMERGED WORK FUNCTION METAL AND VARIABLE FIN PITCH - A semiconductor device includes a plurality of first semiconductor fins formed on a semiconductor substrate to define first fin trenches. At least one second semiconductor fin is formed on the semiconductor substrate to define second fin trenches. A first work function metal layer is formed in the first and second fin trenches. The first work function metal layer formed in the second trenches has a first cavity formed therein such that the at least one second semiconductor fin realizes a different concentration of the first work function metal layer with respect to the plurality of first semiconductor fins. | 10-01-2015 |
20150279996 | SELF-ALIGNED CONTACT PROCESS ENABLED BY LOW TEMPERATURE - Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer. A second sacrificial epitaxial layer is formed on a first sacrificial epitaxial layer. The first sacrificial epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer. The first and second sacrificial epitaxial layers are recessed. The recessing exposes at least a portion of the source/drain regions. A first dielectric layer is formed on the exposed portions of the source/drain regions, and over the gate spacer and metal gate structure. At least one cavity within the first dielectric layer is formed above at least one of the exposed portions of source/drain regions. At least one metal contact is formed within the at least one cavity. | 10-01-2015 |
20150287614 | FINFET SEMICONDUCTOR DEVICE HAVING INTEGRATED SiGe FIN - A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A cladding layer is epitaxially grown on a portion of the at least one semiconductor fin. The cladding layer is oxidized such that r such that ions are condensed therefrom and are diffused into the at least one semiconductor fin while the cladding layer is converted to an oxide layer. The oxide layer is removed to expose the at least one semiconductor fin having a diffused fin portion that enhances electron hole mobility therethrough. | 10-08-2015 |
20150287648 | FINFET INCLUDING TUNABLE FIN HEIGHT AND TUNABLE FIN WIDTH RATIO - A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material. | 10-08-2015 |
20150295065 | NON-MERGED EPITAXIALLY GROWN MOSFET DEVICES - Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins. | 10-15-2015 |
20150303284 | PUNCH THROUGH STOPPER IN BULK FINFET DEVICE - A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure. | 10-22-2015 |
20150318211 | EPITAXIAL BUFFER LAYER FOR FINFET SOURCE AND DRAIN JUNCTION LEAKAGE REDUCTION - A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater. | 11-05-2015 |
20150325576 | INDEPENDENT GATE VERTICAL FINFET STRUCTURE - A semiconductor device includes a substrate extending in a first direction to define a substrate length and a second direction perpendicular to the first direction to define a substrate width. A first semiconductor fin is formed on an upper surface of the substrate. The first semiconductor fin extends along the second direction at a first distance to define a first fin width. A first gate channel is formed between a first source/drain junction formed in the substrate and a second source/drain junction formed in the first semiconductor fin. A first gate stack is formed on sidewalls of the first gate channel. A first spacer is interposed between the first gate stack and the first source/drain junction. | 11-12-2015 |
20150333086 | METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH DIFFERENT FIN SETS - A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions. | 11-19-2015 |
20150333155 | METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH FILLED GATE LINE END RECESSES - A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions. | 11-19-2015 |
20150340272 | STI REGION FOR SMALL FIN PITCH IN FINFET DEVICES - The present invention relates generally to semiconductor devices, and particularly to fabricating a shallow trench isolation (STI) region in fin field effect transistors (FinFETs) having a small fin pitch. According to one embodiment, a method of using selective etching techniques to remove a single fin to form a fin trench and to form an isolation trench having a width approximately equal to a width of the single fin below the removed fin is disclosed. The fin trench and the isolation trench may be filled with isolation material to form an isolation region. | 11-26-2015 |
20150349085 | METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH SIDEWALL SPACERS FOR CONFINING EPITAXIAL GROWTH - A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers. | 12-03-2015 |
20150357243 | METHOD FOR MAKING STRAINED SEMICONDUCTOR DEVICE AND RELATED METHODS - A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states. | 12-10-2015 |
20150357246 | SEMICONDUCTOR DEVICE INCLUDING MERGED-UNMERGED WORK FUNCTION METAL AND VARIABLE FIN PITCH - A method of varying a threshold voltage of a semiconductor device includes forming plural first semiconductor fins atop a substrate and which are separated from one another according to a first fin pitch to define first fin trenches having a first width. At least one second semiconductor fin is formed atop the substrate and is separated from the plural first semiconductor fins by a second fin pitch to define second fin trenches having a second width. The method further includes forming a work function metal layer in the first and second fin trenches. The second trenches have a first cavity formed therein such that at least one second semiconductor fin has a different concentration of work function metal layer with respect to the first plural semiconductor fins so as to vary the threshold voltage of the at least one second semiconductor fin with respect to the first plural semiconductor fins. | 12-10-2015 |
20150357328 | STI REGION FOR SMALL FIN PITCH IN FINFET DEVICES - The present invention relates generally to semiconductor devices, and particularly to fabricating a shallow trench isolation (STI) region in fin field effect transistors (FinFETs) having a small fin pitch. A structure is disclosed. The structure may include: a semiconductor substrate; a plurality of fins on the semiconductor substrate; a plurality of caps on the fins; an isolation layer on the semiconductor substrate and between the plurality of fins, the isolation layer having an upper surface that is substantially flush with an upper surface of the plurality of caps; an isolation trench in the semiconductor substrate; a fin trench where one of the plurality of fins and one of the plurality of caps have been removed; and insulating material in the isolation trench and the fin trench to form an isolation region, the isolation region having an upper surface that is substantially flush with the upper surface of the isolation layer. | 12-10-2015 |
20150357425 | BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME - An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions. | 12-10-2015 |
20150357439 | METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH ISOLATION PILLARS BETWEEN ADJACENT SEMICONDUCTOR FINS - A method for making a semiconductor device may include forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins, and forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins. The method may further include selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material, and forming a region of a second dielectric material different than the first dielectric in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins. | 12-10-2015 |
20150357441 | METHOD FOR MAKING A SEMICONDUCTOR DEVICE WHILE AVOIDING NODULES ON A GATE - A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate, and a gate overlying the semiconductor fins. The gate has a tapered outer surface. A first pair of sidewall spacers is formed adjacent the gate an exposed tapered outer surface is also defined. Portions of the gate are removed at the exposed tapered outer surface to define a recess. A second pair of sidewall spacers is formed covering the first pair of sidewall spacers and the recess. Source/drain regions are formed on the semiconductor fins. | 12-10-2015 |
20150364578 | METHOD OF FORMING A REDUCED RESISTANCE FIN STRUCTURE - Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions. | 12-17-2015 |
20150372104 | MULTI-CHANNEL GATE-ALL-AROUND FET - A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wrap-around gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs. | 12-24-2015 |
20150372107 | SEMICONDUCTOR DEVICES HAVING FINS, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FINS - Methods and structures associated with forming finFETs that have fin pitches less than 30 nm are described. A selective nitridation process may be used during spacer formation on the gate to enable finer fin pitch than could be achieved using traditional spacer deposition processes. The spacer formation may also allow precise control over formation of source and drain junctions. | 12-24-2015 |
20150372140 | FINFETS HAVING STRAINED CHANNELS, AND METHODS OF FABRICATING FINFETS HAVING STRAINED CHANNELS - Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET. | 12-24-2015 |
20150380258 | METHOD FOR CONTROLLING HEIGHT OF A FIN STRUCTURE - Methods and structures for forming fin structures whilst controlling the height of the fin structures with high uniformity across large areas are described. According to some aspects, a multi-layer structure comprising a first etch-stop layer and a second etch-stop layer separated from a substrate and from each other by spacer layers is formed on a substrate. Trenches may be formed through the first and second etch-stop layers. A buffer layer may be formed in the trenches, filling the trenches to a level approximately at a position of the first etch-stop layer. A semiconductor layer may be formed above the buffer layer and etched back to the second etch-stop layer to form semiconductor fins of highly uniform heights. | 12-31-2015 |
20160027776 | DENSELY SPACED FINS FOR SEMICONDUCTOR FIN FIELD EFFECT TRANSISTORS - A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins. | 01-28-2016 |
20160035626 | STRESSED CHANNEL BULK FIN FIELD EFFECT TRANSISTOR - Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins. A gate structure is formed across the semiconductor fins, and the dielectric material layer is patterned employing the gate structure as an etch mask. A gate spacer is formed around the gate stack, and physically exposed portions of the semiconductor fins are removed by an etch. Stress-generating active semiconductor regions are formed by selective epitaxy from physically exposed top surfaces of the semiconductor layer, and apply stress to remaining portions of the semiconductor fins that include channels. | 02-04-2016 |
20160035857 | EXTENDED CONTACT AREA USING UNDERCUT SILICIDE EXTENSIONS - The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (S-D) region of a field effect transistor (FET) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed. The method may include: forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; and forming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region. | 02-04-2016 |
20160043177 | SEMICONDUCTOR DEVICE WITH THINNED CHANNEL REGION AND RELATED METHODS - A method for making a semiconductor device may include forming a dummy gate above a semiconductor layer on an insulating layer, forming sidewall spacers above the semiconductor layer and on opposing sides of the dummy gate, forming source and drain regions on opposing sides of the sidewall spacers, and removing the dummy gate and underlying portions of the semiconductor layer between the sidewall spacers to provide a thinned channel region having a thickness less than a remainder of the semiconductor layer outside the thinned channel region. The method may further include forming a replacement gate stack over the thinned channel region and between the sidewall spacers and having a lower portion extending below a level of adjacent bottom portions of the sidewall spacers. | 02-11-2016 |
20160049402 | SEMICONDUCTOR DEVICE HAVING FINS WITH IN-SITU DOPED, PUNCH-THROUGH STOPPER LAYER AND RELATED METHODS - A method for making a semiconductor device may include forming first and second semiconductor regions laterally adjacent one another and each comprising a first semiconductor material. The method may further include forming an in-situ doped, punch-through stopper layer above the second semiconductor region comprising the first semiconductor material and a first dopant, and forming a semiconductor buffer layer above the punch-through stopper layer, where the punch-through stopper layer includes the first semiconductor material. The method may also include forming a third semiconductor region above the semiconductor buffer layer, where the third semiconductor region includes a second semiconductor material different than the first semiconductor material. In addition, at least one first fin may be formed from the first semiconductor region, and at least one second fin may be formed from the second semiconductor region, the punch-through stopper layer, the semiconductor buffer layer, and the third semiconductor region. | 02-18-2016 |
20160049515 | FINFET INCLUDING IMPROVED EPITAXIAL TOPOLOGY - A semiconductor device includes a semiconductor substrate having a plurality of semiconductor fins formed on an upper surface thereof. An epitaxial material is formed on the upper surface of the semiconductor substrate and on an outer surface of the semiconductor fins. The epitaxial material includes an epi upper surface having a lower region that contacts the semiconductor fins and an upper region formed above the lower region. The upper region extends parallel with an upper surface of the semiconductor fins. | 02-18-2016 |
20160079384 | GATE STRUCTURE INTEGRATION SCHEME FOR FIN FIELD EFFECT TRANSISTORS - In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence. | 03-17-2016 |
20160086820 | LOCALIZED FIN WIDTH SCALING USING A HYDROGEN ANNEAL - Transistors and methods for fabricating the same include annealing channel portions of one or more semiconductor fins that are uncovered by a protective layer in a gaseous environment to reduce fin width, to produce a fin profile that is widest at the bottom and tapers toward the top, and to round corners of the one or more semiconductor fins. | 03-24-2016 |
20160104644 | PROCESS FOR INTEGRATED CIRCUIT FABRICATION INCLUDING A UNIFORM DEPTH TUNGSTEN RECESS TECHNIQUE - Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode. | 04-14-2016 |
20160111513 | MULTI-CHANNEL GATE-ALL-AROUND FET - A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wraparound gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs. | 04-21-2016 |
20160111553 | LOCALIZED FIN WIDTH SCALING USING A HYDROGEN ANNEAL - Transistors including one or more semiconductor fins formed on a substrate. The one or more semiconductor fins are thinner in a channel region than in source and drain regions and have rounded corners formed by an anneal in a gaseous environment. A gate dielectric layer is on the channel region of the one or more semiconductor fins, conforming to the contours of the one or more semiconductor fins. A gate structure is on the gate dielectric layer. | 04-21-2016 |
20160118302 | GATE STRUCTURE INTEGRATION SCHEME FOR FIN FIELD EFFECT TRANSISTORS - In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence. | 04-28-2016 |