Patent application number | Description | Published |
20140373937 | Microvalve Having Improved Air Purging Capability - A microvalve includes a base plate having a surface defining an actuator cavity. A venting groove extends from a first cavity portion of the actuator cavity having a dead end region to a second cavity portion of the actuator cavity having a structure that can vent air from the microvalve. A cover plate includes a surface having an actuator cavity provided therein that includes a first cavity portion having a dead end region and a second cavity portion having a structure that can vent air from the microvalve. An intermediate plate includes a displaceable member that is disposed within the actuator cavity for movement between a closed position, wherein the displaceable member prevents fluid communication through the microvalve, and an opened position, wherein the displaceable member does not prevent fluid communication through the microvalve. | 12-25-2014 |
20140374633 | Microvalve Having Improved Resistance to Contamination - A microvalve includes a base plate including a surface, a recessed area provided within the surface, a first fluid port provided within the recessed area, and a first sealing structure extending about the first fluid port. The microvalve also includes a cover plate including a surface, a recessed area provided within the surface, a second fluid port provided within the recessed area, and a second sealing structure extending about the second fluid port. An intermediate plate is disposed between the base plate and the cover plate and includes a displaceable member that is movable between a closed position, wherein the displaceable member cooperates with the sealing structures to prevent fluid communication between the fluid ports, and an opened position, wherein the displaceable member does not cooperate with at least a portion of the sealing structures to prevent fluid communication between the fluid ports. | 12-25-2014 |
Patent application number | Description | Published |
20090302885 | TWO TRANSISTOR TIE CIRCUIT WITH BODY BIASING - A circuit for body biasing is provided. The circuit includes: (1) a p-type transistor having a first current terminal, which is coupled to a first voltage supply, a second current terminal, a control terminal, and a bulk terminal; and (2) an n-type transistor having a first current terminal, which is coupled to a second voltage supply different from the first voltage supply, a second current terminal, a control terminal, and a bulk terminal, wherein the bulk terminal of the p-type transistor, the second current terminal of the p-type transistor, and the control terminal of the n-type transistor is coupled to a first node, wherein the control terminal of the p-type transistor, the bulk terminal of the n-type transistor, and the second current terminal of the second transistor is coupled to a second node different from the first node. | 12-10-2009 |
20100026343 | CLOCKED SINGLE POWER SUPPLY LEVEL SHIFTER - First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that differs from the first power supply domain. The data signal becomes referenced to the second power supply domain by a clocked level shifter that couples the first circuitry to the second circuitry and buffers the data signal from the first power supply domain to the second power supply domain by only using a single supply voltage. The clocked level shifter is clocked by a signal that is used to precharge a first node and a second node of the clocked level shifter until the data signal is valid for at least a setup time period. The first and second nodes are precharged to establish a known state in the clocked level shifter. | 02-04-2010 |
20130290750 | MEMORY WITH WORD LEVEL POWER GATING - In accordance with at least one embodiment, memory power gating at word level is provided. In accordance with at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.) of a memory array, provides fine-grained power reduction for a memory array. In accordance with at least one embodiment, a gating transistor is provided for each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.). | 10-31-2013 |
20130290753 | MEMORY COLUMN DROWSY CONTROL - In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column. | 10-31-2013 |
20140027810 | SINGLE-EVENT LATCH-UP PREVENTION TECHNIQUES FOR A SEMICONDUCTOR DEVICE - A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL. | 01-30-2014 |
20140167102 | SEMICONDUCTOR DEVICE WITH SINGLE-EVENT LATCH-UP PREVENTION CIRCUITRY - A semiconductor device includes a parasitic silicon-controlled rectifier (SCR) and a first transistor. The parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The first transistor is coupled between a first power supply node and an emitter of the parasitic pnp BJT. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp BJT following a single-event latch-up (SEL) event. | 06-19-2014 |
Patent application number | Description | Published |
20080286488 | METALLIC INK - Forming a conductive film comprising depositing a non-conductive film on a surface of a substrate, wherein the film contains a plurality of copper nanoparticles and exposing at least a portion of the film to light to make the exposed portion conductive. Exposing of the film to light photosinters or fuses the copper nanoparticles. | 11-20-2008 |
20090311440 | PHOTO-CURING PROCESS FOR METALLIC INKS - A solution of metal ink is mixed and then printed or dispensed onto the substrate using the dispenser. The film then is dried to eliminate water or solvents. In some cases, a thermal curing step can be introduced subsequent to dispensing the film and prior to the photo-curing step. The substrate and deposited film can be cured using an oven or by placing the substrate on the surface of a heater, such as a hot plate. Following the drying and/or thermal curing step, a laser beam or focused light from the light source is directed onto the surface of the film in a process known as direct writing. The light serves to photo-cure the film such that it has low resistivity. | 12-17-2009 |
20100000762 | METALLIC PASTES AND INKS - A metallic composition including a solvent and a plurality of metal nanoparticles dispersed therein is formulated such that curing of the metallic composition on a substrate provides a metallic conductor with a resistivity of about 5×10 | 01-07-2010 |
20100005853 | Continuous Range Hydrogen Sensor - A device for sensing hydrogen based on palladium or palladium alloy nanoparticles, wherein the nanoparticles are deposited on a resistive substrate, to permit sensing of less than 1% hydrogen; wherein the nanoparticles are deposited as islands on a continuous resistive layer. | 01-14-2010 |
20110027603 | Enhancing Thermal Properties of Carbon Aluminum Composites - An article of manufacture comprises a carbon-containing matrix. The carbon-containing matrix may comprise at least one type of carbon material selected from the group comprising graphite crystalline carbon materials, carbon powder, and artificial graphite powder. In addition, the carbon-containing matrix comprises a plurality of pores. The article of manufacture also comprises a metal component comprising Al, alloys of Al, or combinations thereof. The metal component is disposed in at least a portion of the plurality of pores. Further, the article of manufacture comprises an additive comprising at least Si. At least a portion of the additive is disposed in an interface between the metal component within the pores and the carbon-containing matrix. The additive enhances phonon coupling and propagation at the interface. | 02-03-2011 |
20110300305 | MECHANICAL SINTERING OF NANOPARTICLE INKS AND POWDERS - Nanoparticle inks and powders are sintered using an applied mechanical energy, such as uniaxial pressure, hydrostatic pressure, and ultrasonic energy, which may also include applying a sheer force to the inks or powders in order to make the resultant film or line conductive. | 12-08-2011 |
20130129935 | Highly Transparent and Electrically Conductive Substrate - A highly transparent and electrically conductive substrate is made by applying a conductive mesh over a transparent substrate, depositing a UV-curable transparent material over the conductive mesh and the transparent substrate, and exposing the UV-curable transparent material to a directional UV light from a UV light source positioned so that the UV light emitted from the UV light source travels through the transparent substrate before being received by the UV-curable transparent material, wherein the UV-curable transparent material is cured in response to exposure from the UV light except for those portions of the UV-curable transparent material masked from exposure to the UV light by the conductive mesh. Uncured portions of the UV-curable transparent material are removed, and a transparent conductive material layer is deposited over the cured UV-curable transparent material and conductive mesh. | 05-23-2013 |
20140057428 | BUFFER LAYER FOR SINTERING - A layer of material having a low thermal conductivity is coated over a substrate. A film of conductive ink is then coated over the layer of material having the low thermal conductivity, and then sintered. The film of conductive ink does not absorb as much energy from the sintering as the film of conductive ink coated over the layer of material having the low thermal conductivity. The layer of material having the low thermal conductivity maybe a polymer, such as polyimide. | 02-27-2014 |
Patent application number | Description | Published |
20080254392 | FLEXIBLE CIRCUIT WITH COVER LAYER - The invention relates to flexible circuits and more particularly to flexible printed circuits having cover layers. The cover layers may be a chemically-etchable adhesive polyimide. The cover layers may be patterned after they are applied to the flexible circuit substrate. | 10-16-2008 |
20090068458 | ADHESIVE-COATED BACKING FOR FLEXIBLE CIRCUIT - The invention relates to adhesive coated backings used during fabrication of flexible circuits. The adhesive coatings exhibit high initial adhesion and a reduced level of adhesion after exposure to suitable radiation. | 03-12-2009 |
20090071696 | PARTIALLY RIGID FLEXIBLE CIRCUITS AND METHOD OF MAKING SAME - The present invention relates to partially rigid flexible circuits having both rigid portions and flexible portions and methods for making the same. | 03-19-2009 |
20100105806 | PASSIVE ELECTRICAL ARTICLE - An electrical article including a dielectric layer having a resin, dielectric particles, a dispersant, and core shell rubber particles. | 04-29-2010 |
20100279566 | PASSIVE ELECTRICAL ARTICLE - A passive electrical article including a dielectric layer having a nonwoven material. | 11-04-2010 |
20130240860 | Composite Diode, Electronic Device, and Methods of Making the Same - A composite diode ( | 09-19-2013 |
Patent application number | Description | Published |
20090302874 | METHOD AND APPARATUS FOR SIGNAL PROBE CONTACT WITH CIRCUIT BOARD VIAS - A method and apparatus for probing a circuit board, is provided. One implementation involves a signal probe including a tip having a plurality of strands of flexible conductive material surrounding the tip, the strands extending out from the tip to provide multiple points of contact with the rim of a via or a conductive barrel of the via when the tip is inserted into the via, the probe tip and probe strands being made of same conductive material; such that aligning the signal probe with the via for engaging the probe tip strands with the via, and inserting the tip into the via, causes bending and flexing of the strands for making contact with a conductor on a top rim of the barrel and inside an inner wall of the barrel. | 12-10-2009 |
20110147044 | SYSTEM TO IMPROVE CORELESS PACKAGE CONNECTIONS AND ASSOCIATED METHODS - A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance. | 06-23-2011 |
20120138349 | SYSTEM TO IMPROVE CORELESS PACKAGE CONNECTIONS AND ASSOCIATED METHODS - A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance. | 06-07-2012 |
20120175763 | INTEGRATED CIRCUIT PACKAGING INCLUDING AUXILIARY CIRCUITRY - An integrated circuit package includes a package core and a primary circuitry chip mounted on the package core. The primary circuitry chip has an active surface in which the core circuitry is fabricated. The active surface of the primary circuitry chip faces the package core and includes contacts. The integrated circuit package further includes an auxiliary circuit chip assembled to the package core and having contacts facing and electrically connected to the contacts of the primary circuitry chip. | 07-12-2012 |
20140156705 | HYBRID FILE SYSTEMS - Systems and computer program products may provide a virtual system with direct access to one or more sectors of a resource of a computer system. The system and computer program products may include providing, by a computer system to a virtual system, first access control data associated with a regular computer file that corresponds to a resource on the computer system. The system and computer program products may additionally include receiving, at the computer system, a direct read from or direct write to one or more sectors of the resource represented by the regular computer file from the virtual system. The system and computer program products may further include hiding, at the computer system, a hidden computer file from the virtual system. The system and computer program products may additionally include routing, at the computer system, the direct read from or direct write to the hidden computer file on the computer system. | 06-05-2014 |
20140156706 | Hybrid File Systems - Methods may provide a virtual system with direct access to one or more sectors of a resource of a computer system. The method may include providing, by a computer system to a virtual system, first access control data associated with a regular computer file that corresponds to a resource on the computer system. The method may additionally include receiving, at the computer system, a direct read from or direct write to one or more sectors of the resource represented by the regular computer file from the virtual system. The method may further include hiding, at the computer system, a hidden computer file from the virtual system. The method may additionally include routing, at the computer system, the direct read from or direct write to the hidden computer file on the computer system. | 06-05-2014 |
Patent application number | Description | Published |
20100090341 | NANO-PATTERNED ACTIVE LAYERS FORMED BY NANO-IMPRINT LITHOGRAPHY - Patterned active layers formed by nano-imprint lithography for use in devices such as photovoltaic cells and hybrid solar cells. One such photovoltaic cell includes a first electrode and a first electrically conductive layer electrically coupled to the first electrode. The first conductive layer has a multiplicity of protrusions and recesses formed by a nano-imprint lithography process. A second electrically conductive layer substantially fills the recesses and covers the protrusions of the first conductive layer, and a second electrode is electrically coupled to the second conductive layer. A circuit electrically connects the first electrode and the second electrode. | 04-15-2010 |
20100120251 | Large Area Patterning of Nano-Sized Shapes - Methods for creating nano-shaped patterns are described. This approach may be used to directly pattern substrates and/or create imprint lithography molds that may be subsequently used to directly replicate nano-shaped patterns into other substrates in a high throughput process. | 05-13-2010 |
20110030770 | NANOSTRUCTURED ORGANIC SOLAR CELLS - Solar cells having at least one N-type material layer and at least one P-type material layer forming a patterned p-n junction are described. A conducting layer may provide electrical communication between the p-n junction and an electrode layer. | 02-10-2011 |
20110048518 | Nanostructured thin film inorganic solar cells - Inorganic solar cells having a nano-patterned p-n or p-i-n junction to reduce electron and hole travel distance to the separation interface to be less than the magnitude of the drift length or diffusion length, and meanwhile to maintain adequate active material to absorb photons. Formation of the inorganic solar cells may include one or more nano-lithography steps. | 03-03-2011 |
20110049096 | Functional Nanoparticles - Functional nanoparticles may be formed using at least one nano-lithography step. In one embodiment, sacrificial material may be patterned on a multi-layer substrate using an imprint lithography system. The pattern may be further etched into the multi-layer substrate. Functional material may then be deposited on multi-layer substrate and solidified. At least a portion of the functional material may then be removed to provide a crown surface exposing pillars. Pillars may be removed from multi-layer substrate forming functional nanoparticles. | 03-03-2011 |
20110180127 | SOLAR CELL FABRICATION BY NANOIMPRINT LITHOGRAPHY - Fabricating a solar cell stack includes forming a nanopatterned polymeric layer on a first surface of a silicon wafer and etching the first surface of the silicon wafer to transfer a pattern of the nanopatterned polymeric layer to the first surface of the silicon wafer. A layer of reflective electrode material is formed on a second surface of the silicon wafer. The nanopatterned first surface of the silicon wafer undergoes a buffered oxide etching. After the buffered oxide etching, the nanopatterned first surface of the silicon wafer is treated to decrease a contact angle of water on the nanopatterned first surface. Electron donor material is deposited on the nanopatterned first surface of the silicon wafer to form an electron donor layer, and a transparent electrode material is deposited on the electron donor layer to form a transparent electrode layer on the electron donor layer. | 07-28-2011 |
20110277827 | NANOSTRUCTURED SOLAR CELL - Systems and methods for fabrication of nanostructured solar cells having arrays of nanostructures are described, including nanostructured solar cells having a repeating pattern of pyramid nanostructures, providing for low cost thin-film solar cells with improved PCE. | 11-17-2011 |
20140021167 | Large Area Patterning of Nano-Sized Shapes - Methods for creating nano-shaped patterns are described. This approach may be used to directly pattern substrates and/or create imprint lithography molds that may be subsequently used to directly replicate nano-shaped patterns into other substrates in a high throughput process. | 01-23-2014 |
Patent application number | Description | Published |
20080267201 | SYSTEM AND METHOD FOR MANAGING DYNAMIC NETWORK SESSIONS - For an Internet Access Gateway operative between an area network and a public network, managing dynamic network sessions therebetween whereby a primary server on the public network in a primary session with a client of the area network initiates an additional session with an additional server on the public network, for which an unexpected data packet received at the gateway from the additional server is associated with the primary session, and accordingly allowed access to the area network through the gateway, provided the gateway received the data packet at an input port exceeding 1023, the additional session comprises a pre-defined Session Triggering Event, and at least one internal network component of the area network indicates willingness to receive the data packet. Wherefore, a preferred Application Level Gateway is thereby provided for firewall and NAT implementations to enhance network security. | 10-30-2008 |
20090282470 | CONTENT AGGREGATION SERVER ON VIRTUAL UNIVERSAL PLUG-N-PLAY NETWORK - A content aggregation server (CAS) establishes an IPSec tunnel with a gateway of a home network and discovers content on the home network. The CAS generates a web page that a user of the home network can access remotely to view an index of content hyperlinks, organize the content on the home network, and if desired select a hyperlink to access the content directly through the gateway, not the CAS, which thus is used for listing and managing content but not for hosting the content. | 11-12-2009 |
20120215926 | Mechanism for Quick Data Path Setup by Cloning Session Content - A custom interface depth may be provided. A content stream, such as a three-dimensional television signal, comprising a plurality of video planes may be displayed. In response to receiving a request to adjust a depth of at least one of the video planes, the display depth of the requested video plane may be adjusted relative to at least one other video plane. | 08-23-2012 |
20120215936 | Feedback-Based Internet Traffic Regulation for Multi-Service Gateways - A method for regulating network traffic may be provided. The method may comprise: measuring usage of a CPU; determining if the CPU usage is greater than an overload threshold value; halting the increase of a data traffic shaping rate associated with traffic regulated by the CPU if the CPU usage is greater than the overload threshold value; determining if the CPU usage is greater than an overflow threshold value; and decreasing the data traffic shaping rate associated with traffic regulated by the CPU if the CPU usage is greater than the overflow threshold value for improving session setup speed. | 08-23-2012 |
Patent application number | Description | Published |
20090243578 | Power Supply with Digital Control Loop - One embodiment of a power supply apparatus includes a switching regulator generating an output voltage VOUT at an output node from an input voltage VIN at an input node in accordance with a pulse width modulated signal having a nominal frequency of f | 10-01-2009 |
20100166019 | SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES - Methods and apparatus for communicating include communicating frames of data having a first timeslot allocation of s timeslots serially from a first device to a second device using a first unidirectional data line at a frequency f | 07-01-2010 |
20100166021 | SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES - Methods and apparatus for synchronizing communications between a first and a second device include serially communicating a frame having a first format from a first device to a second device, wherein only a frame synchronization timeslot (F1) is asserted. The serially communicated frame having the first format is sampled by the second device until the asserted F1 timeslot is detected. The second device serially communicates a frame having a second format to the first device, wherein only a frame synchronization timeslot (R1) is asserted. The serially communicated frame having the second format is sampled by the first device until the asserted R1 timeslot is detected. The first device establishes synchronization when these steps are successfully repeated. On the second sampling to detect the F1 timeslot, however, the sampling is windowed to less than one timeslot within the expected occurrence of the F1 timeslot. | 07-01-2010 |
20100166172 | SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES - Methods and apparatus for communicating include a first device coupled to a second device with a bi-directional data line and a clock line. Frames of data are serially communicated between the first and second devices on the data line. Each frame is synchronized with a clock signal carried by the clock line. Each frame has a portion allocated to data communicated from the first device to the second device and another portion allocated to data communicated from the second device to the first device. | 07-01-2010 |
20100166173 | SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES - Methods and apparatus for communicating include coupling first and second devices with a first unidirectional data line, a second unidirectional data line, and a clock line. Frames of data are serially communicated between the first and second devices using the first and second unidirectional data lines. The frame format of a frame carried by the first unidirectional data line is distinct from a frame format of a frame carried by the second unidirectional data line. Each frame is synchronized with a clock signal carried by the clock line. | 07-01-2010 |
20100166434 | SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES - Methods and apparatus for communicating include communicating frames of data at a frequency f | 07-01-2010 |
Patent application number | Description | Published |
20100051826 | Fluorescent Xanthenes and White Light Fluorophores - Xanthene compounds are disclosed having fluorescence at multiple wavelengths. Also disclosed are methods for their synthesis and use. Some of the compounds fluoresce at three wavelengths, emitting white light. Uses include the imaging of biological tissues, illumination, and display technologies. Many of the compounds have large Stokes shifts, and are resistant to photobleaching. The fluorescence may be readily distinguished from that of endogenous fluorophores, and from that of most existing, commercially-available fluorescent probes. The compounds are well suited for use in “multiplexing” techniques. They exhibit clear isosbestic and isoemissive points, and have broad absorption and emission ranges. | 03-04-2010 |
20120115248 | METHODS OF DETERMINING THE PRESENCE AND/OR CONCENTRATION OF AN ANALYTE IN A SAMPLE - Compositions, methods, and systems for monitoring analyte levels are provided herein. The disclosure provides methods and systems for the real-time monitoring of analytes, such as citrate, calcium, phosphate and magnesium, in a biological fluid in a clinical setting. | 05-10-2012 |
20130302903 | FLUORESCENT NITRIC OXIDE PROBES AND ASSOCIATED METHODS - Nitric oxide probes comprising a compound represented by Formula, I, II, III, IV, V, VI or a combination thereof are provided. Methods of using these nitric oxide probes to detect nitric oxide are also provided. | 11-14-2013 |
20140179014 | FLUORESCENT NITRIC OXIDE PROBES AND ASSOCIATED METHODS - Nitric oxide probes including a compound represented by Formula, I, II, III, IV, V, VI or a combination thereof are provided. Methods of using these nitric oxide probes to detect nitric oxide are also provided. | 06-26-2014 |