Patent application number | Description | Published |
20110179195 | FIELD UPGRADABLE FIRMWARE FOR ELECTRONIC DEVICES - An electronic device includes an input/output (I/O) interface and a plurality of memory elements comprising a non-volatile memory portion for storing a default firmware and a working memory portion having a firmware area. The device also includes a controller coupled to the I/O interface and the memory elements, where the controller is configured for operating the memory elements, according to the firmware area, and for monitoring the I/O interface. In the device, the controller is also configured for loading the default firmware into the firmware area when the controller is enabled and for granting access to the firmware area for loading an alternate firmware if a bypass code is detected at the I/O interface. | 07-21-2011 |
20110179319 | FIELD PROGRAMMABLE REDUNDANT MEMORY FOR ELECTRONIC DEVICES - An electronic device is provided including an input/output (I/O) interface, a plurality of memory elements, a controller coupled to the I/O interface and the plurality of memory elements. In the device, the controller configured for operating the plurality of memory elements during a normal operating mode of the electronic device, where responsive to receiving a command for replacing a selected memory sector in the electronic device during the normal operating mode, the controller is configured for identifying one or more available spare memory sectors in the electronic device and modifying at least one memory map in the electronic device to replace the selected memory sector with the one of the available spare memory sectors. | 07-21-2011 |
20110249838 | Hearing Aid and Circuit for Detecting a Connector - A circuit for a hearing aid includes an interface including a contact element for receiving a connector. The interface is configured to provide produce an electrical signal when the connector contacts the contact element. The circuit further includes a logic circuit coupled to the interface for receiving the electrical signal and configured to detect the connector in response to receiving the electrical signal. | 10-13-2011 |
20120082329 | HEARING AID WITH AUTOMATIC MODE CHANGE CAPABILITIES - A hearing aid includes a casing configured to fit behind an ear of a user's head and against a side of the user's head. The hearing aid further includes a first proximity sensor associated with the casing and configured to generate a first signal that is proportional to a proximity of the casing to the ear and includes a processor coupled to the first proximity sensor and configured to select an operating mode from a plurality of operating modes in response to the first signal. | 04-05-2012 |
20120320680 | METHOD, APPARATUS, AND MANUFACTURE FOR STAGGERED START FOR MEMORY MODULE - A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for a separate, distinct delay period. For each flash memory, after the delay period expires for that flash memory, the flash memory executes a second portion of the instructions for the flash memory. | 12-20-2012 |
20130177188 | SYSTEM AND METHOD FOR REMOTE HEARING AID ADJUSTMENT AND HEARING TESTING BY A HEARING HEALTH PROFESSIONAL - A system for establishing a communications to communicate with a hearing health professional, providing data related to hearing aid settings to the hearing health professional, receiving a hearing aid profile in response to providing the data, and providing the hearing aid profile to a hearing aid through a second communication link. | 07-11-2013 |
20130177189 | System and Method for Automated Hearing Aid Profile Update - A method includes receiving a new hearing aid profile generating instruction, generating a new hearing aid profile corresponding to each of a plurality of hearing aid users in response to receiving the new hearing aid profile, and providing the new hearing aid profile to a computing device associated with the hearing aid users. | 07-11-2013 |
20130178162 | SYSTEM AND METHOD FOR LOCATING A HEARING AID - A smart phone including a computer readable storage medium to store a hearing aid locator application and a processor coupled to the computer readable storage medium to execute the hearing aid locator application to track a last known location of a hearing aid. | 07-11-2013 |
20130301860 | HEARING AID WITH AUTOMATIC MODE CHANGE CAPABILITIES - A hearing aid includes a casing configured to fit behind an ear of a user's head and against a side of the user's head. The hearing aid further includes a first proximity sensor associated with the casing and configured to generate a first signal that is proportional to a proximity of the casing to the ear and includes a processor coupled to the first proximity sensor and configured to select an operating mode from a plurality of operating modes in response to the first signal. | 11-14-2013 |
20140092687 | METHOD, APPARATUS, AND MANUFACTURE FOR STAGGERED START FOR MEMORY MODULE - A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for a separate, distinct delay period. For each flash memory, after the delay period expires for that flash memory, the flash memory executes a second portion of the instructions for the flash memory. | 04-03-2014 |
Patent application number | Description | Published |
20090002023 | Modular ASIC With Crosspoint Switch - Provided is a digital signal processing device, specifically a modular application specific integrated circuit (“ASIC”), having a programmable crosspoint switch for facilitating data transfer and processing within the circuit. A programmable matrix element is operable to perform advanced matrix operations (arithmetic operations) according to user provided commands. The crosspoint switch interconnects the programmable matrix element with various other processing or conditioning modules (i.e. down conversion, filter, pulse processing and demodulation modules) to ensure parallel processing at System Clock rates. The ASIC, which is reconfigurable at a top-level according to user requirements, facilitates design changes and bench testing. | 01-01-2009 |
20100164680 | SYSTEM AND METHOD FOR IDENTIFYING PEOPLE - A system for identifying a person includes at least one biometric sensor for sensing a biometric characteristic of the person; at least one signal sensor for sensing a signal emitted from a device carried by the person; and a computing device for comparing the sensed biometric characteristic and the sensed signal to known characteristics of the person in an attempt to identify the person. | 07-01-2010 |
20110039459 | Solderless carbon nanotube and nanowire electrical contacts and methods of use thereof - Solderless and durable electrical contacts may be made by growing carbon nanotube (CNT) or nanowire forests in a solderless manner directly on the contact surfaces of integrated circuits, PCBs, IC packages, hybrid substrates, contact carriers, rotor components, stator components, etc. The electrical contacts and methods may be employed in a variety of leaded and leadless electronic packaging applications on PCBs, IC packages, and hybrid substrates including, but not limited to, ball grid array (BGA) packages, land grid array (LGA) and leadless chip carrier (LCC) packages, as well as for making interconnections in “flip-chip” configurations, “bare die” configurations, and interconnection of integrated circuit die in multi-layer and “3-D” stacking arrangements. | 02-17-2011 |
20110196907 | RECONFIGURABLE NETWORKED PROCESSING ELEMENTS PARTIAL DIFFERENTIAL EQUATIONS SYSTEM - A method for using a system to compute a solution to a partial differential equation (PDE) broadly comprises the steps of determining the true accuracy required (TAR) to solve the PDE, determining an architecture according to the TAR that performs a plurality of calculations to solve the PDE, determining a time allowed (TA) and a time required (TR) based on the architecture to solve the PDE, rejecting the PDE if the TR is less than or equal to the TA, configuring a plurality of programmable devices with the architecture, initiating the calculations, and ceasing the calculations when an accuracy criteria is met or when the TA expires. The system broadly comprises a plurality of programmable devices, a plurality of storage elements, a device bus, a plurality of printed circuit (PC) boards, and a board to board bus. | 08-11-2011 |
Patent application number | Description | Published |
20080263303 | LINEAR COMBINER WEIGHT MEMORY - A linear combiner weight memory. Various embodiments of the weight memory provide a weight bank and control logic. The weight bank is operable to couple with a data stream and may include four registers. The first register is operable to store a first in-phase weight value. The second register is operable to store a second in-phase weight value and be written with the second in-phase weight value while the first in-phase weight value is read from the first register. The third register is operable to store a first quadrature weight value. The fourth register is operable to store a second quadrature weight value and be written with the second quadrature weight value while the first quadrature weight value is read from the third register. | 10-23-2008 |
20080263317 | DATAPIPE DESTINATION AND SOURCE DEVICES - An integrated circuit ( | 10-23-2008 |
20080263322 | MAC ARCHITECTURE FOR PIPELINED ACCUMULATIONS - A programmable accumulation module ( | 10-23-2008 |
20080263499 | DATAPIPE INTERPOLATION DEVICE - A system for data processing comprises a host circuit ( | 10-23-2008 |
20110153705 | METHOD AND APPARATUS FOR A FINITE IMPULSE RESPONSE FILTER - A finite impulse response filter comprises an input formatter, a plurality of sample registers, a plurality of coefficient registers, an arithmetic unit, a multiply accumulate unit, a crosspoint switch, an interpolator, a control unit, and an output formatter. The input formatter separates the in-phase portion of a complex-number discrete-time sample from the quadrature portion. The sample registers store a plurality of discrete-time samples. The coefficient registers store a plurality of coefficients. The arithmetic unit adds two of the discrete-time samples to create a sum. The multiply accumulate unit includes a multiplier that multiplies the sum by a coefficient to create a product, an adder that adds the product to a sum of products, and a register that stores the sum of products. The crosspoint switch allows communication between the first and second plurality of registers and the arithmetic unit and the multiply accumulate unit. The interpolator inserts a desired number of zeros into the time-sampled data stream to adjust the time-sampled data stream to an increasing sampling rate. The control unit controls the settings of the crosspoint switch, the arithmetic unit, and the multiply accumulate unit. The output formatter combines the in-phase sum of products and the quadrature sum of products to create a filtered complex-number discrete-time sample. | 06-23-2011 |
20110153706 | FAST FOURIER TRANSFORM ARCHITECTURE - A fast Fourier transform (FFT) architecture operable to transform data of variable point size includes a plurality of input ports, a plurality of memory elements, a crosspoint switch, a plurality of processing elements, and a plurality of output ports. The inputs ports read time-domain data from an external source. The memory elements store input data, intermediate calculation results, and output data. The crosspoint switch allows data to flow from any one architecture component to any other architecture component. The processing elements perform the FFT calculation. The output ports write frequency-domain data to an external source. | 06-23-2011 |