Patent application number | Description | Published |
20110064013 | COLLISION MITIGATION FOR MULTICAST TRANSMISSION IN WIRELESS LOCAL AREA NETWORKS - A method and apparatus are described including multicasting a medium reservation message, receiving responses to the medium reservation message and determining if a ratio of the received responses to an expected number of responses exceeds a threshold. Also described are a method and apparatus including receiving a medium reservation message, determining if the medium reservation message specifies this receiver in a list of receivers from which a response is requested, determining if a medium is idle and transmitting the response to the medium reservation message responsive to the second determination. | 03-17-2011 |
20110069628 | CONTENTION BASED MEDIUM RESERVATION FOR MULTICAST TRANSMISSION IN WIRELESS LOCAL AREA NETWORKS - A method and apparatus are described including multicasting a medium reservation message and receiving a response to the medium reservation message. Also described are a method and apparatus including receiving a medium reservation message, determining if a medium is idle and transmitting a response to the medium reservation message responsive to the determination. Further described are a method and apparatus including receiving a medium reservation message, determining if a received network allocation vector in the medium reservation message has a value greater than a current network allocation vector, determining if transmission over a medium during a time interval is detected and resetting the current network allocation vector responsive to the determination of transmission. Yet further described are a method and apparatus including receiving a response to a medium reservation message, determining if a network allocation vector in the response is greater than a current network allocation vector and updating the current network allocation vector responsive to the determination. | 03-24-2011 |
20110080977 | Apparatus for multicast transmissions in wireless local area networks - Message formats and apparatus are described that serve to reserve access to a communication medium in a multi-cast system. A first message, a multicast request-to-send message, includes a duration field having information representing the reserved time for a communication medium, a multicast receiver address field, a multicast transmitter address field, a field that identifies the number of slots for a clear-to-send response, and a field that identifies the number slots for a not-clear-to-send response. A second message includes a duration field, and a multicast receive address field. The second message has a format that can be used as one of a clear-to-send message in response to a multicast request-to-send message, a cancel-clear-to-send message that cancels a data transmission after the clear-to-send message is sent, and a not-clear-to-send message in response to the multicast request-to-send message. | 04-07-2011 |
20110096710 | APPARATUS FOR REQUESTING ACKNOWLEDGEMENT AND TRANSMITTING ACKNOWLEDGEMENT OF MULTICAST DATA IN WIRELESS LOCAL AREA NETWORKS - A signal and apparatus for receiving the signal are described wherein the signal includes a duration field, a multi-cast receiver address field, a transmitter address field, a block acknowledgment request control field, a block acknowledgment request information field and an information field. Also described are a signal and apparatus for transmitting the signal wherein the signal includes a duration field, a multicast receiver address field, a transmitter address field, a block acknowledgment control field and a block acknowledgment information field. | 04-28-2011 |
20110116435 | Method and System for acknowledgement and retransmission of multicast data in wireless local area networks - A method and apparatus are described including multicasting a plurality of data units and multicasting a request for acknowledging receipt of the plurality of data units, receiving signals responsive to the request. Also described are a method and apparatus including receiving a multicast request to acknowledge receipt of data, determining if a response to the request is required, determining status of the data, preparing the response based on the determining acts and transmitting the response. | 05-19-2011 |
Patent application number | Description | Published |
20080276143 | Method and apparatus for broadcasting scan patterns in a random access based integrated circuit - A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit. | 11-06-2008 |
20100287430 | MULTIPLE-CAPTURE DFT SYSTEM TO REDUCE PEAK CAPTURE POWER DURING SELF-TEST OR SCAN TEST - A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein. | 11-11-2010 |
20110022907 | FPGA Test Configuration Minimization - A method for automatically generating test patterns using a close-to-minimum number of configurations for a Field Programmable Gate Array (FPGA) to reduce test data volume and test application time. The FPGA can be a standalone programmable device or a circuit embedded in an Application Specific Integrated Circuit (ASIC). | 01-27-2011 |
20110022908 | ROBUST SCAN SYNTHESIS FOR PROTECTING SOFT ERRORS - A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system. The system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level. | 01-27-2011 |
20110047426 | METHOD AND APPARATUS FOR LOW-PIN-COUNT SCAN COMPRESSION - A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step. | 02-24-2011 |
20120110402 | METHOD AND APPARATUS FOR TESTING 3D INTEGRATED CIRCUITS - A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss. | 05-03-2012 |
20120166903 | MULTIPLE-CAPTURE DFT SYSTEM TO REDUCE PEAK CAPTURE POWER DURING SELF-TEST OR SCAN TEST - A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, includes the steps of: (a) generating and shifting-in N test stimuli to all scan cells within the N clock domains during a shift-in operation; (b) applying an ordered sequence of capture clocks to all scan cells within the N clock domains, the ordered sequence of capture clocks including a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all scan cells to locate any faults therein. | 06-28-2012 |
20120173940 | ROBUST SCAN SYNTHESIS FOR PROTECTING SOFT ERRORS - A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level. | 07-05-2012 |
20120266036 | METHOD AND APPARATUS FOR LOW-PIN-COUNT SCAN COMPRESSION - A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step. | 10-18-2012 |
20140143623 | METHOD AND APPARATUS FOR LOW-PIN-COUNT SCAN COMPRESSION - A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step. | 05-22-2014 |