Patent application number | Description | Published |
20100066959 | LIQUID CRYSTAL PANEL AND LIQUID CRYSTAL MIXTURE - A liquid crystal panel including a first substrate, a second substrate, a liquid crystal layer disposed between the first substrate and the second substrate, a counter electrode, a pixel array structure, at least one alignment layer and at least one polymer layer is provided. The counter electrode is disposed between the liquid crystal layer and the first substrate. The pixel array structure is disposed between the liquid crystal layer and the second substrate. The alignment layer is disposed between the counter electrode and the liquid crystal layer and between the pixel array structure and the liquid crystal layer. The polymer layer is disposed between the alignment layer and the liquid crystal layer, and a material of the polymer layer includes polymer monomers and polymethyl methacrylate (PMMA). A content of PMMA in the polymer layer is greater than 1 ppm and smaller than 15000 ppm. | 03-18-2010 |
20100289996 | CAMBERED LIQUID CRYSTAL DISPLAY PANEL - A cambered liquid crystal display including a first substrate, a second substrate, a sealant, a plurality of photo-spacers and a liquid crystal layer is provided. The sealant is disposed between the first substrate and the second substrate, wherein the first substrate, the second substrate and the sealant are bent to form at least one cambered structure. The photo-spacers are disposed on the first substrate and distributed between the first and the second substrate, wherein a gap formed between a part of the photo-spacers close to the top of the cambered structure and the second substrate is smaller than a gap formed between a part of the photo-spacers apart from the top of the cambered structure and the second substrate. The liquid crystal layer is disposed between the first and the second substrate, wherein the photo-spacers and the liquid crystal layer are surrounded by the sealant. | 11-18-2010 |
20110228190 | CURVED DISPLAY PANEL - A curved display panel includes a first substrate, a second substrate, a display medium, spacers, and padding-islands. The second substrate has a first surface and a second surface opposite to the first surface. The first surface faces toward the first substrate, and the second surface faces against the first substrate. The display medium and the spacers are disposed between the first and the second substrates. The padding-islands are disposed on a plurality of regions of the first surface of the second substrate. The padding-islands on the different regions have different thicknesses. Another curved display panel includes two substrates, a display medium, and spacing pillars. The display medium and the spacing pillars are disposed between the substrates. Bottom areas of the spacing pillars decrease from the center to the outside of the substrates along at least one first direction. Cross-sections of the substrates along the first direction are curved. | 09-22-2011 |
20120026449 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display (LCD) panel including a first substrate, a second substrate, a liquid crystal layer, a photo-curable sealant, and a first light-shielding pattern is provided. The liquid crystal layer is disposed between the first substrate and the second substrate. The photo-curable sealant is disposed between the first substrate and the second substrate, wherein the photo-curable sealant surrounds and is in contact with the liquid crystal layer. The first light-shielding pattern is disposed on the first substrate, wherein a portion of the sidewall of the first light-shielding pattern is substantially aligned with a portion of the sidewall of the first substrate, and the first light-shielding pattern is only overlapped with an outer edge of the photo-curable sealant or is not overlapped with the photo-curable sealant. | 02-02-2012 |
20130128205 | DISPLAY PANEL - A display panel including a display region and a sealant region is provided. The display panel includes a first and a second substrate opposite to each other, a dielectric layer, a planarization layer, a display medium and a sealant. The dielectric layer is disposed on the first substrate. The planarization layer is disposed on the dielectric layer, and has at least one opening exposing the dielectric layer. The opening is disposed at a corner of the sealant region, where a width of the opening is gradually reduced as away from the corner. The display medium and the sealant are respectively disposed in the display and the sealant region between the first and the second substrate. The sealant is filled in a part of the opening without covering at least a sidewall of the opening of the planarization layer, and contacts the dielectric layer through the opening. | 05-23-2013 |
Patent application number | Description | Published |
20150303789 | CONVERTER AND VOLTAGE CLAMP CIRCUIT THEREIN - A converter includes a first bridge arm, a second bridge arm, two switch units and a voltage clamp circuit. The first bridge arm includes a first switch unit and a second switch unit that are electrically coupled in series at an output terminal. The second bridge arm includes two voltage sources that are electrically coupled in series at a neutral point terminal. The two switch units are electrically coupled in series at a common connection terminal, and are arranged between the neutral point terminal and the output terminal. The voltage clamp circuit is electrically coupled to the output terminal, the common connection terminal, the neutral point terminal, and one of a positive input terminal or a negative input terminal, and the circuit is shared by the two switch units to clamp voltages across the two switch units. | 10-22-2015 |
20150303828 | CONVERTER - A converter includes a first bridge arm, a second bridge arm, a switch circuit and a voltage clamp circuit. The first bridge arm includes a first switch unit and a second switch unit that are electrically coupled in series at an output terminal. The second bridge arm includes two voltage sources that are electrically coupled in series at a neutral point terminal. The switch circuit is disposed between the neutral point terminal and the output terminal. The voltage clamp circuit is electrically coupled to the output terminal, the neutral point terminal, and one of a positive input terminal and a negative input terminal, and is configured to clamp voltage across the switch circuit. | 10-22-2015 |
Patent application number | Description | Published |
20130246986 | METHOD OF CIRCUIT DESIGN YIELD ANALYSIS - A method includes (a) generating a set of samples, each sample representing a respective set of semiconductor fabrication process variation values; (b) selecting a first subset of the set of samples based on a probability of the set of semiconductor fabrication process variation values corresponding to each sample; (c) estimating a yield measure for a semiconductor product based on relative sizes of the set of samples and the first subset, without performing a Monte Carlo simulation; and (d) outputting an indication that a design modification is appropriate, if the estimated yield measure is below a specification yield value. | 09-19-2013 |
20140189623 | PARASITIC COMPONENT LIBRARY AND METHOD FOR EFFICIENT CIRCUIT DESIGN AND SIMULATION USING THE SAME - A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included. | 07-03-2014 |
20140282308 | METHOD OF RADIO-FREQUENCY AND MICROWAVE DEVICE GENERATION - The present disclosure relates to an apparatus and method to generate a device library, along with layout versus schematic (LVS) and parasitic extraction set-up files for connecting with official tools of a design window supported by a process design kit (PDK). The device library comprises passive devices which can be utilized at any point in an end-to-end design flow from pre-layout verification to post-layout verification of an integrated circuit design. The device library allows for a single schematic view for pre-layout verification but also post-layout verification, thus allowing for pole or pin comparison, and prevents double-counting of parasitic effects from passive design elements by directly instantiating a device from the device library for a verification step. An LVS and parasitic extraction graphical user interface (GUI) allows for incorporation of the generated device library into a pre-existing PDK without any modification to the PDK. Other devices and methods are also disclosed. | 09-18-2014 |
20150074629 | PARASITIC COMPONENT LIBRARY AND METHOD FOR EFFICIENT CIRCUIT DESIGN AND SIMULATION USING THE SAME - A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included. | 03-12-2015 |
20150089463 | METHOD OF FAILURE ANALYSIS - In some methods, a number of input data sets is provided for an integrated circuit (IC) model. A number of scores for the number of input data sets, respectively, are then determined based on probabilities of the respective input data sets resulting in a failure condition, which exists when the IC model fails to meet a predetermined yield criteria. A simulation order for the number of input data sets is then assigned according to the determined number of scores. | 03-26-2015 |
20150143314 | METHOD OF DESIGNING FIN FIELD EFFECT TRANSISTOR (FINFET)-BASED CIRCUIT AND SYSTEM FOR IMPLEMENTING THE SAME - A method of designing a fin field effect transistor (FinFET)-based circuit includes designing, using a processor, a first circuit schematic design based on a performance specification, the first circuit schematic design is free of artificial elements, wherein the artificial elements are used to simulate electrical performance of the FinFET-based circuit. The method further includes modifying, using the processor, at least one device within the first circuit schematic design to form a second circuit schematic design taking the artificial elements into consideration. The method further includes performing a pre-layout simulation using the second circuit schematic and taking the artificial elements into consideration. The method further includes generating a layout, wherein the layout does not take the artificial elements into consideration, and performing a post-layout simulation, wherein the post-layout simulation does not take the artificial elements into consideration | 05-21-2015 |
20150154333 | INTEGRATED CIRCUIT DESIGN FLOW WITH DEVICE ARRAY LAYOUT GENERATION - A system for designing an integrated circuit generates a schematic of the integrated circuit based on a set of system design rule constraints. The system also receives a proposed device array layout from a device array design module. The device array design module is configured to generate the proposed device array layout free from the set of system design rule constraints. The system further generates a revised schematic of the integrated circuit including the proposed device array layout. The system additionally determines if the revised schematic violates one or more of the system design rule constraints. | 06-04-2015 |
20150317427 | INTEGRATED CIRCUIT DESIGN SYSTEM AND METHOD OF USING THE SAME - A system for designing an integrated circuit includes at least one processor and at least one memory including computer program code for one or more programs. The at least one memory and the computer program code are configured to, with the at least one processor, cause the system to receive a proposed device array layout from a device array design module. The device array design module is configured to generate the proposed device array layout free from a set of system design rule constraints. The system is also caused to revise a schematic of the integrated circuit including the proposed device array layout. The system is further caused to determine whether the revised schematic violates one or more system design rule constraints. | 11-05-2015 |
20150339414 | METHOD FOR PROCESS VARIATION ANALYSIS OF AN INTEGRATED CIRCUIT - A method and a corresponding system for process variation analysis of an integrated circuit are provided. A netlist is generated describing electronic devices of an integrated circuit in terms of device parameters and process parameters. The process parameters include local process parameters individual to the electronic devices and global process parameters common to the electronic devices. Critical electronic devices are identified having device parameters with greatest contributions to a performance parameter of a design specification of the integrated circuit. Sensitivity values are determined for the global process parameters and local process parameters of the critical electronic devices. The sensitivity values represent how sensitive the one or more performance parameters are to variations in the global and local process parameters of the critical electronic devices. Monte Carlo (MC) samples are sorted based on the sensitivity values. | 11-26-2015 |
Patent application number | Description | Published |
20130141855 | PORTABLE COMPUTER - A portable computer includes a base, a display module, at least one support element and at least one sliding assembly. The display module comprises a connecting end and a display face. Each support element comprises a first end pivoted on a portion of the display module other than the display face and a second end pivoted on the rear end of the base. Each sliding assembly comprises a slide rail disposed at least in the second area and a sliding element combined with the connecting end and moving along the slide rail. Each sliding element includes at least one sliding auxiliary structure for decreasing friction during sliding. | 06-06-2013 |
20140134859 | SLIM TYPE ELECTRONIC CONNECTOR AND ELECTRONIC DEVICE HAVING THE SAME - A slim type electronic connector for receiving a plug therein includes a half socket, a covering lid, a holding seat, and a recovering element. The covering lid has a main body, a sheltering portion extended from the main body, and a pair of rotating axles formed at one end of the main body. An inserting space is formed between the half socket and the holding seat. When the covering lid rotates to a covered position, the sheltering portion extends beyond a front edge of the holding seat. When the covering lid rotates to an opening position, the sheltering portion moves away the front edge of the holding seat to allow for inserting the plug. When the plug is inserted between the half socket and the holding seat, the recovering element pushes the sheltering portion to engage the plug for preventing from moving outside. | 05-15-2014 |
20150230013 | FIXING STRUCTURE AND ELECTRONIC DEVICE THEREWITH - An electronic device includes an electronic component and a fixing structure. The electronic component includes a fixing portion, and a fixing hole is formed on the fixing portion. The fixing structure is for fixing the electronic component on a base plate. The fixing structure includes a main body, a fastening portion, a fixing pillar and an engaging component. A supporting plane is formed on an end of the main body. The fastening portion is connected to the other end of the main body and for fastening the main body on the base plate. The fixing pillar is disposed on the supporting plane. The fixing pillar is inserted into the fixing hole for constraining the electronic component. The engaging component is connected to a side of the main body, and the engaging component presses the electronic component so as to engage the electronic component on the supporting plane. | 08-13-2015 |
20160073537 | INSTALLATION MECHANISM FOR REPLACEABLE DEVICE AND ELECTRONIC APPARATUS THEREWITH - An electronic apparatus includes a replaceable device, an apparatus casing, a supporting structure, an abutting structure, and a removable carrier. The supporting structure, the abutting structure, and the removable carrier function as an installation mechanism for installing the replaceable device into the apparatus casing. The supporting structure and the abutting structure are disposed in the apparatus casing. The abutting structure has two side walls oppositely disposed. The removable carrier includes a fixing frame and an actuation part pivotally connected to the fixing frame. The replaceable device is fixed on the fixing frame. When the removable carrier is disposed on the supporting structure, the actuation part can be rotated relative to the fixing frame and alternatively abut against one side wall so that the fixing frame moves on the supporting structure and a connector of the replaceable device is engaged with or disengaged from a connector of the electronic apparatus respectively. | 03-10-2016 |
Patent application number | Description | Published |
20140118975 | ENVIRONMENTAL SENSITIVE ELECTRONIC DEVICE PACKAGE - An environmental sensitive electronic device package may include a first substrate, a second substrate, an environmental sensitive electronic device, at least one side wall barrier structure, and a filler layer. The first substrate has at least one predetermined flexure area. The second substrate is located above the first substrate. The environmental sensitive electronic device is located on the first substrate and between the first substrate and the second substrate. The side wall barrier structure is located between the first substrate and the second substrate and surrounds the environmental sensitive electronic device. The side wall barrier structure has at least one flexure stress dispersing structure that is located in the predetermined flexure area. The filler layer is located between the first substrate and the second substrate and covers the side wall barrier structure and the environmental sensitive electronic device. | 05-01-2014 |
20150109542 | TOUCH PANEL - A touch panel is provided, which includes a poly(vinylidene fluoride) (PVDF) substrate and a touch electrode structure. The PVDF substrate has two opposite surfaces. The touch electrode structure is at least disposed on one of the surfaces. | 04-23-2015 |
20150241924 | TOUCH PANEL - A touch panel includes a substrate, first electrodes, second electrodes, third electrodes, and fourth electrodes. The substrate includes a first touch region, a second touch region, and a first touch folding region disposed between the first touch region and the second touch region. The first electrodes extending from the first touch region to the first touch folding region and the second electrodes are disposed in the first touch region on the substrate. The third electrodes extending from the second touch region to the first touch folding region and the fourth electrodes are disposed in the second touch region on the substrate. The first electrodes and the third electrodes are not intersected with one another. A ratio of any side length of the touch panel to a distance between the first touch region and the second touch region is between 9.5 and 95. | 08-27-2015 |
20150293646 | TOUCH SENSING STRUCTURE - A touch sensing structure including a plastic substrate, a buffer layer, an electrode layer, an insulation unit, and a passivation layer is provided. The buffer layer is disposed on the plastic substrate, and the electrode layer includes a first patterned transparent electrode layer and a second patterned transparent electrode layer. The first patterned transparent electrode layer is disposed on the buffer layer, and the second patterned transparent electrode layer is disposed on the buffer layer. The insulation unit insulates the first patterned transparent electrode layer and the second patterned transparent electrode layer, and the passivation layer is disposed on the electrode layer. Twice a total optical path length of the electrode layer and the passivation layer along a direction substantially parallel to a normal direction of the plastic substrate ranges from 1000 nm to 2500 nm. | 10-15-2015 |
Patent application number | Description | Published |
20130141869 | HEAT DISSIPATING MODULE - A heat dissipation module, comprising: a fan; and a heat dissipating fin; a heat conducting element, made of a conductive material, and composed of a first conductive component and two second conductive components in a manner that the first conductive component is disposed engaging with a heating element while allowing the two second conductive components to engage with the heat dissipating fin; and a wall element; wherein, the heat from the heating element is conducted to the first conductive component where it is further being dividedly conducted to the two second conductive components; and the air flow blowing from the fan is guided to the heating element and then it is blocked by the wall element for diverting the air flow toward the heat dissipating fin from an air intake side to an air outlet side, and then to be discharged out of the heat dissipating module through an outlet. | 06-06-2013 |
20130155605 | ELECTRONIC APPARATUS - An electronic apparatus is disclosed, which comprises: a housing, configured with a plurality of inlets and one outlet; a plurality of electronic elements, disposed inside the housing; and a plurality of gates, arranged at positions corresponding to the plural inlets in an one-by-one manner; wherein, the plural electronic elements are activated while the electronic apparatus is enabled for causing the temperature of the plural electronic elements to be raised to their respective working temperatures, thereby, causing a plurality of heating zones to be formed inside the housing at positions respectively corresponding to the plural inlets; and by enabling each gate to be configured with one thermal expansion element that is enabled to deform with the temperature variation of the corresponding heating zone, each gate is enabled to move between a first position and a second position according to the deformation of the corresponding thermal expansion element. | 06-20-2013 |
20140090819 | HEAT DISSIPATION DEVICE - A heat dissipation device includes a fan module, a first plate structure and a fin assembly. The fan module includes a fan outlet. The first plate structure is disposed at the fan outlet. The thermal conductance of the first plate structure is above 100 W/(m·K). The first plate structure includes a heat-absorbing and a heat-dissipation surface. The heat-absorbing surface includes a heat-absorbing region in thermal contact with a heat source. The heat-dissipation surface includes a heat-dissipation region. The fin assembly is disposed on the heat-dissipation surface and in thermal contact with the heat-dissipation surface. The fan module is adapted to exhaust an air flow flowing above the heat-dissipation surface via the fan outlet. The air flow flows through the heat-dissipation region before through the fin assembly. The distance between the fan outlet and the heat-dissipation region is greater than the distance between the fan outlet and the fin assembly. | 04-03-2014 |
20140118939 | HEAT DISSIPATION MODULE, ELECTRONIC DEVICE AND ITS DUST REMOVAL METHOD - A dust removal method of an electronic device is provided that the electronic device includes a first body, a heat dissipation module and a cover plate. The first body includes a heat dissipation opening. The heat dissipation module comprises a fan and a fin assembly. The fan has a fan case body and a blade assembly. The fan case body includes an air inlet, an air outlet and a dust collecting opening. The air outlet and the heat dissipation opening are connected with each other. The cover plate is installed in the fan case body and adjacent to the dust collecting opening. The blade assembly turns and the cover plate covers the dust collecting opening. An air current flows in from the air inlet and flows out from the air outlet. | 05-01-2014 |
Patent application number | Description | Published |
20110075369 | ELECTRONIC DEVICE - An electronic device including a heat generation element, a heat dissipation plate, and a heat pipe is provided. The heat dissipation plate includes a top surface, a bottom surface, a pair of longitudinal side surfaces, and a pair of lateral side surfaces including a third side surface and a fourth side surface. The longitudinal side surfaces include first and second side surfaces. The lateral side surfaces include third and fourth side surfaces. The first, second, third and fourth side surfaces are connected to both the top surface and the bottom surface. The heat pipe is disposed in contact with the heat dissipation plate, and the heat pipe and the heat generation element are disposed on the bottom surface of the heat dissipation plate. The heat pipe is disposed on the heat dissipation plate and extension of the heat pipe is not beyond the first, second, third and fourth side surfaces. | 03-31-2011 |
20120127652 | ELECTRONIC APPARATUS WITH IMPROVED HEAT DISSIPATION - An electronic apparatus with improved heat dissipation comprises a first body with a first shell and a second shell, a second body, a coupling device and a linkage device. The first shell is pivotally connected to the second shell to form an accommodation space. The first shell can pivot relative to the second shell to enlarge the accommodation space and form an opening between the first shell and the second shell. The coupling device couples the second body and the second shell to pivot the second body relative to the second shell to expose or hide the first shell. The linkage device drives the first shell to pivot relative to the second shell. When the second body pivots relative to the second shell toward a first direction, the linkage device drives the first shell to pivot relative to the second shell toward a second direction opposite to the first direction. | 05-24-2012 |
20120127662 | ELECTRONIC APPARATUS AND KEYBOARD SUPPORTING MODULE THEREOF - An electronic apparatus and a keyboard supporting module thereof are provided. The electronic apparatus includes a heat source, the keyboard supporting module and a push-button key module. The keyboard supporting module includes a keyboard supporting structure and an insulator. The keyboard supporting structure is thermally connected to the heat source. Particularly, the keyboard supporting structure supports the push-button key module with the insulator. | 05-24-2012 |
20140119906 | FAN - A fan includes a casing and a fan blade. The casing has at least one air inlet and an air outlet. The fan blade is disposed in the casing. An air flow compression area is defined in the casing. An auxiliary air inlet is disposed on the casing at the air flow compression area. Furthermore, another fan includes a casing and a fan blade. The casing has an upper casing, a lower casing and a side casing located between the upper casing and the lower casing. The upper casing or the lower casing has at least one air inlet, and the side casing has an air outlet. The fan blade is disposed in the casing. An internal space of the casing is defined as an air flow compression area. An auxiliary air inlet is disposed on the casing at the air flow compression area. | 05-01-2014 |
20140127022 | FAN BLADE STRUCTURE - A fan blade structure includes a hub, an annular partition surrounding the hub, a first blade group and a second blade group. The hub has a top surface and a flank connected to the top surface. The first blade group, disposed on one side of the annular partition, includes two blade arrays having multiple first and second blades respectively. The clearance between the two adjacent first blades is less than that between the two adjacent second blades. The second blade group, disposed on another side of the annular partition, includes another two blade arrays having a plurality of third and fourth blades respectively. The clearance between the two adjacent third blades is less than that between the two fourth blades adjacent to each other. | 05-08-2014 |
Patent application number | Description | Published |
20090271677 | Data Transformation Method and Related Device for a Testing System - A data transformation method for a testing system includes receiving a test signal comprising a test data and a timing information corresponding to the test data, and transforming the test data according to the timing information, so as to generate a test pattern. | 10-29-2009 |
20090296797 | Data Description Method and Related Packet and Testing System for a Serial Transmission Interface - A data description method for a serial transmission interface includes generating a low-speed data and a high-speed data simultaneously, sampling the low-speed data to generate a first sampling result according to a first sampling rate within a specified duration, sampling the high-speed data to generate a second sampling result according to a second sampling rate within the specified duration, and combining the first sampling result and the second sampling result to describe contents of the low-speed data and the high-speed data within the specified duration. | 12-03-2009 |
20100177067 | METHOD AND CIRCUIT FOR CONTROLLING TIMINGS OF DISPLAY DEVICES USING A SINGLE DATA ENABLE SIGNAL - In a first display period of a display device, a first count value is recorded at the rising edge of the data enable signal for controlling the length of a horizontal line. Next, a second count value is recorded at the falling edge of the data enable signal for identifying the time when the data enable signal switches from a high level to a low level. When entering a porch period following the first display period, the counter is cleared when the count value reaches the first count value. In a second display period following the porch period, the counter is cleared at the rising edge of the data enable signal, and the first count value is used for controlling the length of the horizontal line. | 07-15-2010 |