Patent application number | Description | Published |
20090261450 | Electrical Fuse Structure and Method - An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer. The tungsten contact and a neck portion of the silicide layer are the programmable portion of the electrical fuse. High post-programming resistance is achieved by a first programming phase that depletes silicide in the silicide layer, followed by a second programming phase that depletes tungsten in the tungsten contact. | 10-22-2009 |
20100090751 | Electrical Fuse Structure and Method - An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer. The tungsten contact and a neck portion of the silicide layer are the programmable portion of the electrical fuse. High post-programming resistance is achieved by a first programming phase that depletes silicide in the silicide layer, followed by a second programming phase that depletes tungsten in the tungsten contact. | 04-15-2010 |
20110103102 | VOLTAGE CONVERTER WITH HIGH EFFICIENCY - A voltage converter transmits energy in multiple stages using a charge pump so as to decrease the voltage rating of the secondary side of the transformer and reduce the size of the transformer. Meanwhile, the voltage converter stores and recycles the leakage inductance energy by using a snubber circuit so as to increase the efficiency. | 05-05-2011 |
20120119663 | LIGHT EMITTING DIODE CURRENT CONTROL CIRCUIT CAPABLE OF ENERGY RECYCLING - Alight emitting diode current control circuit capable of energy recycling includes at least one diode and at least one converter. The diode has an anode terminal, and a cathode terminal for coupling to a first terminal of at least one series of light emitting diodes. The converter has a first terminal coupled to an anode terminal of a corresponding diode, a second terminal for coupling to a second terminal of a series of light emitting diodes corresponding to the converter, a third terminal, and a fourth terminal coupled to ground. | 05-17-2012 |
20150061118 | Three-Dimensional Chip Stack and Method of Forming the Same - A three-dimensional chip stack includes a first chip bonded to a second chip to form a bonded interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region. | 03-05-2015 |
Patent application number | Description | Published |
20090289345 | ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - An electronic device package and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor substrate containing a plurality of chips having a first surface and an opposite second surface. A plurality of conductive electrodes is disposed on the first surface and the conductive electrodes of the two adjacent chips are arranged asymmetrically along side direction of the chip. A plurality of contact holes is formed in each chip, apart from the side of the chip, to expose the conductive electrodes. | 11-26-2009 |
20100289092 | POWER MOSFET PACKAGE - A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals. | 11-18-2010 |
20110042819 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes a semiconductor substrate having an upper surface and an opposite lower surface, a through-hole penetrating the upper surface and the lower surface of the semiconductor substrate, a chip disposed overlying the upper surface of the semiconductor substrate, a conducting layer overlying a sidewall of the through-hole and electrically connecting the chip, a first insulating layer overlying the upper surface of the semiconductor substrate, a second insulating layer overlying the lower surface of the semiconductor substrate, and a bonding structure disposed overlying the lower surface of the semiconductor substrate, wherein a material of the second insulating layer is different from that of the first insulating layer. | 02-24-2011 |
20110084382 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package is disclosed. The package includes a carrier substrate and at least two semiconductor chips thereon. Each semiconductor chip includes a plurality of conductive pads. A position structure is disposed on the carrier substrate to fix locations of the semiconductor chips at the carrier substrate. A fill material layer is formed on the carrier substrate, covers the semiconductor chips and the position structure, and has a plurality of openings correspondingly exposing the conductive pads. A redistribution layer (RDL) is disposed on the fill material layer and is connected to the conductive pads through the plurality of openings. A protective layer covers the fill material layer and the RDL. A plurality of conductive bumps is disposed on the protective layer and is electrically connected to the RDL. A fabrication method of the chip package is also disclosed. | 04-14-2011 |
20110193225 | ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed. | 08-11-2011 |
20130045571 | METHOD FOR FABRICATING ELECTRONIC DEVICE PACKAGE - A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed. | 02-21-2013 |
20130062759 | ELECTRONIC DEVICE PACKAGE - A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed. | 03-14-2013 |
20130193520 | POWER MOSFET PACKAGE - A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals. | 08-01-2013 |
20130312813 | SOLAR CELL AND MODULE THEREOF - A solar cell includes a silicon semiconductor substrate, a composite multifunctional protective film, a plurality of front electrodes and a plurality of back electrodes. The silicon semiconductor substrate has a roughened first surface. A depth of the doped layer arranged under the first surface ranges from 200 nm to 1000 nm. A surface doping concentration of the doped layer ranges from 1×10 | 11-28-2013 |
20140251422 | SOLAR CELL WITH DOPING BLOCKS - A solar cell with doping blocks is provided, which includes: a semiconductor substrate, an anti-reflection layer, a plurality of front electrodes, and a back electrode layer. The semiconductor substrate has a first surface, and a plurality of doping block layers is arranged under the first surface and spaced from each other. The anti-reflection layer is disposed on the doping block layer and the semiconductor substrate. The front electrodes penetrate the anti-reflection layer and are arranged on the doping block layers. The back electrode layer is disposed on a second surface of the semiconductor substrate. | 09-11-2014 |
20140284792 | ELECTRONIC DEVICE PACKAGE - A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed. | 09-25-2014 |
20140352773 | SOLAR CELL - A solar cell includes a photovoltaic substrate having a first surface and a second surface and a plurality of bus bar electrode net structures. The bus bar electrode net structures are separately disposed on the first surface, each bus bar electrode net structure includes a bus bar electrode, a plurality of finger electrodes, at least one connecting line electrode and at least one vertical finger electrode. The bus bar electrode is disposed on the first surface. The finger electrodes are separately disposed at two sides of the bus bar electrode. The connecting line electrode is disposed on the first surface. Each connecting line electrode connects with ends of at least two finger electrodes. The vertical finger electrode is disposed on the first surface, and is parallel to the bus bar electrode and disposed between the two ends of the finger electrode to connect with at least two adjacent finger electrodes. | 12-04-2014 |
20140366937 | SOLAR CELL - A solar cell is disclosed, which includes: a semiconductor substrate, an anti-reflective layer, a passivation layer, a back electrode and back bus bar. The semiconductor substrate has a first surface and a second surface. The anti-reflective layer is disposed on the first surface. The back electrode is a continuous electrode or a flat electrode overlapping the whole back side of the solar cell. The continuous electrode or the flat electrode connects to the semiconductor substrate through a continuous opening. In another embodiment, the continuous electrode is passing through the passivation layer directly and connecting to the semiconductor substrate. That is, the solar cell includes a continuous opening or a continuous electrode. | 12-18-2014 |
Patent application number | Description | Published |
20110140267 | ELECTRONIC DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME - The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads. | 06-16-2011 |
20120037226 | SEMICONDUCTOR SUBSTRATE - A semiconductor substrate includes a substrate, at least a semiconductor layer, a first anti-reflection layer, and a second anti-reflection layer. The semiconductor layer is disposed on the substrate. The first anti-reflection layer is disposed on the semiconductor layer. The second anti-reflection layer is disposed on the first anti-reflection layer. The second anti-reflection layer is a discontinuous layer with the capability of photon conversion. | 02-16-2012 |
20120192932 | SOLAR CELL AND ITS ELECTRODE STRUCTURE - An electrode structure is disposed on a substrate of a solar cell. The electrode structure includes a plurality of bus electrodes, a plurality of finger electrodes, and at least one connection electrode. The bus electrodes are separately disposed on the substrate. The finger electrodes are disposed on two sides of the bus electrodes and electrically connect to the bus electrodes. The connection electrode is disposed on a side of the substrate and connects with at least two finger electrodes. The connection electrode, bus electrodes and the finger electrodes are formed by at least two screen printing processes, and at least one of the screen printing processes does not form the bus electrodes. Thus, the thicknesses of the finger electrodes are greater than those of the bus electrodes. | 08-02-2012 |
20130032939 | CHIP PACKAGE STRUCTURE - A chip package structure includes a flexible substrate having a chip mounting region, a plurality of leads disposed on the flexible substrate, an insulating layer and a chip. Each lead includes a body portion and an inner lead portion connected to each other. The body portion is located outside the chip mounting region and has a thickness greater than that of the inner lead portion. The insulating layer is disposed on the inner lead portions. The chip has an active surface on which a plurality of bumps and a seal ring adjacent to the chip edges are disposed. The chip is mounted within the chip mounting region and electrically connects the flexible substrate by connecting the inner lead portions of the leads with the bumps. The insulating layer is corresponding to the seal ring in position when the chip is electrically connected to the flexible substrate. | 02-07-2013 |
20140070373 | SEMICONDUCTOR HOLE STRUCTURE - A first dielectric layer is formed over a substrate. A second dielectric layer is formed over the first dielectric layer. A first opening is formed in the second dielectric layer. A second opening is formed in the first dielectric layer. | 03-13-2014 |
Patent application number | Description | Published |
20130193387 | Composition and Process for Preparing NIR Shielding Masterbatch and NIR Shielding Masterbatch and Application Thereof - Disclosed herein is a near infrared shielding masterbatch. The near infrared shielding masterbatch includes a cross-linked thermoplastic polymer and at least one metallic ionic compound powder. The cross-linked thermoplastic polymer comprises a thermoplastic polymer cross-linked by a cross-linking agent and that a weight ratio of the thermoplastic polymer to the cross-linking agent is about 68.7:2 to about 98.7:0.1. The metallic ionic compound powder is dispersed within the cross-linked thermoplastic polymer, and that a weight ratio of the cross-linked thermoplastic polymer to the metallic ionic compound powder is about 2.8:1 to about 98.8:1. | 08-01-2013 |
20130193608 | Composition and Process for Preparing NIR Shielding Masterbatch and NIR Shielding Masterbatch and Application Thereof - Disclosed herein is a method for preparing a near infrared shielding fiber. The method includes the steps of preparing and compounding a composition, then pelletizing the compounded composition to obtain the near-infrared shielding masterbatch, and melt spinning the near-infrared shielding masterbatch into the near-infrared shielding fiber. The composition includes at least one metallic ionic compound powder in an amount of about 1-25 wt %, a cross-linking agent in an amount of about 0.1-2 wt %, a thermoplastic polymer in an amount of about 67-98.7 wt %, a cross-linking initiator in an amount of about 0.1-1 wt %, and a dispersing agent in an amount of about 0.1-2 wt %. | 08-01-2013 |
20130314323 | PORTABLE ELECTRONIC DEVICE AND AN INPUT MODULE AND AN FLEXIBLE BRIDGING BOARD THEREOF - An input module is mounted on a portable electronic device and has a sensing substrate and a cover lens mounted on a top surface of the sensing substrate, a physical switch mounted on and electrically connected to a bottom surface of the sensing substrate, and a flexible bridging board having two opposite short sides respectively protruding from two short sides of the sensing substrate for the two short sides of the flexible bridging board to be mounted on the electronic device. As the two short sides of the input module are mounted on the electronic device and a lever arm between a pressed point to a fixed point of the input module is shortened, a torque applied to the input module is lowered and the input module is not easily deformed. | 11-28-2013 |
20140001659 | MANUFACTURING METHOD FOR AN INPUT MODULE BY PLASTIC INJECTION MOLDING | 01-02-2014 |
20150301864 | RESOURCE ALLOCATION METHOD - A resource allocation method adapted to a mobile device having a multi-core central processing unit (CPU) is provided. The CPU executes at least one application. The method includes steps as follows. A usage status of each of the at least one application is obtained according to a level of concern of a user for each of the at least one application. A sensitivity of at least one thread of each of the at least one application is determined according to the usage status of each of the at least one application. Resources of the CPU are allocated according to the sensitivity of the at least one thread run by the cores. | 10-22-2015 |