Patent application number | Description | Published |
20140077305 | GATE CONTACT STRUCTURE OVER ACTIVE GATE AND METHOD TO FABRICATE SAME - Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate. | 03-20-2014 |
20140175583 | PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE HAVING OFFSET CELLS AND METHOD TO FORM SAME - Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device. | 06-26-2014 |
20140329337 | PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE HAVING OFFSET CELLS AND METHOD TO FORM SAME - Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device. | 11-06-2014 |
Patent application number | Description | Published |
20090283499 | Fabrication of semiconductor interconnect structure - An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting. After the metal regions are etched and recessed in the substrate surface, a conductive capping layer is formed using electroless deposition over the recessed exposed metal regions. | 11-19-2009 |
20100015805 | Wet Etching Methods for Copper Removal and Planarization in Semiconductor Processing - Exposed copper regions on a semiconductor substrate can be etched by a wet etching solution comprising (i) one or more complexing agents selected from the group consisting of bidentate, tridentate, and quadridentate complexing agents; and (ii) an oxidizer, at a pH of between about 5 and 12. In many embodiments, the etching is substantially isotropic and occurs without visible formation of insoluble species on the surface of copper. The etching is useful in a number of processes in semiconductor fabrication, including for partial or complete removal of copper overburden, for planarization of copper surfaces, and for forming recesses in copper-filled damascene features. Examples of suitable etching solutions include solutions comprising a diamine (e.g., ethylenediamine) and/or a triamine (e.g., diethylenetriamine) as bidentate and tridentate complexing agents respectively and hydrogen peroxide as an oxidizer. In some embodiments, the etching solutions further include pH adjustors, such as sulfuric acid, aminoacids, and carboxylic acids. | 01-21-2010 |
20110223772 | FABRICATION OF SEMICONDUCTOR INTERCONNECT STRUCTURE - An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting. After the metal regions are etched and recessed in the substrate surface, a conductive capping layer is formed using electroless deposition over the recessed exposed metal regions. | 09-15-2011 |
20130207030 | WET ETCHING METHODS FOR COPPER REMOVAL AND PLANARIZATION IN SEMICONDUCTOR PROCESSING - Exposed copper regions on a semiconductor substrate can be etched by a wet etching solution comprising (i) one or more complexing agents selected from the group consisting of bidentate, tridentate, and quadridentate complexing agents; and (ii) an oxidizer, at a pH of between about 5 and 12. In many embodiments, the etching is substantially isotropic and occurs without visible formation of insoluble species on the surface of copper. The etching is useful in a number of processes in semiconductor fabrication, including for partial or complete removal of copper overburden, for planarization of copper surfaces, and for forming recesses in copper-filled damascene features. Examples of suitable etching solutions include solutions comprising a diamine (e.g., ethylenediamine) and/or a triamine (e.g., diethylenetriamine) as bidentate and tridentate complexing agents respectively and hydrogen peroxide as an oxidizer. In some embodiments, the etching solutions further include pH adjustors, such as sulfuric acid, aminoacids, and carboxylic acids. | 08-15-2013 |
Patent application number | Description | Published |
20090277801 | Photoresist-free metal deposition - Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed. | 11-12-2009 |
20090277867 | Topography reduction and control by selective accelerator removal - Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity. | 11-12-2009 |
20090280243 | Photoresist-free metal deposition - Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed. | 11-12-2009 |
20090280649 | Topography reduction and control by selective accelerator removal - Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity. | 11-12-2009 |
20140014522 | PHOTORESIST-FREE METAL DEPOSITION - Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed. | 01-16-2014 |
Patent application number | Description | Published |
20120067066 | FREEZE TUNNEL AND METHODS OF USE - A freeze tunnel can have a conveyor configured to move food product from a first end to a second end. At least one first cooling unit and at least one first fan can be positioned on the first side of the conveyor, and at least one second cooling unit and at least one second fan can be positioned on the second side of the conveyor. The fans can cooperate to circulate air inside the freeze tunnel in two opposite rotational directions. | 03-22-2012 |
20120070553 | CONVEYOR-BASED FRYING APPARATUS AND METHODS OF USE - A fryer can include a base having a reservoir for receiving oil for frying a food product and a hood coupled to the base. The fryer can have an inlet at an upstream section and an outlet at a downstream section. At least one conveyor can move food product from the inlet to the outlet. A first baffle member and second baffle member can be positioned over the conveyor to define a frying chamber therebetween. The first and second baffle members can restrict air from flowing into the frying chamber from outside of the frying chamber. | 03-22-2012 |
20120174983 | FLUID-BASED ARTICLE DISTRIBUTION AND SORTING SYSTEM - A fluid-based radial distribution system includes an internal passageway and a plurality of openings radially spaced around the internal passageway. A plurality of gate members are associated with at least some of the plurality of openings, with the gate members are configured to move between an open position that allows product to move through the opening associated with that gate member and a closed position that restricts product from moving through the opening associated with that gate member. | 07-12-2012 |
20140373730 | CONVEYOR-BASED FRYING APPARATUS AND METHODS OF USE - A fryer can include a base having a reservoir for receiving oil for frying a food product and a hood coupled to the base. The fryer can have an inlet at an upstream section and an outlet at a downstream section. At least one conveyor can move food product from the inlet to the outlet. A first baffle member and second baffle member can be positioned over the conveyor to define a frying chamber therebetween. The first and second baffle members can restrict air from flowing into the frying chamber from outside of the frying chamber. | 12-25-2014 |
20150016898 | FLUID-BASED ARTICLE DISTRIBUTION AND SORTING SYSTEM - A fluid-based radial distribution system includes an internal passageway and a plurality of openings radially spaced around the internal passageway. A plurality of gate members are associated with at least some of the plurality of openings, with the gate members are configured to move between an open position that allows product to move through the opening associated with that gate member and a closed position that restricts product from moving through the opening associated with that gate member. | 01-15-2015 |
Patent application number | Description | Published |
20140368565 | PROVIDING REPLACEMENT PRINTING FLUID TO A PRINTER - A method performed using a computer includes receiving a cumulative consumption value for a printing fluid corresponding to a supply from a printer at the computer. The method also includes calculating a plurality of variable values by way of the cumulative consumption value for the printing fluid, a statistically derived depletion quantity for the printing fluid, and an estimated time to ship a supply of replacement printing fluid to the printer to form calculated variable values. The method also includes causing the supply of replacement printing fluid to be shipped to the printer in accordance with the calculating. | 12-18-2014 |
20140380055 | KEY PAIR UPDATES BASED ON DIGITAL SIGNATURE STATES - Example embodiments relate to updating key pairs based on digital signature states. In example embodiments, first credentials that are generated using a first private key may be sent to a user computing device, where the first private key is associated with a first public key. At some stage, second credentials that are generated using the first private key and a second private key are sent to the user computing device, where the second credentials specify that the first private key is deprecated, and where the user computing device authenticates the second credentials using the first public key. In response to receiving confirmation that a firmware upgrade is installed a number of user computing devices such that an upgrade threshold is satisfied, the first private key may be deactivated. The firmware upgrade may be provided in response to receiving a firmware upgrade request from the user computing device. | 12-25-2014 |
20150127498 | PROVIDING REPLACEMENT TANGIBLE RESOURCE TO A DEVICE - Example implementations relate to tangible resources. For example, a method includes receiving, at a computer, a cumulative consumption value of a tangible resource from a device that consumes the tangible resource. The method also includes calculating a plurality of variable values by way of the cumulative consumption value, a statistically derived depletion quantity of the tangible resource, and an estimated time to ship a supply of replacement tangible resource to the device to form calculated variable values such that the calculating is performed at least in part by the computer. The method further includes causing the supply of replacement tangible resource to be shipped to the device in accordance with the calculating. | 05-07-2015 |
Patent application number | Description | Published |
20120133381 | STACKABLE SEMICONDUCTOR CHIP WITH EDGE FEATURES AND METHODS OF FABRICATING AND PROCESSING SAME - A method of performing a function on a three-dimensional semiconductor chip package as well as on individual chips in the package is disclosed. That method involves the creation of an operative relationship between a function performer and an edge feature on the chip or chips wherein the edge feature consists of one or more of an electrically conductive pad, thermally conductive pad, a probe pad, a fuse, a resistor, a capacitor, an inductor, an optical emitter, an optical receiver, a test pad, a bond pad, a contact pin, a heat dissipator, an alignment marker, a metrology feature and a function performer may be any one or more of a test probe, the laser, a programming device, an interrogation device, a loading device or a tuning device. In addition, a chip per se with edge features is disclosed along with a three-dimensional stack of such chips in either of several different configurations. The disclosure provides information regarding the formation of edge feature, the singulation of dice having incipient edge features, the stacking of dice and the handling or dice with edge features. | 05-31-2012 |