Patent application number | Description | Published |
20080273384 | Non-volatile multilevel memory cells with data read of reference cells - Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of reference cells. One method includes programming at least one data cell of a number of data cells coupled to a selected word line to a target data threshold voltage (Vt) level corresponding to a target state; programming at least one reference cell of a number of reference cells coupled to the selected word line to a target reference Vt level, the number of reference cells interleaved with the number of data cells; determining a reference state based on a data read of the at least one reference cell; and changing a state read from the at least one data cell based on a change of the at least one reference cell. | 11-06-2008 |
20080273395 | Expanded programming window for non-volatile multilevel memory cells - Embodiments of the present disclosure provide methods, devices, modules, and systems for utilizing an expanded programming window for non-volatile multilevel memory cells. One method includes associating a different logical state with each of a number of different threshold voltage (Vt) distributions. In various embodiments, at least two Vt distributions include negative Vt levels. The method includes applying a read voltage to a word line of a selected cell while applying a pass voltage to word lines of unselected cells, applying a boost voltage to a source line coupled to the selected cell, applying a voltage greater than the boost voltage to a bit line of the selected cell, and sensing a current variation of the bit line in response to the selected cell changing from a non-conducting state to a conducting state. | 11-06-2008 |
20080278986 | High-Speed and Low-Power Differential Non-Volatile Content Addressable Memory Cell and Array - A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage. Finally, the second terminals of each storage element is connected to a second voltage, different from the first voltage. A current passing through the memory cell is indicative of a mis-match between the contents of the compare data lines and the contents of the storage elements. | 11-13-2008 |
20080310224 | Coarse and fine programming in a solid state memory - Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage. | 12-18-2008 |
20080313493 | PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL - Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels. | 12-18-2008 |
20080316812 | PROGRAMMING A MEMORY WITH VARYING BITS PER CELL - Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals to be stored in a memory array at a particular bit capacity level in order to achieve a desired level of reliability. | 12-25-2008 |
20090021987 | Analog sensing of memory cells in a solid state memory device - A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected memory cell. The memory cell is programmed and then verified with a ramped read voltage. The read voltage that turns on the memory cell is stored in the sample and hold circuit. The target threshold voltage is compared with the read voltage by a comparator circuit. When the read voltage is at least substantially equal to (i.e., is substantially equal to and/or starts to exceed) the target threshold voltage, the comparator circuit generates an inhibit signal. | 01-22-2009 |
20090024904 | Refresh of non-volatile memory cells based on fatigue conditions - In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block. | 01-22-2009 |
20090027960 | Cell deterioration warning apparatus and method - Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Warning of cell deterioration can be performed using reference cells programmed in accordance with a known pattern such as to approximate deterioration of non-volatile memory cells of the device. | 01-29-2009 |
20090027970 | Programming based on controller performance requirements - Methods and solid state drives are disclosed, for example a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits). Programming of the solid state drive, comprising an array of non-volatile memory cells, might include adjusting the level of each memory cell being programmed in response to a desired performance level of a controller circuit. | 01-29-2009 |
20090066547 | ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERSION WINDOW ADJUSTMENT BASED ON REFERENCE CELLS IN A MEMORY DEVICE - An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read to define an upper limit of the conversion window and a second reference voltage is read to define a lower limit of the conversion window. An analog voltage representing a digital bit pattern is read from a memory cell and converted to the digital bit pattern by an analog-to-digital conversion process using the conversion window as the limits for the sampling process. This scheme helps in real time tracking of the ADC window with changes in the program window of the memory array. | 03-12-2009 |
20090067235 | Test circuit and method for multilevel cell flash memory - A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system. | 03-12-2009 |
20090067240 | PROGRAMMING A MEMORY WITH VARYING BITS PER CELL - Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals to be stored in a memory array at a particular bit capacity level in order to achieve a desired level of reliability. | 03-12-2009 |
20090067251 | REDUCING NOISE IN SEMICONDUCTOR DEVICES - The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage. | 03-12-2009 |
20090067266 | MEMORY CONTROLLER SELF-CALIBRATION FOR REMOVING SYSTEMIC INFLUENCE - Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read. | 03-12-2009 |
20090073770 | Independent Bi-Directional Margin Control Per Level And Independently Expandable Reference Cell Levels For Flash Memory Sensing - A memory system includes reference level generators that may provide programmable margins, and programmable verify voltage levels. The reference levels may be shifted within a range of voltages with varying differences between reference voltage levels and with different margins and verify levels. | 03-19-2009 |
20090091973 | REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE - The programming disturb effects in a semiconductor non-volatile memory device are reduced by biasing unselected word lines of a memory block with a negative voltage followed by a positive V | 04-09-2009 |
20090096507 | Integrated Semiconductor Metal-Insulator-Semiconductor Capacitor - An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results. | 04-16-2009 |
20090097311 | NON-EQUAL THRESHOLD VOLTAGE RANGES IN MLC NAND - Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Threshold voltage ranges of the memory cells have a larger range size for ranges that include lower threshold voltages and a smaller range size for ranges that include higher threshold voltages since program disturb is lower at higher threshold voltages. | 04-16-2009 |
20090097318 | Programming sequence in NAND memory - An analog voltage NAND architecture non-volatile memory device and programming process is described that reduce the effects of NAND string resistance in source follower sensing by programming the cells in NAND memory cell strings to maintain the resistance presented by the unselected cells on the source-side of a given selected memory cell of the NAND string during both the verify and read. In particular, in one embodiment of the present invention, the cells in the NAND string are programmed sequentially in order from the cells closest the bit line to the final cell that is closest the source line in the string. This allows the source follower sensing of the verify and later read operations to read the programmed threshold voltage across the same stable source-side resistance | 04-16-2009 |
20090103365 | Sensing of memory cells in NAND flash - An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells utilizing source follower voltage sensing. In a source follower sensing or read operation the programmed threshold voltage of a cell in a NAND string of a NAND architecture Flash memory array is read by applying an elevated voltage to the source line, an elevated pass voltage (Vpass) is placed on the gates of the unselected cells of the string to place them in a pass through mode of operation, and a read gate voltage (Vg) is applied to the gate of the selected cell. The selected memory cell operates as a source follower to set a voltage on the coupled bit line at the read gate voltage minus the threshold voltage of the cell (Vg−Vt), allowing the voltage of the cell to be directly sensed or sampled. | 04-23-2009 |
20090106482 | MEMORY DEVICE PROGRAM WINDOW ADJUSTMENT - In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes. | 04-23-2009 |
20090129146 | MITIGATION OF DATA CORRUPTION FROM BACK PATTERN AND PROGRAM DISTURB IN A NON-VOLATILE MEMORY DEVICE - In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. In an alternate embodiment, a read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations. | 05-21-2009 |
20090129153 | M+N BIT PROGRAMMING AND M+L BIT READ FOR M BIT MEMORY CELLS - A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory. | 05-21-2009 |
20090129169 | METHOD AND APPARATUS FOR READING DATA FROM FLASH MEMORY - Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC). | 05-21-2009 |
20090141558 | Sensing memory cells - The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry. | 06-04-2009 |
20090160411 | FAST VOLTAGE REGULATORS FOR CHARGE PUMPS - A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping. | 06-25-2009 |
20090231926 | ANALOG SENSING OF MEMORY CELLS WITH A SOURCE FOLLOWER DRIVER IN A SEMICONDUCTOR MEMORY DEVICE - Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations. | 09-17-2009 |
20090248952 | DATA CONDITIONING TO IMPROVE FLASH MEMORY RELIABILITY - Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower density memory. Data can be further read, compacted, conditioned and written to higher density memory as background operations. Methods of data conditioning to improve data reliability during storage to higher density memory and methods for managing data across multiple memory arrays are also disclosed. | 10-01-2009 |
20090251969 | ANALOG READ AND WRITE PATHS IN A SOLID STATE MEMORY DEVICE - A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface is comprised of a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage. | 10-08-2009 |
20090257288 | APPARATUS AND METHOD FOR INCREASING DATA LINE NOISE TOLERANCE - Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage, either by providing a higher data line charge voltage with a voltage source, or by providing a higher data line charge voltage with a current source. | 10-15-2009 |
20090273975 | NON-VOLATILE MULTILEVEL MEMORY CELLS WITH DATA READ OF REFERENCE CELLS - Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of reference cells. One method includes programming at least one data cell of a number of data cells coupled to a selected word line to a target data threshold voltage (Vt) level corresponding to a target state; programming at least one reference cell of a number of reference cells coupled to the selected word line to a target reference Vt level, the number of reference cells interleaved with the number of data cells; determining a reference state based on a data read of the at least one reference cell; and changing a state read from the at least one data cell based on a change of the at least one reference cell. | 11-05-2009 |
20090303788 | METHODS AND APPARATUS UTILIZING PREDICTED COUPLING EFFECT IN THE PROGRAMMING OF NON-VOLATILE MEMORY - Methods and memory devices configured to utilize predicted coupling effects of neighboring memory cells in the programming of target memory cells can be utilized to tighten the distribution of threshold voltages for a given bit pattern by compensating for anticipated threshold voltage shift due to capacitive coupling, which can facilitate more discernable Vt ranges, and thus a higher number of bits of data per memory cell. Tightening the distribution of threshold voltages can further facilitate wider margins between Vt ranges, and thus an increased reliability in reading the correct data value of a memory cell. | 12-10-2009 |
20090303803 | Independent Bi-Directional Margin Control Per Level and Independently Expandable Reference Cell Levels for Voltage Mode Sensing - A memory system includes reference level generators that may provide programmable margins, and programmable verify voltage levels. The reference levels may be shifted within a range of voltages with varying differences between reference voltage levels and with different margins and verify levels. | 12-10-2009 |
20090310406 | M+L BIT READ COLUMN ARCHITECTURE FOR M BIT MEMORY CELLS - A memory device and programming and/or reading process is described that programs a row of non-volatile multi-level memory cells (MLC) in a single program operation to minimize disturb within the pages of the row, while verifying each memory cell page of the row separately. In one embodiment of the present invention, the memory device utilizes data latches to program M-bits of data into each cell of the row and then repurposes the data latches during the subsequent page verify operations to read M+L bits from each cell of the selected page at a higher threshold voltage resolution than required. In sensing, the increased threshold voltage resolution/granularity allows interpretations of the actual programmed state of the memory cell and enables more effective use of data encoding and decoding techniques such as convolutional codes where additional granularity of information is used to make soft decisions reducing the overall memory error rate. | 12-17-2009 |
20090310407 | SENSING AGAINST A REFERENCE CELL - Memory devices, bulk storage devices, and methods of operating memory are disclosed, such as those adapted to process and generate analog data signals representative of data values of two or more bits of information. Programming of such memory devices can include programming to a target threshold voltage within a range representative of the desired bit pattern. Reading such memory devices can include generating an analog data signal indicative of a threshold voltage of a target memory cell. The target memory cell can be sensed against a reference cell includes a dummy string of memory cells connected to a target string of memory cells, and, such as by using a differential amplifier to sense a difference between a reference cell and the target cell. This may allow a wider range of voltages to be used for data states. | 12-17-2009 |
20100039863 | MITIGATION OF RUNAWAY PROGRAMMING OF A MEMORY DEVICE - Methods for mitigating runaway programming in a memory device, methods for program verifying a memory device, a memory device, and a memory system are provided. In one such method, a ramp voltage signal is generated by a digital count signal. A memory cell being program verified is turned on by a particular verify voltage of the ramp voltage signal in response to a digital count of the digital count signal. The memory cell turning on generates a bit line indication that causes the digital count to be compared to a representation of the target data to be programmed in the memory cell. The comparator circuit generates an indication when the digital count is greater than or equal to the target data. | 02-18-2010 |
20100039864 | METHODS OF ERASE VERIFICATION FOR A FLASH MEMORY DEVICE - Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification. | 02-18-2010 |
20100046300 | REDUCTION OF QUICK CHARGE LOSS EFFECT IN A MEMORY DEVICE - Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to the word line after the programming pulse to force any electrons trapped in the tunnel oxide of memory cells being programmed back into the tunnel region. After the negative pulse, a program verify operation is performed. | 02-25-2010 |
20100061147 | REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE - The programming disturb effects in a semiconductor non-volatile memory device are reduced by biasing unselected word lines of a memory block with a negative voltage followed by a positive V | 03-11-2010 |
20100074010 | MEMORY DEVICE REFERENCE CELL PROGRAMMING METHOD AND APPARATUS - Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example, one such assignment scheme assigns reference cells in a staggered pattern by row wherein each column contains a single reference cell. Additional schemes of multiple reference cells assigned in a repeating or a pseudo-random pattern are also disclosed. | 03-25-2010 |
20100091565 | M+N BIT PROGRAMMING AND M+L BIT READ FOR M BIT MEMORY CELLS - A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory. | 04-15-2010 |
20100091567 | Test Circuit and Method for Multilevel Cell Flash Memory - A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system. | 04-15-2010 |
20100110798 | PROGRAM WINDOW ADJUST FOR MEMORY CELL SIGNAL LINE DELAY - A memory device and programming and/or reading process is described that compensates for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Memory cell signal line propagation delay compensation can be accomplished by characterizing the memory cell signal line propagation delay, such as determining an amount of error due to the delay, and pre-compensating the programmed threshold voltage of the memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Alternatively, memory cell signal line propagation delay can be post-compensated for, or the pre-compensation fine tuned, after sensing the threshold voltages of the selected memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Other methods, devices, etc., are also disclosed. | 05-06-2010 |
20100115176 | DATA TRANSFER AND PROGRAMMING IN A MEMORY DEVICE - Methods for data transfer and/or programming a memory device, memory devices and memory systems are provided. According to at least one such method, additional data is appended to original data and the resulting data is programmed in a selected memory cell. The appended data increases the program threshold voltage margin of the original data. The appended data can be a duplicate of the original data or logical zeros. When the selected memory cell is read, the memory control circuitry can read just the original data in the MSB field or the memory control circuitry can read the entire programmed data and ignore the LSB field, for example. | 05-06-2010 |
20100122103 | CONFIGURABLE DIGITAL AND ANALOG INPUT/OUTPUT INTERFACE IN A MEMORY DEVICE - Methods and memory devices are disclosed, for example a memory device that has both an analog path and a digital path that both share the same input/output pad. One of the two paths on each pad is selected in response to command signals that indicate the nature of the signal being either transmitted to the device or read from the device. Each digital path includes a latch for latching digital input data. Each analog path includes a sample/hold circuit for storing either analog data being read from or analog data being written to the memory device. | 05-13-2010 |
20100124108 | PROGRAMMING METHODS AND MEMORIES - Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming is inhibited. Overlapping levels and/or voltage ranges can be used. | 05-20-2010 |
20100124126 | ERASE VOLTAGE REDUCTION IN A NON-VOLATILE MEMORY DEVICE - In erasing a memory block of memory cells, a semiconductor tub that contains a memory block to be erased can be biased with a high, positive voltage. The control gates of the memory cells that make up the memory block can be biased with a negative voltage. An erase verification can then be performed to determine if the memory block has been successfully erased. If the memory block has not been erased, the erase operation of biasing the tub with the positive voltage and the control gates with the negative voltage can be repeated until the erase verification is successful. | 05-20-2010 |
20100124127 | SYSTEMS AND METHODS FOR ERASING A MEMORY - Methods of erasing a memory, methods of operating a memory, memory devices, and systems are disclosed, for example. In one such method, an erase block is erased to an intermediate erase voltage before it is erased to a final erase voltage, such as to tighten an erase distribution. Faster erasing cells have their erasing throttled using a positive bias on their access line once a particular number of cells coupled to the access line are erased to the intermediate erase voltage. | 05-20-2010 |
20100124132 | REPLACING DEFECTIVE COLUMNS OF MEMORY CELLS IN RESPONSE TO EXTERNAL ADDRESSES - Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective memory column replaces the defective memory column. The non-defective column of memory cells is proximate non-defective column of memory cells following the defective column of memory cells in the sequence of columns of memory cells that is available to replace the defective column of memory cells. | 05-20-2010 |
20100124133 | REPLACING DEFECTIVE MEMORY BLOCKS IN RESPONSE TO EXTERNAL ADDRESSES - Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective memory block of a sequence of memory blocks of the memory device in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block. | 05-20-2010 |
20100142267 | MEMORY CELL SHIFT ESTIMATION METHOD AND APPARATUS - Memory devices and methods are disclosed, such as those facilitating interpolation methods for reference memory cells based on their reference state and/or location in an array of memory cells. For example, a group of reference cells programmed to a subset of possible data states are utilized to interpolate for data states other than those in the subset. Such embodiments might be used to reduce the quantity of reference cells required. | 06-10-2010 |
20100146329 | CELL DETERIORATION WARNING APPARATUS AND METHOD - Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Warning of cell deterioration can be performed using reference cells programmed in accordance with a known pattern such as to approximate deterioration of non-volatile memory cells of the device. | 06-10-2010 |
20100188138 | Fast Start Charge Pump for Voltage Regulators - A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping. | 07-29-2010 |
20100188898 | REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE - The programming disturb effects in a semiconductor non-volatile memory device can be mitigated by biasing unselected memory cells with a negative voltage while a well containing the memory cells receives a positive voltage. A selected memory cell in the well can be biased with a negative voltage while the well is at the positive voltage then the selected memory cell bias transitions to a positive programming voltage when the well returns to a ground potential. | 07-29-2010 |
20100195403 | ERASE VERIFY IN MEMORY DEVICES - In one or more embodiments, methods for erasing memory devices, and a memory system are disclosed, one such method comprising determining which cells of a sample are not erased, either directly or indirectly. The number of unerased cells in the sample can be compared to a threshold. An erase operation can be performed on the memory block responsive to the comparison until the number of unerased cells is less than the threshold. | 08-05-2010 |
20100208524 | SOFT LANDING FOR DESIRED PROGRAM THRESHOLD VOLTAGE - Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage, and applying a second set of programming pulses to program to a final threshold voltage. | 08-19-2010 |
20100246261 | PROGRAMMING A MEMORY WITH VARYING BITS PER CELL - Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals to be stored in a memory array at a particular bit capacity level in order to achieve a desired level of reliability. | 09-30-2010 |
20100246271 | ANALOG SENSING OF MEMORY CELLS WITH A SOURCE FOLLOWER DRIVER IN A SEMICONDUCTOR MEMORY DEVICE - Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations. | 09-30-2010 |
20100259978 | METHODS AND APPARATUS UTILIZING EXPECTED COUPLING EFFECT IN THE PROGRAMMING OF MEMORY CELLS - Methods and memory devices configured to utilize predicted coupling effects of neighboring memory cells in the programming of target memory cells can be utilized to tighten the distribution of threshold voltages for a given bit pattern by compensating for anticipated threshold voltage shift due to capacitive coupling, which can facilitate more discernable Vt ranges, and thus a higher number of bits of data per memory cell. Tightening the distribution of threshold voltages can further facilitate wider margins between Vt ranges, and thus an increased reliability in reading the correct data value of a memory cell. | 10-14-2010 |
20100265771 | METHOD OF PROGRAMMING MEMORY CELLS OF SERIES STRINGS OF MEMORY CELLS - Method of programming memory cells of series strings of memory cells include programming a target memory cell of a series string of memory cells after programming each memory cell of the string located between the target memory cell and a first end of the string, and verifying the programming of the target memory cell by applying a bias at a second end of the string opposite the first end and sensing a voltage developed at the first end in response to the bias. | 10-21-2010 |
20100271872 | ANALOG READ AND WRITE PATHS IN A SOLID STATE MEMORY DEVICE - A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage. | 10-28-2010 |
20100321995 | MEMORY CELL THRESHOLD VOLTAGE DRIFT ESTIMATION METHODS AND APPARATUS - Methods of operating memory devices include determining a threshold voltage drift of two or more reference memory cells of the memory device programmed to only a subset of data states of the memory device and, using the determined threshold voltage drift of the two or more reference memory cells, estimating a threshold voltage drift of one or more user data memory cells programmed to a data state of the memory device that is mutually exclusive to the subset of data states of the memory device. Apparatus include memory devices having an array of memory cells having one or more user data memory cells and two or more reference memory cells, and control circuitry configured to maintain locations and initial programmed threshold voltages of the two or more reference memory cells corresponding to only a subset of data states of the memory device. | 12-23-2010 |
20110007566 | MEMORY CONTROLLER SELF-CALIBRATION FOR REMOVING SYSTEMIC INFLUENCE - Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read. | 01-13-2011 |
20110019478 | SENSING OF MEMORY CELLS IN NAND FLASH - An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells utilizing source follower voltage sensing. In a source follower sensing or read operation the programmed threshold voltage of a cell in a NAND string of a NAND architecture Flash memory array is read by applying an elevated voltage to the source line, an elevated pass voltage (V | 01-27-2011 |
20110022905 | Test Circuit and Method for Multilevel Cell Flash Memory - A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system. | 01-27-2011 |
20110032761 | METHODS OF ERASE VERIFICATION FOR A FLASH MEMORY DEVICE - Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification. | 02-10-2011 |
20110058413 | MITIGATION OF DATA CORRUPTION FROM BACK PATTERN AND PROGRAM DISTURB IN A NON-VOLATILE MEMORY DEVICE - In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. In an alternate embodiment, a read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations. | 03-10-2011 |
20110063906 | MEMORY ADAPTED TO PROGRAM A NUMBER OF BITS TO A MEMORY CELL AND READ A DIFFERENT NUMBER OF BITS FROM THE MEMORY CELL - A memory has a memory array with a memory cell. The memory is adapted to program a first number of bits into the memory cell. The memory is adapted to sense a second number of bits, different from the first number of bits, from the memory cell. | 03-17-2011 |
20110090735 | EXPANDED PROGRAMMING WINDOW FOR NON-VOLATILE MULTILEVEL MEMORY CELLS - Embodiments of the present disclosure provide methods, devices, modules, and systems for utilizing an expanded programming window for non-volatile multilevel memory cells. One method includes associating a different logical state with each of a number of different threshold voltage (Vt) distributions. In various embodiments, at least two Vt distributions include negative Vt levels. The method includes applying a read voltage to a word line of a selected cell while applying a pass voltage to word lines of unselected cells, applying a boost voltage to a source line coupled to the selected cell, applying a voltage greater than the boost voltage to a bit line of the selected cell, and sensing a current variation of the bit line in response to the selected cell changing from a non-conducting state to a conducting state. | 04-21-2011 |
20110096608 | MITIGATION OF RUNAWAY PROGRAMMING OF A MEMORY DEVICE - Methods for mitigating runaway programming in a memory device, methods for program verifying a memory device, a memory device, and a memory system are provided. In one such method, a ramp voltage signal is generated by a digital count signal. A memory cell being program verified is turned on by a particular verify voltage of the ramp voltage signal in response to a digital count of the digital count signal. The memory cell turning on generates a bit line indication that causes the digital count to be compared to a representation of the target data to be programmed in the memory cell. The comparator circuit generates an indication when the digital count is greater than or equal to the target data. | 04-28-2011 |
20110110152 | NON-VOLATILE MULTILEVEL MEMORY CELLS WITH DATA READ OF REFERENCE CELLS - Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of reference cells. One method includes programming at least one data cell of a number of data cells coupled to a selected word line to a target data threshold voltage (Vt) level corresponding to a target state; programming at least one reference cell of a number of reference cells coupled to the selected word line to a target reference Vt level, the number of reference cells interleaved with the number of data cells; determining a reference state based on a data read of the at least one reference cell; and changing a state read from the at least one data cell based on a change of the at least one reference cell. | 05-12-2011 |
20110121799 | Fast Voltage Regulators For Charge Pumps - A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping. | 05-26-2011 |
20110122717 | REPLACING DEFECTIVE COLUMNS OF MEMORY CELLS IN RESPONSE TO EXTERNAL ADDRESSES - Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device in place of a defective column of memory cells of the memory device in response to receiving an address of the defective column of memory cells from the memory device. In another embodiment, a memory device has columns of memory cells and is configured to receive an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective column replaces the defective column. The non-defective column is a proximate non-defective column following the defective column in the sequence of columns that is available to replace the defective column. | 05-26-2011 |
20110134701 | MEMORY KINK COMPENSATION - This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude. | 06-09-2011 |
20110199831 | COARSE AND FINE PROGRAMMING IN A SOLID STATE MEMORY - Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage. | 08-18-2011 |
20110205792 | MEMORY DEVICE REFERENCE CELL PROGRAMMING METHOD AND APPARATUS - Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example, one such assignment scheme assigns reference cells in a staggered pattern by row wherein each column contains a single reference cell. Additional schemes of multiple reference cells assigned in a repeating or a pseudo-random pattern are also disclosed. | 08-25-2011 |
20110222353 | SENSING OPERATIONS IN A MEMORY DEVICE - Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell. | 09-15-2011 |
20110235422 | APPARATUS HAVING A STRING OF MEMORY CELLS - Apparatus having a string of memory cells are useful in semiconductor memory. Some apparatus have circuitry configured to program memory cells of the string in a particular sequence. Some apparatus have circuitry configured to program a threshold voltage of a selected memory cell in the string to match a target voltage compensating, at least in part, for a voltage drop across any unselected memory cells in the string on a source side of the selected memory cell during a sensing operation. Some apparatus have circuitry configured to maintain a resistance presented by source-side unselected memory cells of the string the same between a program verify operation and a later read operation. | 09-29-2011 |
20110249507 | SENSING MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry. | 10-13-2011 |
20110273933 | ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERSION WINDOW ADJUSTMENT BASED ON REFERENCE CELLS IN A MEMORY DEVICE - An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read to define an upper limit of the conversion window and a second reference voltage is read to define a lower limit of the conversion window. An analog voltage representing a digital bit pattern is read from a memory cell and converted to the digital bit pattern by an analog-to-digital conversion process using the conversion window as the limits for the sampling process. This scheme helps in real time tracking of the ADC window with changes in the program window of the memory array. | 11-10-2011 |
20110289254 | CONFIGURABLE DIGITAL AND ANALOG INPUT/OUTPUT INTERFACE IN A MEMORY DEVICE - Methods and memory devices are disclosed, for example a memory device that has both an analog path and a digital path that both share the same input/output pad. One of the two paths on each pad is selected in response to command signals that indicate the nature of the signal being either transmitted to the device or read from the device. Each digital path includes a latch for latching digital input data. Each analog path includes a sample/hold circuit for storing either analog data being read from or analog data being written to the memory device. | 11-24-2011 |
20110289387 | PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL - Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels. | 11-24-2011 |
20110305090 | MEMORY CONTROLLER SELF-CALIBRATION FOR REMOVING SYSTEMIC INFLUENCE - Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read. | 12-15-2011 |
20120002468 | CELL DETERIORATION WARNING APPARATUS AND METHOD - Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Warning of cell deterioration can be performed using reference cells programmed in accordance with a known pattern such as to approximate deterioration of non-volatile memory cells of the device. | 01-05-2012 |
20120008399 | METHODS OF OPERATING MEMORIES INCLUDING CHARACTERIZING MEMORY CELL SIGNAL LINES - Methods of operating memories facilitate compensating for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Methods include selecting a memory cell signal line of a memory and characterizing the memory cell signal line by determining an RC time constant of the memory cell signal line. | 01-12-2012 |
20120008409 | REDUCTION OF QUICK CHARGE LOSS EFFECT IN A MEMORY DEVICE - Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to the word line after the programming pulse to force any electrons trapped in the tunnel oxide of memory cells being programmed back into the tunnel region. After the negative pulse, a program verify operation is performed. | 01-12-2012 |
20120030529 | REFRESH OF NON-VOLATILE MEMORY CELLS BASED ON FATIGUE CONDITIONS - In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block. | 02-02-2012 |
20120033504 | ERASE VOLTAGE REDUCTION IN A NON-VOLATILE MEMORY DEVICE - In erasing a memory block of memory cells, a semiconductor tub that contains a memory block to be erased can be biased with a high, positive voltage. The control gates of the memory cells that make up the memory block can be biased with a negative voltage. An erase verification can then be performed to determine if the memory block has been successfully erased. If the memory block has not been erased, the erase operation of biasing the tub with the positive voltage and the control gates with the negative voltage can be repeated until the erase verification is successful. | 02-09-2012 |
20120069675 | REDUCING NOISE IN SEMICONDUCTOR DEVICES - The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage. | 03-22-2012 |
20120074923 | Fast Voltage Regulators For Charge Pumps - A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping. | 03-29-2012 |
20120075929 | SENSING OF MEMORY CELLS IN NAND FLASH - An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells utilizing source follower voltage sensing. In a source follower sensing or read operation the programmed threshold voltage of a cell in a NAND string of a NAND architecture Flash memory array is read by applying an elevated voltage to the source line, an elevated pass voltage (V | 03-29-2012 |
20120092932 | PROGRAMMING METHODS AND MEMORIES - Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming is inhibited. Overlapping levels and/or voltage ranges can be used. | 04-19-2012 |
20120106249 | PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL - Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels. | 05-03-2012 |
20120106261 | SYSTEMS AND METHODS FOR ERASING A MEMORY - Methods of erasing a memory, methods of operating a memory, memory devices, and systems. In one such method, an erase block is erased to an intermediate erase voltage before it is erased to a final erase voltage, such as to tighten an erase distribution. Faster erasing cells have their erasing throttled using a positive bias on their access line once a particular number of cells coupled to the access line are erased to the intermediate erase voltage. | 05-03-2012 |
20120113723 | MITIGATION OF DATA CORRUPTION FROM BACK PATTERN AND PROGRAM DISTURB IN A NON-VOLATILE MEMORY DEVICE - In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. In an alternate embodiment, a read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations. | 05-10-2012 |
20120117313 | MEMORY DEVICE PROGRAM WINDOW ADJUSTMENT - In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes. | 05-10-2012 |
20120144101 | PROGRAMMING MEMORY CELLS WITH ADDITIONAL DATA FOR INCREASED THRESHOLD VOLTAGE RESOLUTION - Methods for programming memory and memory devices are provided. According to at least one such method, additional data is appended to original data and the resulting data is programmed in a selected memory cell. The appended data increases the program threshold voltage margin of the original data. The appended data can be a duplicate of the original data or logical zeros. When the selected memory cell is read, the memory control circuitry can read just the original data in the MSB field or the memory control circuitry can read the entire programmed data and ignore the LSB field, for example. | 06-07-2012 |
20120163076 | SINGLE CHECK MEMORY DEVICES AND METHODS - Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells. | 06-28-2012 |
20120275233 | SOFT LANDING FOR DESIRED PROGRAM THRESHOLD VOLTAGE - Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage, and applying a second set of programming pulses to program to a final threshold voltage. | 11-01-2012 |
20120281480 | SENSING OPERATIONS IN A MEMORY DEVICE - Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell. | 11-08-2012 |
20120307564 | METHOD FOR KINK COMPENSATION IN A MEMORY - This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude. | 12-06-2012 |
20120307576 | ANALOG SENSING OF MEMORY CELLS WITH A SOURCE FOLLOWER DRIVER IN A SEMICONDUCTOR MEMORY DEVICE - Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations. | 12-06-2012 |
20120314503 | COARSE AND FINE PROGRAMMING IN A SOLID STATE MEMORY - Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage. | 12-13-2012 |
20120331217 | MEMORY DEVICE PROGRAM WINDOW ADJUSTMENT - In one or more embodiments, a memory device has an adjustable programming window with a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes. | 12-27-2012 |
20130007355 | DATA CONDITIONING TO IMPROVE FLASH MEMORY RELIABILITY - Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower density memory. Data can be further read, compacted, conditioned and written to higher density memory as background operations. Methods of data conditioning to improve data reliability during storage to higher density memory and methods for managing data across multiple memory arrays are also disclosed. | 01-03-2013 |
20130010542 | PROGRAMMING METHODS AND MEMORIES - Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell. | 01-10-2013 |
20130024736 | PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL - Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels. | 01-24-2013 |
20130051141 | THRESHOLD VOLTAGE COMPENSATION IN A MULTILEVEL MEMORY - Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. | 02-28-2013 |
20130058164 | MEMORY APPARATUS, SYSTEMS, AND METHODS - Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided. | 03-07-2013 |
20130135926 | APPARATUS HAVING INDICATIONS OF MEMORY CELL DENSITY AND METHODS OF THEIR DETERMINATION AND USE - Methods and apparatus utilizing indications of memory cell density facilitate management of memory density of a memory device. By permitting each of a plurality of portions of a memory array of the memory device to be assigned a corresponding memory cell density determined through an evaluation of those portions of the memory array, better performing portions of the memory array may not be hindered by lesser performing portions of the memory array. | 05-30-2013 |
20130301357 | REDUCING NOISE IN SEMICONDUCTOR DEVICES - The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage. | 11-14-2013 |
20140043912 | METHOD FOR KINK COMPENSATION IN A MEMORY - This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude. | 02-13-2014 |
20140098607 | SENSING MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry. | 04-10-2014 |
20140104956 | SENSING OPERATIONS IN A MEMORY DEVICE - Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell. | 04-17-2014 |
20140298088 | DATA CONDITIONING TO IMPROVE FLASH MEMORY RELIABILITY - Methods for managing data stored in a memory device facilitate managing utilization of memory of different densities. The methods include reading first data from a first number of pages or blocks of memory cells having a first density, performing a data handling operation on the read first data to generate second data, and writing the second data to a second number of pages or blocks of memory cells having a second density, wherein the second density is different than the first density, and wherein the second number is different than the first number. | 10-02-2014 |
20140351663 | SINGLE CHECK MEMORY DEVICES AND METHODS - Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells. | 11-27-2014 |