Patent application number | Description | Published |
20080239806 | NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING - Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number of program states. The method includes determining whether the Vt of each of the cells has reached a pre-verify voltage (PVFY) associated with the program state, selectively biasing bit lines coupled to those cells whose Vt has reached the PVFY, adjusting the PVFY to a different level, and selectively biasing bit lines coupled to cells whose Vt has reached the adjusted PVFY, wherein the PVFY and the adjusted PVFY are less than the VFY. | 10-02-2008 |
20080285341 | READING NON-VOLATILE MULTILEVEL MEMORY CELLS - Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an adjacent cell of a second word line in response to the request, determining whether the first cell is in a disturbed condition based on the read operation. The method includes reading data stored in the first cell in response to the read request by applying a read reference voltage to the first word line and adjusting a sensing parameter if the first cell is in the disturbed condition. | 11-20-2008 |
20080304327 | Methods and apparatuses for refreshing non-volatile memory - Methods and apparatuses for refreshing non-volatile memories due to changes in memory cell charges, such as charge loss, are disclosed. Embodiments generally comprise a voltage generator to create a sub-threshold voltage for a memory state of memory cells in a block. Once the sub-threshold voltage is applied to a word line a state reader determines states of memory cells coupled to the word line. If the state reader determines that one or more of the memory cells coupled to the word line is in the memory state, despite the sub-threshold voltage, a memory refresher may program a number of memory cells in the block. Method embodiments generally comprise applying a sub-threshold voltage to a word line for a plurality of memory cells, detecting at least one memory cell of the plurality violates a state parameter, and refreshing a block of memory cells associated with the plurality of cells. | 12-11-2008 |
20090052269 | Charge loss compensation methods and apparatus - Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis. | 02-26-2009 |
20090135650 | COMPENSATION OF BACK PATTERN EFFECT IN A MEMORY DEVICE - In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation. | 05-28-2009 |
20090219761 | CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE - A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation. | 09-03-2009 |
20090290426 | CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE - In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page. | 11-26-2009 |
20100031096 | INTERNAL FAIL BIT OR BYTE COUNTER - Briefly, in accordance with one or more embodiments, an internal fail byte counter is disclosed. | 02-04-2010 |
20100091582 | ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING - Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line. | 04-15-2010 |
20100128534 | Word Line Voltage Boost System and Method for Non-Volatile Memory Devices and Memory Devices and Processor-Based System Using Same - The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array. | 05-27-2010 |
20100157685 | PROGRAMMING IN A MEMORY DEVICE - Methods for programming a memory device, memory devices, and a memory systems are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude. | 06-24-2010 |
20100246265 | ERASE CYCLE COUNTER USAGE IN A MEMORY DEVICE - Memory devices and methods are disclosed to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of memory. Programming voltage levels utilized during program operations of memory cells are determined, at least in part, based upon the value of the erase cycle counter stored in a memory block undergoing a programming operation, for example. | 09-30-2010 |
20100246270 | CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE - A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation. | 09-30-2010 |
20110063920 | SENSING FOR ALL BIT LINE ARCHITECTURE IN A MEMORY DEVICE - Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells of the first selected word line is complete, the precharge voltage is maintained on the bit lines while a second word line is selected. | 03-17-2011 |
20110134701 | MEMORY KINK COMPENSATION - This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude. | 06-09-2011 |
20110157980 | TECHNIQUE TO REDUCE FG-FG INTERFERENCE IN MULTI BIT NAND FLASH MEMORY IN CASE OF ADJACENT PAGES NOT FULLY PROGRAMMED - A method of reducing floating gate-floating gate interference in programming NAND flash memory is provided. Prior to programming an upper page of a memory cell, the method includes checking whether adjacent pages of near memory cells have been programmed. The method may program adjacent pages of near memory cells that have not been programmed. | 06-30-2011 |
20110170359 | WORD LINE VOLTAGE BOOST SYSTEM AND METHOD FOR NON-VOLATILE MEMORY DEVICES AND MEMORY DEVICES AND PROCESSOR-BASED SYSTEM USING SAME - The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array. | 07-14-2011 |
20110194350 | COMPENSATION OF BACK PATTERN EFFECT IN A MEMORY DEVICE - In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation. | 08-11-2011 |
20110199826 | CHARGE LOSS COMPENSATION METHODS AND APPARATUS - Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis. | 08-18-2011 |
20110255343 | PROGRAMMING IN A MEMORY DEVICE - Methods for programming a memory device and memory devices are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude. | 10-20-2011 |
20110255344 | CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE - A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation. | 10-20-2011 |
20120026792 | ERASE CYCLE COUNTER USAGE IN A MEMORY DEVICE - Memory devices to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of memory. Programming voltage levels utilized during program operations of memory cells are determined, at least in part, based upon the value of the erase cycle counter stored in a memory block undergoing a programming operation, for example. | 02-02-2012 |
20120075932 | CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE - In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page. | 03-29-2012 |
20120081972 | MEMORY ARRAYS AND METHODS OF OPERATING MEMORY - Apparatus and methods for determining pass/fail condition of memories are disclosed. In at least one embodiment, a set of common lines, one for each rank of page buffers corresponding to a page, determine the pass/fail status of all connected memory cells, and the pass/fail status results for each line can be combined to determine a pass/fail for the page of memory. | 04-05-2012 |
20120127794 | PROGRAM VERIFY OPERATION IN A MEMORY DEVICE - Methods for program verifying, program verify circuits, and memory devices are disclosed. One such method for program verifying includes generating a ramped voltage for a plurality of count values. The ramped voltage is applied to a control gate of a memory cell being program verified. At least a portion of each count value is compared to an indication of a target threshold voltage for the memory cell. When the at least a portion of the count value is equal to the indication of the target threshold voltage indication, sense circuitry is used to check if the memory cell has been activated by the voltage generated by the count. If the memory cell has been activated, an inhibit latch is set to inhibit further programming of the memory cell. If the memory cell has not been activated by the voltage, the memory cell is biased with another programming pulse. | 05-24-2012 |
20120176843 | MEMORIES AND METHODS OF PROGRAMMING MEMORIES - Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper limit is determined after a single programming pulse for lower page programming, and upper page programming start voltages are adjusted based on the determined upper limit of the threshold voltage distribution. | 07-12-2012 |
20120206974 | SENSING FOR ALL BIT LINE ARCHITECTURE IN A MEMORY DEVICE - Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells of the first selected word line is complete, the precharge voltage is maintained on the bit lines while a second word line is selected. | 08-16-2012 |
20120224429 | METHODS FOR PROGRAMMING A MEMORY DEVICE AND MEMORY DEVICES - Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS | 09-06-2012 |
20120262993 | SENSING SCHEME IN A MEMORY DEVICE - Methods of operating memory devices, generating reference currents in memory devices, and sensing data states of memory cells in a memory device are disclosed. One such method includes generating reference currents utilized in sense amplifier circuitry to manage leakage currents while performing a sense operation within a memory device. Another such method activates one of two serially coupled transistors along with activating and deactivating the second transistor serially coupled with the first transistor thereby regulating a current through both serially coupled transistors and establishing a particular reference current. | 10-18-2012 |
20120287726 | ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING - Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line. | 11-15-2012 |
20120307566 | MEMORY CELL SENSING USING A BOOST VOLTAGE - The present disclosure includes devices, methods, and systems including memory cell sensing using a boost voltage. One or more embodiments include pre-charging and/or floating a data line associated with a selected memory cell, boosting the pre-charged and/or floating data line, and determining a state of the selected memory cell based on a sensed discharge of the data line after boosting the data line. | 12-06-2012 |
20130028022 | DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE - Methods for determining a program window and memory devices are disclosed. One such method for determining the program window measures an amount of program disturb experienced by a particular state and determines the program window responsive to the amount of program disturb. | 01-31-2013 |
20130039138 | METHODS FOR PROVIDING REDUNDANCY AND APPARATUSES - Methods for providing redundancy and apparatuses are disclosed. One such method for providing redundancy performs a mapping of data between an address of a memory determined to indicate a defective memory cell and an address of a redundant area of the memory, only after the data has been loaded into a buffer. The direction of the mapping is determined by the operation (e.g., programming or reading). | 02-14-2013 |
20130272071 | DETERMINING SOFT DATA FOR COMBINATIONS OF MEMORY CELLS - The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and a second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells. | 10-17-2013 |
20130343132 | MEMORY ARRAYS AND METHODS OF OPERATING MEMORY - Apparatus and methods for determining pass/fail condition of memories are disclosed. In at least one embodiment, a set of common lines, one for each rank of page buffers corresponding to a page, determine the pass/fail status of all connected memory cells, and the pass/fail status results for each line can be combined to determine a pass/fail for the page of memory. | 12-26-2013 |
20140016409 | MULTIPLE STEP PROGRAMMING IN A MEMORY DEVICE - A method for multiple step programming programs data to an even page of memory cells. The even page of memory cells is read into a page buffer and the uncertain data is removed. An odd page of memory cells is programmed and the data from the even page data from the page buffer is reprogrammed to the even page of memory cells without the uncertain data. | 01-16-2014 |
20140112068 | METHODS OF PROGRAMMING MEMORY DEVICES - Methods of programming memory devices include biasing each data line of a plurality of data lines to a program inhibit voltage; discharging a first portion of data lines of the plurality of data lines, wherein the first portion of data lines of the plurality of data lines are coupled to memory cells selected for programming; and applying a plurality of programming pulses to the memory cells selected for programming while biasing a remaining portion of data lines of the plurality of data lines to the program inhibit voltage. | 04-24-2014 |
20140177342 | MEMORY CELL SENSING USING A BOOST VOLTAGE - The present disclosure includes devices, methods, and systems including memory cell sensing using a boost voltage. One or more embodiments include pre-charging and/or floating a data line associated with a selected memory cell, boosting the pre-charged and/or floating data line, and determining a state of the selected memory cell based on a sensed discharge of the data line after boosting the data line. | 06-26-2014 |
20140219032 | METHODS FOR PROGRAMMING A MEMORY DEVICE AND MEMORY DEVICES - Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS2 situations are detected. If the number of detected potential CS2 situations is greater than a threshold, programming compensation for a CS2 situation is used in a subsequent programming operation. | 08-07-2014 |
20140241097 | LOADING TRIM ADDRESS AND TRIM DATA PAIRS - Methods of loading trim address and trim data pairs to a trim register array, and apparatus configured to perform such methods. The methods maintain a correspondence between the trim address and the trim data of each trim address and trim data pair in the trim register array. The trim address of a particular trim address and trim data pair corresponds to a storage location of a trim settings array containing trim settings used in performing operations on an array of memory cells. The trim data of the particular trim address and trim data pair corresponds to data to modify a value of the storage location of the trim settings array corresponding to the trim address of the particular trim address and trim data pair. | 08-28-2014 |
20140293697 | CHARGE LOSS COMPENSATION METHODS AND APPARATUS - Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis. | 10-02-2014 |
20140321205 | MEMORY DEVICE PAGE BUFFER CONFIGURATION AND METHODS - Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time. | 10-30-2014 |
20140369117 | MULTIPLE STEP PROGRAMMING IN A MEMORY DEVICE - Method of operating a memory include programming a memory cell and reading the memory cell to determine a programmed threshold voltage of the memory cell. If the programmed threshold voltage is within a threshold voltage distribution of a plurality of threshold voltage distributions, the memory cell is reprogrammed, and if the programmed threshold voltage is not within a threshold voltage distribution of the plurality of threshold voltage distributions, the memory cell is allowed to remain at the programmed threshold voltage. | 12-18-2014 |
20150029788 | METHODS OF PROGRAMMING MEMORY DEVICES - Methods of programming memory devices include biasing each data line of a plurality of data lines to a program inhibit voltage; discharging a first portion of data lines of the plurality of data lines, wherein the first portion of data lines of the plurality of data lines are coupled to memory cells selected for programming; and applying a plurality of programming pulses to the memory cells selected for programming while biasing a remaining portion of data lines of the plurality of data lines to the program inhibit voltage. | 01-29-2015 |